From fd55628c5e7c0b4d345c7bc5bdd522297f35afbf Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Sat, 11 Jun 2022 09:49:35 +0100
Subject: [PATCH]

---
 openpower/sv/mv.vec.mdwn | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/openpower/sv/mv.vec.mdwn b/openpower/sv/mv.vec.mdwn
index ae7dd3b12..805c45754 100644
--- a/openpower/sv/mv.vec.mdwn
+++ b/openpower/sv/mv.vec.mdwn
@@ -51,6 +51,18 @@ in this example RA elwidth=32 and RB elwidth=8, RB is a vec4.
          for j in range(SUBVL): # vec4
               start_point[j] = some_op(int_regfile[RB].b[i*SUBVL + j])
 
+RM Mode Concept:
+
+MVRM-2P-2S1D:
+
+| Field Name | Field bits | Description                     |
+|------------|------------|----------------------------|
+| Rdest_EXTRA2 | `10:11`  | extends Rdest (R\*\_EXTRA2 Encoding)   |
+| Rsrc_EXTRA2  | `12:13`  | extends Rsrc  (R\*\_EXTRA2 Encoding)   |
+| src_SUBVL    | `14:15`  | SUBVL for Source              |
+| MASK_SRC     | `16:18`  | Execution Mask for Source     |
+
+
 ## Twin Predication, saturation, swizzle, and elwidth overrides
 
 Note that mv is a twin-predicated operation, and is swizzlable.  This implies that from the vec2, vec3 or vec4, 1 to 8 bytes may be selected and re-ordered (XYZW), mixed with 0 and 1 constants, skipped by way of twin predicate pack and unpack, and a huge amount besides.
-- 
2.30.2