From fd5ee548b6e333c92877440524c116e09bdd7c73 Mon Sep 17 00:00:00 2001 From: whitequark Date: Thu, 2 Jul 2020 22:49:04 +0000 Subject: [PATCH] test: remove FHDLTestCase.assertRaisesRegex. This method is only there because I misunderstood the documentation of unittest. --- nmigen/test/test_hdl_ast.py | 6 +++--- nmigen/test/test_sim.py | 6 +++--- nmigen/test/utils.py | 8 -------- 3 files changed, 6 insertions(+), 14 deletions(-) diff --git a/nmigen/test/test_hdl_ast.py b/nmigen/test/test_hdl_ast.py index 4946c3e..b724ad6 100644 --- a/nmigen/test/test_hdl_ast.py +++ b/nmigen/test/test_hdl_ast.py @@ -764,13 +764,13 @@ class ArrayTestCase(FHDLTestCase): v1 = a[s1] v2 = a[s2] with self.assertRaisesRegex(ValueError, - regex=r"^Array can no longer be mutated after it was indexed with a value at "): + r"^Array can no longer be mutated after it was indexed with a value at "): a[1] = 2 with self.assertRaisesRegex(ValueError, - regex=r"^Array can no longer be mutated after it was indexed with a value at "): + r"^Array can no longer be mutated after it was indexed with a value at "): del a[1] with self.assertRaisesRegex(ValueError, - regex=r"^Array can no longer be mutated after it was indexed with a value at "): + r"^Array can no longer be mutated after it was indexed with a value at "): a.insert(1, 2) def test_repr(self): diff --git a/nmigen/test/test_sim.py b/nmigen/test/test_sim.py index a3a6913..8f48207 100644 --- a/nmigen/test/test_sim.py +++ b/nmigen/test/test_sim.py @@ -582,7 +582,7 @@ class SimulatorIntegrationTestCase(FHDLTestCase): def process(): nonlocal survived with self.assertRaisesRegex(TypeError, - regex=r"Received unsupported command 1 from process .+?"): + r"Received unsupported command 1 from process .+?"): yield 1 yield Settle() survived = True @@ -774,7 +774,7 @@ class SimulatorIntegrationTestCase(FHDLTestCase): sim.add_clock(1e-6) sim.run_until(1e-5) with self.assertRaisesRegex(ValueError, - regex=r"^Cannot start writing waveforms after advancing simulation time$"): + r"^Cannot start writing waveforms after advancing simulation time$"): with sim.write_vcd(open(os.path.devnull, "wt")): pass @@ -785,7 +785,7 @@ class SimulatorIntegrationTestCase(FHDLTestCase): sim = Simulator(m) sim.add_clock(1e-6) with self.assertRaisesRegex(ValueError, - regex=r"^Already writing waveforms to .+$"): + r"^Already writing waveforms to .+$"): with sim.write_vcd(open(os.path.devnull, "wt")): with sim.write_vcd(open(os.path.devnull, "wt")): pass diff --git a/nmigen/test/utils.py b/nmigen/test/utils.py index c3907ce..d8a168c 100644 --- a/nmigen/test/utils.py +++ b/nmigen/test/utils.py @@ -36,14 +36,6 @@ class FHDLTestCase(unittest.TestCase): # WTF? unittest.assertRaises is completely broken. self.assertEqual(str(cm.exception), msg) - @contextmanager - def assertRaisesRegex(self, exception, regex=None): - with super().assertRaises(exception) as cm: - yield - if regex is not None: - # unittest.assertRaisesRegex also seems broken... - self.assertRegex(str(cm.exception), regex) - @contextmanager def assertWarns(self, category, msg=None): with warnings.catch_warnings(record=True) as warns: -- 2.30.2