From fd60a396ad21f8a18e51c7d630b0200a0dcb3da1 Mon Sep 17 00:00:00 2001 From: Tobias Platen Date: Thu, 20 Aug 2020 19:34:32 +0200 Subject: [PATCH] add new class TestCachedMemoryPortInterface --- src/soc/experiment/pimem.py | 40 +++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/src/soc/experiment/pimem.py b/src/soc/experiment/pimem.py index 6361f456..8f9f0df9 100644 --- a/src/soc/experiment/pimem.py +++ b/src/soc/experiment/pimem.py @@ -338,3 +338,43 @@ class TestMemoryPortInterface(PortInterfaceBase): def ports(self): yield from super().ports() # TODO: memory ports + +class TestCachedMemoryPortInterface(PortInterfaceBase): + """TestCacheMemoryPortInterface + + This is a test class for simple verification of LDSTSplitter + conforming to PortInterface, + """ + + def __init__(self, regwid=64, addrwid=4): + super().__init__(regwid, addrwid) + # hard-code memory addressing width to 6 bits + self.mem = None + + def set_wr_addr(self, m, addr, mask): + lsbaddr, msbaddr = self.splitaddr(addr) + m.d.comb += self.mem.wrport.addr.eq(msbaddr) + + def set_rd_addr(self, m, addr, mask): + lsbaddr, msbaddr = self.splitaddr(addr) + m.d.comb += self.mem.rdport.addr.eq(msbaddr) + + def set_wr_data(self, m, data, wen): + m.d.comb += self.mem.wrport.data.eq(data) # write st to mem + m.d.comb += self.mem.wrport.en.eq(wen) # enable writes + return Const(1, 1) + + def get_rd_data(self, m): + return self.mem.rdport.data, Const(1, 1) + + def elaborate(self, platform): + m = super().elaborate(platform) + + # add TestMemory as submodule + m.submodules.mem = self.mem + + return m + + def ports(self): + yield from super().ports() + # TODO: memory ports -- 2.30.2