From fd8758366bce3cf764ef47c2aa5ddf461875b4c9 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Nicolai=20H=C3=A4hnle?= Date: Tue, 19 Jun 2018 17:44:24 +0200 Subject: [PATCH] radeonsi/gfx10: set llvm_has_working_vgpr_indexing Acked-by: Bas Nieuwenhuizen --- src/gallium/drivers/radeonsi/si_pipe.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index 9ea08c8fb26..7eaa400849e 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -1140,10 +1140,9 @@ radeonsi_screen_create_impl(struct radeon_winsys *ws, } /* While it would be nice not to have this flag, we are constrained - * by the reality that LLVM 5.0 doesn't have working VGPR indexing - * on GFX9. + * by the reality that LLVM 9.0 has buggy VGPR indexing on GFX9. */ - sscreen->llvm_has_working_vgpr_indexing = sscreen->info.chip_class <= GFX8; + sscreen->llvm_has_working_vgpr_indexing = sscreen->info.chip_class != GFX9; /* Some chips have RB+ registers, but don't support RB+. Those must * always disable it. -- 2.30.2