From fd9408e1317c07aa0f9898024ea3a94f1390a748 Mon Sep 17 00:00:00 2001 From: whitequark Date: Wed, 12 Dec 2018 09:49:02 +0000 Subject: [PATCH] =?utf8?q?ClockDomain.{rst=E2=86=92reset},=20for=20consist?= =?utf8?q?ency=20with=20ResetInserter.?= MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit nmigen.compat.ClockDomain would alias this, for Migen compatibility. --- examples/arst.py | 4 ++-- nmigen/back/rtlil.py | 2 +- nmigen/fhdl/cd.py | 6 +++--- nmigen/fhdl/ir.py | 2 +- 4 files changed, 7 insertions(+), 7 deletions(-) diff --git a/examples/arst.py b/examples/arst.py index 73d90fa..c8fa8c7 100644 --- a/examples/arst.py +++ b/examples/arst.py @@ -17,5 +17,5 @@ class ClockDivisor: sys = ClockDomain(async_reset=True) ctr = ClockDivisor(factor=16) frag = ctr.get_fragment(platform=None) -# print(rtlil.convert(frag, ports=[sys.clk, sys.rst, ctr.o], clock_domains={"sys": sys})) -print(verilog.convert(frag, ports=[sys.clk, sys.rst, ctr.o], clock_domains={"sys": sys})) +# print(rtlil.convert(frag, ports=[sys.clk, sys.reset, ctr.o], clock_domains={"sys": sys})) +print(verilog.convert(frag, ports=[sys.clk, sys.reset, ctr.o], clock_domains={"sys": sys})) diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py index 5d6f7d9..6fe5788 100644 --- a/nmigen/back/rtlil.py +++ b/nmigen/back/rtlil.py @@ -445,7 +445,7 @@ def convert_fragment(builder, fragment, name, clock_domains): cd = clock_domains[cd_name] triggers.append(("posedge", xformer(cd.clk))) if cd.async_reset: - triggers.append(("posedge", xformer(cd.rst))) + triggers.append(("posedge", xformer(cd.reset))) for trigger in triggers: with process.sync(*trigger) as sync: diff --git a/nmigen/fhdl/cd.py b/nmigen/fhdl/cd.py index 5e21220..280292f 100644 --- a/nmigen/fhdl/cd.py +++ b/nmigen/fhdl/cd.py @@ -27,7 +27,7 @@ class ClockDomain: clk : Signal, inout The clock for this domain. Can be driven or used to drive other signals (preferably in combinatorial context). - rst : Signal or None, inout + reset : Signal or None, inout Reset signal for this domain. Can be driven or used to drive. """ def __init__(self, name=None, reset_less=False, async_reset=False): @@ -41,8 +41,8 @@ class ClockDomain: self.clk = Signal(name=self.name + "_clk") if reset_less: - self.rst = None + self.reset = None else: - self.rst = Signal(name=self.name + "_rst") + self.reset = Signal(name=self.name + "_reset") self.async_reset = async_reset diff --git a/nmigen/fhdl/ir.py b/nmigen/fhdl/ir.py index 5a00cc4..eeeace1 100644 --- a/nmigen/fhdl/ir.py +++ b/nmigen/fhdl/ir.py @@ -53,7 +53,7 @@ class Fragment: def prepare(self, ports, clock_domains): from .xfrm import ResetInserter - resets = {cd.name: cd.rst for cd in clock_domains.values() if cd.rst is not None} + resets = {cd.name: cd.reset for cd in clock_domains.values() if cd.reset is not None} frag = ResetInserter(resets)(self) self_driven = union(s._lhs_signals() for s in self.statements) -- 2.30.2