From fda338f8d3ba6f6cb271e2c10cb880ff064edb61 Mon Sep 17 00:00:00 2001
From: Andreas Hansson <andreas.hansson@arm.com>
Date: Mon, 9 Jul 2012 12:35:41 -0400
Subject: [PATCH] Stats: Updates due to bus changes

This patch bumps all the stats to reflect the bus changes, i.e. the
introduction of the state variable, the division into a request and
response layer, and the new default bus width of 8 bytes.
---
 .../alpha/linux/tsunami-o3-dual/config.ini    |    6 +-
 .../ref/alpha/linux/tsunami-o3-dual/simout    |    8 +-
 .../ref/alpha/linux/tsunami-o3-dual/stats.txt | 3016 ++++++-------
 .../ref/alpha/linux/tsunami-o3/config.ini     |    6 +-
 .../ref/alpha/linux/tsunami-o3/simout         |    6 +-
 .../ref/alpha/linux/tsunami-o3/stats.txt      | 1514 +++----
 .../arm/linux/realview-o3-checker/config.ini  |    8 +-
 .../ref/arm/linux/realview-o3-checker/simerr  |   28 +-
 .../ref/arm/linux/realview-o3-checker/simout  |    6 +-
 .../arm/linux/realview-o3-checker/stats.txt   | 1598 ++++---
 .../ref/arm/linux/realview-o3-dual/config.ini |    8 +-
 .../ref/arm/linux/realview-o3-dual/simerr     |    1 -
 .../ref/arm/linux/realview-o3-dual/simout     |    6 +-
 .../ref/arm/linux/realview-o3-dual/stats.txt  | 2964 +++++++------
 .../ref/arm/linux/realview-o3/config.ini      |    8 +-
 .../ref/arm/linux/realview-o3/simout          |    6 +-
 .../ref/arm/linux/realview-o3/stats.txt       | 1568 ++++---
 .../ref/x86/linux/pc-o3-timing/config.ini     |    6 +-
 .../ref/x86/linux/pc-o3-timing/simout         |    6 +-
 .../ref/x86/linux/pc-o3-timing/stats.txt      | 1782 ++++----
 .../config.ini                                |    2 +-
 .../simout                                    |    9 +-
 .../stats.txt                                 |  192 +-
 .../ref/alpha/tru64/inorder-timing/config.ini |    4 +-
 .../ref/alpha/tru64/inorder-timing/simout     |    6 +-
 .../ref/alpha/tru64/inorder-timing/stats.txt  |  554 +--
 .../ref/alpha/tru64/o3-timing/config.ini      |    4 +-
 .../00.gzip/ref/alpha/tru64/o3-timing/simout  |    6 +-
 .../ref/alpha/tru64/o3-timing/stats.txt       | 1138 ++---
 .../ref/alpha/tru64/simple-timing/config.ini  |    4 +-
 .../ref/alpha/tru64/simple-timing/simout      |    6 +-
 .../ref/alpha/tru64/simple-timing/stats.txt   |  188 +-
 .../ref/arm/linux/o3-timing/config.ini        |    4 +-
 .../se/00.gzip/ref/arm/linux/o3-timing/simout |    6 +-
 .../00.gzip/ref/arm/linux/o3-timing/stats.txt | 1112 ++---
 .../ref/arm/linux/simple-timing/config.ini    |    4 +-
 .../ref/arm/linux/simple-timing/simout        |    6 +-
 .../ref/arm/linux/simple-timing/stats.txt     |  186 +-
 .../ref/sparc/linux/o3-timing/config.ini      |    4 +-
 .../00.gzip/ref/sparc/linux/o3-timing/simout  |    6 +-
 .../ref/sparc/linux/o3-timing/stats.txt       | 1018 ++---
 .../ref/sparc/linux/simple-timing/config.ini  |    4 +-
 .../ref/sparc/linux/simple-timing/simout      |    6 +-
 .../ref/sparc/linux/simple-timing/stats.txt   |  188 +-
 .../ref/x86/linux/o3-timing/config.ini        |    4 +-
 .../se/00.gzip/ref/x86/linux/o3-timing/simout |    7 +-
 .../00.gzip/ref/x86/linux/o3-timing/stats.txt |  986 ++---
 .../ref/x86/linux/simple-timing/config.ini    |    4 +-
 .../ref/x86/linux/simple-timing/simout        |    6 +-
 .../ref/x86/linux/simple-timing/stats.txt     |  186 +-
 .../10.mcf/ref/arm/linux/o3-timing/config.ini |    4 +-
 .../se/10.mcf/ref/arm/linux/o3-timing/simout  |    6 +-
 .../10.mcf/ref/arm/linux/o3-timing/stats.txt  | 1144 ++---
 .../ref/arm/linux/simple-timing/config.ini    |    4 +-
 .../10.mcf/ref/arm/linux/simple-timing/simout |    6 +-
 .../ref/arm/linux/simple-timing/stats.txt     |  180 +-
 .../ref/sparc/linux/simple-timing/config.ini  |    4 +-
 .../ref/sparc/linux/simple-timing/simout      |    6 +-
 .../ref/sparc/linux/simple-timing/stats.txt   |  194 +-
 .../10.mcf/ref/x86/linux/o3-timing/config.ini |    4 +-
 .../se/10.mcf/ref/x86/linux/o3-timing/simout  |    9 +-
 .../10.mcf/ref/x86/linux/o3-timing/stats.txt  | 1100 ++---
 .../ref/x86/linux/simple-timing/config.ini    |    4 +-
 .../10.mcf/ref/x86/linux/simple-timing/simout |    6 +-
 .../ref/x86/linux/simple-timing/stats.txt     |  182 +-
 .../ref/arm/linux/o3-timing/config.ini        |    4 +-
 .../20.parser/ref/arm/linux/o3-timing/simerr  |    1 -
 .../20.parser/ref/arm/linux/o3-timing/simout  |    6 +-
 .../ref/arm/linux/o3-timing/stats.txt         | 1150 ++---
 .../ref/arm/linux/simple-timing/config.ini    |    4 +-
 .../ref/arm/linux/simple-timing/simout        |    6 +-
 .../ref/arm/linux/simple-timing/stats.txt     |  190 +-
 .../ref/x86/linux/o3-timing/config.ini        |    4 +-
 .../20.parser/ref/x86/linux/o3-timing/simout  |   10 +-
 .../ref/x86/linux/o3-timing/stats.txt         | 1142 ++---
 .../ref/x86/linux/simple-timing/config.ini    |    4 +-
 .../ref/x86/linux/simple-timing/simout        |    6 +-
 .../ref/x86/linux/simple-timing/stats.txt     |  188 +-
 .../ref/alpha/tru64/inorder-timing/config.ini |    4 +-
 .../ref/alpha/tru64/inorder-timing/simout     |    6 +-
 .../ref/alpha/tru64/inorder-timing/stats.txt  |  564 +--
 .../ref/alpha/tru64/o3-timing/config.ini      |    4 +-
 .../30.eon/ref/alpha/tru64/o3-timing/simout   |    6 +-
 .../ref/alpha/tru64/o3-timing/stats.txt       | 1024 ++---
 .../ref/alpha/tru64/simple-timing/config.ini  |    4 +-
 .../ref/alpha/tru64/simple-timing/simout      |    6 +-
 .../ref/alpha/tru64/simple-timing/stats.txt   |  176 +-
 .../30.eon/ref/arm/linux/o3-timing/config.ini |    4 +-
 .../se/30.eon/ref/arm/linux/o3-timing/simout  |    6 +-
 .../30.eon/ref/arm/linux/o3-timing/stats.txt  | 1040 +++--
 .../ref/arm/linux/simple-timing/config.ini    |    4 +-
 .../30.eon/ref/arm/linux/simple-timing/simout |    6 +-
 .../ref/arm/linux/simple-timing/stats.txt     |  176 +-
 .../ref/alpha/tru64/o3-timing/config.ini      |    4 +-
 .../ref/alpha/tru64/o3-timing/simout          |    6 +-
 .../ref/alpha/tru64/o3-timing/stats.txt       | 1132 +++--
 .../ref/alpha/tru64/simple-timing/config.ini  |    4 +-
 .../ref/alpha/tru64/simple-timing/simout      |    6 +-
 .../ref/alpha/tru64/simple-timing/stats.txt   |  186 +-
 .../ref/arm/linux/o3-timing/config.ini        |    4 +-
 .../40.perlbmk/ref/arm/linux/o3-timing/simout |    6 +-
 .../ref/arm/linux/o3-timing/stats.txt         | 1218 +++---
 .../ref/arm/linux/simple-timing/config.ini    |    4 +-
 .../ref/arm/linux/simple-timing/simout        |    6 +-
 .../ref/arm/linux/simple-timing/stats.txt     |  184 +-
 .../ref/alpha/tru64/inorder-timing/config.ini |    4 +-
 .../ref/alpha/tru64/inorder-timing/simout     |    6 +-
 .../ref/alpha/tru64/inorder-timing/stats.txt  |  692 +--
 .../ref/alpha/tru64/o3-timing/config.ini      |    4 +-
 .../ref/alpha/tru64/o3-timing/simout          |    6 +-
 .../ref/alpha/tru64/o3-timing/stats.txt       | 1090 ++---
 .../ref/alpha/tru64/simple-timing/config.ini  |    4 +-
 .../ref/alpha/tru64/simple-timing/simout      |    6 +-
 .../ref/alpha/tru64/simple-timing/stats.txt   |  188 +-
 .../ref/arm/linux/o3-timing/config.ini        |    4 +-
 .../50.vortex/ref/arm/linux/o3-timing/simout  |    6 +-
 .../ref/arm/linux/o3-timing/stats.txt         | 1150 ++---
 .../ref/arm/linux/simple-timing/config.ini    |    4 +-
 .../ref/arm/linux/simple-timing/simout        |    6 +-
 .../ref/arm/linux/simple-timing/stats.txt     |  188 +-
 .../ref/sparc/linux/simple-timing/config.ini  |    4 +-
 .../ref/sparc/linux/simple-timing/simout      |    6 +-
 .../ref/sparc/linux/simple-timing/stats.txt   |  206 +-
 .../ref/alpha/tru64/inorder-timing/config.ini |    4 +-
 .../ref/alpha/tru64/inorder-timing/simout     |    6 +-
 .../ref/alpha/tru64/inorder-timing/stats.txt  |  668 +--
 .../ref/alpha/tru64/o3-timing/config.ini      |    4 +-
 .../60.bzip2/ref/alpha/tru64/o3-timing/simout |    6 +-
 .../ref/alpha/tru64/o3-timing/stats.txt       | 1130 ++---
 .../ref/alpha/tru64/simple-timing/config.ini  |    4 +-
 .../ref/alpha/tru64/simple-timing/simout      |    6 +-
 .../ref/alpha/tru64/simple-timing/stats.txt   |  184 +-
 .../ref/arm/linux/o3-timing/config.ini        |    4 +-
 .../60.bzip2/ref/arm/linux/o3-timing/simout   |    6 +-
 .../ref/arm/linux/o3-timing/stats.txt         | 1172 ++---
 .../ref/arm/linux/simple-timing/config.ini    |    4 +-
 .../ref/arm/linux/simple-timing/simout        |    6 +-
 .../ref/arm/linux/simple-timing/stats.txt     |  190 +-
 .../ref/x86/linux/simple-timing/config.ini    |    4 +-
 .../ref/x86/linux/simple-timing/simout        |    6 +-
 .../ref/x86/linux/simple-timing/stats.txt     |  172 +-
 .../ref/alpha/tru64/inorder-timing/config.ini |    4 +-
 .../ref/alpha/tru64/inorder-timing/simout     |    8 +-
 .../ref/alpha/tru64/inorder-timing/stats.txt  |  590 +--
 .../ref/alpha/tru64/o3-timing/config.ini      |    4 +-
 .../70.twolf/ref/alpha/tru64/o3-timing/simout |    8 +-
 .../ref/alpha/tru64/o3-timing/stats.txt       | 1052 ++---
 .../ref/alpha/tru64/simple-timing/config.ini  |    4 +-
 .../ref/alpha/tru64/simple-timing/simout      |    8 +-
 .../ref/alpha/tru64/simple-timing/stats.txt   |  160 +-
 .../ref/arm/linux/o3-timing/config.ini        |    4 +-
 .../70.twolf/ref/arm/linux/o3-timing/simout   |    8 +-
 .../ref/arm/linux/o3-timing/stats.txt         | 1158 +++--
 .../ref/arm/linux/simple-timing/config.ini    |    4 +-
 .../ref/arm/linux/simple-timing/simout        |    8 +-
 .../ref/arm/linux/simple-timing/stats.txt     |  110 +-
 .../ref/sparc/linux/simple-timing/config.ini  |    6 +-
 .../ref/sparc/linux/simple-timing/simout      |   12 +-
 .../ref/sparc/linux/simple-timing/stats.txt   |   64 +-
 .../ref/x86/linux/o3-timing/config.ini        |    4 +-
 .../70.twolf/ref/x86/linux/o3-timing/simout   |    8 +-
 .../ref/x86/linux/o3-timing/stats.txt         |  988 ++---
 .../ref/x86/linux/simple-timing/config.ini    |    4 +-
 .../ref/x86/linux/simple-timing/simout        |    8 +-
 .../ref/x86/linux/simple-timing/stats.txt     |  156 +-
 .../tsunami-simple-timing-dual/config.ini     |    6 +-
 .../linux/tsunami-simple-timing-dual/simout   |    8 +-
 .../tsunami-simple-timing-dual/stats.txt      | 2032 ++++-----
 .../linux/tsunami-simple-timing/config.ini    |    6 +-
 .../alpha/linux/tsunami-simple-timing/simout  |    6 +-
 .../linux/tsunami-simple-timing/stats.txt     |  976 ++---
 .../realview-simple-timing-dual/config.ini    |    8 +-
 .../linux/realview-simple-timing-dual/simout  |    6 +-
 .../realview-simple-timing-dual/stats.txt     | 1728 ++++----
 .../linux/realview-simple-timing/config.ini   |    8 +-
 .../arm/linux/realview-simple-timing/simout   |    6 +-
 .../linux/realview-simple-timing/stats.txt    |  936 ++--
 .../ref/x86/linux/pc-simple-timing/config.ini |    6 +-
 .../ref/x86/linux/pc-simple-timing/simout     |    6 +-
 .../ref/x86/linux/pc-simple-timing/stats.txt  | 1146 ++---
 .../ref/alpha/linux/inorder-timing/config.ini |    4 +-
 .../ref/alpha/linux/inorder-timing/simout     |    8 +-
 .../ref/alpha/linux/inorder-timing/stats.txt  |  444 +-
 .../ref/alpha/linux/o3-timing/config.ini      |    4 +-
 .../00.hello/ref/alpha/linux/o3-timing/simout |    6 +-
 .../ref/alpha/linux/o3-timing/stats.txt       |  990 ++---
 .../ref/alpha/linux/simple-timing/config.ini  |    4 +-
 .../ref/alpha/linux/simple-timing/simout      |    8 +-
 .../ref/alpha/linux/simple-timing/stats.txt   |   64 +-
 .../ref/alpha/tru64/o3-timing/config.ini      |    4 +-
 .../00.hello/ref/alpha/tru64/o3-timing/simout |    6 +-
 .../ref/alpha/tru64/o3-timing/stats.txt       |  842 ++--
 .../ref/alpha/tru64/simple-timing/config.ini  |    4 +-
 .../ref/alpha/tru64/simple-timing/simout      |    8 +-
 .../ref/alpha/tru64/simple-timing/stats.txt   |   60 +-
 .../arm/linux/o3-timing-checker/config.ini    |    4 +-
 .../ref/arm/linux/o3-timing-checker/simout    |    6 +-
 .../ref/arm/linux/o3-timing-checker/stats.txt |  943 ++--
 .../ref/arm/linux/o3-timing/config.ini        |    4 +-
 .../00.hello/ref/arm/linux/o3-timing/simout   |    6 +-
 .../ref/arm/linux/o3-timing/stats.txt         |  943 ++--
 .../ref/arm/linux/simple-timing/config.ini    |    4 +-
 .../ref/arm/linux/simple-timing/simout        |    6 +-
 .../ref/arm/linux/simple-timing/stats.txt     |   62 +-
 .../ref/mips/linux/inorder-timing/config.ini  |    4 +-
 .../ref/mips/linux/inorder-timing/simout      |    8 +-
 .../ref/mips/linux/inorder-timing/stats.txt   |  460 +-
 .../ref/mips/linux/o3-timing/config.ini       |    4 +-
 .../00.hello/ref/mips/linux/o3-timing/simout  |    6 +-
 .../ref/mips/linux/o3-timing/stats.txt        |  904 ++--
 .../ref/mips/linux/simple-timing/config.ini   |    4 +-
 .../ref/mips/linux/simple-timing/simout       |    8 +-
 .../ref/mips/linux/simple-timing/stats.txt    |   64 +-
 .../ref/power/linux/o3-timing/config.ini      |    4 +-
 .../00.hello/ref/power/linux/o3-timing/simout |    6 +-
 .../ref/power/linux/o3-timing/stats.txt       |  952 ++--
 .../ref/sparc/linux/inorder-timing/config.ini |    4 +-
 .../ref/sparc/linux/inorder-timing/simout     |    8 +-
 .../ref/sparc/linux/inorder-timing/stats.txt  |  462 +-
 .../ref/sparc/linux/simple-timing/config.ini  |    4 +-
 .../ref/sparc/linux/simple-timing/simout      |    8 +-
 .../ref/sparc/linux/simple-timing/stats.txt   |   64 +-
 .../ref/x86/linux/o3-timing/config.ini        |    4 +-
 .../00.hello/ref/x86/linux/o3-timing/simout   |    8 +-
 .../ref/x86/linux/o3-timing/stats.txt         |  942 ++--
 .../ref/x86/linux/simple-timing/config.ini    |    4 +-
 .../ref/x86/linux/simple-timing/simout        |    8 +-
 .../ref/x86/linux/simple-timing/stats.txt     |   64 +-
 .../ref/alpha/linux/o3-timing/config.ini      |    4 +-
 .../ref/alpha/linux/o3-timing/simout          |    6 +-
 .../ref/alpha/linux/o3-timing/stats.txt       | 1221 +++---
 .../ref/sparc/linux/inorder-timing/config.ini |    4 +-
 .../ref/sparc/linux/inorder-timing/simout     |    8 +-
 .../ref/sparc/linux/inorder-timing/stats.txt  |  454 +-
 .../ref/sparc/linux/o3-timing/config.ini      |    4 +-
 .../ref/sparc/linux/o3-timing/simout          |    6 +-
 .../ref/sparc/linux/o3-timing/stats.txt       |  916 ++--
 .../ref/sparc/linux/simple-timing/config.ini  |    4 +-
 .../ref/sparc/linux/simple-timing/simout      |    8 +-
 .../ref/sparc/linux/simple-timing/stats.txt   |   64 +-
 .../ref/sparc/linux/o3-timing-mp/config.ini   |    4 +-
 .../ref/sparc/linux/o3-timing-mp/simout       |   76 +-
 .../ref/sparc/linux/o3-timing-mp/stats.txt    | 3860 ++++++++---------
 .../sparc/linux/simple-timing-mp/config.ini   |    4 +-
 .../ref/sparc/linux/simple-timing-mp/simout   |   84 +-
 .../sparc/linux/simple-timing-mp/stats.txt    | 1823 ++++----
 .../50.memtest/ref/alpha/linux/memtest/simerr |  146 +-
 .../50.memtest/ref/alpha/linux/memtest/simout |    6 +-
 .../ref/alpha/linux/memtest/stats.txt         | 2859 ++++++------
 249 files changed, 34082 insertions(+), 34090 deletions(-)

diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
index bf1bde417..1c28eff64 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
@@ -941,7 +941,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=true
-width=64
+width=8
 default=system.tsunami.pciconfig.pio
 master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
 slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
@@ -1003,7 +1003,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 default=system.membus.badaddr_responder.pio
 master=system.bridge.slave system.physmem.port[0]
 slave=system.system_port system.iocache.mem_side system.l2c.mem_side
@@ -1060,7 +1060,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.l2c.cpu_side
 slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side
 
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
index 94dc81bdc..11f244941 100755
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:05:18
-gem5 started Jun 28 2012 22:47:55
+gem5 compiled Jul  2 2012 08:30:56
+gem5 started Jul  2 2012 11:07:21
 gem5 executing on zizzer
 command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/vmlinux
 info: Entering event queue @ 0.  Starting simulation...
-info: Launching CPU 1 @ 106801000
-Exiting @ tick 1896395899500 because m5_exit instruction encountered
+info: Launching CPU 1 @ 112168000
+Exiting @ tick 1900530800500 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
index 0c462a770..3f76d2026 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
@@ -1,218 +1,218 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.896396                       # Number of seconds simulated
-sim_ticks                                1896395899500                       # Number of ticks simulated
-final_tick                               1896395899500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.900531                       # Number of seconds simulated
+sim_ticks                                1900530800500                       # Number of ticks simulated
+final_tick                               1900530800500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 196112                       # Simulator instruction rate (inst/s)
-host_op_rate                                   196112                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             6628227410                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 302056                       # Number of bytes of host memory used
-host_seconds                                   286.11                       # Real time elapsed on the host
-sim_insts                                    56109524                       # Number of instructions simulated
-sim_ops                                      56109524                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu0.inst           881728                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         24808704                       # Number of bytes read from this memory
-system.physmem.bytes_read::tsunami.ide        2650688                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst            99648                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data           472640                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             28913408                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       881728                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst        99648                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          981376                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7865856                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7865856                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst             13777                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            387636                       # Number of read requests responded to by this memory
-system.physmem.num_reads::tsunami.ide           41417                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              1557                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data              7385                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                451772                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          122904                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               122904                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst              464949                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            13082028                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide           1397750                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               52546                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              249231                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                15246504                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         464949                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          52546                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             517495                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           4147792                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4147792                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           4147792                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             464949                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           13082028                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide          1397750                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              52546                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             249231                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               19394296                       # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements                        344859                       # number of replacements
-system.l2c.tagsinuse                     65321.127934                       # Cycle average of tags in use
-system.l2c.total_refs                         2609636                       # Total number of references to valid blocks.
-system.l2c.sampled_refs                        410035                       # Sample count of references to valid blocks.
-system.l2c.avg_refs                          6.364423                       # Average number of references to valid blocks.
-system.l2c.warmup_cycle                    6312493000                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks        53767.491128                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst          5338.607060                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data          6047.920982                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.inst           140.590955                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.data            26.517809                       # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks           0.820427                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.inst            0.081461                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.data            0.092284                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.inst            0.002145                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.data            0.000405                       # Average percentage of cache occupancy
-system.l2c.occ_percent::total                0.996721                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0.inst             978177                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             784326                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             102747                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data              33274                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1898524                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          832872                       # number of Writeback hits
-system.l2c.Writeback_hits::total               832872                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data             159                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data              41                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                 200                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data            29                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data            22                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                51                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           175658                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data             7994                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               183652                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.inst              978177                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              959984                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              102747                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data               41268                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2082176                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst             978177                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             959984                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             102747                       # number of overall hits
-system.l2c.overall_hits::cpu1.data              41268                       # number of overall hits
-system.l2c.overall_hits::total                2082176                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.inst            13779                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data           273160                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst             1574                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data              765                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total               289278                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data          2448                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data           557                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              3005                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data           42                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data           80                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total             122                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data         114897                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data           6716                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             121613                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.inst             13779                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            388057                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              1574                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data              7481                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                410891                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst            13779                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           388057                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             1574                       # number of overall misses
-system.l2c.overall_misses::cpu1.data             7481                       # number of overall misses
-system.l2c.overall_misses::total               410891                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.inst    720793500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data  14208419500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst     82364000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data     41213000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total    15052790000                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0.data      2256000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data      1409000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total      3665000                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data       419000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data       157000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total       576000                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data   6027292500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data    352112000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   6379404500                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.inst    720793500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data  20235712000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst     82364000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data    393325000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total     21432194500                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.inst    720793500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data  20235712000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst     82364000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data    393325000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    21432194500                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.inst         991956                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data        1057486                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst         104321                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data          34039                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2187802                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       832872                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           832872                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data         2607                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data          598                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            3205                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data           71                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data          102                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total           173                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       290555                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data        14710                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           305265                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst          991956                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data         1348041                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          104321                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data           48749                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2493067                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         991956                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data        1348041                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         104321                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data          48749                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2493067                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.013891                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.258311                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.015088                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.022474                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.132223                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.939010                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.931438                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.937598                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.591549                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.784314                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.705202                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.395440                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.456560                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.398385                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.013891                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.287867                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.015088                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.153460                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.164813                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.013891                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.287867                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.015088                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.153460                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.164813                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52311.016765                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 52015.007688                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52327.827192                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 53873.202614                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 52035.723422                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   921.568627                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  2529.622980                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  1219.633943                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  9976.190476                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  1962.500000                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  4721.311475                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52458.223452                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52428.826683                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 52456.600035                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 52311.016765                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 52146.236249                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 52327.827192                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 52576.527202                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 52160.291902                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 52311.016765                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 52146.236249                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 52327.827192                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 52576.527202                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 52160.291902                       # average overall miss latency
+host_inst_rate                                 119697                       # Simulator instruction rate (inst/s)
+host_op_rate                                   119697                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             3968630665                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 303044                       # Number of bytes of host memory used
+host_seconds                                   478.89                       # Real time elapsed on the host
+sim_insts                                    57321719                       # Number of instructions simulated
+sim_ops                                      57321719                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu0.inst           875648                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         24657536                       # Number of bytes read from this memory
+system.physmem.bytes_read::tsunami.ide        2650816                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           107456                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data           693056                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             28984512                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       875648                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       107456                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          983104                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7921792                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7921792                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst             13682                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            385274                       # Number of read requests responded to by this memory
+system.physmem.num_reads::tsunami.ide           41419                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              1679                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             10829                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                452883                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          123778                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               123778                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst              460739                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data            12974026                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide           1394777                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               56540                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              364664                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                15250746                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         460739                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          56540                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             517279                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           4168200                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                4168200                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           4168200                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             460739                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           12974026                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide          1394777                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              56540                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             364664                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               19418945                       # Total bandwidth to/from this memory (bytes/s)
+system.l2c.replacements                        345959                       # number of replacements
+system.l2c.tagsinuse                     65264.030293                       # Cycle average of tags in use
+system.l2c.total_refs                         2564962                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                        411131                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                          6.238795                       # Average number of references to valid blocks.
+system.l2c.warmup_cycle                    6370050000                       # Cycle when the warmup percentage was hit.
+system.l2c.occ_blocks::writebacks        53566.099176                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst          5313.179425                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data          6099.564968                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst           209.813021                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.data            75.373703                       # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks           0.817354                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.inst            0.081073                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.data            0.093072                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.inst            0.003201                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.data            0.001150                       # Average percentage of cache occupancy
+system.l2c.occ_percent::total                0.995850                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu0.inst             777532                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data             689515                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst             314287                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data             100987                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1882321                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          806312                       # number of Writeback hits
+system.l2c.Writeback_hits::total               806312                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data             176                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data             440                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                 616                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data            51                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data            30                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total                81                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data           128023                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            44351                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               172374                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.inst              777532                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              817538                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              314287                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              145338                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 2054695                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.inst             777532                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             817538                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             314287                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             145338                       # number of overall hits
+system.l2c.overall_hits::total                2054695                       # number of overall hits
+system.l2c.ReadReq_misses::cpu0.inst            13684                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data           272967                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst             1696                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data              861                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total               289208                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data          2867                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data          1568                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              4435                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data          726                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data          747                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total            1473                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data         113091                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data          10063                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             123154                       # number of ReadExReq misses
+system.l2c.demand_misses::cpu0.inst             13684                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data            386058                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst              1696                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data             10924                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                412362                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.inst            13684                       # number of overall misses
+system.l2c.overall_misses::cpu0.data           386058                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst             1696                       # number of overall misses
+system.l2c.overall_misses::cpu1.data            10924                       # number of overall misses
+system.l2c.overall_misses::total               412362                       # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu0.inst    728665998                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.data  14214168999                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst     90803000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data     47077499                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total    15080715496                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu0.data      2584000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data     19661414                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total     22245414                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data      2793000                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data       314000                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total      3107000                       # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data   6061091997                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data    549004499                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   6610096496                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu0.inst    728665998                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data  20275260996                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst     90803000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data    596081998                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total     21690811992                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.inst    728665998                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data  20275260996                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst     90803000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data    596081998                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total    21690811992                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.inst         791216                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data         962482                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst         315983                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data         101848                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            2171529                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       806312                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           806312                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data         3043                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data         2008                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            5051                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data          777                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data          777                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total          1554                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       241114                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data        54414                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           295528                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.inst          791216                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data         1203596                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          315983                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data          156262                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             2467057                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         791216                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data        1203596                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         315983                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data         156262                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            2467057                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.017295                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.283607                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.005367                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data      0.008454                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.133182                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.942162                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.780876                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.878044                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.934363                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.961390                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.947876                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.469035                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.184934                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.416725                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.017295                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.320754                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.005367                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.069908                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.167147                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.017295                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.320754                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.005367                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.069908                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.167147                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53249.488308                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.data 52072.847630                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 53539.504717                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 54677.699187                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 52144.876684                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   901.290548                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 12539.167092                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  5015.876888                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  3847.107438                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data   420.348059                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total  2109.300747                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 53594.821843                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 54556.742423                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 53673.421050                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 53249.488308                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 52518.691482                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 53539.504717                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 54566.275906                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 52601.384201                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 53249.488308                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 52518.691482                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 53539.504717                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 54566.275906                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 52601.384201                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -221,8 +221,8 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               81384                       # number of writebacks
-system.l2c.writebacks::total                    81384                       # number of writebacks
+system.l2c.writebacks::writebacks               82258                       # number of writebacks
+system.l2c.writebacks::total                    82258                       # number of writebacks
 system.l2c.ReadReq_mshr_hits::cpu0.inst             1                       # number of ReadReq MSHR hits
 system.l2c.ReadReq_mshr_hits::cpu1.inst            17                       # number of ReadReq MSHR hits
 system.l2c.ReadReq_mshr_hits::total                18                       # number of ReadReq MSHR hits
@@ -232,111 +232,111 @@ system.l2c.demand_mshr_hits::total                 18                       # nu
 system.l2c.overall_mshr_hits::cpu0.inst             1                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::cpu1.inst            17                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::total                18                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu0.inst        13778                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.data       273160                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst         1557                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data          765                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total          289260                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data         2448                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data          557                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total         3005                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data           42                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data           80                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total          122                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data       114897                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data         6716                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        121613                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst        13778                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data       388057                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst         1557                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data         7481                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           410873                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst        13778                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data       388057                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst         1557                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data         7481                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          410873                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    552060500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.data  10929358000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst     62432500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data     31914000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total  11575765000                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     97983500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     22281000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total    120264500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      1681500                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      3200000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total      4881500                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   4629799500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    270393000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   4900192500                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst    552060500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data  15559157500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst     62432500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data    302307000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  16475957500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst    552060500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data  15559157500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst     62432500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data    302307000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  16475957500                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data    821481000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data     16663000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total    838144000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   1131946998                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    287746500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   1419693498                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   1953427998                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data    304409500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   2257837498                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.013890                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.258311                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.014925                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.022474                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.132215                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.939010                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.931438                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.937598                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.591549                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.784314                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.705202                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.395440                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.456560                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.398385                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.013890                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.287867                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.014925                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.153460                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.164806                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.013890                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.287867                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.014925                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.153460                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.164806                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40068.260996                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40010.828818                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40097.944766                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 41717.647059                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 40018.547328                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40025.939542                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40001.795332                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40021.464226                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40035.714286                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadReq_mshr_misses::cpu0.inst        13683                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.data       272967                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.inst         1679                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.data          861                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total          289190                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data         2867                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data         1568                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total         4435                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          726                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          747                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total         1473                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data       113091                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data        10063                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        123154                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst        13683                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data       386058                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst         1679                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data        10924                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           412344                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst        13683                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data       386058                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst         1679                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data        10924                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          412344                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    561385998                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.data  10939069000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst     69521500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data     36634000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total  11606610498                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    114796000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     62749500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    177545500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     29087500                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     29880000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total     58967500                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   4695316997                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    427005999                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   5122322996                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst    561385998                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data  15634385997                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst     69521500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data    463639999                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  16728933494                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst    561385998                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data  15634385997                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst     69521500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data    463639999                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  16728933494                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data    820941530                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data     16650000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total    837591530                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   1194248500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    359420000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   1553668500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   2015190030                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data    376070000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   2391260030                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.017294                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.283607                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.005314                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.008454                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.133173                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.942162                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.780876                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.878044                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.934363                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.961390                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.947876                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.469035                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.184934                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.416725                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.017294                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.320754                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.005314                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.069908                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.167140                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.017294                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.320754                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.005314                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.069908                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.167140                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41027.990791                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40074.694011                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 41406.491959                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 42548.199768                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 40134.895736                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40040.460412                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40018.813776                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40032.807215                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40065.426997                       # average SCUpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        40000                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40012.295082                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40295.216585                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40261.018463                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 40293.328016                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40068.260996                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40095.031142                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40097.944766                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40409.971929                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 40099.878795                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40068.260996                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40095.031142                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40097.944766                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40409.971929                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 40099.878795                       # average overall mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40032.247115                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41518.042965                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 42433.270297                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 41592.826835                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41027.990791                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40497.505548                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 41406.491959                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 42442.328726                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 40570.333251                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41027.990791                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40497.505548                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 41406.491959                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 42442.328726                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 40570.333251                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -347,39 +347,39 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.iocache.replacements                     41697                       # number of replacements
-system.iocache.tagsinuse                     0.462803                       # Cycle average of tags in use
+system.iocache.replacements                     41698                       # number of replacements
+system.iocache.tagsinuse                     0.465240                       # Cycle average of tags in use
 system.iocache.total_refs                           0                       # Total number of references to valid blocks.
-system.iocache.sampled_refs                     41713                       # Sample count of references to valid blocks.
+system.iocache.sampled_refs                     41714                       # Sample count of references to valid blocks.
 system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
-system.iocache.warmup_cycle              1708345741000                       # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::tsunami.ide       0.462803                       # Average occupied blocks per requestor
-system.iocache.occ_percent::tsunami.ide      0.028925                       # Average percentage of cache occupancy
-system.iocache.occ_percent::total            0.028925                       # Average percentage of cache occupancy
-system.iocache.ReadReq_misses::tsunami.ide          177                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              177                       # number of ReadReq misses
+system.iocache.warmup_cycle              1711281170000                       # Cycle when the warmup percentage was hit.
+system.iocache.occ_blocks::tsunami.ide       0.465240                       # Average occupied blocks per requestor
+system.iocache.occ_percent::tsunami.ide      0.029077                       # Average percentage of cache occupancy
+system.iocache.occ_percent::total            0.029077                       # Average percentage of cache occupancy
+system.iocache.ReadReq_misses::tsunami.ide          178                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              178                       # number of ReadReq misses
 system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
-system.iocache.demand_misses::tsunami.ide        41729                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             41729                       # number of demand (read+write) misses
-system.iocache.overall_misses::tsunami.ide        41729                       # number of overall misses
-system.iocache.overall_misses::total            41729                       # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide     20390998                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     20390998                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::tsunami.ide   5719191806                       # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total   5719191806                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide   5739582804                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   5739582804                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide   5739582804                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   5739582804                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::tsunami.ide          177                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            177                       # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::tsunami.ide        41730                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             41730                       # number of demand (read+write) misses
+system.iocache.overall_misses::tsunami.ide        41730                       # number of overall misses
+system.iocache.overall_misses::total            41730                       # number of overall misses
+system.iocache.ReadReq_miss_latency::tsunami.ide     21238998                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     21238998                       # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::tsunami.ide   7637775806                       # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total   7637775806                       # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide   7659014804                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   7659014804                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide   7659014804                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   7659014804                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::tsunami.ide          178                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            178                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::tsunami.ide        41729                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           41729                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::tsunami.ide        41729                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          41729                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::tsunami.ide        41730                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           41730                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::tsunami.ide        41730                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          41730                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
@@ -388,40 +388,40 @@ system.iocache.demand_miss_rate::tsunami.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115203.378531                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 115203.378531                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137639.386937                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 137639.386937                       # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 137544.221141                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 137544.221141                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 137544.221141                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 137544.221141                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs      64663068                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119320.213483                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 119320.213483                       # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183812.471265                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 183812.471265                       # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 183537.378481                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 183537.378481                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 183537.378481                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 183537.378481                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs       7710000                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                10457                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 7151                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs  6183.711198                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs  1078.170885                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           41520                       # number of writebacks
 system.iocache.writebacks::total                41520                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::tsunami.ide          177                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          177                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::tsunami.ide          178                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          178                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::tsunami.ide        41552                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total        41552                       # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses::tsunami.ide        41729                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total        41729                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::tsunami.ide        41729                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total        41729                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     11186998                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     11186998                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::tsunami.ide   3558333000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total   3558333000                       # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide   3569519998                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   3569519998                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide   3569519998                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   3569519998                       # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::tsunami.ide        41730                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total        41730                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::tsunami.ide        41730                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total        41730                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     11982000                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     11982000                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::tsunami.ide   5476916000                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total   5476916000                       # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide   5488898000                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   5488898000                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide   5488898000                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   5488898000                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
@@ -430,14 +430,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63203.378531                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 63203.378531                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85635.661340                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 85635.661340                       # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85540.511347                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 85540.511347                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85540.511347                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 85540.511347                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67314.606742                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 67314.606742                       # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131808.721602                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 131808.721602                       # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131533.620896                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 131533.620896                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131533.620896                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 131533.620896                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -455,22 +455,22 @@ system.cpu0.dtb.fetch_hits                          0                       # IT
 system.cpu0.dtb.fetch_misses                        0                       # ITB misses
 system.cpu0.dtb.fetch_acv                           0                       # ITB acv
 system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu0.dtb.read_hits                     9453856                       # DTB read hits
-system.cpu0.dtb.read_misses                     36184                       # DTB read misses
-system.cpu0.dtb.read_acv                          571                       # DTB read access violations
-system.cpu0.dtb.read_accesses                  675976                       # DTB read accesses
-system.cpu0.dtb.write_hits                    6300368                       # DTB write hits
-system.cpu0.dtb.write_misses                     8347                       # DTB write misses
-system.cpu0.dtb.write_acv                         346                       # DTB write access violations
-system.cpu0.dtb.write_accesses                 234133                       # DTB write accesses
-system.cpu0.dtb.data_hits                    15754224                       # DTB hits
-system.cpu0.dtb.data_misses                     44531                       # DTB misses
-system.cpu0.dtb.data_acv                          917                       # DTB access violations
-system.cpu0.dtb.data_accesses                  910109                       # DTB accesses
-system.cpu0.itb.fetch_hits                    1108660                       # ITB hits
-system.cpu0.itb.fetch_misses                    28136                       # ITB misses
-system.cpu0.itb.fetch_acv                        1047                       # ITB acv
-system.cpu0.itb.fetch_accesses                1136796                       # ITB accesses
+system.cpu0.dtb.read_hits                     8334313                       # DTB read hits
+system.cpu0.dtb.read_misses                     29661                       # DTB read misses
+system.cpu0.dtb.read_acv                          416                       # DTB read access violations
+system.cpu0.dtb.read_accesses                  650050                       # DTB read accesses
+system.cpu0.dtb.write_hits                    5360515                       # DTB write hits
+system.cpu0.dtb.write_misses                     6017                       # DTB write misses
+system.cpu0.dtb.write_acv                         275                       # DTB write access violations
+system.cpu0.dtb.write_accesses                 211537                       # DTB write accesses
+system.cpu0.dtb.data_hits                    13694828                       # DTB hits
+system.cpu0.dtb.data_misses                     35678                       # DTB misses
+system.cpu0.dtb.data_acv                          691                       # DTB access violations
+system.cpu0.dtb.data_accesses                  861587                       # DTB accesses
+system.cpu0.itb.fetch_hits                     972456                       # ITB hits
+system.cpu0.itb.fetch_misses                    29747                       # ITB misses
+system.cpu0.itb.fetch_acv                         802                       # ITB acv
+system.cpu0.itb.fetch_accesses                1002203                       # ITB accesses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.read_acv                            0                       # DTB read access violations
@@ -483,279 +483,279 @@ system.cpu0.itb.data_hits                           0                       # DT
 system.cpu0.itb.data_misses                         0                       # DTB misses
 system.cpu0.itb.data_acv                            0                       # DTB access violations
 system.cpu0.itb.data_accesses                       0                       # DTB accesses
-system.cpu0.numCycles                       111705884                       # number of cpu cycles simulated
+system.cpu0.numCycles                       107494535                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.BPredUnit.lookups                13423445                       # Number of BP lookups
-system.cpu0.BPredUnit.condPredicted          11229595                       # Number of conditional branches predicted
-system.cpu0.BPredUnit.condIncorrect            405618                       # Number of conditional branches incorrect
-system.cpu0.BPredUnit.BTBLookups              9732141                       # Number of BTB lookups
-system.cpu0.BPredUnit.BTBHits                 5644182                       # Number of BTB hits
+system.cpu0.BPredUnit.lookups                11769770                       # Number of BP lookups
+system.cpu0.BPredUnit.condPredicted           9862090                       # Number of conditional branches predicted
+system.cpu0.BPredUnit.condIncorrect            345528                       # Number of conditional branches incorrect
+system.cpu0.BPredUnit.BTBLookups              8388023                       # Number of BTB lookups
+system.cpu0.BPredUnit.BTBHits                 5075121                       # Number of BTB hits
 system.cpu0.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.BPredUnit.usedRAS                  889528                       # Number of times the RAS was used to get a target.
-system.cpu0.BPredUnit.RASInCorrect              35792                       # Number of incorrect RAS predictions.
-system.cpu0.fetch.icacheStallCycles          28347650                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                      67883922                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                   13423445                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches           6533710                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                     12779049                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles                1882893                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.BlockedCycles              34959873                       # Number of cycles fetch has spent blocked
-system.cpu0.fetch.MiscStallCycles               30735                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles       200156                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles       304542                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles          145                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                  8317299                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes               264993                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.rateDist::samples          77847394                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             0.872013                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            2.211541                       # Number of instructions fetched each cycle (Total)
+system.cpu0.BPredUnit.usedRAS                  768289                       # Number of times the RAS was used to get a target.
+system.cpu0.BPredUnit.RASInCorrect              29261                       # Number of incorrect RAS predictions.
+system.cpu0.fetch.icacheStallCycles          25151812                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                      60423976                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                   11769770                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches           5843410                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                     11477495                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles                1678868                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.BlockedCycles              36441754                       # Number of cycles fetch has spent blocked
+system.cpu0.fetch.MiscStallCycles               35468                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles       189532                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles       310248                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles          196                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                  7504127                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes               232204                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.rateDist::samples          74712100                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             0.808758                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            2.135218                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0                65068345     83.58%     83.58% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                  840291      1.08%     84.66% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                 1663244      2.14%     86.80% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                  773630      0.99%     87.79% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4                 2654406      3.41%     91.20% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5                  587924      0.76%     91.96% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6                  633021      0.81%     92.77% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7                  971381      1.25%     94.02% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8                 4655152      5.98%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0                63234605     84.64%     84.64% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                  741221      0.99%     85.63% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                 1559530      2.09%     87.72% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                  686170      0.92%     88.64% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4                 2492076      3.34%     91.97% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5                  531561      0.71%     92.68% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6                  568906      0.76%     93.44% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7                  718608      0.96%     94.41% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8                 4179423      5.59%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total            77847394                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.120168                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.607702                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles                29292805                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles             34750406                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                 11695757                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles               922620                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles               1185805                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved              575553                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred                39816                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts              66717094                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts               118720                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles               1185805                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles                30365496                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles               12492089                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles      18756431                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                 10933791                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles              4113780                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts              63191653                       # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents                 6630                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents                474971                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LSQFullEvents              1473898                       # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.RenamedOperands           42180100                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups             76536527                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups        76096983                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups           439544                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps             36808161                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                 5371931                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts           1596682                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts        238140                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                 11595704                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads             9967009                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores            6589337                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads          1245862                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores          818929                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                  55970736                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded            2008418                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                 54697537                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued           108647                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined        6579388                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined      3235320                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved       1364468                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples     77847394                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.702625                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.358580                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total            74712100                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.109492                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.562112                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles                26235752                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles             36073897                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                 10433111                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles               896014                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles               1073325                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved              504398                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred                32602                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts              59387121                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts                93497                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles               1073325                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles                27172169                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles               15317742                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles      17291837                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                  9793019                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles              4064006                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts              56407383                       # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents                 7139                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents                656540                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LSQFullEvents              1492805                       # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.RenamedOperands           37953017                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups             68861567                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups        68508934                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups           352633                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps             33050954                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                 4902063                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts           1333181                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts        200244                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                 10589201                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads             8773580                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores            5638577                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads          1132250                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores          738910                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                  50116652                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded            1669804                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                 48856794                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued           108488                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined        5944129                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined      3041029                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved       1132337                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples     74712100                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.653934                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.297915                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0           53933184     69.28%     69.28% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1           10617760     13.64%     82.92% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2            4942911      6.35%     89.27% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3            3320001      4.26%     93.53% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4            2532609      3.25%     96.79% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5            1408678      1.81%     98.60% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6             686959      0.88%     99.48% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7             303964      0.39%     99.87% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8             101328      0.13%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0           52667189     70.49%     70.49% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1           10185163     13.63%     84.13% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2            4563652      6.11%     90.23% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3            2983683      3.99%     94.23% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4            2257783      3.02%     97.25% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5            1142078      1.53%     98.78% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6             582516      0.78%     99.56% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7             283628      0.38%     99.94% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8              46408      0.06%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total       77847394                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total       74712100                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                  87681     11.80%     11.80% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                     0      0.00%     11.80% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                      0      0.00%     11.80% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     11.80% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     11.80% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     11.80% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%     11.80% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     11.80% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     11.80% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     11.80% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     11.80% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     11.80% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     11.80% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     11.80% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     11.80% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%     11.80% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     11.80% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%     11.80% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     11.80% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     11.80% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     11.80% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     11.80% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     11.80% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     11.80% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     11.80% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     11.80% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     11.80% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     11.80% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     11.80% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead                349168     46.97%     58.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite               306477     41.23%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                  73121     11.93%     11.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                     0      0.00%     11.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                      0      0.00%     11.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     11.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     11.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     11.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%     11.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     11.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     11.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     11.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     11.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     11.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     11.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     11.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     11.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%     11.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     11.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%     11.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     11.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     11.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     11.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     11.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     11.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     11.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     11.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     11.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     11.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     11.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     11.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead                287582     46.92%     58.85% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite               252262     41.15%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass             3778      0.01%      0.01% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu             37484034     68.53%     68.54% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult               60241      0.11%     68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd              16826      0.03%     68.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv               1883      0.00%     68.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     68.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead             9867065     18.04%     86.72% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite            6373328     11.65%     98.37% # Type of FU issued
-system.cpu0.iq.FU_type_0::IprAccess            890382      1.63%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass             4467      0.01%      0.01% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu             33934109     69.46%     69.47% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult               53582      0.11%     69.58% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     69.58% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd              16546      0.03%     69.61% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     69.61% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     69.61% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     69.61% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv               2231      0.00%     69.61% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     69.61% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     69.61% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     69.61% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     69.61% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     69.61% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     69.61% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     69.61% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     69.61% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     69.61% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     69.61% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     69.61% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     69.61% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     69.61% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     69.61% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     69.61% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     69.61% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     69.61% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     69.61% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     69.61% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     69.61% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     69.61% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead             8675974     17.76%     87.37% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite            5426955     11.11%     98.48% # Type of FU issued
+system.cpu0.iq.FU_type_0::IprAccess            742930      1.52%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total              54697537                       # Type of FU issued
-system.cpu0.iq.rate                          0.489657                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                     743326                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.013590                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads         187461216                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes         64264846                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses     53535096                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads             633224                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes            306465                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses       298013                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses              55105300                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                 331785                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads          567631                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total              48856794                       # Type of FU issued
+system.cpu0.iq.rate                          0.454505                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                     612965                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.012546                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads         172645923                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes         57499135                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses     47860626                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads             501218                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes            243758                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses       236014                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses              49202996                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                 262296                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads          518056                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads      1269870                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses         3726                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation        13071                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores       496722                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads      1116510                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses         2510                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation        12661                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores       476371                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads        18808                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked       143577                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads        18849                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked        94368                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles               1185805                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles                8725439                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles               608869                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts           61441844                       # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts           619329                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts              9967009                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts             6589337                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts           1767664                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                482033                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents                12133                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents         13071                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect        215254                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect       393579                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts              608833                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts             54218225                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts              9516523                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts           479311                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles               1073325                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles               10798667                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles               779958                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts           54837290                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts           559703                       # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts              8773580                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts             5638577                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts           1469305                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                544312                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents                 8344                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents         12661                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect        186183                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect       327984                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts              514167                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts             48431427                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts              8385093                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts           425367                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                      3462690                       # number of nop insts executed
-system.cpu0.iew.exec_refs                    15839640                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches                 8639850                       # Number of branches executed
-system.cpu0.iew.exec_stores                   6323117                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.485366                       # Inst execution rate
-system.cpu0.iew.wb_sent                      53937806                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                     53833109                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                 26624302                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                 35973761                       # num instructions consuming a value
+system.cpu0.iew.exec_nop                      3050834                       # number of nop insts executed
+system.cpu0.iew.exec_refs                    13764236                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches                 7758760                       # Number of branches executed
+system.cpu0.iew.exec_stores                   5379143                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.450548                       # Inst execution rate
+system.cpu0.iew.wb_sent                      48183951                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                     48096640                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                 24100280                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                 32401803                       # num instructions consuming a value
 system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate                      0.481918                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.740103                       # average fanout of values written-back
+system.cpu0.iew.wb_rate                      0.447433                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.743794                       # average fanout of values written-back
 system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitCommittedInsts      54183968                       # The number of committed instructions
-system.cpu0.commit.commitCommittedOps        54183968                       # The number of committed instructions
-system.cpu0.commit.commitSquashedInsts        7167159                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls         643950                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts           567683                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples     76661589                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.706794                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.627118                       # Number of insts commited each cycle
+system.cpu0.commit.commitCommittedInsts      48294177                       # The number of committed instructions
+system.cpu0.commit.commitCommittedOps        48294177                       # The number of committed instructions
+system.cpu0.commit.commitSquashedInsts        6449436                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls         537467                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts           480768                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples     73638775                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.655825                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.560295                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0     56437400     73.62%     73.62% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1      8432395     11.00%     84.62% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2      4492859      5.86%     90.48% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3      2495159      3.25%     93.73% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4      1450592      1.89%     95.63% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5       646072      0.84%     96.47% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6       460772      0.60%     97.07% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7       487702      0.64%     97.71% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8      1758638      2.29%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0     55222738     74.99%     74.99% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1      7735232     10.50%     85.50% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2      4278280      5.81%     91.31% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3      2283958      3.10%     94.41% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4      1242509      1.69%     96.09% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5       524248      0.71%     96.81% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6       435052      0.59%     97.40% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7       385141      0.52%     97.92% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8      1531617      2.08%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total     76661589                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts            54183968                       # Number of instructions committed
-system.cpu0.commit.committedOps              54183968                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total     73638775                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts            48294177                       # Number of instructions committed
+system.cpu0.commit.committedOps              48294177                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                      14789754                       # Number of memory references committed
-system.cpu0.commit.loads                      8697139                       # Number of loads committed
-system.cpu0.commit.membars                     219715                       # Number of memory barriers committed
-system.cpu0.commit.branches                   8176675                       # Number of branches committed
-system.cpu0.commit.fp_insts                    295518                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                 50137398                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls              709743                       # Number of function calls committed.
-system.cpu0.commit.bw_lim_events              1758638                       # number cycles where commit BW limit reached
+system.cpu0.commit.refs                      12819276                       # Number of memory references committed
+system.cpu0.commit.loads                      7657070                       # Number of loads committed
+system.cpu0.commit.membars                     181890                       # Number of memory barriers committed
+system.cpu0.commit.branches                   7325526                       # Number of branches committed
+system.cpu0.commit.fp_insts                    233448                       # Number of committed floating point instructions.
+system.cpu0.commit.int_insts                 44748110                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls              610965                       # Number of function calls committed.
+system.cpu0.commit.bw_lim_events              1531617                       # number cycles where commit BW limit reached
 system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads                   136054419                       # The number of ROB reads
-system.cpu0.rob.rob_writes                  123888625                       # The number of ROB writes
-system.cpu0.timesIdled                        1249831                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                       33858490                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                  3681079567                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                   51051860                       # Number of Instructions Simulated
-system.cpu0.committedOps                     51051860                       # Number of Ops (including micro ops) Simulated
-system.cpu0.committedInsts_total             51051860                       # Number of Instructions Simulated
-system.cpu0.cpi                              2.188086                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        2.188086                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.457020                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.457020                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads                71111535                       # number of integer regfile reads
-system.cpu0.int_regfile_writes               38857328                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                   146185                       # number of floating regfile reads
-system.cpu0.fp_regfile_writes                  148692                       # number of floating regfile writes
-system.cpu0.misc_regfile_reads                1886112                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes                899559                       # number of misc regfile writes
+system.cpu0.rob.rob_reads                   126666255                       # The number of ROB reads
+system.cpu0.rob.rob_writes                  110560293                       # The number of ROB writes
+system.cpu0.timesIdled                        1221795                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                       32782435                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                  3693291566                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                   45532520                       # Number of Instructions Simulated
+system.cpu0.committedOps                     45532520                       # Number of Ops (including micro ops) Simulated
+system.cpu0.committedInsts_total             45532520                       # Number of Instructions Simulated
+system.cpu0.cpi                              2.360830                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        2.360830                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.423580                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.423580                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads                63860317                       # number of integer regfile reads
+system.cpu0.int_regfile_writes               34945795                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                   117013                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                  117648                       # number of floating regfile writes
+system.cpu0.misc_regfile_reads                1550179                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes                750147                       # number of misc regfile writes
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
 system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
@@ -787,247 +787,247 @@ system.tsunami.ethernet.totalRxOrn                  0                       # to
 system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
 system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.cpu0.icache.replacements                991395                       # number of replacements
-system.cpu0.icache.tagsinuse               510.024196                       # Cycle average of tags in use
-system.cpu0.icache.total_refs                 7272203                       # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs                991905                       # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs                  7.331552                       # Average number of references to valid blocks.
-system.cpu0.icache.warmup_cycle           23165696000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst   510.024196                       # Average occupied blocks per requestor
-system.cpu0.icache.occ_percent::cpu0.inst     0.996141                       # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::total        0.996141                       # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst      7272203                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total        7272203                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst      7272203                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total         7272203                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst      7272203                       # number of overall hits
-system.cpu0.icache.overall_hits::total        7272203                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      1045096                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      1045096                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      1045096                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       1045096                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      1045096                       # number of overall misses
-system.cpu0.icache.overall_misses::total      1045096                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  15554108994                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  15554108994                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  15554108994                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  15554108994                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  15554108994                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  15554108994                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst      8317299                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total      8317299                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst      8317299                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total      8317299                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst      8317299                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total      8317299                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.125653                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.125653                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.125653                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.125653                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.125653                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.125653                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14882.947590                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 14882.947590                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14882.947590                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 14882.947590                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14882.947590                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 14882.947590                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs      1419995                       # number of cycles access was blocked
+system.cpu0.icache.replacements                790628                       # number of replacements
+system.cpu0.icache.tagsinuse               510.000717                       # Cycle average of tags in use
+system.cpu0.icache.total_refs                 6669453                       # Total number of references to valid blocks.
+system.cpu0.icache.sampled_refs                791140                       # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs                  8.430180                       # Average number of references to valid blocks.
+system.cpu0.icache.warmup_cycle           23654486000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.occ_blocks::cpu0.inst   510.000717                       # Average occupied blocks per requestor
+system.cpu0.icache.occ_percent::cpu0.inst     0.996095                       # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::total        0.996095                       # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits::cpu0.inst      6669453                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total        6669453                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst      6669453                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total         6669453                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst      6669453                       # number of overall hits
+system.cpu0.icache.overall_hits::total        6669453                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       834673                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       834673                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       834673                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        834673                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       834673                       # number of overall misses
+system.cpu0.icache.overall_misses::total       834673                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  13767352493                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  13767352493                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  13767352493                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  13767352493                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  13767352493                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  13767352493                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst      7504126                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total      7504126                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst      7504126                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total      7504126                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst      7504126                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total      7504126                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.111229                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.111229                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.111229                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.111229                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.111229                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.111229                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16494.306744                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 16494.306744                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16494.306744                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 16494.306744                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16494.306744                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 16494.306744                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs      1480996                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              129                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              162                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs 11007.713178                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs  9141.950617                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.writebacks::writebacks          253                       # number of writebacks
-system.cpu0.icache.writebacks::total              253                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        53062                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        53062                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst        53062                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        53062                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst        53062                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        53062                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       992034                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       992034                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       992034                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       992034                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       992034                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       992034                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  11805368995                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  11805368995                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  11805368995                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  11805368995                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  11805368995                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  11805368995                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.119274                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.119274                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.119274                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.119274                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.119274                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.119274                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11900.165715                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11900.165715                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11900.165715                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 11900.165715                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11900.165715                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 11900.165715                       # average overall mshr miss latency
+system.cpu0.icache.writebacks::writebacks          247                       # number of writebacks
+system.cpu0.icache.writebacks::total              247                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        43336                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        43336                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst        43336                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        43336                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst        43336                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        43336                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       791337                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       791337                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       791337                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       791337                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       791337                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       791337                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  10689365997                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  10689365997                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  10689365997                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  10689365997                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  10689365997                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  10689365997                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.105454                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.105454                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.105454                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.105454                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.105454                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.105454                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13507.982057                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13507.982057                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13507.982057                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 13507.982057                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13507.982057                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 13507.982057                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.replacements               1352160                       # number of replacements
-system.cpu0.dcache.tagsinuse               506.886378                       # Cycle average of tags in use
-system.cpu0.dcache.total_refs                11309312                       # Total number of references to valid blocks.
-system.cpu0.dcache.sampled_refs               1352672                       # Sample count of references to valid blocks.
-system.cpu0.dcache.avg_refs                  8.360720                       # Average number of references to valid blocks.
-system.cpu0.dcache.warmup_cycle              19277000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::cpu0.data   506.886378                       # Average occupied blocks per requestor
-system.cpu0.dcache.occ_percent::cpu0.data     0.990012                       # Average percentage of cache occupancy
-system.cpu0.dcache.occ_percent::total        0.990012                       # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::cpu0.data      6911324                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        6911324                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      3997215                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       3997215                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       183850                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       183850                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       210761                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       210761                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     10908539                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        10908539                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     10908539                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       10908539                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      1709932                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      1709932                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1869031                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      1869031                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        22271                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        22271                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data          641                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total          641                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      3578963                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       3578963                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      3578963                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      3578963                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  36329127500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  36329127500                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  56639435392                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  56639435392                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    326225500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    326225500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data      5918000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total      5918000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  92968562892                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  92968562892                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  92968562892                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  92968562892                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      8621256                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      8621256                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      5866246                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      5866246                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       206121                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       206121                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       211402                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       211402                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     14487502                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     14487502                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     14487502                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     14487502                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.198339                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.198339                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.318608                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.318608                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.108048                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.108048                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.003032                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.003032                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.247038                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.247038                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.247038                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.247038                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21245.948669                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 21245.948669                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30304.171195                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 30304.171195                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14647.995151                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14647.995151                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  9232.449298                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  9232.449298                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25976.396764                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 25976.396764                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 25976.396764                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 25976.396764                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs    790531306                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets       168000                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs            99401                       # number of cycles access was blocked
+system.cpu0.dcache.replacements               1206208                       # number of replacements
+system.cpu0.dcache.tagsinuse               505.878050                       # Cycle average of tags in use
+system.cpu0.dcache.total_refs                 9822290                       # Total number of references to valid blocks.
+system.cpu0.dcache.sampled_refs               1206649                       # Sample count of references to valid blocks.
+system.cpu0.dcache.avg_refs                  8.140139                       # Average number of references to valid blocks.
+system.cpu0.dcache.warmup_cycle              19675000                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.occ_blocks::cpu0.data   505.878050                       # Average occupied blocks per requestor
+system.cpu0.dcache.occ_percent::cpu0.data     0.988043                       # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::total        0.988043                       # Average percentage of cache occupancy
+system.cpu0.dcache.ReadReq_hits::cpu0.data      6113680                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        6113680                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      3377171                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       3377171                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       150549                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       150549                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       171656                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       171656                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data      9490851                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total         9490851                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data      9490851                       # number of overall hits
+system.cpu0.dcache.overall_hits::total        9490851                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      1478314                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      1478314                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      1593619                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      1593619                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        18637                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        18637                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data         4699                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total         4699                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      3071933                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       3071933                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      3071933                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      3071933                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  41272950000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  41272950000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  65317405497                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  65317405497                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    315155000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    315155000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     68652000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total     68652000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 106590355497                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 106590355497                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 106590355497                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 106590355497                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      7591994                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      7591994                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      4970790                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      4970790                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       169186                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       169186                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       176355                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       176355                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     12562784                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     12562784                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     12562784                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     12562784                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.194720                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.194720                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.320597                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.320597                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.110157                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.110157                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.026645                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.026645                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.244526                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.244526                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.244526                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.244526                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27918.933325                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 27918.933325                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40986.839073                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 40986.839073                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16910.178677                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16910.178677                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 14609.917004                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14609.917004                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34698.138109                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 34698.138109                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34698.138109                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 34698.138109                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs    716537144                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets       178000                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs            65430                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets              7                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs  7952.951238                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets        24000                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10951.201956                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets 25428.571429                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       805259                       # number of writebacks
-system.cpu0.dcache.writebacks::total           805259                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       661851                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       661851                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1575507                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      1575507                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         5029                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total         5029                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      2237358                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      2237358                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      2237358                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      2237358                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      1048081                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      1048081                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       293524                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       293524                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        17242                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total        17242                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data          640                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total          640                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      1341605                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      1341605                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      1341605                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      1341605                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  23566810500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  23566810500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   8456840306                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   8456840306                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    195574000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    195574000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data      3991500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      3991500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  32023650806                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  32023650806                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  32023650806                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  32023650806                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data    917307000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total    917307000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1253595498                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1253595498                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   2170902498                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   2170902498                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.121569                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.121569                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.050036                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.050036                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.083650                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.083650                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.003027                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.003027                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.092604                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.092604                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.092604                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.092604                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 22485.676680                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 22485.676680                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 28811.409990                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 28811.409990                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11342.883656                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11342.883656                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  6236.718750                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  6236.718750                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23869.656722                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23869.656722                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23869.656722                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23869.656722                       # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks       693284                       # number of writebacks
+system.cpu0.dcache.writebacks::total           693284                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       515563                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       515563                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1344321                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      1344321                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         3732                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total         3732                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      1859884                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      1859884                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      1859884                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      1859884                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       962751                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       962751                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       249298                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       249298                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        14905                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total        14905                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         4699                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total         4699                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      1212049                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      1212049                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      1212049                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      1212049                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  25942792600                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  25942792600                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   8699231964                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   8699231964                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    186934001                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    186934001                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     54037501                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     54037501                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  34642024564                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  34642024564                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  34642024564                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  34642024564                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data    918343000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total    918343000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1327727998                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1327727998                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   2246070998                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   2246070998                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.126811                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.126811                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.050153                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.050153                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.088098                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.088098                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.026645                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.026645                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.096479                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.096479                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.096479                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.096479                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26946.523660                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26946.523660                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 34894.912771                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34894.912771                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12541.697484                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12541.697484                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11499.787402                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11499.787402                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 28581.373001                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28581.373001                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 28581.373001                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 28581.373001                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1039,22 +1039,22 @@ system.cpu1.dtb.fetch_hits                          0                       # IT
 system.cpu1.dtb.fetch_misses                        0                       # ITB misses
 system.cpu1.dtb.fetch_acv                           0                       # ITB acv
 system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu1.dtb.read_hits                     1211336                       # DTB read hits
-system.cpu1.dtb.read_misses                      9865                       # DTB read misses
-system.cpu1.dtb.read_acv                            6                       # DTB read access violations
-system.cpu1.dtb.read_accesses                  283619                       # DTB read accesses
-system.cpu1.dtb.write_hits                     674221                       # DTB write hits
-system.cpu1.dtb.write_misses                     1908                       # DTB write misses
-system.cpu1.dtb.write_acv                          40                       # DTB write access violations
-system.cpu1.dtb.write_accesses                 107232                       # DTB write accesses
-system.cpu1.dtb.data_hits                     1885557                       # DTB hits
-system.cpu1.dtb.data_misses                     11773                       # DTB misses
-system.cpu1.dtb.data_acv                           46                       # DTB access violations
-system.cpu1.dtb.data_accesses                  390851                       # DTB accesses
-system.cpu1.itb.fetch_hits                     332989                       # ITB hits
-system.cpu1.itb.fetch_misses                     6158                       # ITB misses
-system.cpu1.itb.fetch_acv                         143                       # ITB acv
-system.cpu1.itb.fetch_accesses                 339147                       # ITB accesses
+system.cpu1.dtb.read_hits                     2499316                       # DTB read hits
+system.cpu1.dtb.read_misses                     12569                       # DTB read misses
+system.cpu1.dtb.read_acv                          105                       # DTB read access violations
+system.cpu1.dtb.read_accesses                  313735                       # DTB read accesses
+system.cpu1.dtb.write_hits                    1734639                       # DTB write hits
+system.cpu1.dtb.write_misses                     3525                       # DTB write misses
+system.cpu1.dtb.write_acv                         140                       # DTB write access violations
+system.cpu1.dtb.write_accesses                 132367                       # DTB write accesses
+system.cpu1.dtb.data_hits                     4233955                       # DTB hits
+system.cpu1.dtb.data_misses                     16094                       # DTB misses
+system.cpu1.dtb.data_acv                          245                       # DTB access violations
+system.cpu1.dtb.data_accesses                  446102                       # DTB accesses
+system.cpu1.itb.fetch_hits                     489806                       # ITB hits
+system.cpu1.itb.fetch_misses                     8851                       # ITB misses
+system.cpu1.itb.fetch_acv                         360                       # ITB acv
+system.cpu1.itb.fetch_accesses                 498657                       # ITB accesses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.read_acv                            0                       # DTB read access violations
@@ -1067,520 +1067,520 @@ system.cpu1.itb.data_hits                           0                       # DT
 system.cpu1.itb.data_misses                         0                       # DTB misses
 system.cpu1.itb.data_acv                            0                       # DTB access violations
 system.cpu1.itb.data_accesses                       0                       # DTB accesses
-system.cpu1.numCycles                         8872891                       # number of cpu cycles simulated
+system.cpu1.numCycles                        22717311                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.BPredUnit.lookups                 1582523                       # Number of BP lookups
-system.cpu1.BPredUnit.condPredicted           1301899                       # Number of conditional branches predicted
-system.cpu1.BPredUnit.condIncorrect             53959                       # Number of conditional branches incorrect
-system.cpu1.BPredUnit.BTBLookups               749480                       # Number of BTB lookups
-system.cpu1.BPredUnit.BTBHits                  495600                       # Number of BTB hits
+system.cpu1.BPredUnit.lookups                 3442703                       # Number of BP lookups
+system.cpu1.BPredUnit.condPredicted           2849702                       # Number of conditional branches predicted
+system.cpu1.BPredUnit.condIncorrect            108899                       # Number of conditional branches incorrect
+system.cpu1.BPredUnit.BTBLookups              2361843                       # Number of BTB lookups
+system.cpu1.BPredUnit.BTBHits                 1192387                       # Number of BTB hits
 system.cpu1.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.BPredUnit.usedRAS                  108561                       # Number of times the RAS was used to get a target.
-system.cpu1.BPredUnit.RASInCorrect               5012                       # Number of incorrect RAS predictions.
-system.cpu1.fetch.icacheStallCycles           3100077                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                       7469135                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                    1582523                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches            604161                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                      1348473                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles                 293042                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.BlockedCycles               3524434                       # Number of cycles fetch has spent blocked
-system.cpu1.fetch.MiscStallCycles               23987                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles        56676                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles        47433                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles           22                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                   951392                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes                34043                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.rateDist::samples           8293149                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             0.900639                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            2.276932                       # Number of instructions fetched each cycle (Total)
+system.cpu1.BPredUnit.usedRAS                  236332                       # Number of times the RAS was used to get a target.
+system.cpu1.BPredUnit.RASInCorrect              10679                       # Number of incorrect RAS predictions.
+system.cpu1.fetch.icacheStallCycles           9037199                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                      16321027                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                    3442703                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches           1428719                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                      2924126                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles                 526603                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.BlockedCycles               8306285                       # Number of cycles fetch has spent blocked
+system.cpu1.fetch.MiscStallCycles               28121                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles        87140                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles        64229                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles           29                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                  1963514                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes                75345                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.rateDist::samples          20778311                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             0.785484                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            2.154367                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0                 6944676     83.74%     83.74% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                   71085      0.86%     84.60% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                  161786      1.95%     86.55% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                  117935      1.42%     87.97% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4                  195029      2.35%     90.32% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5                   79896      0.96%     91.29% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6                   91030      1.10%     92.38% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7                   58799      0.71%     93.09% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8                  572913      6.91%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0                17854185     85.93%     85.93% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                  203613      0.98%     86.91% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                  301133      1.45%     88.36% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                  225724      1.09%     89.44% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4                  404540      1.95%     91.39% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5                  151692      0.73%     92.12% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6                  164507      0.79%     92.91% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7                  309022      1.49%     94.40% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8                 1163895      5.60%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total             8293149                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.178355                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       0.841793                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                 3156648                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles              3626684                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                  1266182                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles                55854                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles                187780                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved               69682                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred                 4376                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts               7275177                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts                13096                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles                187780                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles                 3279437                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles                 303001                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles       2955129                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                  1188563                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles               379237                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts               6712088                       # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents                   44                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents                 36332                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LSQFullEvents                73621                       # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.RenamedOperands            4503320                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups              8147567                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups         8100022                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups            47545                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps              3660294                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                  843026                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts            283944                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts         19782                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                  1166048                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads             1294582                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores             736122                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads           125256                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores           86989                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                   5902743                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded             293921                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                  5640439                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued            22605                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined        1087589                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined       606184                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved        224688                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples      8293149                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.680132                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.353961                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total            20778311                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.151545                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       0.718440                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                 8812255                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles              8762880                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                  2709089                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles               172906                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles                321180                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved              151088                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred                10133                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts              16020033                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts                29351                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles                321180                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles                 9094333                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles                 882455                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles       6951469                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                  2594850                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles               934022                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts              14843152                       # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents                  114                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents                 83650                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LSQFullEvents               279958                       # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.RenamedOperands            9660007                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups             17630674                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups        17422680                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups           207994                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps              8331005                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                 1328994                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts            594043                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts         64597                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                  2775458                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads             2641121                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores            1825529                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads           246953                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores          159017                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                  12975245                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded             664400                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                 12700763                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued            35708                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined        1746535                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined       829425                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved        468662                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples     20778311                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.611251                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.284414                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0            5841725     70.44%     70.44% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1            1091278     13.16%     83.60% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2             496152      5.98%     89.58% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3             349787      4.22%     93.80% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4             258149      3.11%     96.91% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5             126242      1.52%     98.43% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6              71640      0.86%     99.30% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7              51558      0.62%     99.92% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8               6618      0.08%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0           15115816     72.75%     72.75% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1            2653114     12.77%     85.52% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2            1112593      5.35%     90.87% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3             724594      3.49%     94.36% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4             603153      2.90%     97.26% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5             287847      1.39%     98.65% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6             182303      0.88%     99.52% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7              88112      0.42%     99.95% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8              10779      0.05%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total        8293149                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total       20778311                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                   3067      2.40%      2.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                     0      0.00%      2.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                      0      0.00%      2.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      2.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      2.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      2.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%      2.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      2.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      2.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      2.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      2.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      2.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      2.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      2.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      2.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%      2.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      2.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%      2.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      2.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      2.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      2.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      2.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      2.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      2.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      2.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      2.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      2.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      2.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      2.40% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead                 73236     57.36%     59.76% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite                51382     40.24%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                   3869      1.53%      1.53% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                     0      0.00%      1.53% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                      0      0.00%      1.53% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      1.53% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      1.53% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      1.53% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%      1.53% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      1.53% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      1.53% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      1.53% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      1.53% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      1.53% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      1.53% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      1.53% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      1.53% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%      1.53% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      1.53% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%      1.53% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      1.53% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      1.53% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      1.53% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      1.53% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      1.53% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      1.53% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      1.53% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      1.53% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      1.53% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      1.53% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      1.53% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead                134765     53.16%     54.68% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite               114892     45.32%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass             3518      0.06%      0.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu              3484656     61.78%     61.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult               10025      0.18%     62.02% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     62.02% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd               8917      0.16%     62.18% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     62.18% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     62.18% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     62.18% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv               1759      0.03%     62.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     62.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     62.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     62.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     62.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     62.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     62.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     62.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     62.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     62.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     62.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     62.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     62.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     62.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     62.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     62.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     62.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     62.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     62.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     62.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     62.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     62.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead             1261676     22.37%     84.58% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite             692210     12.27%     96.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::IprAccess            177678      3.15%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass             2823      0.02%      0.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu              7927502     62.42%     62.44% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult               20764      0.16%     62.60% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     62.60% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd              10543      0.08%     62.69% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     62.69% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     62.69% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     62.69% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv               1411      0.01%     62.70% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     62.70% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     62.70% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     62.70% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     62.70% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     62.70% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     62.70% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     62.70% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     62.70% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     62.70% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     62.70% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     62.70% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     62.70% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     62.70% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     62.70% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     62.70% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     62.70% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     62.70% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     62.70% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     62.70% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     62.70% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     62.70% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead             2623377     20.66%     83.35% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite            1764952     13.90%     97.25% # Type of FU issued
+system.cpu1.iq.FU_type_0::IprAccess            349391      2.75%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total               5640439                       # Type of FU issued
-system.cpu1.iq.rate                          0.635693                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                     127685                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.022637                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads          19654183                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes          7250568                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses      5466934                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads              70134                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes             35039                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses        33778                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses               5728452                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                  36154                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads           64737                       # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total              12700763                       # Type of FU issued
+system.cpu1.iq.rate                          0.559079                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                     253526                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.019961                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads          46169663                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes         15243166                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses     12341001                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads             299407                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes            145151                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses       140846                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses              12794667                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                 156799                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads          115193                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads       237812                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses          428                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation         1426                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores       105246                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads       347930                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses          808                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation         2222                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores       153073                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads          373                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked        23964                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads          370                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked        11635                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles                187780                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles                 210633                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles                 9248                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts            6437285                       # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts            88203                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts              1294582                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts              736122                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts            274301                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                  3887                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents                 3376                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents          1426                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect         25150                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect        66283                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts               91433                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts              5579037                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts              1224301                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts            61402                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles                321180                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles                 537224                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles                73444                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts           14366092                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts           206312                       # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts              2641121                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts             1825529                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts            596088                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                 55197                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents                 6016                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents          2222                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect         53937                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect       130013                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts              183950                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts             12579473                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts              2523314                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts           121289                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                       240621                       # number of nop insts executed
-system.cpu1.iew.exec_refs                     1903575                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches                  816845                       # Number of branches executed
-system.cpu1.iew.exec_stores                    679274                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.628773                       # Inst execution rate
-system.cpu1.iew.wb_sent                       5526738                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                      5500712                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                  2655801                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                  3693565                       # num instructions consuming a value
+system.cpu1.iew.exec_nop                       726447                       # number of nop insts executed
+system.cpu1.iew.exec_refs                     4269906                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches                 1887172                       # Number of branches executed
+system.cpu1.iew.exec_stores                   1746592                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.553740                       # Inst execution rate
+system.cpu1.iew.wb_sent                      12515990                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                     12481847                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                  5700900                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                  8040202                       # num instructions consuming a value
 system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate                      0.619946                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.719035                       # average fanout of values written-back
+system.cpu1.iew.wb_rate                      0.549442                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.709049                       # average fanout of values written-back
 system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitCommittedInsts       5260797                       # The number of committed instructions
-system.cpu1.commit.commitCommittedOps         5260797                       # The number of committed instructions
-system.cpu1.commit.commitSquashedInsts        1110508                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls          69233                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts            85933                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples      8105369                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.649051                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.577854                       # Number of insts commited each cycle
+system.cpu1.commit.commitCommittedInsts      12433159                       # The number of committed instructions
+system.cpu1.commit.commitCommittedOps        12433159                       # The number of committed instructions
+system.cpu1.commit.commitSquashedInsts        1857667                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls         195738                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts           173364                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples     20457131                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.607767                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.554530                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0      6083727     75.06%     75.06% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1       977563     12.06%     87.12% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2       351716      4.34%     91.46% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3       209459      2.58%     94.04% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4       128681      1.59%     95.63% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5        67803      0.84%     96.47% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6        72265      0.89%     97.36% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7        49144      0.61%     97.96% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8       165011      2.04%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0     15844350     77.45%     77.45% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1      2122437     10.38%     87.83% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2       810532      3.96%     91.79% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3       497134      2.43%     94.22% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4       362445      1.77%     95.99% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5       133722      0.65%     96.64% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6       129038      0.63%     97.27% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7       154146      0.75%     98.03% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8       403327      1.97%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total      8105369                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts             5260797                       # Number of instructions committed
-system.cpu1.commit.committedOps               5260797                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total     20457131                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts            12433159                       # Number of instructions committed
+system.cpu1.commit.committedOps              12433159                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                       1687646                       # Number of memory references committed
-system.cpu1.commit.loads                      1056770                       # Number of loads committed
-system.cpu1.commit.membars                      18284                       # Number of memory barriers committed
-system.cpu1.commit.branches                    746127                       # Number of branches committed
-system.cpu1.commit.fp_insts                     32538                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                  4917553                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls               83297                       # Number of function calls committed.
-system.cpu1.commit.bw_lim_events               165011                       # number cycles where commit BW limit reached
+system.cpu1.commit.refs                       3965647                       # Number of memory references committed
+system.cpu1.commit.loads                      2293191                       # Number of loads committed
+system.cpu1.commit.membars                      64658                       # Number of memory barriers committed
+system.cpu1.commit.branches                   1777478                       # Number of branches committed
+system.cpu1.commit.fp_insts                    139699                       # Number of committed floating point instructions.
+system.cpu1.commit.int_insts                 11488003                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls              194670                       # Number of function calls committed.
+system.cpu1.commit.bw_lim_events               403327                       # number cycles where commit BW limit reached
 system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads                    14229924                       # The number of ROB reads
-system.cpu1.rob.rob_writes                   12929135                       # The number of ROB writes
-system.cpu1.timesIdled                          74630                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                         579742                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                  3783284242                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                    5057664                       # Number of Instructions Simulated
-system.cpu1.committedOps                      5057664                       # Number of Ops (including micro ops) Simulated
-system.cpu1.committedInsts_total              5057664                       # Number of Instructions Simulated
-system.cpu1.cpi                              1.754346                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        1.754346                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.570013                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.570013                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads                 7235777                       # number of integer regfile reads
-system.cpu1.int_regfile_writes                3986410                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                    21879                       # number of floating regfile reads
-system.cpu1.fp_regfile_writes                   20613                       # number of floating regfile writes
-system.cpu1.misc_regfile_reads                 262487                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes                123180                       # number of misc regfile writes
-system.cpu1.icache.replacements                103776                       # number of replacements
-system.cpu1.icache.tagsinuse               452.422972                       # Cycle average of tags in use
-system.cpu1.icache.total_refs                  841895                       # Total number of references to valid blocks.
-system.cpu1.icache.sampled_refs                104287                       # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs                  8.072866                       # Average number of references to valid blocks.
-system.cpu1.icache.warmup_cycle          1873827117000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::cpu1.inst   452.422972                       # Average occupied blocks per requestor
-system.cpu1.icache.occ_percent::cpu1.inst     0.883639                       # Average percentage of cache occupancy
-system.cpu1.icache.occ_percent::total        0.883639                       # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst       841895                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total         841895                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst       841895                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total          841895                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst       841895                       # number of overall hits
-system.cpu1.icache.overall_hits::total         841895                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       109497                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       109497                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       109497                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        109497                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       109497                       # number of overall misses
-system.cpu1.icache.overall_misses::total       109497                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   1632285999                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   1632285999                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   1632285999                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   1632285999                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   1632285999                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   1632285999                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst       951392                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total       951392                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst       951392                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total       951392                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst       951392                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total       951392                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.115091                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.115091                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.115091                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.115091                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.115091                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.115091                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14907.129867                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 14907.129867                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14907.129867                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 14907.129867                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14907.129867                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 14907.129867                       # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs       108999                       # number of cycles access was blocked
+system.cpu1.rob.rob_reads                    34238592                       # The number of ROB reads
+system.cpu1.rob.rob_writes                   28901418                       # The number of ROB writes
+system.cpu1.timesIdled                         230949                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                        1939000                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                  3778341690                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                   11789199                       # Number of Instructions Simulated
+system.cpu1.committedOps                     11789199                       # Number of Ops (including micro ops) Simulated
+system.cpu1.committedInsts_total             11789199                       # Number of Instructions Simulated
+system.cpu1.cpi                              1.926960                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        1.926960                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.518952                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.518952                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads                16196586                       # number of integer regfile reads
+system.cpu1.int_regfile_writes                8796247                       # number of integer regfile writes
+system.cpu1.fp_regfile_reads                    73611                       # number of floating regfile reads
+system.cpu1.fp_regfile_writes                   74214                       # number of floating regfile writes
+system.cpu1.misc_regfile_reads                 699711                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes                299448                       # number of misc regfile writes
+system.cpu1.icache.replacements                315447                       # number of replacements
+system.cpu1.icache.tagsinuse               471.003081                       # Cycle average of tags in use
+system.cpu1.icache.total_refs                 1635327                       # Total number of references to valid blocks.
+system.cpu1.icache.sampled_refs                315959                       # Sample count of references to valid blocks.
+system.cpu1.icache.avg_refs                  5.175757                       # Average number of references to valid blocks.
+system.cpu1.icache.warmup_cycle          1877367216000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.occ_blocks::cpu1.inst   471.003081                       # Average occupied blocks per requestor
+system.cpu1.icache.occ_percent::cpu1.inst     0.919928                       # Average percentage of cache occupancy
+system.cpu1.icache.occ_percent::total        0.919928                       # Average percentage of cache occupancy
+system.cpu1.icache.ReadReq_hits::cpu1.inst      1635327                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total        1635327                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst      1635327                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total         1635327                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst      1635327                       # number of overall hits
+system.cpu1.icache.overall_hits::total        1635327                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       328187                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       328187                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       328187                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        328187                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       328187                       # number of overall misses
+system.cpu1.icache.overall_misses::total       328187                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   5323842998                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   5323842998                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   5323842998                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   5323842998                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   5323842998                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   5323842998                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst      1963514                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total      1963514                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst      1963514                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total      1963514                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst      1963514                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total      1963514                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.167143                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.167143                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.167143                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.167143                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.167143                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.167143                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 16221.980145                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 16221.980145                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 16221.980145                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 16221.980145                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 16221.980145                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 16221.980145                       # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs       228998                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs               15                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs               37                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs  7266.600000                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs  6189.135135                       # average number of cycles each access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.writebacks::writebacks           39                       # number of writebacks
-system.cpu1.icache.writebacks::total               39                       # number of writebacks
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst         5150                       # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total         5150                       # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst         5150                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total         5150                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst         5150                       # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total         5150                       # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       104347                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       104347                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       104347                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       104347                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       104347                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       104347                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   1240890499                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   1240890499                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   1240890499                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   1240890499                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   1240890499                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   1240890499                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.109678                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.109678                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.109678                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.109678                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.109678                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.109678                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11891.961427                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11891.961427                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11891.961427                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 11891.961427                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11891.961427                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 11891.961427                       # average overall mshr miss latency
+system.cpu1.icache.writebacks::writebacks           38                       # number of writebacks
+system.cpu1.icache.writebacks::total               38                       # number of writebacks
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        12173                       # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total        12173                       # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst        12173                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total        12173                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst        12173                       # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total        12173                       # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       316014                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       316014                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       316014                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       316014                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       316014                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       316014                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   4183208998                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   4183208998                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   4183208998                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   4183208998                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   4183208998                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   4183208998                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.160943                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.160943                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.160943                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.160943                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.160943                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.160943                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13237.416690                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13237.416690                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13237.416690                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 13237.416690                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13237.416690                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 13237.416690                       # average overall mshr miss latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.replacements                 49122                       # number of replacements
-system.cpu1.dcache.tagsinuse               427.490507                       # Cycle average of tags in use
-system.cpu1.dcache.total_refs                 1549420                       # Total number of references to valid blocks.
-system.cpu1.dcache.sampled_refs                 49435                       # Sample count of references to valid blocks.
-system.cpu1.dcache.avg_refs                 31.342571                       # Average number of references to valid blocks.
-system.cpu1.dcache.warmup_cycle          1873347092000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::cpu1.data   427.490507                       # Average occupied blocks per requestor
-system.cpu1.dcache.occ_percent::cpu1.data     0.834942                       # Average percentage of cache occupancy
-system.cpu1.dcache.occ_percent::total        0.834942                       # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::cpu1.data      1023689                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        1023689                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data       507974                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total        507974                       # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        14665                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        14665                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        12767                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        12767                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data      1531663                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total         1531663                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data      1531663                       # number of overall hits
-system.cpu1.dcache.overall_hits::total        1531663                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data        89035                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total        89035                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data       104470                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total       104470                       # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         1314                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total         1314                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data          680                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total          680                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       193505                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        193505                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       193505                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       193505                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   1323211000                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   1323211000                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   3353600320                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total   3353600320                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     16083500                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total     16083500                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data      7995500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total      7995500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data   4676811320                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total   4676811320                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data   4676811320                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total   4676811320                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      1112724                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      1112724                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data       612444                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total       612444                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        15979                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        15979                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        13447                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        13447                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data      1725168                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total      1725168                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data      1725168                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total      1725168                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.080015                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.080015                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.170579                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.170579                       # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.082233                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.082233                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.050569                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.050569                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.112166                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.112166                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.112166                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.112166                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14861.694839                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 14861.694839                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32101.084713                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 32101.084713                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12240.106545                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12240.106545                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 11758.088235                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 11758.088235                       # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24168.943025                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 24168.943025                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24168.943025                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 24168.943025                       # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs     52059498                       # number of cycles access was blocked
+system.cpu1.dcache.replacements                159076                       # number of replacements
+system.cpu1.dcache.tagsinuse               488.854290                       # Cycle average of tags in use
+system.cpu1.dcache.total_refs                 3388834                       # Total number of references to valid blocks.
+system.cpu1.dcache.sampled_refs                159588                       # Sample count of references to valid blocks.
+system.cpu1.dcache.avg_refs                 21.234892                       # Average number of references to valid blocks.
+system.cpu1.dcache.warmup_cycle           42819944000                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.occ_blocks::cpu1.data   488.854290                       # Average occupied blocks per requestor
+system.cpu1.dcache.occ_percent::cpu1.data     0.954794                       # Average percentage of cache occupancy
+system.cpu1.dcache.occ_percent::total        0.954794                       # Average percentage of cache occupancy
+system.cpu1.dcache.ReadReq_hits::cpu1.data      2022458                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        2022458                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      1251052                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       1251052                       # number of WriteReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        49972                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        49972                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        48601                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        48601                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data      3273510                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total         3273510                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data      3273510                       # number of overall hits
+system.cpu1.dcache.overall_hits::total        3273510                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       307183                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       307183                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data       360837                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total       360837                       # number of WriteReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         8700                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total         8700                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data         5048                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total         5048                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       668020                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        668020                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       668020                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       668020                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   6372115000                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   6372115000                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  11323925707                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total  11323925707                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    121529000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total    121529000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     68413000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total     68413000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data  17696040707                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total  17696040707                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data  17696040707                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total  17696040707                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      2329641                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      2329641                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      1611889                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      1611889                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        58672                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        58672                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        53649                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        53649                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data      3941530                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total      3941530                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data      3941530                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total      3941530                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.131859                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.131859                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.223860                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.223860                       # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.148282                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.148282                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.094093                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.094093                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.169482                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.169482                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.169482                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.169482                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20743.709776                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 20743.709776                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 31382.385141                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 31382.385141                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13968.850575                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13968.850575                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13552.496038                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 13552.496038                       # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26490.285780                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 26490.285780                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 26490.285780                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 26490.285780                       # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs     57515988                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs             4983                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs             6825                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs 10447.420831                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs  8427.250989                       # average number of cycles each access was blocked
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks        27321                       # number of writebacks
-system.cpu1.dcache.writebacks::total            27321                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        51379                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total        51379                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data        87869                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total        87869                       # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data          246                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total          246                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data       139248                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total       139248                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data       139248                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total       139248                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data        37656                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total        37656                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        16601                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total        16601                       # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         1068                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total         1068                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data          674                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total          674                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data        54257                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total        54257                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data        54257                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total        54257                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data    431650500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total    431650500                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data    497061484                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total    497061484                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data      9472500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total      9472500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data      5965000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total      5965000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data    928711984                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total    928711984                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data    928711984                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total    928711984                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     18616500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     18616500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    318558500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    318558500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    337175000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total    337175000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.033841                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.033841                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.027106                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.027106                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.066838                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.066838                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.050123                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.050123                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.031450                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.031450                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.031450                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.031450                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11462.993945                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11462.993945                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29941.659177                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 29941.659177                       # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  8869.382022                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8869.382022                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  8850.148368                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  8850.148368                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17116.906279                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17116.906279                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17116.906279                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17116.906279                       # average overall mshr miss latency
+system.cpu1.dcache.writebacks::writebacks       112743                       # number of writebacks
+system.cpu1.dcache.writebacks::total           112743                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       196860                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total       196860                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       298722                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total       298722                       # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data         1021                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total         1021                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data       495582                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total       495582                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data       495582                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total       495582                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       110323                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total       110323                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        62115                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total        62115                       # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         7679                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total         7679                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data         5048                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total         5048                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       172438                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       172438                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       172438                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       172438                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1760210564                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1760210564                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   1471458330                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   1471458330                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     78242000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     78242000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     52885501                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     52885501                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   3231668894                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   3231668894                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   3231668894                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   3231668894                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     18623000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     18623000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    400648500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    400648500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    419271500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total    419271500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.047356                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.047356                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.038536                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.038536                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.130880                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.130880                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.094093                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.094093                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.043749                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.043749                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.043749                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.043749                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15955.064347                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15955.064347                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23689.259116                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23689.259116                       # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 10189.087121                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10189.087121                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 10476.525555                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 10476.525555                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18741.048342                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18741.048342                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18741.048342                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18741.048342                       # average overall mshr miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1589,161 +1589,171 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf
 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    6349                       # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei                    201504                       # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0                   72229     40.68%     40.68% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::21                    237      0.13%     40.82% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22                   1919      1.08%     41.90% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::30                      6      0.00%     41.90% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31                 103147     58.10%    100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total              177538                       # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0                    70862     49.25%     49.25% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::21                     237      0.16%     49.42% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22                    1919      1.33%     50.75% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::30                       6      0.00%     50.75% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31                   70856     49.25%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total               143880                       # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0            1857798011000     97.96%     97.96% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21               91384000      0.00%     97.97% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22              387547000      0.02%     97.99% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::30                3124500      0.00%     97.99% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31            38114922000      2.01%    100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total        1896394988500                       # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0                 0.981074                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.inst.quiesce                    6699                       # number of quiesce instructions executed
+system.cpu0.kern.inst.hwrei                    167510                       # number of hwrei instructions executed
+system.cpu0.kern.ipl_count::0                   58590     40.24%     40.24% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::21                    238      0.16%     40.40% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::22                   1924      1.32%     41.72% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::30                    340      0.23%     41.96% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31                  84509     58.04%    100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total              145601                       # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0                    57892     49.08%     49.08% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::21                     238      0.20%     49.29% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::22                    1924      1.63%     50.92% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::30                     340      0.29%     51.20% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::31                   57552     48.80%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::total               117946                       # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks::0            1862592276000     98.01%     98.01% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21               96187500      0.01%     98.02% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22              394889000      0.02%     98.04% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::30              155178500      0.01%     98.04% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31            37157854000      1.96%    100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total        1900396385000                       # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used::0                 0.988087                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31                0.686942                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total             0.810418                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.syscall::2                         8      3.51%      3.51% # number of syscalls executed
-system.cpu0.kern.syscall::3                        19      8.33%     11.84% # number of syscalls executed
-system.cpu0.kern.syscall::4                         4      1.75%     13.60% # number of syscalls executed
-system.cpu0.kern.syscall::6                        33     14.47%     28.07% # number of syscalls executed
-system.cpu0.kern.syscall::12                        1      0.44%     28.51% # number of syscalls executed
-system.cpu0.kern.syscall::17                        9      3.95%     32.46% # number of syscalls executed
-system.cpu0.kern.syscall::19                       10      4.39%     36.84% # number of syscalls executed
-system.cpu0.kern.syscall::20                        6      2.63%     39.47% # number of syscalls executed
-system.cpu0.kern.syscall::23                        1      0.44%     39.91% # number of syscalls executed
-system.cpu0.kern.syscall::24                        3      1.32%     41.23% # number of syscalls executed
-system.cpu0.kern.syscall::33                        7      3.07%     44.30% # number of syscalls executed
-system.cpu0.kern.syscall::41                        2      0.88%     45.18% # number of syscalls executed
-system.cpu0.kern.syscall::45                       36     15.79%     60.96% # number of syscalls executed
-system.cpu0.kern.syscall::47                        3      1.32%     62.28% # number of syscalls executed
-system.cpu0.kern.syscall::48                       10      4.39%     66.67% # number of syscalls executed
-system.cpu0.kern.syscall::54                       10      4.39%     71.05% # number of syscalls executed
-system.cpu0.kern.syscall::58                        1      0.44%     71.49% # number of syscalls executed
-system.cpu0.kern.syscall::59                        6      2.63%     74.12% # number of syscalls executed
-system.cpu0.kern.syscall::71                       27     11.84%     85.96% # number of syscalls executed
-system.cpu0.kern.syscall::73                        3      1.32%     87.28% # number of syscalls executed
-system.cpu0.kern.syscall::74                        7      3.07%     90.35% # number of syscalls executed
-system.cpu0.kern.syscall::87                        1      0.44%     90.79% # number of syscalls executed
-system.cpu0.kern.syscall::90                        3      1.32%     92.11% # number of syscalls executed
-system.cpu0.kern.syscall::92                        9      3.95%     96.05% # number of syscalls executed
-system.cpu0.kern.syscall::97                        2      0.88%     96.93% # number of syscalls executed
-system.cpu0.kern.syscall::98                        2      0.88%     97.81% # number of syscalls executed
-system.cpu0.kern.syscall::132                       1      0.44%     98.25% # number of syscalls executed
-system.cpu0.kern.syscall::144                       2      0.88%     99.12% # number of syscalls executed
-system.cpu0.kern.syscall::147                       2      0.88%    100.00% # number of syscalls executed
-system.cpu0.kern.syscall::total                   228                       # number of syscalls executed
+system.cpu0.kern.ipl_used::31                0.681016                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::total             0.810063                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.syscall::2                         5      2.38%      2.38% # number of syscalls executed
+system.cpu0.kern.syscall::3                        18      8.57%     10.95% # number of syscalls executed
+system.cpu0.kern.syscall::4                         3      1.43%     12.38% # number of syscalls executed
+system.cpu0.kern.syscall::6                        28     13.33%     25.71% # number of syscalls executed
+system.cpu0.kern.syscall::12                        1      0.48%     26.19% # number of syscalls executed
+system.cpu0.kern.syscall::15                        1      0.48%     26.67% # number of syscalls executed
+system.cpu0.kern.syscall::17                        9      4.29%     30.95% # number of syscalls executed
+system.cpu0.kern.syscall::19                        5      2.38%     33.33% # number of syscalls executed
+system.cpu0.kern.syscall::20                        4      1.90%     35.24% # number of syscalls executed
+system.cpu0.kern.syscall::23                        2      0.95%     36.19% # number of syscalls executed
+system.cpu0.kern.syscall::24                        4      1.90%     38.10% # number of syscalls executed
+system.cpu0.kern.syscall::33                        7      3.33%     41.43% # number of syscalls executed
+system.cpu0.kern.syscall::41                        2      0.95%     42.38% # number of syscalls executed
+system.cpu0.kern.syscall::45                       35     16.67%     59.05% # number of syscalls executed
+system.cpu0.kern.syscall::47                        4      1.90%     60.95% # number of syscalls executed
+system.cpu0.kern.syscall::48                        6      2.86%     63.81% # number of syscalls executed
+system.cpu0.kern.syscall::54                        9      4.29%     68.10% # number of syscalls executed
+system.cpu0.kern.syscall::58                        1      0.48%     68.57% # number of syscalls executed
+system.cpu0.kern.syscall::59                        4      1.90%     70.48% # number of syscalls executed
+system.cpu0.kern.syscall::71                       32     15.24%     85.71% # number of syscalls executed
+system.cpu0.kern.syscall::73                        3      1.43%     87.14% # number of syscalls executed
+system.cpu0.kern.syscall::74                        9      4.29%     91.43% # number of syscalls executed
+system.cpu0.kern.syscall::87                        1      0.48%     91.90% # number of syscalls executed
+system.cpu0.kern.syscall::90                        1      0.48%     92.38% # number of syscalls executed
+system.cpu0.kern.syscall::92                        7      3.33%     95.71% # number of syscalls executed
+system.cpu0.kern.syscall::97                        2      0.95%     96.67% # number of syscalls executed
+system.cpu0.kern.syscall::98                        2      0.95%     97.62% # number of syscalls executed
+system.cpu0.kern.syscall::132                       2      0.95%     98.57% # number of syscalls executed
+system.cpu0.kern.syscall::144                       1      0.48%     99.05% # number of syscalls executed
+system.cpu0.kern.syscall::147                       2      0.95%    100.00% # number of syscalls executed
+system.cpu0.kern.syscall::total                   210                       # number of syscalls executed
 system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu0.kern.callpal::wripir                  104      0.06%      0.06% # number of callpals executed
-system.cpu0.kern.callpal::wrmces                    1      0.00%      0.06% # number of callpals executed
-system.cpu0.kern.callpal::wrfen                     1      0.00%      0.06% # number of callpals executed
-system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.06% # number of callpals executed
-system.cpu0.kern.callpal::swpctx                 3893      2.09%      2.15% # number of callpals executed
-system.cpu0.kern.callpal::tbi                      50      0.03%      2.17% # number of callpals executed
-system.cpu0.kern.callpal::wrent                     7      0.00%      2.18% # number of callpals executed
-system.cpu0.kern.callpal::swpipl               170509     91.52%     93.70% # number of callpals executed
-system.cpu0.kern.callpal::rdps                   6338      3.40%     97.10% # number of callpals executed
-system.cpu0.kern.callpal::wrkgp                     1      0.00%     97.10% # number of callpals executed
-system.cpu0.kern.callpal::wrusp                     3      0.00%     97.10% # number of callpals executed
-system.cpu0.kern.callpal::rdusp                     9      0.00%     97.11% # number of callpals executed
-system.cpu0.kern.callpal::whami                     2      0.00%     97.11% # number of callpals executed
-system.cpu0.kern.callpal::rti                    4866      2.61%     99.72% # number of callpals executed
-system.cpu0.kern.callpal::callsys                 386      0.21%     99.93% # number of callpals executed
-system.cpu0.kern.callpal::imb                     138      0.07%    100.00% # number of callpals executed
-system.cpu0.kern.callpal::total                186310                       # number of callpals executed
-system.cpu0.kern.mode_switch::kernel             7415                       # number of protection mode switches
-system.cpu0.kern.mode_switch::user               1346                       # number of protection mode switches
+system.cpu0.kern.callpal::wripir                  439      0.29%      0.29% # number of callpals executed
+system.cpu0.kern.callpal::wrmces                    1      0.00%      0.29% # number of callpals executed
+system.cpu0.kern.callpal::wrfen                     1      0.00%      0.29% # number of callpals executed
+system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.29% # number of callpals executed
+system.cpu0.kern.callpal::swpctx                 3076      2.00%      2.29% # number of callpals executed
+system.cpu0.kern.callpal::tbi                      37      0.02%      2.32% # number of callpals executed
+system.cpu0.kern.callpal::wrent                     7      0.00%      2.32% # number of callpals executed
+system.cpu0.kern.callpal::swpipl               138810     90.43%     92.75% # number of callpals executed
+system.cpu0.kern.callpal::rdps                   6361      4.14%     96.89% # number of callpals executed
+system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.89% # number of callpals executed
+system.cpu0.kern.callpal::wrusp                     3      0.00%     96.89% # number of callpals executed
+system.cpu0.kern.callpal::rdusp                     6      0.00%     96.90% # number of callpals executed
+system.cpu0.kern.callpal::whami                     2      0.00%     96.90% # number of callpals executed
+system.cpu0.kern.callpal::rti                    4288      2.79%     99.69% # number of callpals executed
+system.cpu0.kern.callpal::callsys                 327      0.21%     99.90% # number of callpals executed
+system.cpu0.kern.callpal::imb                     146      0.10%    100.00% # number of callpals executed
+system.cpu0.kern.callpal::total                153507                       # number of callpals executed
+system.cpu0.kern.mode_switch::kernel             6690                       # number of protection mode switches
+system.cpu0.kern.mode_switch::user               1098                       # number of protection mode switches
 system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
-system.cpu0.kern.mode_good::kernel               1345                      
-system.cpu0.kern.mode_good::user                 1346                      
+system.cpu0.kern.mode_good::kernel               1098                      
+system.cpu0.kern.mode_good::user                 1098                      
 system.cpu0.kern.mode_good::idle                    0                      
-system.cpu0.kern.mode_switch_good::kernel     0.181389                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::kernel     0.164126                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total     0.307157                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel      1894436238500     99.90%     99.90% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user          1958742000      0.10%    100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_switch_good::total     0.281972                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel      1897963397000     99.90%     99.90% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user          1861803000      0.10%    100.00% # number of ticks spent at the given mode
 system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context                    3894                       # number of times the context was actually changed
+system.cpu0.kern.swap_context                    3077                       # number of times the context was actually changed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    2266                       # number of quiesce instructions executed
-system.cpu1.kern.inst.hwrei                     36241                       # number of hwrei instructions executed
-system.cpu1.kern.ipl_count::0                    9521     32.62%     32.62% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::22                   1918      6.57%     39.19% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::30                    104      0.36%     39.54% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31                  17647     60.46%    100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total               29190                       # number of times we switched to this ipl
-system.cpu1.kern.ipl_good::0                     9511     45.42%     45.42% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::22                    1918      9.16%     54.58% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::30                     104      0.50%     55.08% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::31                    9407     44.92%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::total                20940                       # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0            1870201149000     98.64%     98.64% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22              342845500      0.02%     98.65% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30               41642500      0.00%     98.66% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31            25494039500      1.34%    100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total        1896079676500                       # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used::0                 0.998950                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.inst.quiesce                    2601                       # number of quiesce instructions executed
+system.cpu1.kern.inst.hwrei                     74467                       # number of hwrei instructions executed
+system.cpu1.kern.ipl_count::0                   24565     38.36%     38.36% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::22                   1923      3.00%     41.36% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::30                    439      0.69%     42.05% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::31                  37108     57.95%    100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::total               64035                       # number of times we switched to this ipl
+system.cpu1.kern.ipl_good::0                    23886     48.07%     48.07% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::22                    1923      3.87%     51.93% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::30                     439      0.88%     52.82% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::31                   23447     47.18%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::total                49695                       # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks::0            1870827437000     98.44%     98.44% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::22              343518500      0.02%     98.46% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::30              182737500      0.01%     98.46% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::31            29176221000      1.54%    100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total        1900529914000                       # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used::0                 0.972359                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31                0.533065                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::total             0.717369                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.syscall::3                        11     11.22%     11.22% # number of syscalls executed
-system.cpu1.kern.syscall::6                         9      9.18%     20.41% # number of syscalls executed
-system.cpu1.kern.syscall::15                        1      1.02%     21.43% # number of syscalls executed
-system.cpu1.kern.syscall::17                        6      6.12%     27.55% # number of syscalls executed
-system.cpu1.kern.syscall::23                        3      3.06%     30.61% # number of syscalls executed
-system.cpu1.kern.syscall::24                        3      3.06%     33.67% # number of syscalls executed
-system.cpu1.kern.syscall::33                        4      4.08%     37.76% # number of syscalls executed
-system.cpu1.kern.syscall::45                       18     18.37%     56.12% # number of syscalls executed
-system.cpu1.kern.syscall::47                        3      3.06%     59.18% # number of syscalls executed
-system.cpu1.kern.syscall::59                        1      1.02%     60.20% # number of syscalls executed
-system.cpu1.kern.syscall::71                       27     27.55%     87.76% # number of syscalls executed
-system.cpu1.kern.syscall::74                        9      9.18%     96.94% # number of syscalls executed
-system.cpu1.kern.syscall::132                       3      3.06%    100.00% # number of syscalls executed
-system.cpu1.kern.syscall::total                    98                       # number of syscalls executed
+system.cpu1.kern.ipl_used::31                0.631858                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::total             0.776060                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.syscall::2                         3      2.59%      2.59% # number of syscalls executed
+system.cpu1.kern.syscall::3                        12     10.34%     12.93% # number of syscalls executed
+system.cpu1.kern.syscall::4                         1      0.86%     13.79% # number of syscalls executed
+system.cpu1.kern.syscall::6                        14     12.07%     25.86% # number of syscalls executed
+system.cpu1.kern.syscall::17                        6      5.17%     31.03% # number of syscalls executed
+system.cpu1.kern.syscall::19                        5      4.31%     35.34% # number of syscalls executed
+system.cpu1.kern.syscall::20                        2      1.72%     37.07% # number of syscalls executed
+system.cpu1.kern.syscall::23                        2      1.72%     38.79% # number of syscalls executed
+system.cpu1.kern.syscall::24                        2      1.72%     40.52% # number of syscalls executed
+system.cpu1.kern.syscall::33                        4      3.45%     43.97% # number of syscalls executed
+system.cpu1.kern.syscall::45                       19     16.38%     60.34% # number of syscalls executed
+system.cpu1.kern.syscall::47                        2      1.72%     62.07% # number of syscalls executed
+system.cpu1.kern.syscall::48                        4      3.45%     65.52% # number of syscalls executed
+system.cpu1.kern.syscall::54                        1      0.86%     66.38% # number of syscalls executed
+system.cpu1.kern.syscall::59                        3      2.59%     68.97% # number of syscalls executed
+system.cpu1.kern.syscall::71                       22     18.97%     87.93% # number of syscalls executed
+system.cpu1.kern.syscall::74                        7      6.03%     93.97% # number of syscalls executed
+system.cpu1.kern.syscall::90                        2      1.72%     95.69% # number of syscalls executed
+system.cpu1.kern.syscall::92                        2      1.72%     97.41% # number of syscalls executed
+system.cpu1.kern.syscall::132                       2      1.72%     99.14% # number of syscalls executed
+system.cpu1.kern.syscall::144                       1      0.86%    100.00% # number of syscalls executed
+system.cpu1.kern.syscall::total                   116                       # number of syscalls executed
 system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu1.kern.callpal::wripir                    6      0.02%      0.02% # number of callpals executed
-system.cpu1.kern.callpal::wrmces                    1      0.00%      0.03% # number of callpals executed
-system.cpu1.kern.callpal::wrfen                     1      0.00%      0.03% # number of callpals executed
-system.cpu1.kern.callpal::swpctx                  334      1.11%      1.14% # number of callpals executed
-system.cpu1.kern.callpal::tbi                       3      0.01%      1.15% # number of callpals executed
-system.cpu1.kern.callpal::wrent                     7      0.02%      1.17% # number of callpals executed
-system.cpu1.kern.callpal::swpipl                24745     82.19%     83.36% # number of callpals executed
-system.cpu1.kern.callpal::rdps                   2407      7.99%     91.36% # number of callpals executed
-system.cpu1.kern.callpal::wrkgp                     1      0.00%     91.36% # number of callpals executed
-system.cpu1.kern.callpal::wrusp                     4      0.01%     91.37% # number of callpals executed
-system.cpu1.kern.callpal::whami                     3      0.01%     91.38% # number of callpals executed
-system.cpu1.kern.callpal::rti                    2422      8.04%     99.43% # number of callpals executed
-system.cpu1.kern.callpal::callsys                 129      0.43%     99.86% # number of callpals executed
-system.cpu1.kern.callpal::imb                      42      0.14%    100.00% # number of callpals executed
+system.cpu1.kern.callpal::wripir                  340      0.51%      0.51% # number of callpals executed
+system.cpu1.kern.callpal::wrmces                    1      0.00%      0.51% # number of callpals executed
+system.cpu1.kern.callpal::wrfen                     1      0.00%      0.52% # number of callpals executed
+system.cpu1.kern.callpal::swpctx                 1824      2.74%      3.26% # number of callpals executed
+system.cpu1.kern.callpal::tbi                      16      0.02%      3.28% # number of callpals executed
+system.cpu1.kern.callpal::wrent                     7      0.01%      3.29% # number of callpals executed
+system.cpu1.kern.callpal::swpipl                57992     87.22%     90.51% # number of callpals executed
+system.cpu1.kern.callpal::rdps                   2394      3.60%     94.11% # number of callpals executed
+system.cpu1.kern.callpal::wrkgp                     1      0.00%     94.11% # number of callpals executed
+system.cpu1.kern.callpal::wrusp                     4      0.01%     94.12% # number of callpals executed
+system.cpu1.kern.callpal::rdusp                     3      0.00%     94.13% # number of callpals executed
+system.cpu1.kern.callpal::whami                     3      0.00%     94.13% # number of callpals executed
+system.cpu1.kern.callpal::rti                    3680      5.53%     99.66% # number of callpals executed
+system.cpu1.kern.callpal::callsys                 188      0.28%     99.95% # number of callpals executed
+system.cpu1.kern.callpal::imb                      34      0.05%    100.00% # number of callpals executed
 system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
-system.cpu1.kern.callpal::total                 30107                       # number of callpals executed
-system.cpu1.kern.mode_switch::kernel              710                       # number of protection mode switches
-system.cpu1.kern.mode_switch::user                392                       # number of protection mode switches
-system.cpu1.kern.mode_switch::idle               2048                       # number of protection mode switches
-system.cpu1.kern.mode_good::kernel                420                      
-system.cpu1.kern.mode_good::user                  392                      
-system.cpu1.kern.mode_good::idle                   28                      
-system.cpu1.kern.mode_switch_good::kernel     0.591549                       # fraction of useful protection mode switches
+system.cpu1.kern.callpal::total                 66490                       # number of callpals executed
+system.cpu1.kern.mode_switch::kernel             2119                       # number of protection mode switches
+system.cpu1.kern.mode_switch::user                641                       # number of protection mode switches
+system.cpu1.kern.mode_switch::idle               2717                       # number of protection mode switches
+system.cpu1.kern.mode_good::kernel               1003                      
+system.cpu1.kern.mode_good::user                  641                      
+system.cpu1.kern.mode_good::idle                  362                      
+system.cpu1.kern.mode_switch_good::kernel     0.473336                       # fraction of useful protection mode switches
 system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::idle      0.013672                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::total     0.266667                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel        1688462500      0.09%      0.09% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user           719657500      0.04%      0.13% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle        1893332404000     99.87%    100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context                     335                       # number of times the context was actually changed
+system.cpu1.kern.mode_switch_good::idle      0.133235                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good::total     0.366259                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_ticks::kernel        7877043500      0.41%      0.41% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::user           912149500      0.05%      0.46% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::idle        1891740713000     99.54%    100.00% # number of ticks spent at the given mode
+system.cpu1.kern.swap_context                    1825                       # number of times the context was actually changed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
index 3ccfd349b..b1df0f096 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
@@ -517,7 +517,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=true
-width=64
+width=8
 default=system.tsunami.pciconfig.pio
 master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
 slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
@@ -579,7 +579,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 default=system.membus.badaddr_responder.pio
 master=system.bridge.slave system.physmem.port[0]
 slave=system.system_port system.iocache.mem_side system.l2c.mem_side
@@ -636,7 +636,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.l2c.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
index 3b2f5c4a1..a30a37ba8 100755
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
@@ -1,11 +1,11 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:05:18
-gem5 started Jun 28 2012 22:47:37
+gem5 compiled Jul  2 2012 08:30:56
+gem5 started Jul  2 2012 11:00:25
 gem5 executing on zizzer
 command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/vmlinux
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 1858879782500 because m5_exit instruction encountered
+Exiting @ tick 1865402113500 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
index 90f62bf97..a9a5c3cb0 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
@@ -1,142 +1,142 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.858880                       # Number of seconds simulated
-sim_ticks                                1858879782500                       # Number of ticks simulated
-final_tick                               1858879782500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.865402                       # Number of seconds simulated
+sim_ticks                                1865402113500                       # Number of ticks simulated
+final_tick                               1865402113500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 196297                       # Simulator instruction rate (inst/s)
-host_op_rate                                   196297                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             6876664069                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 298988                       # Number of bytes of host memory used
-host_seconds                                   270.32                       # Real time elapsed on the host
-sim_insts                                    53062487                       # Number of instructions simulated
-sim_ops                                      53062487                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst            969088                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          24884032                       # Number of bytes read from this memory
+host_inst_rate                                 131129                       # Simulator instruction rate (inst/s)
+host_op_rate                                   131129                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             4607058697                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 298956                       # Number of bytes of host memory used
+host_seconds                                   404.90                       # Real time elapsed on the host
+sim_insts                                    53094243                       # Number of instructions simulated
+sim_ops                                      53094243                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst            967424                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          24877312                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide        2652288                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             28505408                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       969088                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          969088                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7524864                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7524864                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst              15142                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             388813                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total             28497024                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       967424                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          967424                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7516928                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7516928                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst              15116                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             388708                       # Number of read requests responded to by this memory
 system.physmem.num_reads::tsunami.ide           41442                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                445397                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          117576                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               117576                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               521329                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             13386574                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide           1426821                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                15334724                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          521329                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             521329                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           4048064                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4048064                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           4048064                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              521329                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            13386574                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide          1426821                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               19382788                       # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements                        338457                       # number of replacements
-system.l2c.tagsinuse                     65351.732427                       # Cycle average of tags in use
-system.l2c.total_refs                         2557615                       # Total number of references to valid blocks.
-system.l2c.sampled_refs                        403631                       # Sample count of references to valid blocks.
-system.l2c.avg_refs                          6.336518                       # Average number of references to valid blocks.
-system.l2c.warmup_cycle                    4816079000                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks        53832.150010                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.inst           5352.172668                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.data           6167.409749                       # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks           0.821413                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.inst             0.081668                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.data             0.094107                       # Average percentage of cache occupancy
-system.l2c.occ_percent::total                0.997188                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu.inst             1006386                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.data              826813                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1833199                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          841169                       # number of Writeback hits
-system.l2c.Writeback_hits::total               841169                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu.data               15                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                  15                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu.data              1                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                 1                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu.data            185491                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               185491                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu.inst              1006386                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.data              1012304                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2018690                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu.inst             1006386                       # number of overall hits
-system.l2c.overall_hits::cpu.data             1012304                       # number of overall hits
-system.l2c.overall_hits::total                2018690                       # number of overall hits
-system.l2c.ReadReq_misses::cpu.inst             15144                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu.data            273879                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total               289023                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu.data             27                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total                27                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu.data          115423                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             115423                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu.inst              15144                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu.data             389302                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                404446                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu.inst             15144                       # number of overall misses
-system.l2c.overall_misses::cpu.data            389302                       # number of overall misses
-system.l2c.overall_misses::total               404446                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu.inst    792218000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu.data  14246173000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total    15038391000                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu.data       322000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total       322000                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu.data   6056487000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   6056487000                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu.inst    792218000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.data  20302660000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total     21094878000                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu.inst    792218000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu.data  20302660000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    21094878000                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu.inst         1021530                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.data         1100692                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2122222                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       841169                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           841169                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu.data           42                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total              42                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu.data            1                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total             1                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu.data        300914                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           300914                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu.inst          1021530                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.data          1401606                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2423136                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu.inst         1021530                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.data         1401606                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2423136                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu.inst       0.014825                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.data       0.248824                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.136189                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu.data     0.642857                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.642857                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu.data     0.383575                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.383575                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu.inst        0.014825                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.data        0.277754                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.166910                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu.inst       0.014825                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.data       0.277754                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.166910                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu.inst 52312.334918                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu.data 52016.302820                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 52031.814077                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu.data 11925.925926                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 11925.925926                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu.data 52472.098282                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 52472.098282                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu.inst 52312.334918                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu.data 52151.440270                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 52157.464779                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.inst 52312.334918                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.data 52151.440270                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 52157.464779                       # average overall miss latency
+system.physmem.num_reads::total                445266                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          117452                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               117452                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               518614                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             13336166                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide           1421832                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                15276612                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          518614                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             518614                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           4029656                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                4029656                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           4029656                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              518614                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            13336166                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide          1421832                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               19306267                       # Total bandwidth to/from this memory (bytes/s)
+system.l2c.replacements                        338323                       # number of replacements
+system.l2c.tagsinuse                     65346.781313                       # Cycle average of tags in use
+system.l2c.total_refs                         2566599                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                        403491                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                          6.360982                       # Average number of references to valid blocks.
+system.l2c.warmup_cycle                    4861120000                       # Cycle when the warmup percentage was hit.
+system.l2c.occ_blocks::writebacks        53937.288272                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.inst           5357.413768                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.data           6052.079273                       # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks           0.823018                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.inst             0.081748                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.data             0.092347                       # Average percentage of cache occupancy
+system.l2c.occ_percent::total                0.997113                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu.inst             1010692                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.data              829338                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1840030                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          843192                       # number of Writeback hits
+system.l2c.Writeback_hits::total               843192                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu.data               35                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                  35                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu.data              4                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total                 4                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu.data            185767                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               185767                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu.inst              1010692                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.data              1015105                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 2025797                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu.inst             1010692                       # number of overall hits
+system.l2c.overall_hits::cpu.data             1015105                       # number of overall hits
+system.l2c.overall_hits::total                2025797                       # number of overall hits
+system.l2c.ReadReq_misses::cpu.inst             15118                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.data            273845                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total               288963                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu.data             49                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total                49                       # number of UpgradeReq misses
+system.l2c.ReadExReq_misses::cpu.data          115352                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             115352                       # number of ReadExReq misses
+system.l2c.demand_misses::cpu.inst              15118                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.data             389197                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                404315                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu.inst             15118                       # number of overall misses
+system.l2c.overall_misses::cpu.data            389197                       # number of overall misses
+system.l2c.overall_misses::total               404315                       # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu.inst    805739998                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.data  14260725000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total    15066464998                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu.data       501500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total       501500                       # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu.data   6190534997                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   6190534997                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu.inst    805739998                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.data  20451259997                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total     21256999995                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu.inst    805739998                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu.data  20451259997                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total    21256999995                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu.inst         1025810                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.data         1103183                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            2128993                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       843192                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           843192                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu.data           84                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total              84                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu.data            4                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total             4                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu.data        301119                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           301119                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu.inst          1025810                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.data          1404302                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             2430112                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu.inst         1025810                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.data         1404302                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            2430112                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu.inst       0.014738                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.data       0.248232                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.135728                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu.data     0.583333                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.583333                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu.data     0.383078                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.383078                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu.inst        0.014738                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.data        0.277146                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.166377                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu.inst       0.014738                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.data       0.277146                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.166377                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu.inst 53296.732240                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.data 52075.900601                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 52139.772213                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu.data 10234.693878                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 10234.693878                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu.data 53666.473030                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 53666.473030                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu.inst 53296.732240                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.data 52547.321786                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 52575.343470                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.inst 53296.732240                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.data 52547.321786                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 52575.343470                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -145,72 +145,72 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               76064                       # number of writebacks
-system.l2c.writebacks::total                    76064                       # number of writebacks
+system.l2c.writebacks::writebacks               75940                       # number of writebacks
+system.l2c.writebacks::total                    75940                       # number of writebacks
 system.l2c.ReadReq_mshr_hits::cpu.inst              1                       # number of ReadReq MSHR hits
 system.l2c.ReadReq_mshr_hits::total                 1                       # number of ReadReq MSHR hits
 system.l2c.demand_mshr_hits::cpu.inst               1                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_hits::total                  1                       # number of demand (read+write) MSHR hits
 system.l2c.overall_mshr_hits::cpu.inst              1                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::total                 1                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu.inst        15143                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu.data       273879                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total          289022                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu.data           27                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total           27                       # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu.data       115423                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        115423                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu.inst         15143                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu.data        389302                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           404445                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu.inst        15143                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu.data       389302                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          404445                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu.inst    606782500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu.data  10958767000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total  11565549500                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu.data      1142000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total      1142000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu.data   4653345000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   4653345000                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.inst    606782500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.data  15612112000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  16218894500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.inst    606782500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.data  15612112000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  16218894500                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data    810071000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total    810071000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data   1114787998                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   1114787998                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu.data   1924858998                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   1924858998                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.014824                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.248824                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.136188                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.642857                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.642857                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.383575                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.383575                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu.inst     0.014824                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu.data     0.277754                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.166910                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu.inst     0.014824                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu.data     0.277754                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.166910                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40070.164432                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40013.170050                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 40016.156210                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 42296.296296                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 42296.296296                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40315.578351                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 40315.578351                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40070.164432                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.data 40102.830194                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 40101.607141                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40070.164432                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.data 40102.830194                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 40101.607141                       # average overall mshr miss latency
+system.l2c.ReadReq_mshr_misses::cpu.inst        15117                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.data       273845                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total          288962                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu.data           49                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total           49                       # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu.data       115352                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        115352                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu.inst         15117                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu.data        389197                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           404314                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu.inst        15117                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu.data       389197                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          404314                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu.inst    620965998                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.data  10975082500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total  11596048498                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu.data      2065000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total      2065000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu.data   4796966997                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   4796966997                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.inst    620965998                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.data  15772049497                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  16393015495                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.inst    620965998                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.data  15772049497                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  16393015495                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data    810224030                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total    810224030                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data   1103797000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   1103797000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu.data   1914021030                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   1914021030                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.014737                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.248232                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.135727                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.583333                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.583333                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.383078                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.383078                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu.inst     0.014737                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.data     0.277146                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.166377                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu.inst     0.014737                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.data     0.277146                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.166377                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41077.330026                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40077.717322                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 40130.011898                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 42142.857143                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 42142.857143                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 41585.468800                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 41585.468800                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41077.330026                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.data 40524.591652                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 40545.258129                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41077.330026                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.data 40524.591652                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 40545.258129                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -219,14 +219,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data          inf
 system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.iocache.replacements                     41685                       # number of replacements
-system.iocache.tagsinuse                     1.268378                       # Cycle average of tags in use
+system.iocache.tagsinuse                     1.294799                       # Cycle average of tags in use
 system.iocache.total_refs                           0                       # Total number of references to valid blocks.
 system.iocache.sampled_refs                     41701                       # Sample count of references to valid blocks.
 system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
-system.iocache.warmup_cycle              1708338896000                       # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::tsunami.ide       1.268378                       # Average occupied blocks per requestor
-system.iocache.occ_percent::tsunami.ide      0.079274                       # Average percentage of cache occupancy
-system.iocache.occ_percent::total            0.079274                       # Average percentage of cache occupancy
+system.iocache.warmup_cycle              1711277767000                       # Cycle when the warmup percentage was hit.
+system.iocache.occ_blocks::tsunami.ide       1.294799                       # Average occupied blocks per requestor
+system.iocache.occ_percent::tsunami.ide      0.080925                       # Average percentage of cache occupancy
+system.iocache.occ_percent::total            0.080925                       # Average percentage of cache occupancy
 system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
 system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
@@ -235,14 +235,14 @@ system.iocache.demand_misses::tsunami.ide        41725                       # n
 system.iocache.demand_misses::total             41725                       # number of demand (read+write) misses
 system.iocache.overall_misses::tsunami.ide        41725                       # number of overall misses
 system.iocache.overall_misses::total            41725                       # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide     19937998                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     19937998                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::tsunami.ide   5721900806                       # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total   5721900806                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide   5741838804                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   5741838804                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide   5741838804                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   5741838804                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::tsunami.ide     20672998                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     20672998                       # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::tsunami.ide   7641897806                       # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total   7641897806                       # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide   7662570804                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   7662570804                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide   7662570804                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   7662570804                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
@@ -259,19 +259,19 @@ system.iocache.demand_miss_rate::tsunami.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115248.543353                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 115248.543353                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137704.582355                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 137704.582355                       # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 137611.475231                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 137611.475231                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 137611.475231                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 137611.475231                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs      64649068                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119497.098266                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 119497.098266                       # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183911.672266                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 183911.672266                       # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 183644.596860                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 183644.596860                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 183644.596860                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 183644.596860                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs       7656000                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                10476                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 7143                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs  6171.159603                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs  1071.818564                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -285,14 +285,14 @@ system.iocache.demand_mshr_misses::tsunami.ide        41725
 system.iocache.demand_mshr_misses::total        41725                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::tsunami.ide        41725                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total        41725                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     10941998                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     10941998                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::tsunami.ide   3561047996                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total   3561047996                       # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide   3571989994                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   3571989994                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide   3571989994                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   3571989994                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     11676000                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     11676000                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::tsunami.ide   5481043992                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total   5481043992                       # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide   5492719992                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   5492719992                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide   5492719992                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   5492719992                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
@@ -301,14 +301,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63248.543353                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 63248.543353                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85701.001059                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 85701.001059                       # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85607.908784                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 85607.908784                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85607.908784                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 85607.908784                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67491.329480                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 67491.329480                       # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131908.066808                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 131908.066808                       # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131640.982433                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 131640.982433                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131640.982433                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 131640.982433                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -326,22 +326,22 @@ system.cpu.dtb.fetch_hits                           0                       # IT
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                      9957395                       # DTB read hits
-system.cpu.dtb.read_misses                      44300                       # DTB read misses
-system.cpu.dtb.read_acv                           564                       # DTB read access violations
-system.cpu.dtb.read_accesses                   948872                       # DTB read accesses
-system.cpu.dtb.write_hits                     6634412                       # DTB write hits
-system.cpu.dtb.write_misses                     10394                       # DTB write misses
-system.cpu.dtb.write_acv                          384                       # DTB write access violations
-system.cpu.dtb.write_accesses                  338929                       # DTB write accesses
-system.cpu.dtb.data_hits                     16591807                       # DTB hits
-system.cpu.dtb.data_misses                      54694                       # DTB misses
-system.cpu.dtb.data_acv                           948                       # DTB access violations
-system.cpu.dtb.data_accesses                  1287801                       # DTB accesses
-system.cpu.itb.fetch_hits                     1332166                       # ITB hits
-system.cpu.itb.fetch_misses                     40283                       # ITB misses
-system.cpu.itb.fetch_acv                         1114                       # ITB acv
-system.cpu.itb.fetch_accesses                 1372449                       # ITB accesses
+system.cpu.dtb.read_hits                      9972402                       # DTB read hits
+system.cpu.dtb.read_misses                      43929                       # DTB read misses
+system.cpu.dtb.read_acv                           494                       # DTB read access violations
+system.cpu.dtb.read_accesses                   957886                       # DTB read accesses
+system.cpu.dtb.write_hits                     6649938                       # DTB write hits
+system.cpu.dtb.write_misses                     10071                       # DTB write misses
+system.cpu.dtb.write_acv                          391                       # DTB write access violations
+system.cpu.dtb.write_accesses                  340693                       # DTB write accesses
+system.cpu.dtb.data_hits                     16622340                       # DTB hits
+system.cpu.dtb.data_misses                      54000                       # DTB misses
+system.cpu.dtb.data_acv                           885                       # DTB access violations
+system.cpu.dtb.data_accesses                  1298579                       # DTB accesses
+system.cpu.itb.fetch_hits                     1343669                       # ITB hits
+system.cpu.itb.fetch_misses                     37345                       # ITB misses
+system.cpu.itb.fetch_acv                         1146                       # ITB acv
+system.cpu.itb.fetch_accesses                 1381014                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -354,279 +354,279 @@ system.cpu.itb.data_hits                            0                       # DT
 system.cpu.itb.data_misses                          0                       # DTB misses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.numCycles                        114963877                       # number of cpu cycles simulated
+system.cpu.numCycles                        122571263                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                 13985774                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted           11671873                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect             444413                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups              10112209                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                  5892039                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                 14075987                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           11741614                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect             452517                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              10126525                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                  5926302                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                   933191                       # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect               42453                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles           29251616                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                       71181997                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    13985774                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            6825230                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      13396576                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 2069716                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles               36268090                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                34293                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        258776                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles       311439                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          136                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                   8761444                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                288106                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples           80878220                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.880113                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.220739                       # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS                   942334                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect               45003                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles           31564050                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                       71567580                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    14075987                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            6868636                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      13486844                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 2151091                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               41804632                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                33708                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        276041                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles       314295                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          187                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                   8859322                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                305645                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples           88896899                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.805063                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.137281                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 67481644     83.44%     83.44% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                   875531      1.08%     84.52% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  1743396      2.16%     86.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                   848384      1.05%     87.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  2751006      3.40%     91.12% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                   598052      0.74%     91.86% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                   674963      0.83%     92.70% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1011492      1.25%     93.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                  4893752      6.05%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 75410055     84.83%     84.83% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                   885656      1.00%     85.82% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  1762066      1.98%     87.81% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                   856601      0.96%     88.77% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  2772547      3.12%     91.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                   605003      0.68%     92.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                   676052      0.76%     93.33% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1014878      1.14%     94.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                  4914041      5.53%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total             80878220                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.121654                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.619168                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 30302953                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              36036206                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  12267887                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                956730                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                1314443                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved               612620                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 43298                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts               69919175                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                129721                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                1314443                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 31429322                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                12715444                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       19630106                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  11479703                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               4309200                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts               66239771                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                  6813                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 505927                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               1528052                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands            44253229                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups              80320067                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups         79838854                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups            481213                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps              38235996                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                  6017225                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts            1699905                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts         247549                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  12108783                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             10535735                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores             6944708                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1299665                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores           826518                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                   58678192                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             2085341                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                  57178934                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            114167                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined         7323387                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined      3670404                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved        1417353                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples      80878220                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.706976                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.364710                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total             88896899                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.114839                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.583885                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 32604567                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              41610698                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  12250426                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               1057078                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                1374129                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved               617310                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 43428                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts               70293890                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                133239                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                1374129                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 33752767                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                16324711                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       21058224                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  11548980                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               4838086                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts               66572257                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                  7187                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 753146                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               1801877                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands            44498273                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups              80714962                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups         80226097                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups            488865                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps              38261328                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                  6236937                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            1703640                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts         251709                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  12757763                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             10570492                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores             6981683                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1316603                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores           922104                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                   58981346                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             2097651                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                  57326676                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            120953                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined         7579711                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined      3887654                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved        1429592                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples      88896899                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.644867                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.291957                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            55943146     69.17%     69.17% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            11029219     13.64%     82.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             5183069      6.41%     89.21% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             3467547      4.29%     93.50% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             2613614      3.23%     96.73% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             1475312      1.82%     98.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6              724581      0.90%     99.45% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              331422      0.41%     99.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              110310      0.14%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            62967728     70.83%     70.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            12048856     13.55%     84.39% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             5390899      6.06%     90.45% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             3449544      3.88%     94.33% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             2613461      2.94%     97.27% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             1329807      1.50%     98.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6              686975      0.77%     99.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              354371      0.40%     99.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8               55258      0.06%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total        80878220                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        88896899                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                   90406     11.39%     11.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     11.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     11.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     11.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     11.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     11.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     11.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     11.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     11.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     11.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     11.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     11.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     11.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     11.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     11.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     11.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     11.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     11.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     11.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     11.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     11.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     11.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     11.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     11.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     11.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     11.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     11.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     11.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     11.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                 375907     47.36%     58.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                327352     41.25%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   75491     10.00%     10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 363771     48.19%     58.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                315594     41.81%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass              7281      0.01%      0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              39009688     68.22%     68.24% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                61923      0.11%     68.34% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     68.34% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd               25607      0.04%     68.39% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     68.39% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     68.39% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     68.39% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                3636      0.01%     68.40% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     68.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     68.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     68.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     68.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     68.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     68.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     68.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     68.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     68.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     68.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     68.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     68.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     68.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     68.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     68.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     68.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     68.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     68.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     68.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     68.40% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             10404436     18.20%     86.59% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             6713568     11.74%     98.33% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess             952795      1.67%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass              7291      0.01%      0.01% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              39127581     68.25%     68.27% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                61956      0.11%     68.37% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     68.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd               25607      0.04%     68.42% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     68.42% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     68.42% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     68.42% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                3636      0.01%     68.43% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     68.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     68.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     68.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     68.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     68.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     68.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     68.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     68.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     68.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     68.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     68.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     68.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     68.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     68.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     68.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     68.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     68.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     68.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     68.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     68.43% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             10418296     18.17%     86.60% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             6729507     11.74%     98.34% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess             952802      1.66%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total               57178934                       # Type of FU issued
-system.cpu.iq.rate                           0.497364                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                      793665                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.013880                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          195448703                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes          67761433                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     55894957                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads              695216                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes             339032                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses       327938                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses               57602239                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                  363079                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads           589978                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total               57326676                       # Type of FU issued
+system.cpu.iq.rate                           0.467701                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                      754856                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.013168                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          203729346                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes          68333375                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     56036726                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads              696713                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes             339202                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses       327718                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses               57709702                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                  364539                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads           594776                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      1427299                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         3440                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        13878                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores       554882                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      1456655                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         2870                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        14252                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores       588832                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        18323                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        151980                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        18348                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        104302                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                1314443                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 8887747                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                615033                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts            64324837                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            661005                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              10535735                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts              6944708                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            1835122                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 481853                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 16088                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          13878                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         240769                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       420658                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               661427                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts              56655096                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              10030988                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            523837                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                1374129                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                11393417                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                869281                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts            64652535                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            684492                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              10570492                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts              6981683                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            1845589                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 621506                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 12714                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          14252                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         241539                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       423865                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               665404                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts              56791406                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              10044983                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            535269                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                       3561304                       # number of nop insts executed
-system.cpu.iew.exec_refs                     16691010                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                  8986521                       # Number of branches executed
-system.cpu.iew.exec_stores                    6660022                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.492808                       # Inst execution rate
-system.cpu.iew.wb_sent                       56341255                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      56222895                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  27828941                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  37695611                       # num instructions consuming a value
+system.cpu.iew.exec_nop                       3573538                       # number of nop insts executed
+system.cpu.iew.exec_refs                     16720258                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                  9005988                       # Number of branches executed
+system.cpu.iew.exec_stores                    6675275                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.463334                       # Inst execution rate
+system.cpu.iew.wb_sent                       56476627                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      56364444                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  27797872                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  37663953                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.489048                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.738254                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.459850                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.738050                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts       56255888                       # The number of committed instructions
-system.cpu.commit.commitCommittedOps         56255888                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts         7955379                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls          667988                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            613263                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples     79563777                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.707054                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.631051                       # Number of insts commited each cycle
+system.cpu.commit.commitCommittedInsts       56288834                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps         56288834                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts         8251602                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls          668059                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            621198                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples     87522770                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.643134                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.558246                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     58612311     73.67%     73.67% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1      8734565     10.98%     84.65% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      4655391      5.85%     90.50% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      2574186      3.24%     93.73% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1496332      1.88%     95.61% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5       659939      0.83%     96.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       486345      0.61%     97.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       472774      0.59%     97.65% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      1871934      2.35%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     66254825     75.70%     75.70% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1      8962066     10.24%     85.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      4828588      5.52%     91.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      2603942      2.98%     94.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1449491      1.66%     96.09% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5       603705      0.69%     96.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       515511      0.59%     97.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       488925      0.56%     97.93% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      1815717      2.07%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total     79563777                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts             56255888                       # Number of instructions committed
-system.cpu.commit.committedOps               56255888                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total     87522770                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts             56288834                       # Number of instructions committed
+system.cpu.commit.committedOps               56288834                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       15498262                       # Number of memory references committed
-system.cpu.commit.loads                       9108436                       # Number of loads committed
-system.cpu.commit.membars                      227920                       # Number of memory barriers committed
-system.cpu.commit.branches                    8459857                       # Number of branches committed
+system.cpu.commit.refs                       15506688                       # Number of memory references committed
+system.cpu.commit.loads                       9113837                       # Number of loads committed
+system.cpu.commit.membars                      227975                       # Number of memory barriers committed
+system.cpu.commit.branches                    8463674                       # Number of branches committed
 system.cpu.commit.fp_insts                     324384                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                  52095164                       # Number of committed integer instructions.
-system.cpu.commit.function_calls               744157                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events               1871934                       # number cycles where commit BW limit reached
+system.cpu.commit.int_insts                  52126817                       # Number of committed integer instructions.
+system.cpu.commit.function_calls               744625                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events               1815717                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    141652037                       # The number of ROB reads
-system.cpu.rob.rob_writes                   129738562                       # The number of ROB writes
-system.cpu.timesIdled                         1269768                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        34085657                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   3602789251                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                    53062487                       # Number of Instructions Simulated
-system.cpu.committedOps                      53062487                       # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total              53062487                       # Number of Instructions Simulated
-system.cpu.cpi                               2.166575                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         2.166575                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.461558                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.461558                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                 74266984                       # number of integer regfile reads
-system.cpu.int_regfile_writes                40553865                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                    166054                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                   167450                       # number of floating regfile writes
-system.cpu.misc_regfile_reads                 1999349                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                 950331                       # number of misc regfile writes
+system.cpu.rob.rob_reads                    149996318                       # The number of ROB reads
+system.cpu.rob.rob_writes                   130455868                       # The number of ROB writes
+system.cpu.timesIdled                         1387986                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        33674364                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   3608226532                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                    53094243                       # Number of Instructions Simulated
+system.cpu.committedOps                      53094243                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total              53094243                       # Number of Instructions Simulated
+system.cpu.cpi                               2.308560                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         2.308560                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.433170                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.433170                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                 74446052                       # number of integer regfile reads
+system.cpu.int_regfile_writes                40661007                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                    166346                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                   166939                       # number of floating regfile writes
+system.cpu.misc_regfile_reads                 1998850                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                 950370                       # number of misc regfile writes
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
 system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
@@ -658,247 +658,247 @@ system.tsunami.ethernet.totalRxOrn                  0                       # to
 system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
 system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.cpu.icache.replacements                1020915                       # number of replacements
-system.cpu.icache.tagsinuse                509.977219                       # Cycle average of tags in use
-system.cpu.icache.total_refs                  7681837                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                1021424                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                   7.520713                       # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle            23212946000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     509.977219                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.996049                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.996049                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst      7681838                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total         7681838                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst       7681838                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total          7681838                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst      7681838                       # number of overall hits
-system.cpu.icache.overall_hits::total         7681838                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1079605                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1079605                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1079605                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1079605                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1079605                       # number of overall misses
-system.cpu.icache.overall_misses::total       1079605                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  16072965497                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  16072965497                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  16072965497                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  16072965497                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  16072965497                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  16072965497                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst      8761443                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total      8761443                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst      8761443                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total      8761443                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst      8761443                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total      8761443                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.123222                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.123222                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.123222                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.123222                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.123222                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.123222                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14887.820543                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 14887.820543                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 14887.820543                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 14887.820543                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 14887.820543                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 14887.820543                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs      1368497                       # number of cycles access was blocked
+system.cpu.icache.replacements                1025209                       # number of replacements
+system.cpu.icache.tagsinuse                509.960172                       # Cycle average of tags in use
+system.cpu.icache.total_refs                  7772148                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                1025718                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                   7.577276                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle            23722278000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::cpu.inst     509.960172                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.996016                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.996016                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst      7772149                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total         7772149                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst       7772149                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total          7772149                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst      7772149                       # number of overall hits
+system.cpu.icache.overall_hits::total         7772149                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1087170                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1087170                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1087170                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1087170                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1087170                       # number of overall misses
+system.cpu.icache.overall_misses::total       1087170                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  17528418489                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  17528418489                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  17528418489                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  17528418489                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  17528418489                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  17528418489                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst      8859319                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total      8859319                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst      8859319                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total      8859319                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst      8859319                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total      8859319                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.122715                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.122715                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.122715                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.122715                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.122715                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.122715                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16122.978457                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 16122.978457                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 16122.978457                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 16122.978457                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 16122.978457                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 16122.978457                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs      1581994                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               139                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               196                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs  9845.302158                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs  8071.397959                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks          236                       # number of writebacks
-system.cpu.icache.writebacks::total               236                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        57973                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        57973                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        57973                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        57973                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        57973                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        57973                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1021632                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      1021632                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      1021632                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      1021632                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      1021632                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      1021632                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12173342997                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  12173342997                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12173342997                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  12173342997                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12173342997                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  12173342997                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.116605                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.116605                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.116605                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.116605                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.116605                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.116605                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11915.585061                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11915.585061                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11915.585061                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11915.585061                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11915.585061                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11915.585061                       # average overall mshr miss latency
+system.cpu.icache.writebacks::writebacks          238                       # number of writebacks
+system.cpu.icache.writebacks::total               238                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        61204                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        61204                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        61204                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        61204                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        61204                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        61204                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1025966                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total      1025966                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst      1025966                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total      1025966                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst      1025966                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total      1025966                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  13510508994                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  13510508994                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  13510508994                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  13510508994                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  13510508994                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  13510508994                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.115806                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.115806                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.115806                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.115806                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.115806                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.115806                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13168.573807                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13168.573807                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13168.573807                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 13168.573807                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13168.573807                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 13168.573807                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                1401226                       # number of replacements
-system.cpu.dcache.tagsinuse                511.995976                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 11915698                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                1401738                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                   8.500660                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle               19319000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data     511.995976                       # Average occupied blocks per requestor
+system.cpu.dcache.replacements                1403926                       # number of replacements
+system.cpu.dcache.tagsinuse                511.995922                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 11884045                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                1404438                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                   8.461780                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle               19693000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data     511.995922                       # Average occupied blocks per requestor
 system.cpu.dcache.occ_percent::cpu.data      0.999992                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_percent::total         0.999992                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data      7290659                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total         7290659                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      4213930                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        4213930                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       190794                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       190794                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       220142                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       220142                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      11504589                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         11504589                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     11504589                       # number of overall hits
-system.cpu.dcache.overall_hits::total        11504589                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1799381                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1799381                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1940587                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1940587                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        23075                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        23075                       # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data            1                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total            1                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      3739968                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3739968                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      3739968                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3739968                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  37711411500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  37711411500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  57880522429                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  57880522429                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    335593000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    335593000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data        14000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total        14000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  95591933929                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  95591933929                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  95591933929                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  95591933929                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data      9090040                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total      9090040                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      6154517                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      6154517                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       213869                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       213869                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       220143                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       220143                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     15244557                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     15244557                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     15244557                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     15244557                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.197951                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.197951                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.315311                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.315311                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.107893                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.107893                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000005                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total     0.000005                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.245331                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.245331                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.245331                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.245331                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20957.991387                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 20957.991387                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29826.296079                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 29826.296079                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14543.575298                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14543.575298                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        14000                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total        14000                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 25559.559314                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 25559.559314                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 25559.559314                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 25559.559314                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs    805076325                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets       168000                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs             99334                       # number of cycles access was blocked
+system.cpu.dcache.ReadReq_hits::cpu.data      7283526                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total         7283526                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      4189382                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        4189382                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       190687                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       190687                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       220149                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       220149                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      11472908                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         11472908                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     11472908                       # number of overall hits
+system.cpu.dcache.overall_hits::total        11472908                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1829585                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1829585                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1968134                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1968134                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        23417                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        23417                       # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data            4                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total            4                       # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data      3797719                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3797719                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      3797719                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3797719                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  48849966500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  48849966500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  74989002011                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  74989002011                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    432032000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    432032000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data        56500                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total        56500                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 123838968511                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 123838968511                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 123838968511                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 123838968511                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data      9113111                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total      9113111                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      6157516                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      6157516                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       214104                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       214104                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       220153                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       220153                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     15270627                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     15270627                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     15270627                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     15270627                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.200764                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.200764                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.319631                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.319631                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.109372                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.109372                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000018                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total     0.000018                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.248694                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.248694                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.248694                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.248694                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26700.025689                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 26700.025689                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38101.573374                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 38101.573374                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18449.502498                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18449.502498                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        14125                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total        14125                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 32608.776087                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 32608.776087                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 32608.776087                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 32608.776087                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs    732928021                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets       178000                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs             72145                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               7                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs  8104.740824                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets        24000                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 10159.096556                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 25428.571429                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       840933                       # number of writebacks
-system.cpu.dcache.writebacks::total            840933                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       715397                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       715397                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1640618                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      1640618                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         5145                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total         5145                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      2356015                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      2356015                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      2356015                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      2356015                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1083984                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1083984                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       299969                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       299969                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        17930                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total        17930                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            1                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total            1                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1383953                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1383953                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1383953                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1383953                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  24067895500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  24067895500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8474806325                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   8474806325                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    206484500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    206484500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data        11000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total        11000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  32542701825                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  32542701825                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  32542701825                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  32542701825                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data    904540000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total    904540000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   1234101998                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   1234101998                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   2138641998                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total   2138641998                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.119250                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.119250                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.048740                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.048740                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.083836                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.083836                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000005                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000005                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.090783                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.090783                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.090783                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.090783                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22203.183350                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22203.183350                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28252.273818                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28252.273818                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11516.146124                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11516.146124                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.writebacks::writebacks       842954                       # number of writebacks
+system.cpu.dcache.writebacks::total            842954                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       743747                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       743747                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1667534                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      1667534                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         5230                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total         5230                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      2411281                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      2411281                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      2411281                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      2411281                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1085838                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1085838                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       300600                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       300600                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        18187                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total        18187                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            4                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total            4                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1386438                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1386438                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1386438                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1386438                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  28239740000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  28239740000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   9650792448                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   9650792448                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    273508500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    273508500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data        44000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total        44000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  37890532448                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  37890532448                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  37890532448                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  37890532448                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data    905949500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total    905949500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   1225663998                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   1225663998                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   2131613498                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   2131613498                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.119151                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.119151                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.048818                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.048818                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.084945                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.084945                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000018                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000018                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.090791                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.090791                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.090791                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.090791                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 26007.323376                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26007.323376                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32105.097964                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32105.097964                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15038.681476                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15038.681476                       # average LoadLockedReq mshr miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        11000                       # average StoreCondReq mshr miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        11000                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23514.311414                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 23514.311414                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23514.311414                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 23514.311414                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27329.409933                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 27329.409933                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27329.409933                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 27329.409933                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -907,28 +907,28 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                     6438                       # number of quiesce instructions executed
-system.cpu.kern.inst.hwrei                     211701                       # number of hwrei instructions executed
-system.cpu.kern.ipl_count::0                    74930     40.96%     40.96% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::21                     243      0.13%     41.09% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::22                    1882      1.03%     42.12% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31                  105874     57.88%    100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total               182929                       # number of times we switched to this ipl
-system.cpu.kern.ipl_good::0                     73563     49.29%     49.29% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::21                      243      0.16%     49.45% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::22                     1882      1.26%     50.71% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::31                    73566     49.29%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::total                149254                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0             1820291216500     97.92%     97.92% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21                94615000      0.01%     97.93% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22               380636500      0.02%     97.95% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31             38112442500      2.05%    100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total         1858878910500                       # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used::0                  0.981756                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.inst.quiesce                     6433                       # number of quiesce instructions executed
+system.cpu.kern.inst.hwrei                     211694                       # number of hwrei instructions executed
+system.cpu.kern.ipl_count::0                    74899     40.95%     40.95% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::21                     247      0.14%     41.08% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::22                    1887      1.03%     42.11% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::31                  105884     57.89%    100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::total               182917                       # number of times we switched to this ipl
+system.cpu.kern.ipl_good::0                     73532     49.28%     49.28% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::21                      247      0.17%     49.45% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::22                     1887      1.26%     50.71% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::31                    73537     49.29%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::total                149203                       # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks::0             1825754390000     97.87%     97.87% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::21                99081000      0.01%     97.88% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22               381309500      0.02%     97.90% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31             39166410000      2.10%    100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total         1865401190500                       # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used::0                  0.981749                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31                 0.694845                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::total              0.815912                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::31                 0.694505                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::total              0.815687                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
 system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
 system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
@@ -967,29 +967,29 @@ system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # nu
 system.cpu.kern.callpal::swpctx                  4176      2.17%      2.17% # number of callpals executed
 system.cpu.kern.callpal::tbi                       54      0.03%      2.20% # number of callpals executed
 system.cpu.kern.callpal::wrent                      7      0.00%      2.20% # number of callpals executed
-system.cpu.kern.callpal::swpipl                175590     91.19%     93.39% # number of callpals executed
-system.cpu.kern.callpal::rdps                    6787      3.52%     96.92% # number of callpals executed
+system.cpu.kern.callpal::swpipl                175564     91.19%     93.39% # number of callpals executed
+system.cpu.kern.callpal::rdps                    6792      3.53%     96.92% # number of callpals executed
 system.cpu.kern.callpal::wrkgp                      1      0.00%     96.92% # number of callpals executed
 system.cpu.kern.callpal::wrusp                      7      0.00%     96.92% # number of callpals executed
-system.cpu.kern.callpal::rdusp                      9      0.00%     96.93% # number of callpals executed
+system.cpu.kern.callpal::rdusp                      9      0.00%     96.92% # number of callpals executed
 system.cpu.kern.callpal::whami                      2      0.00%     96.93% # number of callpals executed
-system.cpu.kern.callpal::rti                     5216      2.71%     99.64% # number of callpals executed
+system.cpu.kern.callpal::rti                     5223      2.71%     99.64% # number of callpals executed
 system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
 system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
-system.cpu.kern.callpal::total                 192549                       # number of callpals executed
+system.cpu.kern.callpal::total                 192535                       # number of callpals executed
 system.cpu.kern.mode_switch::kernel              5955                       # number of protection mode switches
-system.cpu.kern.mode_switch::user                1738                       # number of protection mode switches
-system.cpu.kern.mode_switch::idle                2103                       # number of protection mode switches
-system.cpu.kern.mode_good::kernel                1908                      
-system.cpu.kern.mode_good::user                  1738                      
+system.cpu.kern.mode_switch::user                1736                       # number of protection mode switches
+system.cpu.kern.mode_switch::idle                2110                       # number of protection mode switches
+system.cpu.kern.mode_good::kernel                1906                      
+system.cpu.kern.mode_good::user                  1736                      
 system.cpu.kern.mode_good::idle                   170                      
-system.cpu.kern.mode_switch_good::kernel     0.320403                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::kernel     0.320067                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::idle       0.080837                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total      0.389547                       # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel        29004913500      1.56%      1.56% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user           2663331000      0.14%      1.70% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle         1827210658000     98.30%    100.00% # number of ticks spent at the given mode
+system.cpu.kern.mode_switch_good::idle       0.080569                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::total      0.388940                       # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks::kernel        29632954500      1.59%      1.59% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user           2782152500      0.15%      1.74% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle         1832986075500     98.26%    100.00% # number of ticks spent at the given mode
 system.cpu.kern.swap_context                     4177                       # number of times the context was actually changed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini
index ea1e9a4d7..7eac6f043 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini
@@ -20,7 +20,7 @@ kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 load_addr_mask=268435455
 machine_type=RealView_PBX
 mem_mode=timing
-memories=system.realview.nvmem system.physmem
+memories=system.physmem system.realview.nvmem
 midr_regval=890224640
 multi_proc=true
 num_work_ids=16
@@ -577,7 +577,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
 
@@ -638,7 +638,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 default=system.membus.badaddr_responder.pio
 master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
 slave=system.system_port system.iocache.mem_side system.l2c.mem_side
@@ -1051,7 +1051,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.l2c.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port
 
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr
index 570320fa8..3620c0fb4 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr
@@ -10,25 +10,25 @@ warn: 	instruction 'mcr icialluis' unimplemented
 warn: 	instruction 'mcr dccimvac' unimplemented
 warn: 	instruction 'mcr dccmvau' unimplemented
 warn: 	instruction 'mcr icimvau' unimplemented
-warn: 5596738500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3744, checker: 0x3748
-warn: 5604531500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708
-warn: 5613988500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8
-warn: 5652343500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608
-warn: 5668456500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8
-warn: 6102531000: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8
+warn: 5800930000: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708
+warn: 5810491000: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8
+warn: 5849158000: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608
+warn: 5865375000: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8
+warn: 6307702500: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8
 warn: LCD dual screen mode not supported
-warn: 53268640500: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04
+warn: 53639390500: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04
 warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
 warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
 warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
 warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
 warn: 	instruction 'mcr icialluis' unimplemented
 warn: 	instruction 'mcr bpiallis' unimplemented
-warn: 2455592103500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0
-warn: 2467697849500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
-warn: 2487360820500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
-warn: 2487895818500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
-warn: 2493686984500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0
-warn: 2494805379500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0
-warn: 2494806652500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0
+warn: 2456135822500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0
+warn: 2468351819500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
+warn: 2488200522500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
+warn: 2488780405500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
+warn: 2494975875500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0
+warn: 2496192426500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0
+warn: 2496193716500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0
+warn: 2496816594500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2fc, checker: 0
 hack: be nice to actually delete the event here
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout
index 494cdd6ff..f106f905a 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:10:14
-gem5 started Jun 29 2012 01:32:52
+gem5 compiled Jul  2 2012 09:08:16
+gem5 started Jul  2 2012 17:05:39
 gem5 executing on zizzer
 command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-checker
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 info: Using bootloader at address 0x80000000
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 2500827052500 because m5_exit instruction encountered
+Exiting @ tick 2502549875500 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
index 655a3d26b..4976e4992 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
@@ -1,16 +1,54 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.500827                       # Number of seconds simulated
-sim_ticks                                2500827052500                       # Number of ticks simulated
-final_tick                               2500827052500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.502550                       # Number of seconds simulated
+sim_ticks                                2502549875500                       # Number of ticks simulated
+final_tick                               2502549875500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  76093                       # Simulator instruction rate (inst/s)
-host_op_rate                                    98249                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             3194009596                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 386968                       # Number of bytes of host memory used
-host_seconds                                   782.97                       # Real time elapsed on the host
-sim_insts                                    59579144                       # Number of instructions simulated
-sim_ops                                      76926734                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  75474                       # Simulator instruction rate (inst/s)
+host_op_rate                                    97450                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             3170228022                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 386888                       # Number of bytes of host memory used
+host_seconds                                   789.39                       # Real time elapsed on the host
+sim_insts                                    59578267                       # Number of instructions simulated
+sim_ops                                      76925839                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::realview.clcd    118994504                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker         3776                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker           64                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst            800128                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9094928                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            128893400                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       800128                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          800128                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      3786176                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu.data        3016072                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           6802248                       # Number of bytes written to this memory
+system.physmem.num_reads::realview.clcd      14874313                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker           59                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker            1                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              12502                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             142142                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total              15029017                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           59159                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu.data            754018                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               813177                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        47549304                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker           1509                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker             26                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               319725                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3634264                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                51504828                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          319725                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             319725                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1512927                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data             1205200                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2718127                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1512927                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       47549304                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker          1509                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker            26                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              319725                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             4839464                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               54222954                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bytes_read::cpu.inst           64                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total            64                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_inst_read::cpu.inst           64                       # Number of instructions bytes read from this memory
@@ -23,191 +61,149 @@ system.realview.nvmem.bw_inst_read::cpu.inst           26
 system.realview.nvmem.bw_inst_read::total           26                       # Instruction read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu.inst           26                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total              26                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bytes_read::realview.clcd    117964800                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker         3328                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst            799424                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9095824                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            127863440                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       799424                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          799424                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      3784576                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu.data        3016072                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6800648                       # Number of bytes written to this memory
-system.physmem.num_reads::realview.clcd      14745600                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker           52                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              12491                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             142156                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total              14900300                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           59134                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu.data            754018                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               813152                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd        47170315                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker           1331                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker             26                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               319664                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3637126                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                51128462                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          319664                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             319664                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1513330                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data             1206030                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2719360                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1513330                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd       47170315                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker          1331                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker            26                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              319664                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             4843156                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               53847821                       # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements                         64425                       # number of replacements
-system.l2c.tagsinuse                     51220.169448                       # Cycle average of tags in use
-system.l2c.total_refs                         2029411                       # Total number of references to valid blocks.
-system.l2c.sampled_refs                        129819                       # Sample count of references to valid blocks.
-system.l2c.avg_refs                         15.632619                       # Average number of references to valid blocks.
-system.l2c.warmup_cycle                  2490891834000                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks        36757.661469                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.dtb.walker       42.093314                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.itb.walker        0.000181                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.inst           8185.117102                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.data           6235.297383                       # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks           0.560877                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.dtb.walker       0.000642                       # Average percentage of cache occupancy
+system.l2c.replacements                         64431                       # number of replacements
+system.l2c.tagsinuse                     51237.782352                       # Cycle average of tags in use
+system.l2c.total_refs                         2028510                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                        129827                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                         15.624716                       # Average number of references to valid blocks.
+system.l2c.warmup_cycle                  2492014554000                       # Cycle when the warmup percentage was hit.
+system.l2c.occ_blocks::writebacks        36760.884600                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.dtb.walker       47.476285                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.itb.walker        0.000184                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.inst           8187.042847                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.data           6242.378435                       # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks           0.560927                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.dtb.walker       0.000724                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu.itb.walker       0.000000                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.inst             0.124895                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.data             0.095143                       # Average percentage of cache occupancy
-system.l2c.occ_percent::total                0.781558                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu.dtb.walker        122696                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.itb.walker         11776                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.inst              977061                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.data              384470                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1496003                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          675876                       # number of Writeback hits
-system.l2c.Writeback_hits::total               675876                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu.data               50                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                  50                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu.data             12                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                12                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu.data            112893                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               112893                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu.dtb.walker         122696                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.itb.walker          11776                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.inst               977061                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.data               497363                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1608896                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu.dtb.walker        122696                       # number of overall hits
-system.l2c.overall_hits::cpu.itb.walker         11776                       # number of overall hits
-system.l2c.overall_hits::cpu.inst              977061                       # number of overall hits
-system.l2c.overall_hits::cpu.data              497363                       # number of overall hits
-system.l2c.overall_hits::total                1608896                       # number of overall hits
-system.l2c.ReadReq_misses::cpu.dtb.walker           52                       # number of ReadReq misses
+system.l2c.occ_percent::cpu.inst             0.124924                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.data             0.095251                       # Average percentage of cache occupancy
+system.l2c.occ_percent::total                0.781827                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu.dtb.walker        121963                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.itb.walker         11826                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.inst              977935                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.data              383708                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1495432                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          675442                       # number of Writeback hits
+system.l2c.Writeback_hits::total               675442                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu.data               42                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                  42                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu.data             16                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total                16                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu.data            112737                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               112737                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu.dtb.walker         121963                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.itb.walker          11826                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.inst               977935                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.data               496445                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 1608169                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu.dtb.walker        121963                       # number of overall hits
+system.l2c.overall_hits::cpu.itb.walker         11826                       # number of overall hits
+system.l2c.overall_hits::cpu.inst              977935                       # number of overall hits
+system.l2c.overall_hits::cpu.data              496445                       # number of overall hits
+system.l2c.overall_hits::total                1608169                       # number of overall hits
+system.l2c.ReadReq_misses::cpu.dtb.walker           59                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu.itb.walker            1                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu.inst             12370                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu.data             10695                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                23118                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu.data           2910                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              2910                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu.data            5                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total               5                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu.data          133257                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             133257                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu.dtb.walker           52                       # number of demand (read+write) misses
+system.l2c.ReadReq_misses::cpu.inst             12384                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.data             10691                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                23135                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu.data           2909                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              2909                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu.data            3                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total               3                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu.data          133229                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             133229                       # number of ReadExReq misses
+system.l2c.demand_misses::cpu.dtb.walker           59                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu.itb.walker            1                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu.inst              12370                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu.data             143952                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                156375                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu.dtb.walker           52                       # number of overall misses
+system.l2c.demand_misses::cpu.inst              12384                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.data             143920                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                156364                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu.dtb.walker           59                       # number of overall misses
 system.l2c.overall_misses::cpu.itb.walker            1                       # number of overall misses
-system.l2c.overall_misses::cpu.inst             12370                       # number of overall misses
-system.l2c.overall_misses::cpu.data            143952                       # number of overall misses
-system.l2c.overall_misses::total               156375                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu.dtb.walker      2714000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu.itb.walker        53000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu.inst    647826500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu.data    558032000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total     1208625500                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu.data       993500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total       993500                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu.data        52000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total        52000                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu.data   6991862500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   6991862500                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu.dtb.walker      2714000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.itb.walker        53000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.inst    647826500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.data   7549894500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total      8200488000                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu.dtb.walker      2714000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu.itb.walker        53000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu.inst    647826500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu.data   7549894500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total     8200488000                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu.dtb.walker       122748                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.itb.walker        11777                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.inst          989431                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.data          395165                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            1519121                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       675876                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           675876                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu.data         2960                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            2960                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu.data           17                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total            17                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu.data        246150                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           246150                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu.dtb.walker       122748                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.itb.walker        11777                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.inst           989431                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.data           641315                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             1765271                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu.dtb.walker       122748                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.itb.walker        11777                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.inst          989431                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.data          641315                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            1765271                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu.dtb.walker     0.000424                       # miss rate for ReadReq accesses
+system.l2c.overall_misses::cpu.inst             12384                       # number of overall misses
+system.l2c.overall_misses::cpu.data            143920                       # number of overall misses
+system.l2c.overall_misses::total               156364                       # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu.dtb.walker      3091500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.itb.walker        60000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.inst    659591498                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.data    562236498                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total     1224979496                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu.data       944500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total       944500                       # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu.data   7069904999                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   7069904999                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu.dtb.walker      3091500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.itb.walker        60000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.inst    659591498                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.data   7632141497                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total      8294884495                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu.dtb.walker      3091500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu.itb.walker        60000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu.inst    659591498                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu.data   7632141497                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total     8294884495                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu.dtb.walker       122022                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.itb.walker        11827                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.inst          990319                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.data          394399                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            1518567                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       675442                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           675442                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu.data         2951                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            2951                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu.data           19                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total            19                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu.data        245966                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           245966                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu.dtb.walker       122022                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.itb.walker        11827                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.inst           990319                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.data           640365                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             1764533                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu.dtb.walker       122022                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.itb.walker        11827                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.inst          990319                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.data          640365                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            1764533                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu.dtb.walker     0.000484                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu.itb.walker     0.000085                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.inst       0.012502                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.data       0.027065                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.015218                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu.data     0.983108                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.983108                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu.data     0.294118                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.294118                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu.data     0.541365                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.541365                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu.dtb.walker     0.000424                       # miss rate for demand accesses
+system.l2c.ReadReq_miss_rate::cpu.inst       0.012505                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.data       0.027107                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.015235                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu.data     0.985768                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.985768                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu.data     0.157895                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.157895                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu.data     0.541656                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.541656                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu.dtb.walker     0.000484                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu.itb.walker     0.000085                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.inst        0.012502                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.data        0.224464                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.088584                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu.dtb.walker     0.000424                       # miss rate for overall accesses
+system.l2c.demand_miss_rate::cpu.inst        0.012505                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.data        0.224747                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.088615                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu.dtb.walker     0.000484                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu.itb.walker     0.000085                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.inst       0.012502                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.data       0.224464                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.088584                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52192.307692                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker        53000                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu.inst 52370.776071                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu.data 52176.905096                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 52280.711999                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu.data   341.408935                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total   341.408935                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu.data        10400                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total        10400                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu.data 52469.007257                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 52469.007257                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52192.307692                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu.itb.walker        53000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu.inst 52370.776071                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu.data 52447.305352                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 52441.170264                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52192.307692                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.itb.walker        53000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.inst 52370.776071                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.data 52447.305352                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 52441.170264                       # average overall miss latency
+system.l2c.overall_miss_rate::cpu.inst       0.012505                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.data       0.224747                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.088615                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52398.305085                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker        60000                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.inst 53261.587371                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.data 52589.701431                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 52949.189367                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu.data   324.682021                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total   324.682021                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu.data 53065.811490                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 53065.811490                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52398.305085                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.itb.walker        60000                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.inst 53261.587371                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.data 53030.443976                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 53048.556541                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52398.305085                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.itb.walker        60000                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.inst 53261.587371                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.data 53030.443976                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 53048.556541                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -216,109 +212,109 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               59134                       # number of writebacks
-system.l2c.writebacks::total                    59134                       # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu.inst              8                       # number of ReadReq MSHR hits
+system.l2c.writebacks::writebacks               59159                       # number of writebacks
+system.l2c.writebacks::total                    59159                       # number of writebacks
+system.l2c.ReadReq_mshr_hits::cpu.inst              9                       # number of ReadReq MSHR hits
 system.l2c.ReadReq_mshr_hits::cpu.data             62                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total                70                       # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits::cpu.inst               8                       # number of demand (read+write) MSHR hits
+system.l2c.ReadReq_mshr_hits::total                71                       # number of ReadReq MSHR hits
+system.l2c.demand_mshr_hits::cpu.inst               9                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_hits::cpu.data              62                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                 70                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu.inst              8                       # number of overall MSHR hits
+system.l2c.demand_mshr_hits::total                 71                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu.inst              9                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::cpu.data             62                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                70                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu.dtb.walker           52                       # number of ReadReq MSHR misses
+system.l2c.overall_mshr_hits::total                71                       # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses::cpu.dtb.walker           59                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu.itb.walker            1                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu.inst        12362                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu.data        10633                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total           23048                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu.data         2910                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total         2910                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu.data            5                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total            5                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu.data       133257                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        133257                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu.dtb.walker           52                       # number of demand (read+write) MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.inst        12375                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.data        10629                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total           23064                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu.data         2909                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total         2909                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu.data            3                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total            3                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu.data       133229                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        133229                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu.dtb.walker           59                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu.itb.walker            1                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu.inst         12362                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu.data        143890                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           156305                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu.dtb.walker           52                       # number of overall MSHR misses
+system.l2c.demand_mshr_misses::cpu.inst         12375                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu.data        143858                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           156293                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu.dtb.walker           59                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu.itb.walker            1                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu.inst        12362                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu.data       143890                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          156305                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker      2081000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker        41000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu.inst    496452000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu.data    425891000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total    924465000                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu.data    116622000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total    116622000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data       200000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total       200000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu.data   5338935000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   5338935000                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.dtb.walker      2081000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.itb.walker        41000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.inst    496452000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.data   5764826000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total   6263400000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.dtb.walker      2081000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.itb.walker        41000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.inst    496452000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.data   5764826000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total   6263400000                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst      5219000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131764564500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 131769783500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data  32353763131                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total  32353763131                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu.inst      5219000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu.data 164118327631                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 164123546631                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000424                       # mshr miss rate for ReadReq accesses
+system.l2c.overall_mshr_misses::cpu.inst        12375                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu.data       143858                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          156293                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker      2372000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker        48000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.inst    508160500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.data    430170499                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total    940750999                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu.data    116825000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    116825000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data       120000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total       120000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu.data   5436034999                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   5436034999                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.dtb.walker      2372000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.itb.walker        48000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.inst    508160500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.data   5866205498                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   6376785998                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.dtb.walker      2372000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.itb.walker        48000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.inst    508160500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.data   5866205498                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   6376785998                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst      5323000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131417115000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 131422438000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data  31373446015                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total  31373446015                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu.inst      5323000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu.data 162790561015                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 162795884015                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000484                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000085                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.012494                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.026908                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.015172                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.983108                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.983108                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data     0.294118                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.294118                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.541365                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.541365                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu.dtb.walker     0.000424                       # mshr miss rate for demand accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.012496                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.026950                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.015188                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.985768                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.985768                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data     0.157895                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.157895                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.541656                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.541656                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu.dtb.walker     0.000484                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu.itb.walker     0.000085                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu.inst     0.012494                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu.data     0.224367                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.088544                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu.dtb.walker     0.000424                       # mshr miss rate for overall accesses
+system.l2c.demand_mshr_miss_rate::cpu.inst     0.012496                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.data     0.224650                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.088575                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu.dtb.walker     0.000484                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu.itb.walker     0.000085                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu.inst     0.012494                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu.data     0.224367                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.088544                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40019.230769                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        41000                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40159.521113                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40053.700743                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 40110.421729                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40076.288660                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40076.288660                       # average UpgradeReq mshr miss latency
+system.l2c.overall_mshr_miss_rate::cpu.inst     0.012496                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.data     0.224650                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.088575                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40203.389831                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        48000                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41063.474747                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40471.398909                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 40788.718306                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40159.848745                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40159.848745                       # average UpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        40000                       # average SCUpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        40000                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40064.949684                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 40064.949684                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40019.230769                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker        41000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40159.521113                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.data 40064.118424                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 40071.654778                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40019.230769                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker        41000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40159.521113                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.data 40064.118424                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 40071.654778                       # average overall mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40802.190206                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 40802.190206                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40203.389831                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker        48000                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41063.474747                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.data 40777.749572                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 40800.202172                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40203.389831                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker        48000                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41063.474747                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.data 40777.749572                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 40800.202172                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -336,26 +332,26 @@ system.cf0.dma_write_bytes                          0                       # Nu
 system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
 system.cpu.checker.dtb.inst_hits                    0                       # ITB inst hits
 system.cpu.checker.dtb.inst_misses                  0                       # ITB inst misses
-system.cpu.checker.dtb.read_hits             15048239                       # DTB read hits
-system.cpu.checker.dtb.read_misses               7308                       # DTB read misses
-system.cpu.checker.dtb.write_hits            11293838                       # DTB write hits
-system.cpu.checker.dtb.write_misses              2191                       # DTB write misses
+system.cpu.checker.dtb.read_hits             15048164                       # DTB read hits
+system.cpu.checker.dtb.read_misses               7309                       # DTB read misses
+system.cpu.checker.dtb.write_hits            11293826                       # DTB write hits
+system.cpu.checker.dtb.write_misses              2190                       # DTB write misses
 system.cpu.checker.dtb.flush_tlb                    4                       # Number of times complete TLB was flushed
 system.cpu.checker.dtb.flush_tlb_mva                0                       # Number of times TLB was flushed by MVA
 system.cpu.checker.dtb.flush_tlb_mva_asid         2878                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.checker.dtb.flush_tlb_asid             126                       # Number of times TLB was flushed by ASID
-system.cpu.checker.dtb.flush_entries             6416                       # Number of entries that have been flushed from TLB
+system.cpu.checker.dtb.flush_entries             6410                       # Number of entries that have been flushed from TLB
 system.cpu.checker.dtb.align_faults                 0                       # Number of TLB faults due to alignment restrictions
-system.cpu.checker.dtb.prefetch_faults            179                       # Number of TLB faults due to prefetch
+system.cpu.checker.dtb.prefetch_faults            177                       # Number of TLB faults due to prefetch
 system.cpu.checker.dtb.domain_faults                0                       # Number of TLB faults due to domain restrictions
 system.cpu.checker.dtb.perms_faults               452                       # Number of TLB faults due to permissions restrictions
-system.cpu.checker.dtb.read_accesses         15055547                       # DTB read accesses
-system.cpu.checker.dtb.write_accesses        11296029                       # DTB write accesses
+system.cpu.checker.dtb.read_accesses         15055473                       # DTB read accesses
+system.cpu.checker.dtb.write_accesses        11296016                       # DTB write accesses
 system.cpu.checker.dtb.inst_accesses                0                       # ITB inst accesses
-system.cpu.checker.dtb.hits                  26342077                       # DTB hits
+system.cpu.checker.dtb.hits                  26341990                       # DTB hits
 system.cpu.checker.dtb.misses                    9499                       # DTB misses
-system.cpu.checker.dtb.accesses              26351576                       # DTB accesses
-system.cpu.checker.itb.inst_hits             60745761                       # ITB inst hits
+system.cpu.checker.dtb.accesses              26351489                       # DTB accesses
+system.cpu.checker.itb.inst_hits             60744881                       # ITB inst hits
 system.cpu.checker.itb.inst_misses               4471                       # ITB inst misses
 system.cpu.checker.itb.read_hits                    0                       # DTB read hits
 system.cpu.checker.itb.read_misses                  0                       # DTB read misses
@@ -372,36 +368,36 @@ system.cpu.checker.itb.domain_faults                0                       # Nu
 system.cpu.checker.itb.perms_faults                 0                       # Number of TLB faults due to permissions restrictions
 system.cpu.checker.itb.read_accesses                0                       # DTB read accesses
 system.cpu.checker.itb.write_accesses               0                       # DTB write accesses
-system.cpu.checker.itb.inst_accesses         60750232                       # ITB inst accesses
-system.cpu.checker.itb.hits                  60745761                       # DTB hits
+system.cpu.checker.itb.inst_accesses         60749352                       # ITB inst accesses
+system.cpu.checker.itb.hits                  60744881                       # DTB hits
 system.cpu.checker.itb.misses                    4471                       # DTB misses
-system.cpu.checker.itb.accesses              60750232                       # DTB accesses
-system.cpu.checker.numCycles                 77205158                       # number of cpu cycles simulated
+system.cpu.checker.itb.accesses              60749352                       # DTB accesses
+system.cpu.checker.numCycles                 77204260                       # number of cpu cycles simulated
 system.cpu.checker.numWorkItemsStarted              0                       # number of work items this cpu started
 system.cpu.checker.numWorkItemsCompleted            0                       # number of work items this cpu completed
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     51785537                       # DTB read hits
-system.cpu.dtb.read_misses                      81591                       # DTB read misses
-system.cpu.dtb.write_hits                    11872923                       # DTB write hits
-system.cpu.dtb.write_misses                     18231                       # DTB write misses
+system.cpu.dtb.read_hits                     51771660                       # DTB read hits
+system.cpu.dtb.read_misses                      81258                       # DTB read misses
+system.cpu.dtb.write_hits                    11880398                       # DTB write hits
+system.cpu.dtb.write_misses                     17961                       # DTB write misses
 system.cpu.dtb.flush_tlb                            4                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid                2878                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                     126                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                     8065                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                      2988                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                    690                       # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries                     8043                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                      3044                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                    609                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                      1351                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 51867128                       # DTB read accesses
-system.cpu.dtb.write_accesses                11891154                       # DTB write accesses
+system.cpu.dtb.perms_faults                      1282                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                 51852918                       # DTB read accesses
+system.cpu.dtb.write_accesses                11898359                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          63658460                       # DTB hits
-system.cpu.dtb.misses                           99822                       # DTB misses
-system.cpu.dtb.accesses                      63758282                       # DTB accesses
-system.cpu.itb.inst_hits                     13022422                       # ITB inst hits
-system.cpu.itb.inst_misses                      12153                       # ITB inst misses
+system.cpu.dtb.hits                          63652058                       # DTB hits
+system.cpu.dtb.misses                           99219                       # DTB misses
+system.cpu.dtb.accesses                      63751277                       # DTB accesses
+system.cpu.itb.inst_hits                     13142261                       # ITB inst hits
+system.cpu.itb.inst_misses                      12247                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
@@ -410,542 +406,542 @@ system.cpu.itb.flush_tlb                            4                       # Nu
 system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
 system.cpu.itb.flush_tlb_mva_asid                2878                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.itb.flush_tlb_asid                     126                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                     5249                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries                     5262                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                      3259                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                      3496                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                 13034575                       # ITB inst accesses
-system.cpu.itb.hits                          13022422                       # DTB hits
-system.cpu.itb.misses                           12153                       # DTB misses
-system.cpu.itb.accesses                      13034575                       # DTB accesses
-system.cpu.numCycles                        408047924                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                 13154508                       # ITB inst accesses
+system.cpu.itb.hits                          13142261                       # DTB hits
+system.cpu.itb.misses                           12247                       # DTB misses
+system.cpu.itb.accesses                      13154508                       # DTB accesses
+system.cpu.numCycles                        413642740                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                 14895929                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted           11838635                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect             749498                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups               9774236                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                  7761608                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                 14974990                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           11915620                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect             753400                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              10068197                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                  7820088                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                  1450585                       # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect               80646                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles           32131999                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                       99541579                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    14895929                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            9212193                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      21738174                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 6062724                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                     161664                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles               89532236                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                 2475                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        119247                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles       208172                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          243                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  13018415                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                931788                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                    6733                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          148050131                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.832729                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.216336                       # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS                  1448775                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect               80927                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles           33422471                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                       99542070                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    14974990                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            9268863                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      21759182                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 6002262                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                     163536                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles               93319816                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                 2533                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        133610                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles       208459                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          397                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  13138017                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               1024097                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                    6504                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          153128307                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.804842                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.182667                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                126328884     85.33%     85.33% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  1364567      0.92%     86.25% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  1757577      1.19%     87.44% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  2627928      1.78%     89.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  1817598      1.23%     90.44% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  1139974      0.77%     91.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  2881875      1.95%     93.16% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                   793207      0.54%     93.69% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                  9338521      6.31%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                131386008     85.80%     85.80% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  1369017      0.89%     86.70% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  1759019      1.15%     87.84% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  2640315      1.72%     89.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  1819667      1.19%     90.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  1142419      0.75%     91.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  2920911      1.91%     93.41% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                   807762      0.53%     93.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                  9283189      6.06%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            148050131                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.036505                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.243946                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 34138786                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              89344652                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  19542719                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               1039822                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                3984152                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              2096721                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                174752                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              115904821                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                572765                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                3984152                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 36116919                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                36990471                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       46307759                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  18567490                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               6083340                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              109034273                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                  3076                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                1021710                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               4089268                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents            41156                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           113585552                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             502111824                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        502019660                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups             92164                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps              77687957                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 35897594                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts             898050                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts         797560                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  12232946                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             20954804                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            13881914                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1960286                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          2534637                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                   99654588                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             1554944                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 124705745                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            186396                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        23520309                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     64631044                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         267642                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     148050131                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.842321                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.546134                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            153128307                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.036203                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.240647                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 35537493                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              93048586                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  19509299                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               1086349                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                3946580                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              2100058                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                174557                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              116122172                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                568338                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                3946580                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 37621271                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                39594801                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       46881047                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  18412397                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               6672211                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              108597287                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                  4175                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                1156489                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               4484156                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents            30967                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           113073752                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             499820515                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        499727174                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups             93341                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps              77686691                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 35387060                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts             898607                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts         797702                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  13307124                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             21058263                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            13875749                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1965166                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          2564814                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                   99781831                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             1555350                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 124613166                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            199798                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        23638127                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     65777806                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         268083                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     153128307                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.813783                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.516400                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           103452672     69.88%     69.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            13854502      9.36%     79.23% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             7174552      4.85%     84.08% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             5822865      3.93%     88.01% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            12669865      8.56%     96.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             2797622      1.89%     98.46% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             1712436      1.16%     99.62% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              433578      0.29%     99.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              132039      0.09%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           107849903     70.43%     70.43% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            14560254      9.51%     79.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             7302452      4.77%     84.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             5913038      3.86%     88.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            12593494      8.22%     96.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             2809204      1.83%     98.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             1536315      1.00%     99.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              438168      0.29%     99.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              125479      0.08%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       148050131                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       153128307                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                   59948      0.68%      0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      2      0.00%      0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                8388673     94.51%     95.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                427083      4.81%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   53462      0.61%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      2      0.00%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                8367005     94.75%     95.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                409700      4.64%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass            106530      0.09%      0.09% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              58643579     47.03%     47.11% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                95161      0.08%     47.19% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     47.19% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     47.19% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     47.19% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     47.19% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     47.19% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     47.19% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     47.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     47.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     47.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     47.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     47.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     47.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                  13      0.00%     47.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     47.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     47.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  6      0.00%     47.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               8      0.00%     47.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     47.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     47.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     47.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     47.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     47.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     47.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc           2111      0.00%     47.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     47.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            8      0.00%     47.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     47.19% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             53352582     42.78%     89.97% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            12505747     10.03%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              58482659     46.93%     47.02% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                95330      0.08%     47.09% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     47.09% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     47.09% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     47.09% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     47.09% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     47.09% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     47.09% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     47.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     47.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     47.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     47.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     47.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     47.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                  11      0.00%     47.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     47.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     47.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  5      0.00%     47.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               6      0.00%     47.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     47.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     47.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     47.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     47.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     47.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     47.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc           2111      0.00%     47.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     47.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            6      0.00%     47.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     47.10% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             53414157     42.86%     89.96% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            12512351     10.04%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              124705745                       # Type of FU issued
-system.cpu.iq.rate                           0.305615                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     8875706                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.071173                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          406599918                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         124750196                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     85869603                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads               23265                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes              12672                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses        10345                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              133462587                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                   12334                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads           642048                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              124613166                       # Type of FU issued
+system.cpu.iq.rate                           0.301258                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     8830169                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.070861                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          411460543                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         124996425                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     85630389                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads               22925                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes              12868                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses        10343                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              133324707                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                   12098                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads           646336                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      5239514                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        10265                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        34172                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      2083712                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      5343093                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        11106                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        35068                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      2077574                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads     34107049                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked       1151692                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads     34107202                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked       1049886                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                3984152                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                28395992                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                447371                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           101464012                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            233619                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              20954804                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             13881914                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts             964089                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 112476                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                  6557                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          34172                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         381147                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       331860                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               713007                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             121711788                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              52474170                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           2993957                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                3946580                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                29463666                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                540836                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           101593235                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            217276                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              21058263                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             13875749                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts             964547                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 125689                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 40656                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          35068                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         381127                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       332167                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               713294                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             121438397                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              52461807                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           3174769                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                        254480                       # number of nop insts executed
-system.cpu.iew.exec_refs                     64857639                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 11392260                       # Number of branches executed
-system.cpu.iew.exec_stores                   12383469                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.298278                       # Inst execution rate
-system.cpu.iew.wb_sent                      120307041                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      85879948                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  46962413                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  87363153                       # num instructions consuming a value
+system.cpu.iew.exec_nop                        256054                       # number of nop insts executed
+system.cpu.iew.exec_refs                     64853171                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 11412736                       # Number of branches executed
+system.cpu.iew.exec_stores                   12391364                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.293583                       # Inst execution rate
+system.cpu.iew.wb_sent                      120063166                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      85640732                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  46459932                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  84649521                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.210465                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.537554                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.207040                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.548851                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts       59729525                       # The number of committed instructions
-system.cpu.commit.commitCommittedOps         77077115                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts        24198873                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls         1287302                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            621123                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    144148394                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.534707                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.521609                       # Number of insts commited each cycle
+system.cpu.commit.commitCommittedInsts       59728648                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps         77076220                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts        24329020                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         1287267                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            625309                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    149264139                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.516375                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.492760                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    116600934     80.89%     80.89% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     13538329      9.39%     90.28% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      3987949      2.77%     93.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      2150587      1.49%     94.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1741345      1.21%     95.75% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1028717      0.71%     96.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      1566098      1.09%     97.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       669906      0.46%     98.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      2864529      1.99%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    121340444     81.29%     81.29% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     13976446      9.36%     90.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      3929866      2.63%     93.29% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      2230737      1.49%     94.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1774137      1.19%     95.97% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1064202      0.71%     96.68% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      1398926      0.94%     97.62% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       658331      0.44%     98.06% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      2891050      1.94%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    144148394                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts             59729525                       # Number of instructions committed
-system.cpu.commit.committedOps               77077115                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    149264139                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts             59728648                       # Number of instructions committed
+system.cpu.commit.committedOps               77076220                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       27513492                       # Number of memory references committed
-system.cpu.commit.loads                      15715290                       # Number of loads committed
-system.cpu.commit.membars                      413064                       # Number of memory barriers committed
-system.cpu.commit.branches                    9904425                       # Number of branches committed
+system.cpu.commit.refs                       27513345                       # Number of memory references committed
+system.cpu.commit.loads                      15715170                       # Number of loads committed
+system.cpu.commit.membars                      413057                       # Number of memory barriers committed
+system.cpu.commit.branches                    9904308                       # Number of branches committed
 system.cpu.commit.fp_insts                      10212                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                  68617780                       # Number of committed integer instructions.
-system.cpu.commit.function_calls               995959                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events               2864529                       # number cycles where commit BW limit reached
+system.cpu.commit.int_insts                  68616986                       # Number of committed integer instructions.
+system.cpu.commit.function_calls               995953                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events               2891050                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    240802540                       # The number of ROB reads
-system.cpu.rob.rob_writes                   206662154                       # The number of ROB writes
-system.cpu.timesIdled                         1878638                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                       259997793                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   4593518134                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                    59579144                       # Number of Instructions Simulated
-system.cpu.committedOps                      76926734                       # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total              59579144                       # Number of Instructions Simulated
-system.cpu.cpi                               6.848838                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         6.848838                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.146010                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.146010                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                552215112                       # number of integer regfile reads
-system.cpu.int_regfile_writes                88113132                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                      8314                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                     2878                       # number of floating regfile writes
-system.cpu.misc_regfile_reads               131767968                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                 912736                       # number of misc regfile writes
-system.cpu.icache.replacements                 990445                       # number of replacements
-system.cpu.icache.tagsinuse                511.614969                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 11943122                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                 990957                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                  12.052109                       # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle             6217994000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     511.614969                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.999248                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.999248                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst     11943122                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        11943122                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      11943122                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         11943122                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     11943122                       # number of overall hits
-system.cpu.icache.overall_hits::total        11943122                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1075156                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1075156                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1075156                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1075156                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1075156                       # number of overall misses
-system.cpu.icache.overall_misses::total       1075156                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  15637742995                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  15637742995                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  15637742995                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  15637742995                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  15637742995                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  15637742995                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     13018278                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     13018278                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     13018278                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     13018278                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     13018278                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     13018278                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.082588                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.082588                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.082588                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.082588                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.082588                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.082588                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14544.627008                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 14544.627008                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 14544.627008                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 14544.627008                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 14544.627008                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 14544.627008                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs      2121995                       # number of cycles access was blocked
+system.cpu.rob.rob_reads                    246021016                       # The number of ROB reads
+system.cpu.rob.rob_writes                   206855771                       # The number of ROB writes
+system.cpu.timesIdled                         1910853                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                       260514433                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   4591368963                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                    59578267                       # Number of Instructions Simulated
+system.cpu.committedOps                      76925839                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total              59578267                       # Number of Instructions Simulated
+system.cpu.cpi                               6.942846                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         6.942846                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.144033                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.144033                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                551124725                       # number of integer regfile reads
+system.cpu.int_regfile_writes                87730819                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                      8186                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                     2858                       # number of floating regfile writes
+system.cpu.misc_regfile_reads               131789755                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                 912697                       # number of misc regfile writes
+system.cpu.icache.replacements                 991190                       # number of replacements
+system.cpu.icache.tagsinuse                511.611770                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 12061455                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                 991702                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                  12.162378                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle             6426198000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::cpu.inst     511.611770                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.999242                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.999242                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst     12061455                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        12061455                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      12061455                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         12061455                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     12061455                       # number of overall hits
+system.cpu.icache.overall_hits::total        12061455                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1076423                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1076423                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1076423                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1076423                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1076423                       # number of overall misses
+system.cpu.icache.overall_misses::total       1076423                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  16851120991                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  16851120991                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  16851120991                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  16851120991                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  16851120991                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  16851120991                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     13137878                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     13137878                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     13137878                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     13137878                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     13137878                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     13137878                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.081933                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.081933                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.081933                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.081933                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.081933                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.081933                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15654.738881                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 15654.738881                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 15654.738881                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 15654.738881                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 15654.738881                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 15654.738881                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs      2871493                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               289                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               461                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs  7342.543253                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs  6228.835141                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks        67776                       # number of writebacks
-system.cpu.icache.writebacks::total             67776                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        84152                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        84152                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        84152                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        84152                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        84152                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        84152                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       991004                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       991004                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       991004                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       991004                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       991004                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       991004                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  11660559495                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  11660559495                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  11660559495                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  11660559495                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  11660559495                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  11660559495                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst      6997000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::total      6997000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst      6997000                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total      6997000                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.076124                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.076124                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.076124                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.076124                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.076124                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.076124                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11766.410120                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11766.410120                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11766.410120                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11766.410120                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11766.410120                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11766.410120                       # average overall mshr miss latency
+system.cpu.icache.writebacks::writebacks        67899                       # number of writebacks
+system.cpu.icache.writebacks::total             67899                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        84680                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        84680                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        84680                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        84680                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        84680                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        84680                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       991743                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       991743                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       991743                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       991743                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       991743                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       991743                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12825867499                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  12825867499                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12825867499                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  12825867499                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12825867499                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  12825867499                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst      7992500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::total      7992500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst      7992500                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::total      7992500                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.075487                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.075487                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.075487                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.075487                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.075487                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.075487                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12932.652410                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12932.652410                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12932.652410                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 12932.652410                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12932.652410                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12932.652410                       # average overall mshr miss latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                 644124                       # number of replacements
-system.cpu.dcache.tagsinuse                511.991568                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 21775548                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                 644636                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  33.779603                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle               49161000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data     511.991568                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.999984                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.999984                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data     13910712                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        13910712                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      7293091                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        7293091                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       282930                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       282930                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       285654                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       285654                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      21203803                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         21203803                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     21203803                       # number of overall hits
-system.cpu.dcache.overall_hits::total        21203803                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       740801                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        740801                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      2957315                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      2957315                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        13662                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        13662                       # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data           17                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total           17                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      3698116                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3698116                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      3698116                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3698116                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  10501483000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  10501483000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 106800352759                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 106800352759                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    200535500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    200535500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       452000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total       452000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 117301835759                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 117301835759                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 117301835759                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 117301835759                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     14651513                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     14651513                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.replacements                 643139                       # number of replacements
+system.cpu.dcache.tagsinuse                511.991335                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 21733833                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 643651                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  33.766487                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle               50933000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data     511.991335                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.999983                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.999983                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     13904166                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        13904166                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      7257095                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        7257095                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       283844                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       283844                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       285639                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       285639                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      21161261                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         21161261                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     21161261                       # number of overall hits
+system.cpu.dcache.overall_hits::total        21161261                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       765252                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        765252                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      2993311                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      2993311                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        13765                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        13765                       # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data           19                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total           19                       # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data      3758563                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3758563                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      3758563                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3758563                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  14844603000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  14844603000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 129412035593                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 129412035593                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    223977000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    223977000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       405000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total       405000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 144256638593                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 144256638593                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 144256638593                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 144256638593                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     14669418                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     14669418                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     10250406                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     10250406                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       296592                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       296592                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       285671                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       285671                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     24901919                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     24901919                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     24901919                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     24901919                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.050561                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.050561                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.288507                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.288507                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.046063                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.046063                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000060                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total     0.000060                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.148507                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.148507                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.148507                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.148507                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14175.848845                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14175.848845                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36113.959033                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 36113.959033                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14678.341385                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14678.341385                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 26588.235294                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 26588.235294                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 31719.350004                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 31719.350004                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 31719.350004                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 31719.350004                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs     14079439                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets      7830500                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs              2852                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets             275                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs  4936.689691                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 28474.545455                       # average number of cycles each access was blocked
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       297609                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       297609                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       285658                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       285658                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     24919824                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     24919824                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     24919824                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     24919824                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.052166                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.052166                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.292019                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.292019                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.046252                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.046252                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000067                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total     0.000067                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.150826                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.150826                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.150826                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.150826                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19398.319769                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 19398.319769                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43233.742031                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 43233.742031                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16271.485652                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16271.485652                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 21315.789474                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 21315.789474                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 38380.795691                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 38380.795691                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 38380.795691                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 38380.795691                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs     32633902                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets      7260500                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              7285                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets             283                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  4479.602196                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 25655.477032                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       608100                       # number of writebacks
-system.cpu.dcache.writebacks::total            608100                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       354542                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       354542                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      2708293                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      2708293                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         1346                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total         1346                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      3062835                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      3062835                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      3062835                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      3062835                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       386259                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       386259                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       249022                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       249022                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        12316                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total        12316                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data           17                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total           17                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       635281                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       635281                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       635281                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       635281                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   4943544500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   4943544500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8596724439                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   8596724439                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    143823500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    143823500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       395000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       395000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  13540268939                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  13540268939                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  13540268939                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  13540268939                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147158057500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147158057500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data  42257629539                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  42257629539                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189415687039                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 189415687039                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.026363                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.026363                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.024294                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.024294                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.041525                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.041525                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000060                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000060                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.025511                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.025511                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.025511                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.025511                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12798.522494                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12798.522494                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34521.947615                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34521.947615                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11677.776876                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11677.776876                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 23235.294118                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 23235.294118                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21313.826384                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 21313.826384                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21313.826384                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 21313.826384                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks       607543                       # number of writebacks
+system.cpu.dcache.writebacks::total            607543                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       379767                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       379767                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      2744505                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      2744505                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         1453                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total         1453                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      3124272                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      3124272                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      3124272                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      3124272                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       385485                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       385485                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       248806                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       248806                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        12312                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total        12312                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data           19                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total           19                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       634291                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       634291                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       634291                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       634291                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6242554097                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   6242554097                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   9246380950                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   9246380950                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    164108000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    164108000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       341500                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       341500                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  15488935047                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  15488935047                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  15488935047                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  15488935047                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147082070000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147082070000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data  41215087708                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  41215087708                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 188297157708                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 188297157708                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.026278                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.026278                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.024273                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.024273                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.041370                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.041370                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000067                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000067                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.025453                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.025453                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.025453                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.025453                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16194.025960                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16194.025960                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37163.014357                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37163.014357                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13329.109812                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13329.109812                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17973.684211                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17973.684211                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24419.288697                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 24419.288697                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24419.288697                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 24419.288697                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -967,16 +963,16 @@ system.iocache.avg_blocked_cycles::no_mshrs          nan                       #
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1290934638893                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1290934638893                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1290934638893                       # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1290934638893                       # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1298563544001                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1298563544001                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1298563544001                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1298563544001                       # number of overall MSHR uncacheable cycles
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                    88048                       # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce                    88049                       # number of quiesce instructions executed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
index 8259e7988..8ee00f929 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
@@ -20,7 +20,7 @@ kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 load_addr_mask=268435455
 machine_type=RealView_PBX
 mem_mode=timing
-memories=system.physmem system.realview.nvmem
+memories=system.realview.nvmem system.physmem
 midr_regval=890224640
 multi_proc=true
 num_work_ids=16
@@ -960,7 +960,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
 
@@ -1021,7 +1021,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 default=system.membus.badaddr_responder.pio
 master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
 slave=system.system_port system.iocache.mem_side system.l2c.mem_side
@@ -1434,7 +1434,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.l2c.cpu_side
 slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
 
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr
index c3484784a..6f1b9eba3 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr
@@ -14,7 +14,6 @@ warn: Returning thumbEE disabled for now since we don't support CP14config regis
 warn: 	instruction 'mcr bpiallis' unimplemented
 warn: LCD dual screen mode not supported
 warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
-warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
 warn: 	instruction 'mcr icialluis' unimplemented
 warn: 	instruction 'mcr icialluis' unimplemented
 hack: be nice to actually delete the event here
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
index 02c5cc88a..fe27005da 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:10:14
-gem5 started Jun 29 2012 01:33:16
+gem5 compiled Jul  2 2012 09:08:16
+gem5 started Jul  2 2012 17:16:08
 gem5 executing on zizzer
 command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-dual
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 info: Using bootloader at address 0x80000000
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 2569716290500 because m5_exit instruction encountered
+Exiting @ tick 2581527583500 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
index 038e4aa5b..ba015b214 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
@@ -1,75 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.569716                       # Number of seconds simulated
-sim_ticks                                2569716290500                       # Number of ticks simulated
-final_tick                               2569716290500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.581528                       # Number of seconds simulated
+sim_ticks                                2581527583500                       # Number of ticks simulated
+final_tick                               2581527583500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  91215                       # Simulator instruction rate (inst/s)
-host_op_rate                                   117813                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             3779331614                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 391064                       # Number of bytes of host memory used
-host_seconds                                   679.94                       # Real time elapsed on the host
-sim_insts                                    62020337                       # Number of instructions simulated
-sim_ops                                      80105642                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::realview.clcd    119537664                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker          640                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           383040                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          4310004                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker          960                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           438272                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          5311600                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            129982372                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       383040                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       438272                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          821312                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      4277376                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data         17000                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data       3012136                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7306512                       # Number of bytes written to this memory
-system.physmem.num_reads::realview.clcd      14942208                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker           10                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst              5985                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             67416                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker           15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              6848                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             83020                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total              15105505                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           66834                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data             4250                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data           753034                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               824118                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd        46517845                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker           249                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker            25                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              149059                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             1677230                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker           374                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker            50                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst              170553                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             2066999                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                50582382                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         149059                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst         170553                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             319612                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1664532                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data               6616                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data            1172167                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2843315                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1664532                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd       46517845                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker          249                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker           25                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             149059                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            1683845                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker          374                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker           50                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst             170553                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            3239165                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               53425697                       # Total bandwidth to/from this memory (bytes/s)
+host_inst_rate                                  89313                       # Simulator instruction rate (inst/s)
+host_op_rate                                   115365                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             3717496726                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 390980                       # Number of bytes of host memory used
+host_seconds                                   694.43                       # Real time elapsed on the host
+sim_insts                                    62021206                       # Number of instructions simulated
+sim_ops                                      80112751                       # Number of ops (including micro ops) simulated
 system.realview.nvmem.bytes_read::cpu0.inst           64                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu1.inst          320                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           384                       # Number of bytes read from this memory
@@ -80,259 +21,300 @@ system.realview.nvmem.num_reads::cpu0.inst            1                       #
 system.realview.nvmem.num_reads::cpu1.inst            5                       # Number of read requests responded to by this memory
 system.realview.nvmem.num_reads::total              6                       # Number of read requests responded to by this memory
 system.realview.nvmem.bw_read::cpu0.inst           25                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.inst          125                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.inst          124                       # Total read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_read::total              149                       # Total read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_inst_read::cpu0.inst           25                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst          125                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu1.inst          124                       # Instruction read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_inst_read::total          149                       # Instruction read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu0.inst           25                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst          125                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.inst          124                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total             149                       # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements                         72902                       # number of replacements
-system.l2c.tagsinuse                     52914.655952                       # Cycle average of tags in use
-system.l2c.total_refs                         2024041                       # Total number of references to valid blocks.
-system.l2c.sampled_refs                        138037                       # Sample count of references to valid blocks.
-system.l2c.avg_refs                         14.663032                       # Average number of references to valid blocks.
+system.physmem.bytes_read::realview.clcd    119537664                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker          576                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           395008                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          4372084                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker         1344                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           425536                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          5226480                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            129958756                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       395008                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       425536                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          820544                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      4244480                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data         17000                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data       3012136                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7273616                       # Number of bytes written to this memory
+system.physmem.num_reads::realview.clcd      14942208                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker            9                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst              6172                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             68386                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker           21                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              6649                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             81690                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total              15105136                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           66320                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data             4250                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data           753034                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               823604                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        46305011                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker           223                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker            25                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              153013                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             1693603                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker           521                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst              164839                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             2024569                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                50341804                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         153013                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst         164839                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             317852                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1644174                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data               6585                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data            1166804                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2817563                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1644174                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       46305011                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker          223                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker           25                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             153013                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            1700189                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker          521                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst             164839                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            3191372                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               53159367                       # Total bandwidth to/from this memory (bytes/s)
+system.l2c.replacements                         72536                       # number of replacements
+system.l2c.tagsinuse                     53024.626088                       # Cycle average of tags in use
+system.l2c.total_refs                         2019266                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                        137732                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                         14.660834                       # Average number of references to valid blocks.
 system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks        37560.940783                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.dtb.walker       3.394478                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.itb.walker       0.000176                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst          4213.394018                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data          2969.636370                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.dtb.walker      12.170115                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.itb.walker       0.970249                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.inst          4028.311406                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.data          4125.838357                       # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks           0.573134                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.dtb.walker      0.000052                       # Average percentage of cache occupancy
+system.l2c.occ_blocks::writebacks        37701.415204                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.dtb.walker       3.259804                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.itb.walker       0.000179                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst          4215.968317                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data          2959.624437                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.dtb.walker      13.637835                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst          4028.150256                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.data          4102.570055                       # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks           0.575278                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.dtb.walker      0.000050                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu0.itb.walker      0.000000                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.inst            0.064291                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.data            0.045313                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.dtb.walker      0.000186                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.itb.walker      0.000015                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.inst            0.061467                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.data            0.062955                       # Average percentage of cache occupancy
-system.l2c.occ_percent::total                0.807414                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0.dtb.walker        50859                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker         5940                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst             395141                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             161674                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker        79156                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker         6590                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             619717                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data             202375                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1521452                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          646021                       # number of Writeback hits
-system.l2c.Writeback_hits::total               646021                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data             861                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data            1085                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                1946                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data           209                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data           164                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total               373                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            50919                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            55813                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               106732                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker         50859                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker          5940                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              395141                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              212593                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker         79156                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          6590                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              619717                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              258188                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1628184                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker        50859                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker         5940                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             395141                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             212593                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker        79156                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         6590                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             619717                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             258188                       # number of overall hits
-system.l2c.overall_hits::total                1628184                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker           10                       # number of ReadReq misses
+system.l2c.occ_percent::cpu0.inst            0.064331                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.data            0.045160                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.dtb.walker      0.000208                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.inst            0.061465                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.data            0.062600                       # Average percentage of cache occupancy
+system.l2c.occ_percent::total                0.809092                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu0.dtb.walker        53338                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker         6106                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.inst             398719                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data             164464                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker        78886                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker         6452                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst             615129                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data             199702                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1522796                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          645710                       # number of Writeback hits
+system.l2c.Writeback_hits::total               645710                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data            1043                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data             806                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                1849                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data           213                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data           143                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total               356                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data            48030                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            59189                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               107219                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.dtb.walker         53338                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker          6106                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst              398719                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              212494                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker         78886                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker          6452                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              615129                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              258891                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 1630015                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker        53338                       # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker         6106                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst             398719                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             212494                       # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker        78886                       # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker         6452                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             615129                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             258891                       # number of overall hits
+system.l2c.overall_hits::total                1630015                       # number of overall hits
+system.l2c.ReadReq_misses::cpu0.dtb.walker            9                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu0.itb.walker            1                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst             5853                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data             6139                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.dtb.walker           15                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.itb.walker            2                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst             6809                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data             6537                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                25366                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data          5294                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data          4767                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             10061                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data          775                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data          577                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total            1352                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          62637                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          77700                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             140337                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.dtb.walker           10                       # number of demand (read+write) misses
+system.l2c.ReadReq_misses::cpu0.inst             6044                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data             6302                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.dtb.walker           21                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst             6609                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data             6328                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                25314                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data          5683                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data          4287                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              9970                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data          777                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data          589                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total            1366                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data          63451                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data          76572                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             140023                       # number of ReadExReq misses
+system.l2c.demand_misses::cpu0.dtb.walker            9                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu0.itb.walker            1                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst              5853                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data             68776                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker           15                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.itb.walker            2                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              6809                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             84237                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                165703                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker           10                       # number of overall misses
+system.l2c.demand_misses::cpu0.inst              6044                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data             69753                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.dtb.walker           21                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst              6609                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data             82900                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                165337                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.dtb.walker            9                       # number of overall misses
 system.l2c.overall_misses::cpu0.itb.walker            1                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst             5853                       # number of overall misses
-system.l2c.overall_misses::cpu0.data            68776                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker           15                       # number of overall misses
-system.l2c.overall_misses::cpu1.itb.walker            2                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             6809                       # number of overall misses
-system.l2c.overall_misses::cpu1.data            84237                       # number of overall misses
-system.l2c.overall_misses::total               165703                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.dtb.walker       521500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.itb.walker        53000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.inst    306091000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data    320158000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.dtb.walker       783000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.itb.walker       104000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst    356464000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data    341134500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total     1325309000                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0.data     18664500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data     31259000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total     49923500                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data      1307000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data      6272500                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total      7579500                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data   3285106999                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data   4081053500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   7366160499                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker       521500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.itb.walker        53000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst    306091000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data   3605264999                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker       783000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.itb.walker       104000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst    356464000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data   4422188000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total      8691469499                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker       521500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.itb.walker        53000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst    306091000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data   3605264999                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker       783000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.itb.walker       104000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst    356464000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data   4422188000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total     8691469499                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.dtb.walker        50869                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker         5941                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst         400994                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data         167813                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker        79171                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker         6592                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst         626526                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data         208912                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            1546818                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       646021                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           646021                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data         6155                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data         5852                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total           12007                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data          984                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data          741                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total          1725                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       113556                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data       133513                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           247069                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker        50869                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker         5941                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          400994                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data          281369                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker        79171                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker         6592                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          626526                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          342425                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             1793887                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker        50869                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker         5941                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         400994                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data         281369                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker        79171                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker         6592                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         626526                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         342425                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            1793887                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000197                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000168                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.014596                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.036582                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000189                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.000303                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.010868                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.031291                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.016399                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.860114                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.814593                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.837928                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.787602                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.778677                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.783768                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.551596                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.581966                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.568007                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000197                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.000168                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.014596                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.244433                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000189                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.000303                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.010868                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.246001                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.092371                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000197                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.000168                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.014596                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.244433                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000189                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.000303                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.010868                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.246001                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.092371                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker        52150                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        53000                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52296.429182                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 52151.490471                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        52200                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker        52000                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52351.887208                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 52185.176687                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 52247.457226                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  3525.595013                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  6557.373610                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  4962.081304                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  1686.451613                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 10870.883882                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  5606.139053                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52446.748711                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52523.211068                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 52489.083413                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker        52150                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker        53000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 52296.429182                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 52420.393727                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        52200                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker        52000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 52351.887208                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 52496.978762                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 52452.095007                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker        52150                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker        53000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 52296.429182                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 52420.393727                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        52200                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker        52000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 52351.887208                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 52496.978762                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 52452.095007                       # average overall miss latency
+system.l2c.overall_misses::cpu0.inst             6044                       # number of overall misses
+system.l2c.overall_misses::cpu0.data            69753                       # number of overall misses
+system.l2c.overall_misses::cpu1.dtb.walker           21                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst             6609                       # number of overall misses
+system.l2c.overall_misses::cpu1.data            82900                       # number of overall misses
+system.l2c.overall_misses::total               165337                       # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu0.dtb.walker       471000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.itb.walker        60000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.inst    322261499                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.data    330895497                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.dtb.walker      1101000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst    351559997                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data    332583499                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total     1338932492                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu0.data     20202500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data     27410499                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total     47612999                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data      1721500                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data      7138500                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total      8860000                       # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data   3379920986                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data   4071556980                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   7451477966                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu0.dtb.walker       471000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.itb.walker        60000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.inst    322261499                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data   3710816483                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.dtb.walker      1101000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst    351559997                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data   4404140479                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total      8790410458                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.dtb.walker       471000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.itb.walker        60000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.inst    322261499                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data   3710816483                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.dtb.walker      1101000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst    351559997                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data   4404140479                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total     8790410458                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.dtb.walker        53347                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker         6107                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.inst         404763                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data         170766                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker        78907                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker         6452                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst         621738                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data         206030                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            1548110                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       645710                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           645710                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data         6726                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data         5093                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total           11819                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data          990                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data          732                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total          1722                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       111481                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data       135761                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           247242                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker        53347                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker         6107                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst          404763                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data          282247                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker        78907                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker         6452                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          621738                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data          341791                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             1795352                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker        53347                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker         6107                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         404763                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data         282247                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker        78907                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker         6452                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         621738                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data         341791                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            1795352                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000169                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000164                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.014932                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.036904                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000266                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.010630                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data      0.030714                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.016352                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.844930                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.841744                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.843557                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.784848                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.804645                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.793264                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.569164                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.564021                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.566340                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000169                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.000164                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.014932                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.247135                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000266                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.010630                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.242546                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.092092                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000169                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.000164                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.014932                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.247135                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000266                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.010630                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.242546                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.092092                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52333.333333                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        60000                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53319.242058                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.data 52506.426055                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52428.571429                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 53194.128764                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 52557.442952                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 52892.964052                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  3554.900581                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  6393.864941                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  4775.626780                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  2215.572716                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 12119.694397                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total  6486.090776                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 53268.206742                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53172.921956                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 53216.099969                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52333.333333                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.itb.walker        60000                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 53319.242058                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 53199.381862                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52428.571429                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 53194.128764                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 53125.940639                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 53166.626091                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52333.333333                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.itb.walker        60000                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 53319.242058                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 53199.381862                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52428.571429                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 53194.128764                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 53125.940639                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 53166.626091                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -341,180 +323,170 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               66834                       # number of writebacks
-system.l2c.writebacks::total                    66834                       # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu0.inst             4                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu0.data            38                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.inst             6                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.data            25                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total                73                       # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.inst              4                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.data             38                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst              6                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.data             25                       # number of demand (read+write) MSHR hits
+system.l2c.writebacks::writebacks               66320                       # number of writebacks
+system.l2c.writebacks::total                    66320                       # number of writebacks
+system.l2c.ReadReq_mshr_hits::cpu0.inst             5                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu0.data            39                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu1.inst             5                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu1.data            23                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::total                72                       # number of ReadReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu0.data            1                       # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::total               1                       # number of ReadExReq MSHR hits
+system.l2c.demand_mshr_hits::cpu0.inst              5                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu0.data             40                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.inst              5                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.data             23                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_hits::total                 73                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.inst             4                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu0.data            38                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst             6                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.data            25                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu0.inst             5                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu0.data            40                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.inst             5                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.data            23                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::total                73                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker           10                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker            9                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            1                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.inst         5849                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.data         6101                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker           15                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.itb.walker            2                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst         6803                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data         6512                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total           25293                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data         5294                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data         4767                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total        10061                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          775                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          577                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total         1352                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data        62637                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data        77700                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        140337                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.dtb.walker           10                       # number of demand (read+write) MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.inst         6039                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.data         6263                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker           21                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.inst         6604                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.data         6305                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total           25242                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data         5683                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data         4287                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total         9970                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          777                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          589                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total         1366                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data        63450                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data        76572                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        140022                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.dtb.walker            9                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu0.itb.walker            1                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst         5849                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data        68738                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker           15                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.itb.walker            2                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst         6803                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data        84212                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           165630                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.dtb.walker           10                       # number of overall MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst         6039                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data        69713                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.dtb.walker           21                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst         6604                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data        82877                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           165264                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.dtb.walker            9                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu0.itb.walker            1                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst         5849                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data        68738                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.dtb.walker           15                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.itb.walker            2                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst         6803                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data        84212                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          165630                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker       400000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker        41000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    234434500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.data    244221500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker       601000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker        80000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    273121500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data    260689500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total   1013589000                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    211949500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    190864500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total    402814000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     31033000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     23118500                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total     54151500                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   2507451999                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   3115007000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   5622458999                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker       400000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.itb.walker        41000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst    234434500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data   2751673499                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       601000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.itb.walker        80000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst    273121500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data   3375696500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total   6636047999                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker       400000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.itb.walker        41000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst    234434500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data   2751673499                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       601000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.itb.walker        80000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst    273121500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data   3375696500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total   6636047999                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst      5501500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data  21616744000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      2009500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 110336260000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 131960515000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data    713445484                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data  31812115712                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total  32525561196                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.inst      5501500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data  22330189484                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      2009500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data 142148375712                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 164486076196                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000197                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000168                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.014586                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.036356                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000189                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.000303                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.010858                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.031171                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.016352                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.860114                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.814593                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.837928                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.787602                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.778677                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.783768                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.551596                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.581966                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.568007                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000197                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000168                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.014586                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.244298                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000189                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.000303                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.010858                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.245928                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.092330                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000197                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000168                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.014586                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.244298                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000189                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.000303                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.010858                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.245928                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.092330                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_misses::cpu0.inst         6039                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data        69713                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.dtb.walker           21                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst         6604                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data        82877                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          165264                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker       360000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker        48000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    248302999                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.data    253032000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker       846000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    270719997                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data    254713500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total   1028022496                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    227576000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    171718000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    399294000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     31112500                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     23586500                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total     54699000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   2608560498                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   3134816489                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   5743376987                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker       360000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.itb.walker        48000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst    248302999                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data   2861592498                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       846000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst    270719997                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data   3389529989                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   6771399483                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker       360000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.itb.walker        48000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst    248302999                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data   2861592498                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       846000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    270719997                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data   3389529989                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   6771399483                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst      5579000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   9186859000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      2133500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 122397706500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 131592278000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data    704572999                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data  30781654107                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total  31486227106                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.inst      5579000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   9891431999                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      2133500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data 153179360607                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 163078505106                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000169                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000164                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.014920                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.036676                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000266                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.010622                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.030602                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.016305                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.844930                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.841744                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.843557                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.784848                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.804645                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.793264                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.569155                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.564021                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.566336                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000169                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000164                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.014920                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.246993                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000266                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.010622                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.242479                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.092051                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000169                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000164                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.014920                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.246993                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000266                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.010622                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.242479                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.092051                       # mshr miss rate for overall accesses
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker        40000                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        41000                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40081.124979                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40029.749221                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40066.666667                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker        40000                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40147.214464                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40032.171376                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 40073.893963                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40035.795240                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40038.703587                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40037.173243                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40042.580645                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40066.724437                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40052.884615                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40031.482973                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40090.180180                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 40063.981694                       # average ReadExReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        48000                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41116.575426                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40401.085742                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40285.714286                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40993.336917                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40398.651864                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 40726.665716                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40045.046630                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40055.516678                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40049.548646                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40041.827542                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40044.991511                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40043.191801                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41112.064586                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40939.462062                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 41017.675701                       # average ReadExReq mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker        40000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        41000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40081.124979                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40031.329090                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40066.666667                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker        40000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40147.214464                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40085.694438                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 40065.495375                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        48000                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41116.575426                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 41048.190409                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40285.714286                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40993.336917                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40898.319063                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 40973.227581                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker        40000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        41000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40081.124979                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40031.329090                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40066.666667                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker        40000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40147.214464                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40085.694438                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 40065.495375                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        48000                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41116.575426                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 41048.190409                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40285.714286                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40993.336917                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40898.319063                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 40973.227581                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
@@ -537,27 +509,27 @@ system.cf0.dma_write_bytes                          0                       # Nu
 system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    12222008                       # DTB read hits
-system.cpu0.dtb.read_misses                     34799                       # DTB read misses
-system.cpu0.dtb.write_hits                    5155654                       # DTB write hits
-system.cpu0.dtb.write_misses                     4970                       # DTB write misses
+system.cpu0.dtb.read_hits                     9084255                       # DTB read hits
+system.cpu0.dtb.read_misses                     36769                       # DTB read misses
+system.cpu0.dtb.write_hits                    5284576                       # DTB write hits
+system.cpu0.dtb.write_misses                     6773                       # DTB write misses
 system.cpu0.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    2546                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                     1270                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                   369                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries                    2261                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                     1412                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                   383                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      661                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                12256807                       # DTB read accesses
-system.cpu0.dtb.write_accesses                5160624                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      588                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                 9121024                       # DTB read accesses
+system.cpu0.dtb.write_accesses                5291349                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         17377662                       # DTB hits
-system.cpu0.dtb.misses                          39769                       # DTB misses
-system.cpu0.dtb.accesses                     17417431                       # DTB accesses
-system.cpu0.itb.inst_hits                     4312814                       # ITB inst hits
-system.cpu0.itb.inst_misses                      5659                       # ITB inst misses
+system.cpu0.dtb.hits                         14368831                       # DTB hits
+system.cpu0.dtb.misses                          43542                       # DTB misses
+system.cpu0.dtb.accesses                     14412373                       # DTB accesses
+system.cpu0.itb.inst_hits                     4421795                       # ITB inst hits
+system.cpu0.itb.inst_misses                      5958                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
@@ -566,542 +538,542 @@ system.cpu0.itb.flush_tlb                           4                       # Nu
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
 system.cpu0.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    1615                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries                    1415                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                     1550                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                     1713                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                 4318473                       # ITB inst accesses
-system.cpu0.itb.hits                          4312814                       # DTB hits
-system.cpu0.itb.misses                           5659                       # DTB misses
-system.cpu0.itb.accesses                      4318473                       # DTB accesses
-system.cpu0.numCycles                        91755333                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                 4427753                       # ITB inst accesses
+system.cpu0.itb.hits                          4421795                       # DTB hits
+system.cpu0.itb.misses                           5958                       # DTB misses
+system.cpu0.itb.accesses                      4427753                       # DTB accesses
+system.cpu0.numCycles                        66112093                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.BPredUnit.lookups                 5952266                       # Number of BP lookups
-system.cpu0.BPredUnit.condPredicted           4505075                       # Number of conditional branches predicted
-system.cpu0.BPredUnit.condIncorrect            304047                       # Number of conditional branches incorrect
-system.cpu0.BPredUnit.BTBLookups              3800923                       # Number of BTB lookups
-system.cpu0.BPredUnit.BTBHits                 2764349                       # Number of BTB hits
+system.cpu0.BPredUnit.lookups                 6172143                       # Number of BP lookups
+system.cpu0.BPredUnit.condPredicted           4680207                       # Number of conditional branches predicted
+system.cpu0.BPredUnit.condIncorrect            316413                       # Number of conditional branches incorrect
+system.cpu0.BPredUnit.BTBLookups              3902841                       # Number of BTB lookups
+system.cpu0.BPredUnit.BTBHits                 2861272                       # Number of BTB hits
 system.cpu0.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.BPredUnit.usedRAS                  686219                       # Number of times the RAS was used to get a target.
-system.cpu0.BPredUnit.RASInCorrect              29965                       # Number of incorrect RAS predictions.
-system.cpu0.fetch.icacheStallCycles          12225669                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                      31634782                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                    5952266                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches           3450568                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                      7438203                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles                1498517                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles                     86111                       # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.BlockedCycles              25429329                       # Number of cycles fetch has spent blocked
-system.cpu0.fetch.MiscStallCycles                5796                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles        56004                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles        89121                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles          253                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                  4310960                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes               168036                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes                   2895                       # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples          46396814                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             0.887686                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            2.274992                       # Number of instructions fetched each cycle (Total)
+system.cpu0.BPredUnit.usedRAS                  700420                       # Number of times the RAS was used to get a target.
+system.cpu0.BPredUnit.RASInCorrect              30889                       # Number of incorrect RAS predictions.
+system.cpu0.fetch.icacheStallCycles          12972431                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                      32579396                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                    6172143                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches           3561692                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                      7636967                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles                1568394                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles                     92289                       # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.BlockedCycles              21876805                       # Number of cycles fetch has spent blocked
+system.cpu0.fetch.MiscStallCycles                5742                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles        73340                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles        91549                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles          175                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                  4419869                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes               175391                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes                   2999                       # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples          43870869                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             0.963501                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            2.353712                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0                38966492     83.99%     83.99% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                  608768      1.31%     85.30% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                  793531      1.71%     87.01% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                  678621      1.46%     88.47% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4                  615872      1.33%     89.80% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5                  550838      1.19%     90.98% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6                  680018      1.47%     92.45% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7                  365085      0.79%     93.24% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8                 3137589      6.76%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0                36242473     82.61%     82.61% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                  623814      1.42%     84.03% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                  820212      1.87%     85.90% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                  686089      1.56%     87.47% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4                  622737      1.42%     88.89% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5                  578948      1.32%     90.21% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6                  720296      1.64%     91.85% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7                  370745      0.85%     92.69% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8                 3205555      7.31%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total            46396814                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.064871                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.344773                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles                12690058                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles             25456221                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                  6703467                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles               545759                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles               1001309                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved              958631                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred                66338                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts              39766150                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts               219028                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles               1001309                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles                13289637                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles                7972865                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles      15343248                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                  6631332                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles              2158423                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts              38589176                       # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents                  848                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents                416461                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LSQFullEvents              1242307                       # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.FullRegisterEvents             106                       # Number of times there has been no free registers
-system.cpu0.rename.RenamedOperands           38596643                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups            175113710                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups       175069465                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups            44245                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps             30775876                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                 7820767                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts            452714                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts        409285                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                  5195885                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads             7781233                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores            5757511                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads          1120127                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores         1192401                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                  36577178                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded             791583                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                 40176979                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued            83237                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined        5967561                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined     13599049                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved        145097                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples     46396814                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.865943                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.513269                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total            43870869                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.093359                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.492790                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles                13461534                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles             21912526                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                  6836712                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles               603785                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles               1056312                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved              995110                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred                66550                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts              40827533                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts               217718                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles               1056312                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles                14066817                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles                6153021                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles      13456769                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                  6788701                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles              2349249                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts              39593607                       # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents                 1040                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents                472233                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LSQFullEvents              1335984                       # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.FullRegisterEvents             103                       # Number of times there has been no free registers
+system.cpu0.rename.RenamedOperands           39791095                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups            179675714                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups       179640853                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups            34861                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps             31537071                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                 8254023                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts            463697                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts        419128                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                  5673165                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads             7928571                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores            5881726                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads          1132931                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores         1238845                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                  37538443                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded             794373                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                 37739879                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued            92690                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined        6264606                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined     14354053                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved        137507                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples     43870869                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.860249                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.478315                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0           30520128     65.78%     65.78% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1            5937185     12.80%     78.58% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2            3046653      6.57%     85.14% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3            2264959      4.88%     90.03% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4            2893477      6.24%     96.26% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5             928258      2.00%     98.26% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6             563400      1.21%     99.48% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7             186019      0.40%     99.88% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8              56735      0.12%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0           28164784     64.20%     64.20% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1            6326126     14.42%     78.62% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2            3234526      7.37%     85.99% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3            2361316      5.38%     91.37% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4            2098246      4.78%     96.16% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5             936106      2.13%     98.29% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6             514694      1.17%     99.46% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7             181493      0.41%     99.88% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8              53578      0.12%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total       46396814                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total       43870869                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                  26385      1.46%      1.46% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                   453      0.03%      1.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                      0      0.00%      1.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%      1.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%      1.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%      1.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%      1.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%      1.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%      1.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%      1.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%      1.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%      1.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%      1.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%      1.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%      1.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%      1.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%      1.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%      1.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%      1.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%      1.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%      1.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%      1.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%      1.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%      1.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%      1.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%      1.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%      1.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%      1.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%      1.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead               1567613     86.92%     88.41% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite               209022     11.59%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                  27565      2.58%      2.58% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                   466      0.04%      2.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                      0      0.00%      2.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%      2.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%      2.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%      2.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%      2.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%      2.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%      2.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%      2.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%      2.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%      2.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%      2.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%      2.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%      2.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%      2.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%      2.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%      2.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%      2.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%      2.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%      2.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%      2.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%      2.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%      2.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%      2.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%      2.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%      2.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%      2.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%      2.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead                837939     78.44%     81.06% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite               202337     18.94%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass            25309      0.06%      0.06% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu             21935197     54.60%     54.66% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult               48039      0.12%     54.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     54.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     54.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     54.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     54.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     54.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     54.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     54.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     54.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     54.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     54.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     54.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     54.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                 11      0.00%     54.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     54.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     54.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 3      0.00%     54.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              8      0.00%     54.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     54.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     54.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     54.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     54.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     54.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     54.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc           725      0.00%     54.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     54.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            8      0.00%     54.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     54.78% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead            12687286     31.58%     86.36% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite            5480393     13.64%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass            20407      0.05%      0.05% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu             22494595     59.60%     59.66% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult               50051      0.13%     59.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     59.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     59.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     59.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     59.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     59.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     59.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     59.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     59.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     59.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   1      0.00%     59.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     59.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     59.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  8      0.00%     59.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     59.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     59.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 2      0.00%     59.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              5      0.00%     59.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     59.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     59.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     59.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     59.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     59.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     59.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc           684      0.00%     59.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     59.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            5      0.00%     59.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     59.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead             9563453     25.34%     85.13% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite            5610668     14.87%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total              40176979                       # Type of FU issued
-system.cpu0.iq.rate                          0.437871                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                    1803473                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.044888                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads         128665759                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes         43343315                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses     34031138                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads              11205                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes              6096                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses         4927                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses              41949154                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                   5989                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads          311358                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total              37739879                       # Type of FU issued
+system.cpu0.iq.rate                          0.570847                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                    1068307                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.028307                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads         120546534                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes         44606042                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses     34820056                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads               8333                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes              4740                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses         3893                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses              38783456                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                   4323                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads          326383                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads      1414489                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses         4027                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation        13694                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores       607908                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads      1507630                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses         4080                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation        13930                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores       608245                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads      5397304                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked         5188                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads      2149509                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked         5404                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles               1001309                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles                6077720                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles               124694                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts           37485087                       # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts            95046                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts              7781233                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts             5757511                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts            467034                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                 52649                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents                 4313                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents         13694                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect        153875                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect       138964                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts              292839                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts             39778235                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts             12530314                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts           398744                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles               1056312                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles                4064319                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles               129740                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts           38471177                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts            88757                       # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts              7928571                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts             5881726                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts            461616                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                 49674                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents                17745                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents         13930                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect        159357                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect       144737                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts              304094                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts             37337331                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts              9402148                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts           402548                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                       116326                       # number of nop insts executed
-system.cpu0.iew.exec_refs                    17957262                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches                 4780864                       # Number of branches executed
-system.cpu0.iew.exec_stores                   5426948                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.433525                       # Inst execution rate
-system.cpu0.iew.wb_sent                      39572300                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                     34036065                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                 18213937                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                 35297892                       # num instructions consuming a value
+system.cpu0.iew.exec_nop                       138361                       # number of nop insts executed
+system.cpu0.iew.exec_refs                    14958639                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches                 4921687                       # Number of branches executed
+system.cpu0.iew.exec_stores                   5556491                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.564758                       # Inst execution rate
+system.cpu0.iew.wb_sent                      37117116                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                     34823949                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                 18360594                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                 34980725                       # num instructions consuming a value
 system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate                      0.370944                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.516006                       # average fanout of values written-back
+system.cpu0.iew.wb_rate                      0.526741                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.524877                       # average fanout of values written-back
 system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitCommittedInsts      23601687                       # The number of committed instructions
-system.cpu0.commit.commitCommittedOps        31186721                       # The number of committed instructions
-system.cpu0.commit.commitSquashedInsts        6143896                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls         646486                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts           256571                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples     45430638                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.686469                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.654503                       # Number of insts commited each cycle
+system.cpu0.commit.commitCommittedInsts      24134633                       # The number of committed instructions
+system.cpu0.commit.commitCommittedOps        31866160                       # The number of committed instructions
+system.cpu0.commit.commitSquashedInsts        6466683                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls         656866                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts           267750                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples     42850944                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.743651                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.697776                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0     33717084     74.22%     74.22% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1      5850006     12.88%     87.09% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2      1884843      4.15%     91.24% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3       960822      2.11%     93.36% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4       731888      1.61%     94.97% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5       454898      1.00%     95.97% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6       476885      1.05%     97.02% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7       212485      0.47%     97.49% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8      1141727      2.51%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0     30739496     71.74%     71.74% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1      6075340     14.18%     85.91% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2      1944692      4.54%     90.45% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3      1041937      2.43%     92.88% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4       773699      1.81%     94.69% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5       503770      1.18%     95.86% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6       405337      0.95%     96.81% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7       203427      0.47%     97.29% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8      1163246      2.71%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total     45430638                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts            23601687                       # Number of instructions committed
-system.cpu0.commit.committedOps              31186721                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total     42850944                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts            24134633                       # Number of instructions committed
+system.cpu0.commit.committedOps              31866160                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                      11516347                       # Number of memory references committed
-system.cpu0.commit.loads                      6366744                       # Number of loads committed
-system.cpu0.commit.membars                     228774                       # Number of memory barriers committed
-system.cpu0.commit.branches                   4268909                       # Number of branches committed
-system.cpu0.commit.fp_insts                      4838                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                 27636133                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls              492618                       # Number of function calls committed.
-system.cpu0.commit.bw_lim_events              1141727                       # number cycles where commit BW limit reached
+system.cpu0.commit.refs                      11694422                       # Number of memory references committed
+system.cpu0.commit.loads                      6420941                       # Number of loads committed
+system.cpu0.commit.membars                     234529                       # Number of memory barriers committed
+system.cpu0.commit.branches                   4382702                       # Number of branches committed
+system.cpu0.commit.fp_insts                      3838                       # Number of committed floating point instructions.
+system.cpu0.commit.int_insts                 28193395                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls              499856                       # Number of function calls committed.
+system.cpu0.commit.bw_lim_events              1163246                       # number cycles where commit BW limit reached
 system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads                    80832744                       # The number of ROB reads
-system.cpu0.rob.rob_writes                   75665562                       # The number of ROB writes
-system.cpu0.timesIdled                         511317                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                       45358519                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                  5047039822                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                   23536584                       # Number of Instructions Simulated
-system.cpu0.committedOps                     31121618                       # Number of Ops (including micro ops) Simulated
-system.cpu0.committedInsts_total             23536584                       # Number of Instructions Simulated
-system.cpu0.cpi                              3.898413                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        3.898413                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.256515                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.256515                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads               183926116                       # number of integer regfile reads
-system.cpu0.int_regfile_writes               33429350                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                     4511                       # number of floating regfile reads
-system.cpu0.fp_regfile_writes                     934                       # number of floating regfile writes
-system.cpu0.misc_regfile_reads               45525801                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes                515221                       # number of misc regfile writes
-system.cpu0.icache.replacements                402234                       # number of replacements
-system.cpu0.icache.tagsinuse               511.630403                       # Cycle average of tags in use
-system.cpu0.icache.total_refs                 3875529                       # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs                402746                       # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs                  9.622762                       # Average number of references to valid blocks.
-system.cpu0.icache.warmup_cycle            6260006000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst   511.630403                       # Average occupied blocks per requestor
-system.cpu0.icache.occ_percent::cpu0.inst     0.999278                       # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::total        0.999278                       # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst      3875529                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total        3875529                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst      3875529                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total         3875529                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst      3875529                       # number of overall hits
-system.cpu0.icache.overall_hits::total        3875529                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       435289                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       435289                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       435289                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        435289                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       435289                       # number of overall misses
-system.cpu0.icache.overall_misses::total       435289                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   6419795491                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total   6419795491                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst   6419795491                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total   6419795491                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst   6419795491                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total   6419795491                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst      4310818                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total      4310818                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst      4310818                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total      4310818                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst      4310818                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total      4310818                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.100976                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.100976                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.100976                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.100976                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.100976                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.100976                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14748.352223                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 14748.352223                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14748.352223                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 14748.352223                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14748.352223                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 14748.352223                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs      1456992                       # number of cycles access was blocked
+system.cpu0.rob.rob_reads                    79207972                       # The number of ROB reads
+system.cpu0.rob.rob_writes                   77724528                       # The number of ROB writes
+system.cpu0.timesIdled                         427936                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                       22241224                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                  5096899290                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                   24053891                       # Number of Instructions Simulated
+system.cpu0.committedOps                     31785418                       # Number of Ops (including micro ops) Simulated
+system.cpu0.committedInsts_total             24053891                       # Number of Instructions Simulated
+system.cpu0.cpi                              2.748499                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        2.748499                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.363835                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.363835                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads               174526329                       # number of integer regfile reads
+system.cpu0.int_regfile_writes               34331240                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                     3280                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                     898                       # number of floating regfile writes
+system.cpu0.misc_regfile_reads               46875879                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes                527497                       # number of misc regfile writes
+system.cpu0.icache.replacements                406974                       # number of replacements
+system.cpu0.icache.tagsinuse               511.614338                       # Cycle average of tags in use
+system.cpu0.icache.total_refs                 3978434                       # Total number of references to valid blocks.
+system.cpu0.icache.sampled_refs                407486                       # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs                  9.763364                       # Average number of references to valid blocks.
+system.cpu0.icache.warmup_cycle            6469268000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.occ_blocks::cpu0.inst   511.614338                       # Average occupied blocks per requestor
+system.cpu0.icache.occ_percent::cpu0.inst     0.999247                       # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::total        0.999247                       # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits::cpu0.inst      3978434                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total        3978434                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst      3978434                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total         3978434                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst      3978434                       # number of overall hits
+system.cpu0.icache.overall_hits::total        3978434                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       441298                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       441298                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       441298                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        441298                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       441298                       # number of overall misses
+system.cpu0.icache.overall_misses::total       441298                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   7186656997                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total   7186656997                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst   7186656997                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total   7186656997                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst   7186656997                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total   7186656997                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst      4419732                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total      4419732                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst      4419732                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total      4419732                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst      4419732                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total      4419732                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.099847                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.099847                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.099847                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.099847                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.099847                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.099847                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16285.269811                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 16285.269811                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16285.269811                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 16285.269811                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16285.269811                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 16285.269811                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs      1454497                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              163                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              171                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs  8938.601227                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs  8505.830409                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.writebacks::writebacks        31582                       # number of writebacks
-system.cpu0.icache.writebacks::total            31582                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        32527                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        32527                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst        32527                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        32527                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst        32527                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        32527                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       402762                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       402762                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       402762                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       402762                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       402762                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       402762                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   4809385492                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total   4809385492                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   4809385492                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total   4809385492                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   4809385492                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total   4809385492                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst      7376000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total      7376000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst      7376000                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total      7376000                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.093431                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.093431                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.093431                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.093431                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.093431                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.093431                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11941.011049                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11941.011049                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11941.011049                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 11941.011049                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11941.011049                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 11941.011049                       # average overall mshr miss latency
+system.cpu0.icache.writebacks::writebacks        29234                       # number of writebacks
+system.cpu0.icache.writebacks::total            29234                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        33802                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        33802                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst        33802                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        33802                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst        33802                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        33802                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       407496                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       407496                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       407496                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       407496                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       407496                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       407496                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   5527499503                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total   5527499503                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   5527499503                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total   5527499503                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   5527499503                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   5527499503                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst      8379000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total      8379000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst      8379000                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total      8379000                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.092199                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.092199                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.092199                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.092199                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.092199                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.092199                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13564.549107                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13564.549107                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13564.549107                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 13564.549107                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13564.549107                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 13564.549107                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.replacements                272390                       # number of replacements
-system.cpu0.dcache.tagsinuse               477.646995                       # Cycle average of tags in use
-system.cpu0.dcache.total_refs                 9259935                       # Total number of references to valid blocks.
-system.cpu0.dcache.sampled_refs                272772                       # Sample count of references to valid blocks.
-system.cpu0.dcache.avg_refs                 33.947528                       # Average number of references to valid blocks.
-system.cpu0.dcache.warmup_cycle              49645000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::cpu0.data   477.646995                       # Average occupied blocks per requestor
-system.cpu0.dcache.occ_percent::cpu0.data     0.932904                       # Average percentage of cache occupancy
-system.cpu0.dcache.occ_percent::total        0.932904                       # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::cpu0.data      5751664                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        5751664                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      3128629                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       3128629                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       172667                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       172667                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       169954                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       169954                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data      8880293                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total         8880293                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data      8880293                       # number of overall hits
-system.cpu0.dcache.overall_hits::total        8880293                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       380393                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       380393                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1568163                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      1568163                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         9112                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total         9112                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data         7881                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total         7881                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      1948556                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       1948556                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      1948556                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      1948556                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   5112833000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total   5112833000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  57745298395                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  57745298395                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    100839000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    100839000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     84292000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total     84292000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  62858131395                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  62858131395                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  62858131395                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  62858131395                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      6132057                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      6132057                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      4696792                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      4696792                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       181779                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       181779                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       177835                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       177835                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     10828849                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     10828849                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     10828849                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     10828849                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.062034                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.062034                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.333880                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.333880                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.050127                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.050127                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.044316                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.044316                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.179941                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.179941                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.179941                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.179941                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13440.922940                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 13440.922940                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 36823.530714                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 36823.530714                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11066.615452                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11066.615452                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 10695.597005                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 10695.597005                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32258.827252                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 32258.827252                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32258.827252                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 32258.827252                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs      3762493                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets      1470000                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs              438                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets             79                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs  8590.166667                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets 18607.594937                       # average number of cycles each access was blocked
+system.cpu0.dcache.replacements                275761                       # number of replacements
+system.cpu0.dcache.tagsinuse               476.305820                       # Cycle average of tags in use
+system.cpu0.dcache.total_refs                 9551525                       # Total number of references to valid blocks.
+system.cpu0.dcache.sampled_refs                276273                       # Sample count of references to valid blocks.
+system.cpu0.dcache.avg_refs                 34.572778                       # Average number of references to valid blocks.
+system.cpu0.dcache.warmup_cycle              51448000                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.occ_blocks::cpu0.data   476.305820                       # Average occupied blocks per requestor
+system.cpu0.dcache.occ_percent::cpu0.data     0.930285                       # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::total        0.930285                       # Average percentage of cache occupancy
+system.cpu0.dcache.ReadReq_hits::cpu0.data      5934693                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        5934693                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      3224707                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       3224707                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       174478                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       174478                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       171499                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       171499                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data      9159400                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total         9159400                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data      9159400                       # number of overall hits
+system.cpu0.dcache.overall_hits::total        9159400                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       401255                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       401255                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      1594245                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      1594245                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         9007                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total         9007                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data         7794                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total         7794                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      1995500                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       1995500                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      1995500                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      1995500                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   7289566500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total   7289566500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  71816395371                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  71816395371                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    114642500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    114642500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     93715000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total     93715000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  79105961871                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  79105961871                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  79105961871                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  79105961871                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      6335948                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      6335948                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      4818952                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      4818952                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       183485                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       183485                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       179293                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       179293                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     11154900                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     11154900                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     11154900                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     11154900                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.063330                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.063330                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.330828                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.330828                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.049088                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.049088                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.043471                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.043471                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.178890                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.178890                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.178890                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.178890                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 18166.917546                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 18166.917546                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45047.276530                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 45047.276530                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12728.155879                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12728.155879                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 12023.992815                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 12023.992815                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39642.175831                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 39642.175831                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39642.175831                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 39642.175831                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs      7140493                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets      1629000                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs             1441                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets             89                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs  4955.234559                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets 18303.370787                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       253456                       # number of writebacks
-system.cpu0.dcache.writebacks::total           253456                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       195063                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       195063                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1436472                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      1436472                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data          621                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total          621                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      1631535                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      1631535                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      1631535                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      1631535                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       185330                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       185330                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       131691                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       131691                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         8491                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8491                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         7877                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total         7877                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       317021                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       317021                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       317021                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       317021                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2232196000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2232196000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   4281157492                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4281157492                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     67651500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     67651500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     60619000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     60619000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   6513353492                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total   6513353492                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   6513353492                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total   6513353492                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  24166586500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  24166586500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data    850308391                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total    850308391                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  25016894891                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  25016894891                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.030223                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.030223                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.028038                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.028038                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.046711                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.046711                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.044294                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.044294                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.029276                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.029276                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.029276                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.029276                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12044.439648                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12044.439648                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32509.112179                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32509.112179                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data  7967.436109                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  7967.436109                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  7695.696331                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  7695.696331                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20545.495384                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20545.495384                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20545.495384                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20545.495384                       # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks       255942                       # number of writebacks
+system.cpu0.dcache.writebacks::total           255942                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       211815                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       211815                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1463184                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      1463184                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data          509                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total          509                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      1674999                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      1674999                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      1674999                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      1674999                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       189440                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       189440                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       131061                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       131061                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         8498                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8498                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         7791                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total         7791                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       320501                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       320501                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       320501                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       320501                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2806583905                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2806583905                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   4685193022                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4685193022                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     80265007                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     80265007                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     69214057                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     69214057                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   7491776927                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total   7491776927                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   7491776927                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total   7491776927                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  10315161000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  10315161000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data    849550399                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total    849550399                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  11164711399                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11164711399                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.029899                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.029899                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.027197                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.027197                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.046314                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.046314                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.043454                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.043454                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.028732                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.028732                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.028732                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.028732                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14815.159971                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14815.159971                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35748.186127                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35748.186127                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data  9445.164392                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  9445.164392                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  8883.847645                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  8883.847645                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23375.206090                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23375.206090                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23375.206090                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23375.206090                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1111,27 +1083,27 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    40314372                       # DTB read hits
-system.cpu1.dtb.read_misses                     47835                       # DTB read misses
-system.cpu1.dtb.write_hits                    7207214                       # DTB write hits
-system.cpu1.dtb.write_misses                    14308                       # DTB write misses
+system.cpu1.dtb.read_hits                    43446349                       # DTB read hits
+system.cpu1.dtb.read_misses                     46684                       # DTB read misses
+system.cpu1.dtb.write_hits                    7088138                       # DTB write hits
+system.cpu1.dtb.write_misses                    12274                       # DTB write misses
 system.cpu1.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    2204                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                     3789                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   426                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries                    2545                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                     3731                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                   361                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                      618                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                40362207                       # DTB read accesses
-system.cpu1.dtb.write_accesses                7221522                       # DTB write accesses
+system.cpu1.dtb.perms_faults                      673                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                43493033                       # DTB read accesses
+system.cpu1.dtb.write_accesses                7100412                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         47521586                       # DTB hits
-system.cpu1.dtb.misses                          62143                       # DTB misses
-system.cpu1.dtb.accesses                     47583729                       # DTB accesses
-system.cpu1.itb.inst_hits                     9199147                       # ITB inst hits
-system.cpu1.itb.inst_misses                      6537                       # ITB inst misses
+system.cpu1.dtb.hits                         50534487                       # DTB hits
+system.cpu1.dtb.misses                          58958                       # DTB misses
+system.cpu1.dtb.accesses                     50593445                       # DTB accesses
+system.cpu1.itb.inst_hits                     9221438                       # ITB inst hits
+system.cpu1.itb.inst_misses                      6034                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
@@ -1140,542 +1112,546 @@ system.cpu1.itb.flush_tlb                           4                       # Nu
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
 system.cpu1.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                    1398                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                    1610                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                     1778                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                     1730                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                 9205684                       # ITB inst accesses
-system.cpu1.itb.hits                          9199147                       # DTB hits
-system.cpu1.itb.misses                           6537                       # DTB misses
-system.cpu1.itb.accesses                      9205684                       # DTB accesses
-system.cpu1.numCycles                       321589455                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                 9227472                       # ITB inst accesses
+system.cpu1.itb.hits                          9221438                       # DTB hits
+system.cpu1.itb.misses                           6034                       # DTB misses
+system.cpu1.itb.accesses                      9227472                       # DTB accesses
+system.cpu1.numCycles                       353824423                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.BPredUnit.lookups                 9609219                       # Number of BP lookups
-system.cpu1.BPredUnit.condPredicted           7804241                       # Number of conditional branches predicted
-system.cpu1.BPredUnit.condIncorrect            456907                       # Number of conditional branches incorrect
-system.cpu1.BPredUnit.BTBLookups              6466725                       # Number of BTB lookups
-system.cpu1.BPredUnit.BTBHits                 5325877                       # Number of BTB hits
+system.cpu1.BPredUnit.lookups                 9470897                       # Number of BP lookups
+system.cpu1.BPredUnit.condPredicted           7703385                       # Number of conditional branches predicted
+system.cpu1.BPredUnit.condIncorrect            447489                       # Number of conditional branches incorrect
+system.cpu1.BPredUnit.BTBLookups              6420671                       # Number of BTB lookups
+system.cpu1.BPredUnit.BTBHits                 5281203                       # Number of BTB hits
 system.cpu1.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.BPredUnit.usedRAS                  844527                       # Number of times the RAS was used to get a target.
-system.cpu1.BPredUnit.RASInCorrect              50619                       # Number of incorrect RAS predictions.
-system.cpu1.fetch.icacheStallCycles          21504333                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                      71435147                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                    9609219                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches           6170404                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                     15136389                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles                4734420                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles                     89053                       # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.BlockedCycles              66067639                       # Number of cycles fetch has spent blocked
-system.cpu1.fetch.MiscStallCycles                5715                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles        64771                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles       143196                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles           87                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                  9197098                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes               766779                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes                   3914                       # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples         106241109                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             0.815152                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            2.196213                       # Number of instructions fetched each cycle (Total)
+system.cpu1.BPredUnit.usedRAS                  834152                       # Number of times the RAS was used to get a target.
+system.cpu1.BPredUnit.RASInCorrect              50449                       # Number of incorrect RAS predictions.
+system.cpu1.fetch.icacheStallCycles          22167103                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                      70445168                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                    9470897                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches           6115355                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                     14956565                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles                4597208                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles                     88094                       # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.BlockedCycles              73687570                       # Number of cycles fetch has spent blocked
+system.cpu1.fetch.MiscStallCycles                6011                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles        61739                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles       141755                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles          192                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                  9219303                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes               857673                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes                   3541                       # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples         114241434                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             0.747913                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            2.114106                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0                91113370     85.76%     85.76% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                  835957      0.79%     86.55% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                 1038807      0.98%     87.53% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                 2054123      1.93%     89.46% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4                 1283354      1.21%     90.67% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5                  639035      0.60%     91.27% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6                 2277082      2.14%     93.41% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7                  459375      0.43%     93.84% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8                 6540006      6.16%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0                99293168     86.92%     86.92% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                  828706      0.73%     87.64% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                 1015866      0.89%     88.53% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                 2054648      1.80%     90.33% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4                 1280264      1.12%     91.45% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5                  613123      0.54%     91.99% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6                 2273093      1.99%     93.98% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7                  467514      0.41%     94.38% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8                 6415052      5.62%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total           106241109                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.029880                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       0.222131                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                23013271                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles             65947642                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                 13617278                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles               534194                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles               3128724                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved             1272359                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred               103085                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts              80569967                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts               342001                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles               3128724                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles                24438096                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles               29197230                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles      32706540                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                 12706787                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles              4063732                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts              74758294                       # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents                 2356                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents                627503                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LSQFullEvents              2908939                       # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.FullRegisterEvents           45012                       # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands           79187879                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups            346602336                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups       346555262                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups            47074                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps             50022423                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                29165455                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts            496148                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts        429704                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                  7532124                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads            14054260                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores            8745175                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads          1095062                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores         1520090                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                  67170682                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded             857343                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                 88258087                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued           108704                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined       18559774                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined     53338169                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved        154632                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples    106241109                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.830734                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.556038                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total           114241434                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.026767                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       0.199096                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                23740446                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles             73499308                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                 13432186                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles               537783                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles               3031711                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved             1242419                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred               102480                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts              79700896                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts               342426                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles               3031711                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles                25267828                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles               33699109                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles      35312301                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                 12394168                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles              4536317                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts              73261010                       # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents                 3244                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents                714923                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LSQFullEvents              3281779                       # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.FullRegisterEvents           33706                       # Number of times there has been no free registers
+system.cpu1.rename.RenamedOperands           77426546                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups            339504965                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups       339445449                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups            59516                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps             49265102                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                28161444                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts            486276                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts        420659                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                  8155263                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads            14019935                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores            8605996                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads          1069297                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores         1521896                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                  66318588                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded             855610                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                 90596015                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued           108958                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined       18341957                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined     53651445                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved        163223                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples    114241434                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.793022                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.525613                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0           76008182     71.54%     71.54% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1            8446540      7.95%     79.49% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2            4482838      4.22%     83.71% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3            3826420      3.60%     87.31% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4            9985833      9.40%     96.71% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5            1963466      1.85%     98.56% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6            1174590      1.11%     99.67% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7             267511      0.25%     99.92% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8              85729      0.08%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0           83094748     72.74%     72.74% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1            8828314      7.73%     80.46% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2            4518450      3.96%     84.42% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3            3737052      3.27%     87.69% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4           10664138      9.33%     97.02% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5            1972512      1.73%     98.75% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6            1063413      0.93%     99.68% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7             282401      0.25%     99.93% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8              80406      0.07%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total      106241109                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total      114241434                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                  34820      0.48%      0.48% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                   995      0.01%      0.50% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                      0      0.00%      0.50% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      0.50% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      0.50% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      0.50% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%      0.50% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      0.50% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      0.50% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      0.50% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      0.50% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      0.50% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      0.50% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      0.50% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      0.50% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%      0.50% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      0.50% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%      0.50% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      0.50% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      0.50% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      0.50% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      0.50% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      0.50% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      0.50% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      0.50% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      0.50% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      0.50% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      0.50% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      0.50% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead               6868408     95.11%     95.61% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite               317335      4.39%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                  29108      0.37%      0.37% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                   993      0.01%      0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                      0      0.00%      0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%      0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%      0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%      0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead               7574349     95.84%     96.22% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite               298565      3.78%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass            81809      0.09%      0.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu             39074007     44.27%     44.37% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult               63191      0.07%     44.44% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     44.44% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     44.44% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     44.44% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     44.44% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     44.44% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     44.44% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     44.44% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     44.44% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     44.44% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     44.44% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     44.44% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     44.44% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                 10      0.00%     44.44% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     44.44% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     44.44% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 5      0.00%     44.44% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              8      0.00%     44.44% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     44.44% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     44.44% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     44.44% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     44.44% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     44.44% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     44.44% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc          1634      0.00%     44.44% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     44.44% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            8      0.00%     44.44% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     44.44% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead            41444924     46.96%     91.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite            7592491      8.60%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass            86745      0.10%      0.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu             38337785     42.32%     42.41% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult               61539      0.07%     42.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     42.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     42.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     42.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     42.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     42.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     42.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     42.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     42.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     42.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     42.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     42.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     42.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                 11      0.00%     42.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     42.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     42.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 4      0.00%     42.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              6      0.00%     42.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     42.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     42.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     42.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     42.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     42.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     42.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc          1698      0.00%     42.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     42.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            6      0.00%     42.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     42.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead            44639306     49.27%     91.76% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite            7468915      8.24%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total              88258087                       # Type of FU issued
-system.cpu1.iq.rate                          0.274443                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                    7221558                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.081823                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads         290137702                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes         86602000                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses     55480726                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads              11865                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes              6384                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses         5360                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses              95391603                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                   6233                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads          377691                       # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total              90596015                       # Type of FU issued
+system.cpu1.iq.rate                          0.256048                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                    7903015                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.087234                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads         303489486                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes         85529327                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses     54443530                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads              14763                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes              8091                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses         6830                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses              98404572                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                   7713                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads          368848                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads      4014151                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses         6631                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation        21303                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores      1605227                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads      4030694                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses         6909                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation        21919                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores      1587988                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads     28717238                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked      1149940                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads     31965710                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked      1045299                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles               3128724                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles               22478642                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles               328290                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts           68173106                       # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts           141945                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts             14054260                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts             8745175                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts            539434                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                 62530                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents                 3755                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents         21303                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect        237741                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect       202628                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts              440369                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts             85609132                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts             40707747                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts          2648955                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles               3031711                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles               25598263                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles               405605                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts           67299344                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts           135063                       # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts             14019935                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts             8605996                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts            545729                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                 81019                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents                 7196                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents         21919                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect        232087                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect       197105                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts              429192                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts             87765278                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts             43831578                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts          2830737                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                       145081                       # number of nop insts executed
-system.cpu1.iew.exec_refs                    48220727                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches                 7143156                       # Number of branches executed
-system.cpu1.iew.exec_stores                   7512980                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.266206                       # Inst execution rate
-system.cpu1.iew.wb_sent                      84396881                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                     55486086                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                 30755357                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                 55849815                       # num instructions consuming a value
+system.cpu1.iew.exec_nop                       125146                       # number of nop insts executed
+system.cpu1.iew.exec_refs                    51224987                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches                 7024509                       # Number of branches executed
+system.cpu1.iew.exec_stores                   7393409                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.248048                       # Inst execution rate
+system.cpu1.iew.wb_sent                      86598496                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                     54450360                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                 30044182                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                 53342809                       # num instructions consuming a value
 system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate                      0.172537                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.550680                       # average fanout of values written-back
+system.cpu1.iew.wb_rate                      0.153891                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.563228                       # average fanout of values written-back
 system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitCommittedInsts      38569031                       # The number of committed instructions
-system.cpu1.commit.commitCommittedOps        49069302                       # The number of committed instructions
-system.cpu1.commit.commitSquashedInsts       19027054                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls         702711                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts           384240                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples    103162057                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.475653                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.464816                       # Number of insts commited each cycle
+system.cpu1.commit.commitCommittedInsts      38036954                       # The number of committed instructions
+system.cpu1.commit.commitCommittedOps        48396972                       # The number of committed instructions
+system.cpu1.commit.commitSquashedInsts       18817114                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls         692387                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts           376510                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples    111258144                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.434997                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.402953                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0     86125230     83.49%     83.49% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1      8314170      8.06%     91.54% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2      2284328      2.21%     93.76% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3      1318858      1.28%     95.04% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4      1066734      1.03%     96.07% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5       616185      0.60%     96.67% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6      1058049      1.03%     97.69% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7       494277      0.48%     98.17% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8      1884226      1.83%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0     94210177     84.68%     84.68% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1      8524716      7.66%     92.34% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2      2208233      1.98%     94.32% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3      1307974      1.18%     95.50% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4      1064973      0.96%     96.46% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5       589982      0.53%     96.99% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6      1003368      0.90%     97.89% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7       487910      0.44%     98.33% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8      1860811      1.67%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total    103162057                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts            38569031                       # Number of instructions committed
-system.cpu1.commit.committedOps              49069302                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total    111258144                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts            38036954                       # Number of instructions committed
+system.cpu1.commit.committedOps              48396972                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                      17180057                       # Number of memory references committed
-system.cpu1.commit.loads                     10040109                       # Number of loads committed
-system.cpu1.commit.membars                     207982                       # Number of memory barriers committed
-system.cpu1.commit.branches                   6108113                       # Number of branches committed
-system.cpu1.commit.fp_insts                      5310                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                 43785233                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls              563417                       # Number of function calls committed.
-system.cpu1.commit.bw_lim_events              1884226                       # number cycles where commit BW limit reached
+system.cpu1.commit.refs                      17007249                       # Number of memory references committed
+system.cpu1.commit.loads                      9989241                       # Number of loads committed
+system.cpu1.commit.membars                     202226                       # Number of memory barriers committed
+system.cpu1.commit.branches                   5993368                       # Number of branches committed
+system.cpu1.commit.fp_insts                      6758                       # Number of committed floating point instructions.
+system.cpu1.commit.int_insts                 43235909                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls              556157                       # Number of function calls committed.
+system.cpu1.commit.bw_lim_events              1860811                       # number cycles where commit BW limit reached
 system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads                   168322862                       # The number of ROB reads
-system.cpu1.rob.rob_writes                  139443210                       # The number of ROB writes
-system.cpu1.timesIdled                        1396987                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                      215348346                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                  4817788385                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                   38483753                       # Number of Instructions Simulated
-system.cpu1.committedOps                     48984024                       # Number of Ops (including micro ops) Simulated
-system.cpu1.committedInsts_total             38483753                       # Number of Instructions Simulated
-system.cpu1.cpi                              8.356499                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        8.356499                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.119667                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.119667                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads               385614321                       # number of integer regfile reads
-system.cpu1.int_regfile_writes               58138574                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                     3969                       # number of floating regfile reads
-system.cpu1.fp_regfile_writes                    1880                       # number of floating regfile writes
-system.cpu1.misc_regfile_reads               91635789                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes                441645                       # number of misc regfile writes
-system.cpu1.icache.replacements                628575                       # number of replacements
-system.cpu1.icache.tagsinuse               498.649539                       # Cycle average of tags in use
-system.cpu1.icache.total_refs                 8518604                       # Total number of references to valid blocks.
-system.cpu1.icache.sampled_refs                629087                       # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs                 13.541218                       # Average number of references to valid blocks.
-system.cpu1.icache.warmup_cycle           73946666000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::cpu1.inst   498.649539                       # Average occupied blocks per requestor
-system.cpu1.icache.occ_percent::cpu1.inst     0.973925                       # Average percentage of cache occupancy
-system.cpu1.icache.occ_percent::total        0.973925                       # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst      8518604                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total        8518604                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst      8518604                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total         8518604                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst      8518604                       # number of overall hits
-system.cpu1.icache.overall_hits::total        8518604                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       678443                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       678443                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       678443                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        678443                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       678443                       # number of overall misses
-system.cpu1.icache.overall_misses::total       678443                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   9864551499                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   9864551499                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   9864551499                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   9864551499                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   9864551499                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   9864551499                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst      9197047                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total      9197047                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst      9197047                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total      9197047                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst      9197047                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total      9197047                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.073767                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.073767                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.073767                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.073767                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.073767                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.073767                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14539.985672                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 14539.985672                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14539.985672                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 14539.985672                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14539.985672                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 14539.985672                       # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs       932999                       # number of cycles access was blocked
+system.cpu1.rob.rob_reads                   175585773                       # The number of ROB reads
+system.cpu1.rob.rob_writes                  137553768                       # The number of ROB writes
+system.cpu1.timesIdled                        1520299                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                      239582989                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                  4808538839                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                   37967315                       # Number of Instructions Simulated
+system.cpu1.committedOps                     48327333                       # Number of Ops (including micro ops) Simulated
+system.cpu1.committedInsts_total             37967315                       # Number of Instructions Simulated
+system.cpu1.cpi                              9.319185                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        9.319185                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.107306                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.107306                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads               393921761                       # number of integer regfile reads
+system.cpu1.int_regfile_writes               56840694                       # number of integer regfile writes
+system.cpu1.fp_regfile_reads                     4925                       # number of floating regfile reads
+system.cpu1.fp_regfile_writes                    2334                       # number of floating regfile writes
+system.cpu1.misc_regfile_reads               90313719                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes                429414                       # number of misc regfile writes
+system.cpu1.icache.replacements                622931                       # number of replacements
+system.cpu1.icache.tagsinuse               498.760560                       # Cycle average of tags in use
+system.cpu1.icache.total_refs                 8545880                       # Total number of references to valid blocks.
+system.cpu1.icache.sampled_refs                623443                       # Sample count of references to valid blocks.
+system.cpu1.icache.avg_refs                 13.707556                       # Average number of references to valid blocks.
+system.cpu1.icache.warmup_cycle           74633827000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.occ_blocks::cpu1.inst   498.760560                       # Average occupied blocks per requestor
+system.cpu1.icache.occ_percent::cpu1.inst     0.974142                       # Average percentage of cache occupancy
+system.cpu1.icache.occ_percent::total        0.974142                       # Average percentage of cache occupancy
+system.cpu1.icache.ReadReq_hits::cpu1.inst      8545880                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total        8545880                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst      8545880                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total         8545880                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst      8545880                       # number of overall hits
+system.cpu1.icache.overall_hits::total        8545880                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       673372                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       673372                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       673372                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        673372                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       673372                       # number of overall misses
+system.cpu1.icache.overall_misses::total       673372                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  10716931993                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total  10716931993                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst  10716931993                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total  10716931993                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst  10716931993                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total  10716931993                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst      9219252                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total      9219252                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst      9219252                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total      9219252                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst      9219252                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total      9219252                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.073040                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.073040                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.073040                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.073040                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.073040                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.073040                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15915.321684                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 15915.321684                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15915.321684                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 15915.321684                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15915.321684                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 15915.321684                       # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs      1332494                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs              153                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs              205                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs  6098.032680                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs  6499.970732                       # average number of cycles each access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.writebacks::writebacks        30976                       # number of writebacks
-system.cpu1.icache.writebacks::total            30976                       # number of writebacks
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        49327                       # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total        49327                       # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst        49327                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total        49327                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst        49327                       # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total        49327                       # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       629116                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       629116                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       629116                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       629116                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       629116                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       629116                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   7390302499                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   7390302499                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   7390302499                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   7390302499                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   7390302499                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   7390302499                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      2676000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      2676000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      2676000                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total      2676000                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.068404                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.068404                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.068404                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.068404                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.068404                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.068404                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11747.122151                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11747.122151                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11747.122151                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 11747.122151                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11747.122151                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 11747.122151                       # average overall mshr miss latency
+system.cpu1.icache.writebacks::writebacks        33068                       # number of writebacks
+system.cpu1.icache.writebacks::total            33068                       # number of writebacks
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        49906                       # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total        49906                       # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst        49906                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total        49906                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst        49906                       # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total        49906                       # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       623466                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       623466                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       623466                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       623466                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       623466                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       623466                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   8227032008                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   8227032008                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   8227032008                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   8227032008                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   8227032008                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   8227032008                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      3154000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      3154000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      3154000                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total      3154000                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.067627                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.067627                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.067627                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.067627                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.067627                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.067627                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13195.638588                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13195.638588                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13195.638588                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 13195.638588                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13195.638588                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 13195.638588                       # average overall mshr miss latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.replacements                365990                       # number of replacements
-system.cpu1.dcache.tagsinuse               486.374853                       # Cycle average of tags in use
-system.cpu1.dcache.total_refs                13437990                       # Total number of references to valid blocks.
-system.cpu1.dcache.sampled_refs                366502                       # Sample count of references to valid blocks.
-system.cpu1.dcache.avg_refs                 36.665530                       # Average number of references to valid blocks.
-system.cpu1.dcache.warmup_cycle           70078369000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::cpu1.data   486.374853                       # Average occupied blocks per requestor
-system.cpu1.dcache.occ_percent::cpu1.data     0.949951                       # Average percentage of cache occupancy
-system.cpu1.dcache.occ_percent::total        0.949951                       # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::cpu1.data      8795505                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        8795505                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      4385128                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       4385128                       # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data       106581                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total       106581                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data       102282                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total       102282                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data     13180633                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total        13180633                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data     13180633                       # number of overall hits
-system.cpu1.dcache.overall_hits::total       13180633                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       408153                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       408153                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data      1582783                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total      1582783                       # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        13916                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total        13916                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data        10800                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total        10800                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data      1990936                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total       1990936                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data      1990936                       # number of overall misses
-system.cpu1.dcache.overall_misses::total      1990936                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   5766799000                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   5766799000                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  55285236443                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total  55285236443                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    141367500                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total    141367500                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     89573500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total     89573500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data  61052035443                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total  61052035443                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data  61052035443                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total  61052035443                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      9203658                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      9203658                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      5967911                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      5967911                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data       120497                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total       120497                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data       113082                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total       113082                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data     15171569                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total     15171569                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data     15171569                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total     15171569                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.044347                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.044347                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.265216                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.265216                       # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.115488                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.115488                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.095506                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.095506                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.131228                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.131228                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.131228                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.131228                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14129.012895                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 14129.012895                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34929.132069                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 34929.132069                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10158.630354                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10158.630354                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  8293.842593                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  8293.842593                       # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 30664.991463                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 30664.991463                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 30664.991463                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 30664.991463                       # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs     12254574                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets      5966500                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs             3013                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets            167                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs  4067.233322                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets 35727.544910                       # average number of cycles each access was blocked
+system.cpu1.dcache.replacements                362729                       # number of replacements
+system.cpu1.dcache.tagsinuse               487.126779                       # Cycle average of tags in use
+system.cpu1.dcache.total_refs                13112337                       # Total number of references to valid blocks.
+system.cpu1.dcache.sampled_refs                363073                       # Sample count of references to valid blocks.
+system.cpu1.dcache.avg_refs                 36.114878                       # Average number of references to valid blocks.
+system.cpu1.dcache.warmup_cycle           70483759000                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.occ_blocks::cpu1.data   487.126779                       # Average occupied blocks per requestor
+system.cpu1.dcache.occ_percent::cpu1.data     0.951419                       # Average percentage of cache occupancy
+system.cpu1.dcache.occ_percent::total        0.951419                       # Average percentage of cache occupancy
+system.cpu1.dcache.ReadReq_hits::cpu1.data      8613908                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        8613908                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      4252702                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       4252702                       # number of WriteReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data       105106                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total       105106                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data       100709                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total       100709                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data     12866610                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total        12866610                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data     12866610                       # number of overall hits
+system.cpu1.dcache.overall_hits::total       12866610                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       410185                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       410185                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data      1595357                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total      1595357                       # number of WriteReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        14278                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total        14278                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data        10900                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total        10900                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data      2005542                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total       2005542                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data      2005542                       # number of overall misses
+system.cpu1.dcache.overall_misses::total      2005542                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   8114216000                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   8114216000                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  66620735237                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total  66620735237                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    166584000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total    166584000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     94819000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total     94819000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data  74734951237                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total  74734951237                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data  74734951237                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total  74734951237                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      9024093                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      9024093                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      5848059                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      5848059                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data       119384                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total       119384                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data       111609                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total       111609                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data     14872152                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total     14872152                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data     14872152                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total     14872152                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.045454                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.045454                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.272801                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.272801                       # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.119597                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.119597                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.097662                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.097662                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.134852                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.134852                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.134852                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.134852                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19781.844777                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 19781.844777                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41759.139326                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 41759.139326                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11667.180277                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11667.180277                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  8698.990826                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  8698.990826                       # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 37264.216475                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 37264.216475                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 37264.216475                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 37264.216475                       # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs     29196505                       # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets      5606000                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs             6645                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets            174                       # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs  4393.755455                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets 32218.390805                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks       330007                       # number of writebacks
-system.cpu1.dcache.writebacks::total           330007                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       172901                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total       172901                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data      1420692                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total      1420692                       # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data         1265                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total         1265                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data      1593593                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total      1593593                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data      1593593                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total      1593593                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       235252                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       235252                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       162091                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total       162091                       # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data        12651                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total        12651                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        10796                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total        10796                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       397343                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       397343                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       397343                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       397343                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   2772800000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   2772800000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   5167139074                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   5167139074                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     88580000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     88580000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     57154000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     57154000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   7939939074                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   7939939074                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   7939939074                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   7939939074                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 123239389500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 123239389500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  41654166350                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total  41654166350                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 164893555850                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 164893555850                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.025561                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.025561                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.027160                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.027160                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.104990                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.104990                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.095471                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.095471                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.026190                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.026190                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.026190                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.026190                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11786.509785                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11786.509785                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31878.013425                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31878.013425                       # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  7001.818038                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  7001.818038                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  5293.997777                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  5293.997777                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19982.581986                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19982.581986                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19982.581986                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19982.581986                       # average overall mshr miss latency
+system.cpu1.dcache.writebacks::writebacks       327467                       # number of writebacks
+system.cpu1.dcache.writebacks::total           327467                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       179191                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total       179191                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data      1432552                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total      1432552                       # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data         1457                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total         1457                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data      1611743                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total      1611743                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data      1611743                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total      1611743                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       230994                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total       230994                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       162805                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total       162805                       # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data        12821                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total        12821                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        10892                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total        10892                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       393799                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       393799                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       393799                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       393799                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   3545762451                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   3545762451                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   5565749199                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   5565749199                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data    104395505                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total    104395505                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     60832506                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     60832506                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data         1000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total         1000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   9111511650                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   9111511650                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   9111511650                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   9111511650                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 137004750500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 137004750500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  40571899654                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total  40571899654                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 177576650154                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 177576650154                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.025597                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.025597                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.027839                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.027839                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.107393                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.107393                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.097591                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.097591                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.026479                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.026479                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.026479                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.026479                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15350.019702                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15350.019702                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34186.598686                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 34186.598686                       # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  8142.539973                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8142.539973                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  5585.062982                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  5585.062982                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
+system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23137.467718                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23137.467718                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23137.467718                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23137.467718                       # average overall mshr miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1697,18 +1673,18 @@ system.iocache.avg_blocked_cycles::no_mshrs          nan                       #
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1308136748055                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1308136748055                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1308136748055                       # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1308136748055                       # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1305278151135                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1305278151135                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1305278151135                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1305278151135                       # number of overall MSHR uncacheable cycles
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   42935                       # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce                   43785                       # number of quiesce instructions executed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                   54742                       # number of quiesce instructions executed
+system.cpu1.kern.inst.quiesce                   53912                       # number of quiesce instructions executed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
index 027fdffc2..71f536288 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
@@ -20,7 +20,7 @@ kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 load_addr_mask=268435455
 machine_type=RealView_PBX
 mem_mode=timing
-memories=system.realview.nvmem system.physmem
+memories=system.physmem system.realview.nvmem
 midr_regval=890224640
 multi_proc=true
 num_work_ids=16
@@ -518,7 +518,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
 
@@ -579,7 +579,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 default=system.membus.badaddr_responder.pio
 master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
 slave=system.system_port system.iocache.mem_side system.l2c.mem_side
@@ -992,7 +992,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.l2c.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout
index 9c5baf3db..34717b2ec 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:10:14
-gem5 started Jun 29 2012 01:31:55
+gem5 compiled Jul  2 2012 09:08:16
+gem5 started Jul  2 2012 17:04:56
 gem5 executing on zizzer
 command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 info: Using bootloader at address 0x80000000
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 2500827052500 because m5_exit instruction encountered
+Exiting @ tick 2502549875500 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
index 2b0eb45e9..6df4de0df 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
@@ -1,16 +1,54 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.500827                       # Number of seconds simulated
-sim_ticks                                2500827052500                       # Number of ticks simulated
-final_tick                               2500827052500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.502550                       # Number of seconds simulated
+sim_ticks                                2502549875500                       # Number of ticks simulated
+final_tick                               2502549875500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  90125                       # Simulator instruction rate (inst/s)
-host_op_rate                                   116367                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             3783000939                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 386964                       # Number of bytes of host memory used
-host_seconds                                   661.07                       # Real time elapsed on the host
-sim_insts                                    59579144                       # Number of instructions simulated
-sim_ops                                      76926734                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  90191                       # Simulator instruction rate (inst/s)
+host_op_rate                                   116452                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             3788406278                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 386884                       # Number of bytes of host memory used
+host_seconds                                   660.58                       # Real time elapsed on the host
+sim_insts                                    59578267                       # Number of instructions simulated
+sim_ops                                      76925839                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::realview.clcd    118994504                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker         3776                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker           64                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst            800128                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9094928                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            128893400                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       800128                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          800128                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      3786176                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu.data        3016072                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           6802248                       # Number of bytes written to this memory
+system.physmem.num_reads::realview.clcd      14874313                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker           59                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker            1                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              12502                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             142142                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total              15029017                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           59159                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu.data            754018                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               813177                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        47549304                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker           1509                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker             26                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               319725                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3634264                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                51504828                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          319725                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             319725                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1512927                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data             1205200                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2718127                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1512927                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       47549304                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker          1509                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker            26                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              319725                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             4839464                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               54222954                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bytes_read::cpu.inst           64                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total            64                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_inst_read::cpu.inst           64                       # Number of instructions bytes read from this memory
@@ -23,191 +61,149 @@ system.realview.nvmem.bw_inst_read::cpu.inst           26
 system.realview.nvmem.bw_inst_read::total           26                       # Instruction read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu.inst           26                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total              26                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bytes_read::realview.clcd    117964800                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker         3328                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst            799424                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9095824                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            127863440                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       799424                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          799424                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      3784576                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu.data        3016072                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6800648                       # Number of bytes written to this memory
-system.physmem.num_reads::realview.clcd      14745600                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker           52                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              12491                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             142156                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total              14900300                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           59134                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu.data            754018                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               813152                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd        47170315                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker           1331                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker             26                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               319664                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3637126                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                51128462                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          319664                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             319664                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1513330                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data             1206030                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2719360                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1513330                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd       47170315                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker          1331                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker            26                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              319664                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             4843156                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               53847821                       # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements                         64425                       # number of replacements
-system.l2c.tagsinuse                     51220.169448                       # Cycle average of tags in use
-system.l2c.total_refs                         2029411                       # Total number of references to valid blocks.
-system.l2c.sampled_refs                        129819                       # Sample count of references to valid blocks.
-system.l2c.avg_refs                         15.632619                       # Average number of references to valid blocks.
-system.l2c.warmup_cycle                  2490891834000                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks        36757.661469                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.dtb.walker       42.093314                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.itb.walker        0.000181                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.inst           8185.117102                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.data           6235.297383                       # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks           0.560877                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.dtb.walker       0.000642                       # Average percentage of cache occupancy
+system.l2c.replacements                         64431                       # number of replacements
+system.l2c.tagsinuse                     51237.782352                       # Cycle average of tags in use
+system.l2c.total_refs                         2028510                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                        129827                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                         15.624716                       # Average number of references to valid blocks.
+system.l2c.warmup_cycle                  2492014554000                       # Cycle when the warmup percentage was hit.
+system.l2c.occ_blocks::writebacks        36760.884600                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.dtb.walker       47.476285                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.itb.walker        0.000184                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.inst           8187.042847                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.data           6242.378435                       # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks           0.560927                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.dtb.walker       0.000724                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu.itb.walker       0.000000                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.inst             0.124895                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.data             0.095143                       # Average percentage of cache occupancy
-system.l2c.occ_percent::total                0.781558                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu.dtb.walker        122696                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.itb.walker         11776                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.inst              977061                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.data              384470                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1496003                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          675876                       # number of Writeback hits
-system.l2c.Writeback_hits::total               675876                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu.data               50                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                  50                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu.data             12                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                12                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu.data            112893                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               112893                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu.dtb.walker         122696                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.itb.walker          11776                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.inst               977061                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.data               497363                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1608896                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu.dtb.walker        122696                       # number of overall hits
-system.l2c.overall_hits::cpu.itb.walker         11776                       # number of overall hits
-system.l2c.overall_hits::cpu.inst              977061                       # number of overall hits
-system.l2c.overall_hits::cpu.data              497363                       # number of overall hits
-system.l2c.overall_hits::total                1608896                       # number of overall hits
-system.l2c.ReadReq_misses::cpu.dtb.walker           52                       # number of ReadReq misses
+system.l2c.occ_percent::cpu.inst             0.124924                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.data             0.095251                       # Average percentage of cache occupancy
+system.l2c.occ_percent::total                0.781827                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu.dtb.walker        121963                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.itb.walker         11826                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.inst              977935                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.data              383708                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1495432                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          675442                       # number of Writeback hits
+system.l2c.Writeback_hits::total               675442                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu.data               42                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                  42                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu.data             16                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total                16                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu.data            112737                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               112737                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu.dtb.walker         121963                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.itb.walker          11826                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.inst               977935                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.data               496445                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 1608169                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu.dtb.walker        121963                       # number of overall hits
+system.l2c.overall_hits::cpu.itb.walker         11826                       # number of overall hits
+system.l2c.overall_hits::cpu.inst              977935                       # number of overall hits
+system.l2c.overall_hits::cpu.data              496445                       # number of overall hits
+system.l2c.overall_hits::total                1608169                       # number of overall hits
+system.l2c.ReadReq_misses::cpu.dtb.walker           59                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu.itb.walker            1                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu.inst             12370                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu.data             10695                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                23118                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu.data           2910                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              2910                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu.data            5                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total               5                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu.data          133257                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             133257                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu.dtb.walker           52                       # number of demand (read+write) misses
+system.l2c.ReadReq_misses::cpu.inst             12384                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.data             10691                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                23135                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu.data           2909                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              2909                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu.data            3                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total               3                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu.data          133229                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             133229                       # number of ReadExReq misses
+system.l2c.demand_misses::cpu.dtb.walker           59                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu.itb.walker            1                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu.inst              12370                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu.data             143952                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                156375                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu.dtb.walker           52                       # number of overall misses
+system.l2c.demand_misses::cpu.inst              12384                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.data             143920                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                156364                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu.dtb.walker           59                       # number of overall misses
 system.l2c.overall_misses::cpu.itb.walker            1                       # number of overall misses
-system.l2c.overall_misses::cpu.inst             12370                       # number of overall misses
-system.l2c.overall_misses::cpu.data            143952                       # number of overall misses
-system.l2c.overall_misses::total               156375                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu.dtb.walker      2714000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu.itb.walker        53000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu.inst    647826500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu.data    558032000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total     1208625500                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu.data       993500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total       993500                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu.data        52000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total        52000                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu.data   6991862500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   6991862500                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu.dtb.walker      2714000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.itb.walker        53000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.inst    647826500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.data   7549894500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total      8200488000                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu.dtb.walker      2714000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu.itb.walker        53000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu.inst    647826500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu.data   7549894500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total     8200488000                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu.dtb.walker       122748                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.itb.walker        11777                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.inst          989431                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.data          395165                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            1519121                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       675876                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           675876                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu.data         2960                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            2960                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu.data           17                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total            17                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu.data        246150                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           246150                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu.dtb.walker       122748                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.itb.walker        11777                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.inst           989431                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.data           641315                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             1765271                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu.dtb.walker       122748                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.itb.walker        11777                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.inst          989431                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.data          641315                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            1765271                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu.dtb.walker     0.000424                       # miss rate for ReadReq accesses
+system.l2c.overall_misses::cpu.inst             12384                       # number of overall misses
+system.l2c.overall_misses::cpu.data            143920                       # number of overall misses
+system.l2c.overall_misses::total               156364                       # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu.dtb.walker      3091500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.itb.walker        60000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.inst    659591498                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.data    562236498                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total     1224979496                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu.data       944500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total       944500                       # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu.data   7069904999                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   7069904999                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu.dtb.walker      3091500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.itb.walker        60000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.inst    659591498                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.data   7632141497                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total      8294884495                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu.dtb.walker      3091500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu.itb.walker        60000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu.inst    659591498                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu.data   7632141497                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total     8294884495                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu.dtb.walker       122022                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.itb.walker        11827                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.inst          990319                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.data          394399                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            1518567                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       675442                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           675442                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu.data         2951                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            2951                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu.data           19                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total            19                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu.data        245966                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           245966                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu.dtb.walker       122022                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.itb.walker        11827                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.inst           990319                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.data           640365                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             1764533                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu.dtb.walker       122022                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.itb.walker        11827                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.inst          990319                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.data          640365                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            1764533                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu.dtb.walker     0.000484                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu.itb.walker     0.000085                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.inst       0.012502                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.data       0.027065                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.015218                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu.data     0.983108                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.983108                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu.data     0.294118                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.294118                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu.data     0.541365                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.541365                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu.dtb.walker     0.000424                       # miss rate for demand accesses
+system.l2c.ReadReq_miss_rate::cpu.inst       0.012505                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.data       0.027107                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.015235                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu.data     0.985768                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.985768                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu.data     0.157895                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.157895                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu.data     0.541656                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.541656                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu.dtb.walker     0.000484                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu.itb.walker     0.000085                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.inst        0.012502                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.data        0.224464                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.088584                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu.dtb.walker     0.000424                       # miss rate for overall accesses
+system.l2c.demand_miss_rate::cpu.inst        0.012505                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.data        0.224747                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.088615                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu.dtb.walker     0.000484                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu.itb.walker     0.000085                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.inst       0.012502                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.data       0.224464                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.088584                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52192.307692                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker        53000                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu.inst 52370.776071                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu.data 52176.905096                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 52280.711999                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu.data   341.408935                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total   341.408935                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu.data        10400                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total        10400                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu.data 52469.007257                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 52469.007257                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52192.307692                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu.itb.walker        53000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu.inst 52370.776071                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu.data 52447.305352                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 52441.170264                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52192.307692                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.itb.walker        53000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.inst 52370.776071                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.data 52447.305352                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 52441.170264                       # average overall miss latency
+system.l2c.overall_miss_rate::cpu.inst       0.012505                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.data       0.224747                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.088615                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52398.305085                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker        60000                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.inst 53261.587371                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.data 52589.701431                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 52949.189367                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu.data   324.682021                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total   324.682021                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu.data 53065.811490                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 53065.811490                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52398.305085                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.itb.walker        60000                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.inst 53261.587371                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.data 53030.443976                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 53048.556541                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52398.305085                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.itb.walker        60000                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.inst 53261.587371                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.data 53030.443976                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 53048.556541                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -216,109 +212,109 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               59134                       # number of writebacks
-system.l2c.writebacks::total                    59134                       # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu.inst              8                       # number of ReadReq MSHR hits
+system.l2c.writebacks::writebacks               59159                       # number of writebacks
+system.l2c.writebacks::total                    59159                       # number of writebacks
+system.l2c.ReadReq_mshr_hits::cpu.inst              9                       # number of ReadReq MSHR hits
 system.l2c.ReadReq_mshr_hits::cpu.data             62                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total                70                       # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits::cpu.inst               8                       # number of demand (read+write) MSHR hits
+system.l2c.ReadReq_mshr_hits::total                71                       # number of ReadReq MSHR hits
+system.l2c.demand_mshr_hits::cpu.inst               9                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_hits::cpu.data              62                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                 70                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu.inst              8                       # number of overall MSHR hits
+system.l2c.demand_mshr_hits::total                 71                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu.inst              9                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::cpu.data             62                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                70                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu.dtb.walker           52                       # number of ReadReq MSHR misses
+system.l2c.overall_mshr_hits::total                71                       # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses::cpu.dtb.walker           59                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu.itb.walker            1                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu.inst        12362                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu.data        10633                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total           23048                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu.data         2910                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total         2910                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu.data            5                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total            5                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu.data       133257                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        133257                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu.dtb.walker           52                       # number of demand (read+write) MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.inst        12375                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.data        10629                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total           23064                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu.data         2909                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total         2909                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu.data            3                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total            3                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu.data       133229                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        133229                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu.dtb.walker           59                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu.itb.walker            1                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu.inst         12362                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu.data        143890                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           156305                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu.dtb.walker           52                       # number of overall MSHR misses
+system.l2c.demand_mshr_misses::cpu.inst         12375                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu.data        143858                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           156293                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu.dtb.walker           59                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu.itb.walker            1                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu.inst        12362                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu.data       143890                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          156305                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker      2081000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker        41000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu.inst    496452000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu.data    425891000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total    924465000                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu.data    116622000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total    116622000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data       200000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total       200000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu.data   5338935000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   5338935000                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.dtb.walker      2081000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.itb.walker        41000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.inst    496452000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.data   5764826000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total   6263400000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.dtb.walker      2081000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.itb.walker        41000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.inst    496452000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.data   5764826000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total   6263400000                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst      5219000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131764564500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 131769783500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data  32353763131                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total  32353763131                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu.inst      5219000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu.data 164118327631                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 164123546631                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000424                       # mshr miss rate for ReadReq accesses
+system.l2c.overall_mshr_misses::cpu.inst        12375                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu.data       143858                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          156293                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker      2372000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker        48000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.inst    508160500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.data    430170499                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total    940750999                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu.data    116825000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    116825000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data       120000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total       120000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu.data   5436034999                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   5436034999                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.dtb.walker      2372000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.itb.walker        48000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.inst    508160500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.data   5866205498                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   6376785998                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.dtb.walker      2372000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.itb.walker        48000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.inst    508160500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.data   5866205498                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   6376785998                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst      5323000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131417115000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 131422438000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data  31373446015                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total  31373446015                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu.inst      5323000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu.data 162790561015                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 162795884015                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000484                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000085                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.012494                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.026908                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.015172                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.983108                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.983108                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data     0.294118                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.294118                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.541365                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.541365                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu.dtb.walker     0.000424                       # mshr miss rate for demand accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.012496                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.026950                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.015188                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.985768                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.985768                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data     0.157895                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.157895                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.541656                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.541656                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu.dtb.walker     0.000484                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu.itb.walker     0.000085                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu.inst     0.012494                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu.data     0.224367                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.088544                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu.dtb.walker     0.000424                       # mshr miss rate for overall accesses
+system.l2c.demand_mshr_miss_rate::cpu.inst     0.012496                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.data     0.224650                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.088575                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu.dtb.walker     0.000484                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu.itb.walker     0.000085                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu.inst     0.012494                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu.data     0.224367                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.088544                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40019.230769                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        41000                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40159.521113                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40053.700743                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 40110.421729                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40076.288660                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40076.288660                       # average UpgradeReq mshr miss latency
+system.l2c.overall_mshr_miss_rate::cpu.inst     0.012496                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.data     0.224650                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.088575                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40203.389831                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        48000                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41063.474747                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40471.398909                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 40788.718306                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40159.848745                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40159.848745                       # average UpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        40000                       # average SCUpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        40000                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40064.949684                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 40064.949684                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40019.230769                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker        41000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40159.521113                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.data 40064.118424                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 40071.654778                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40019.230769                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker        41000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40159.521113                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.data 40064.118424                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 40071.654778                       # average overall mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40802.190206                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 40802.190206                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40203.389831                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker        48000                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41063.474747                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.data 40777.749572                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 40800.202172                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40203.389831                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker        48000                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41063.474747                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.data 40777.749572                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 40800.202172                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -336,27 +332,27 @@ system.cf0.dma_write_bytes                          0                       # Nu
 system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     51785537                       # DTB read hits
-system.cpu.dtb.read_misses                      81591                       # DTB read misses
-system.cpu.dtb.write_hits                    11872923                       # DTB write hits
-system.cpu.dtb.write_misses                     18231                       # DTB write misses
+system.cpu.dtb.read_hits                     51771660                       # DTB read hits
+system.cpu.dtb.read_misses                      81258                       # DTB read misses
+system.cpu.dtb.write_hits                    11880398                       # DTB write hits
+system.cpu.dtb.write_misses                     17961                       # DTB write misses
 system.cpu.dtb.flush_tlb                            2                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                     4506                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                      2988                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                    690                       # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries                     4471                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                      3044                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                    609                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                      1351                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 51867128                       # DTB read accesses
-system.cpu.dtb.write_accesses                11891154                       # DTB write accesses
+system.cpu.dtb.perms_faults                      1282                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                 51852918                       # DTB read accesses
+system.cpu.dtb.write_accesses                11898359                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          63658460                       # DTB hits
-system.cpu.dtb.misses                           99822                       # DTB misses
-system.cpu.dtb.accesses                      63758282                       # DTB accesses
-system.cpu.itb.inst_hits                     13022422                       # ITB inst hits
-system.cpu.itb.inst_misses                      12153                       # ITB inst misses
+system.cpu.dtb.hits                          63652058                       # DTB hits
+system.cpu.dtb.misses                           99219                       # DTB misses
+system.cpu.dtb.accesses                      63751277                       # DTB accesses
+system.cpu.itb.inst_hits                     13142261                       # ITB inst hits
+system.cpu.itb.inst_misses                      12247                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
@@ -365,542 +361,542 @@ system.cpu.itb.flush_tlb                            2                       # Nu
 system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
 system.cpu.itb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.itb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                     2627                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries                     2634                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                      3259                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                      3496                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                 13034575                       # ITB inst accesses
-system.cpu.itb.hits                          13022422                       # DTB hits
-system.cpu.itb.misses                           12153                       # DTB misses
-system.cpu.itb.accesses                      13034575                       # DTB accesses
-system.cpu.numCycles                        408047924                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                 13154508                       # ITB inst accesses
+system.cpu.itb.hits                          13142261                       # DTB hits
+system.cpu.itb.misses                           12247                       # DTB misses
+system.cpu.itb.accesses                      13154508                       # DTB accesses
+system.cpu.numCycles                        413642740                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                 14895929                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted           11838635                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect             749498                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups               9774236                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                  7761608                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                 14974990                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           11915620                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect             753400                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              10068197                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                  7820088                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                  1450585                       # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect               80646                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles           32131999                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                       99541579                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    14895929                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            9212193                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      21738174                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 6062724                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                     161664                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles               89532236                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                 2475                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        119247                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles       208172                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          243                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  13018415                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                931788                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                    6733                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          148050131                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.832729                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.216336                       # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS                  1448775                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect               80927                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles           33422471                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                       99542070                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    14974990                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            9268863                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      21759182                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 6002262                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                     163536                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles               93319816                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                 2533                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        133610                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles       208459                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          397                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  13138017                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               1024097                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                    6504                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          153128307                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.804842                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.182667                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                126328884     85.33%     85.33% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  1364567      0.92%     86.25% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  1757577      1.19%     87.44% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  2627928      1.78%     89.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  1817598      1.23%     90.44% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  1139974      0.77%     91.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  2881875      1.95%     93.16% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                   793207      0.54%     93.69% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                  9338521      6.31%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                131386008     85.80%     85.80% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  1369017      0.89%     86.70% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  1759019      1.15%     87.84% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  2640315      1.72%     89.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  1819667      1.19%     90.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  1142419      0.75%     91.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  2920911      1.91%     93.41% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                   807762      0.53%     93.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                  9283189      6.06%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            148050131                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.036505                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.243946                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 34138786                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              89344652                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  19542719                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               1039822                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                3984152                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              2096721                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                174752                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              115904821                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                572765                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                3984152                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 36116919                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                36990471                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       46307759                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  18567490                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               6083340                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              109034273                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                  3076                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                1021710                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               4089268                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents            41156                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           113585552                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             502111824                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        502019660                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups             92164                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps              77687957                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 35897594                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts             898050                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts         797560                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  12232946                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             20954804                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            13881914                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1960286                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          2534637                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                   99654588                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             1554944                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 124705745                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            186396                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        23520309                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     64631044                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         267642                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     148050131                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.842321                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.546134                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            153128307                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.036203                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.240647                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 35537493                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              93048586                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  19509299                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               1086349                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                3946580                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              2100058                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                174557                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              116122172                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                568338                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                3946580                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 37621271                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                39594801                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       46881047                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  18412397                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               6672211                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              108597287                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                  4175                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                1156489                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               4484156                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents            30967                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           113073752                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             499820515                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        499727174                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups             93341                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps              77686691                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 35387060                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts             898607                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts         797702                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  13307124                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             21058263                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            13875749                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1965166                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          2564814                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                   99781831                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             1555350                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 124613166                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            199798                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        23638127                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     65777806                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         268083                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     153128307                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.813783                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.516400                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           103452672     69.88%     69.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            13854502      9.36%     79.23% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             7174552      4.85%     84.08% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             5822865      3.93%     88.01% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            12669865      8.56%     96.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             2797622      1.89%     98.46% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             1712436      1.16%     99.62% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              433578      0.29%     99.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              132039      0.09%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           107849903     70.43%     70.43% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            14560254      9.51%     79.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             7302452      4.77%     84.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             5913038      3.86%     88.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            12593494      8.22%     96.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             2809204      1.83%     98.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             1536315      1.00%     99.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              438168      0.29%     99.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              125479      0.08%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       148050131                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       153128307                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                   59948      0.68%      0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      2      0.00%      0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                8388673     94.51%     95.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                427083      4.81%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   53462      0.61%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      2      0.00%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                8367005     94.75%     95.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                409700      4.64%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass            106530      0.09%      0.09% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              58643579     47.03%     47.11% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                95161      0.08%     47.19% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     47.19% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     47.19% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     47.19% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     47.19% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     47.19% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     47.19% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     47.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     47.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     47.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     47.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     47.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     47.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                  13      0.00%     47.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     47.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     47.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  6      0.00%     47.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               8      0.00%     47.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     47.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     47.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     47.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     47.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     47.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     47.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc           2111      0.00%     47.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     47.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            8      0.00%     47.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     47.19% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             53352582     42.78%     89.97% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            12505747     10.03%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              58482659     46.93%     47.02% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                95330      0.08%     47.09% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     47.09% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     47.09% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     47.09% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     47.09% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     47.09% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     47.09% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     47.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     47.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     47.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     47.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     47.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     47.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                  11      0.00%     47.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     47.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     47.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  5      0.00%     47.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               6      0.00%     47.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     47.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     47.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     47.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     47.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     47.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     47.09% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc           2111      0.00%     47.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     47.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            6      0.00%     47.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     47.10% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             53414157     42.86%     89.96% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            12512351     10.04%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              124705745                       # Type of FU issued
-system.cpu.iq.rate                           0.305615                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     8875706                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.071173                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          406599918                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         124750196                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     85869603                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads               23265                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes              12672                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses        10345                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              133462587                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                   12334                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads           642048                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              124613166                       # Type of FU issued
+system.cpu.iq.rate                           0.301258                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     8830169                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.070861                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          411460543                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         124996425                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     85630389                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads               22925                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes              12868                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses        10343                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              133324707                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                   12098                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads           646336                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      5239514                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        10265                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        34172                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      2083712                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      5343093                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        11106                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        35068                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      2077574                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads     34107049                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked       1151692                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads     34107202                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked       1049886                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                3984152                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                28395992                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                447371                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           101464012                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            233619                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              20954804                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             13881914                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts             964089                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 112476                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                  6557                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          34172                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         381147                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       331860                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               713007                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             121711788                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              52474170                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           2993957                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                3946580                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                29463666                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                540836                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           101593235                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            217276                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              21058263                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             13875749                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts             964547                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 125689                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 40656                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          35068                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         381127                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       332167                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               713294                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             121438397                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              52461807                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           3174769                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                        254480                       # number of nop insts executed
-system.cpu.iew.exec_refs                     64857639                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 11392260                       # Number of branches executed
-system.cpu.iew.exec_stores                   12383469                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.298278                       # Inst execution rate
-system.cpu.iew.wb_sent                      120307041                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      85879948                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  46962413                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  87363153                       # num instructions consuming a value
+system.cpu.iew.exec_nop                        256054                       # number of nop insts executed
+system.cpu.iew.exec_refs                     64853171                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 11412736                       # Number of branches executed
+system.cpu.iew.exec_stores                   12391364                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.293583                       # Inst execution rate
+system.cpu.iew.wb_sent                      120063166                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      85640732                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  46459932                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  84649521                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.210465                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.537554                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.207040                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.548851                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts       59729525                       # The number of committed instructions
-system.cpu.commit.commitCommittedOps         77077115                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts        24198873                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls         1287302                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            621123                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    144148394                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.534707                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.521609                       # Number of insts commited each cycle
+system.cpu.commit.commitCommittedInsts       59728648                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps         77076220                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts        24329020                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         1287267                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            625309                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    149264139                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.516375                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.492760                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    116600934     80.89%     80.89% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     13538329      9.39%     90.28% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      3987949      2.77%     93.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      2150587      1.49%     94.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1741345      1.21%     95.75% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1028717      0.71%     96.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      1566098      1.09%     97.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       669906      0.46%     98.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      2864529      1.99%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    121340444     81.29%     81.29% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     13976446      9.36%     90.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      3929866      2.63%     93.29% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      2230737      1.49%     94.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1774137      1.19%     95.97% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1064202      0.71%     96.68% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      1398926      0.94%     97.62% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       658331      0.44%     98.06% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      2891050      1.94%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    144148394                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts             59729525                       # Number of instructions committed
-system.cpu.commit.committedOps               77077115                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    149264139                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts             59728648                       # Number of instructions committed
+system.cpu.commit.committedOps               77076220                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       27513492                       # Number of memory references committed
-system.cpu.commit.loads                      15715290                       # Number of loads committed
-system.cpu.commit.membars                      413064                       # Number of memory barriers committed
-system.cpu.commit.branches                    9904425                       # Number of branches committed
+system.cpu.commit.refs                       27513345                       # Number of memory references committed
+system.cpu.commit.loads                      15715170                       # Number of loads committed
+system.cpu.commit.membars                      413057                       # Number of memory barriers committed
+system.cpu.commit.branches                    9904308                       # Number of branches committed
 system.cpu.commit.fp_insts                      10212                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                  68617780                       # Number of committed integer instructions.
-system.cpu.commit.function_calls               995959                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events               2864529                       # number cycles where commit BW limit reached
+system.cpu.commit.int_insts                  68616986                       # Number of committed integer instructions.
+system.cpu.commit.function_calls               995953                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events               2891050                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    240802540                       # The number of ROB reads
-system.cpu.rob.rob_writes                   206662154                       # The number of ROB writes
-system.cpu.timesIdled                         1878638                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                       259997793                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   4593518134                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                    59579144                       # Number of Instructions Simulated
-system.cpu.committedOps                      76926734                       # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total              59579144                       # Number of Instructions Simulated
-system.cpu.cpi                               6.848838                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         6.848838                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.146010                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.146010                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                552215109                       # number of integer regfile reads
-system.cpu.int_regfile_writes                88113131                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                      8314                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                     2878                       # number of floating regfile writes
-system.cpu.misc_regfile_reads               131767968                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                 912736                       # number of misc regfile writes
-system.cpu.icache.replacements                 990445                       # number of replacements
-system.cpu.icache.tagsinuse                511.614969                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 11943122                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                 990957                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                  12.052109                       # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle             6217994000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     511.614969                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.999248                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.999248                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst     11943122                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        11943122                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      11943122                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         11943122                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     11943122                       # number of overall hits
-system.cpu.icache.overall_hits::total        11943122                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1075156                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1075156                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1075156                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1075156                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1075156                       # number of overall misses
-system.cpu.icache.overall_misses::total       1075156                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  15637742995                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  15637742995                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  15637742995                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  15637742995                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  15637742995                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  15637742995                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     13018278                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     13018278                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     13018278                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     13018278                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     13018278                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     13018278                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.082588                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.082588                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.082588                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.082588                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.082588                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.082588                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14544.627008                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 14544.627008                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 14544.627008                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 14544.627008                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 14544.627008                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 14544.627008                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs      2121995                       # number of cycles access was blocked
+system.cpu.rob.rob_reads                    246021016                       # The number of ROB reads
+system.cpu.rob.rob_writes                   206855771                       # The number of ROB writes
+system.cpu.timesIdled                         1910853                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                       260514433                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   4591368963                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                    59578267                       # Number of Instructions Simulated
+system.cpu.committedOps                      76925839                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total              59578267                       # Number of Instructions Simulated
+system.cpu.cpi                               6.942846                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         6.942846                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.144033                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.144033                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                551124722                       # number of integer regfile reads
+system.cpu.int_regfile_writes                87730818                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                      8186                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                     2858                       # number of floating regfile writes
+system.cpu.misc_regfile_reads               131789755                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                 912697                       # number of misc regfile writes
+system.cpu.icache.replacements                 991190                       # number of replacements
+system.cpu.icache.tagsinuse                511.611770                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 12061455                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                 991702                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                  12.162378                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle             6426198000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::cpu.inst     511.611770                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.999242                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.999242                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst     12061455                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        12061455                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      12061455                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         12061455                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     12061455                       # number of overall hits
+system.cpu.icache.overall_hits::total        12061455                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1076423                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1076423                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1076423                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1076423                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1076423                       # number of overall misses
+system.cpu.icache.overall_misses::total       1076423                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  16851120991                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  16851120991                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  16851120991                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  16851120991                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  16851120991                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  16851120991                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     13137878                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     13137878                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     13137878                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     13137878                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     13137878                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     13137878                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.081933                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.081933                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.081933                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.081933                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.081933                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.081933                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15654.738881                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 15654.738881                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 15654.738881                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 15654.738881                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 15654.738881                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 15654.738881                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs      2871493                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               289                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               461                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs  7342.543253                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs  6228.835141                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks        67776                       # number of writebacks
-system.cpu.icache.writebacks::total             67776                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        84152                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        84152                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        84152                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        84152                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        84152                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        84152                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       991004                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       991004                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       991004                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       991004                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       991004                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       991004                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  11660559495                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  11660559495                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  11660559495                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  11660559495                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  11660559495                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  11660559495                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst      6997000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::total      6997000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst      6997000                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total      6997000                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.076124                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.076124                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.076124                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.076124                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.076124                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.076124                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11766.410120                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11766.410120                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11766.410120                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11766.410120                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11766.410120                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11766.410120                       # average overall mshr miss latency
+system.cpu.icache.writebacks::writebacks        67899                       # number of writebacks
+system.cpu.icache.writebacks::total             67899                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        84680                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        84680                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        84680                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        84680                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        84680                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        84680                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       991743                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       991743                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       991743                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       991743                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       991743                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       991743                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12825867499                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  12825867499                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12825867499                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  12825867499                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12825867499                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  12825867499                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst      7992500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::total      7992500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst      7992500                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::total      7992500                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.075487                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.075487                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.075487                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.075487                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.075487                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.075487                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12932.652410                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12932.652410                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12932.652410                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 12932.652410                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12932.652410                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12932.652410                       # average overall mshr miss latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                 644124                       # number of replacements
-system.cpu.dcache.tagsinuse                511.991568                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 21775548                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                 644636                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  33.779603                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle               49161000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data     511.991568                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.999984                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.999984                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data     13910712                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        13910712                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      7293091                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        7293091                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       282930                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       282930                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       285654                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       285654                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      21203803                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         21203803                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     21203803                       # number of overall hits
-system.cpu.dcache.overall_hits::total        21203803                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       740801                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        740801                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      2957315                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      2957315                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        13662                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        13662                       # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data           17                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total           17                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      3698116                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3698116                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      3698116                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3698116                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  10501483000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  10501483000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 106800352759                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 106800352759                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    200535500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    200535500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       452000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total       452000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 117301835759                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 117301835759                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 117301835759                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 117301835759                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     14651513                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     14651513                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.replacements                 643139                       # number of replacements
+system.cpu.dcache.tagsinuse                511.991335                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 21733833                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 643651                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  33.766487                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle               50933000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data     511.991335                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.999983                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.999983                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     13904166                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        13904166                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      7257095                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        7257095                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       283844                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       283844                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       285639                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       285639                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      21161261                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         21161261                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     21161261                       # number of overall hits
+system.cpu.dcache.overall_hits::total        21161261                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       765252                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        765252                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      2993311                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      2993311                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        13765                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        13765                       # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data           19                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total           19                       # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data      3758563                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3758563                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      3758563                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3758563                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  14844603000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  14844603000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 129412035593                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 129412035593                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    223977000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    223977000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       405000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total       405000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 144256638593                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 144256638593                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 144256638593                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 144256638593                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     14669418                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     14669418                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     10250406                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     10250406                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       296592                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       296592                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       285671                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       285671                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     24901919                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     24901919                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     24901919                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     24901919                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.050561                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.050561                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.288507                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.288507                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.046063                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.046063                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000060                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total     0.000060                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.148507                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.148507                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.148507                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.148507                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14175.848845                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14175.848845                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36113.959033                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 36113.959033                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14678.341385                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14678.341385                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 26588.235294                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 26588.235294                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 31719.350004                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 31719.350004                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 31719.350004                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 31719.350004                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs     14079439                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets      7830500                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs              2852                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets             275                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs  4936.689691                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 28474.545455                       # average number of cycles each access was blocked
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       297609                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       297609                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       285658                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       285658                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     24919824                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     24919824                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     24919824                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     24919824                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.052166                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.052166                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.292019                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.292019                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.046252                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.046252                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000067                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total     0.000067                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.150826                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.150826                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.150826                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.150826                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19398.319769                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 19398.319769                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43233.742031                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 43233.742031                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16271.485652                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16271.485652                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 21315.789474                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 21315.789474                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 38380.795691                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 38380.795691                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 38380.795691                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 38380.795691                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs     32633902                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets      7260500                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              7285                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets             283                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  4479.602196                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 25655.477032                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       608100                       # number of writebacks
-system.cpu.dcache.writebacks::total            608100                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       354542                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       354542                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      2708293                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      2708293                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         1346                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total         1346                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      3062835                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      3062835                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      3062835                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      3062835                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       386259                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       386259                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       249022                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       249022                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        12316                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total        12316                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data           17                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total           17                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       635281                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       635281                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       635281                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       635281                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   4943544500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   4943544500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8596724439                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   8596724439                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    143823500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    143823500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       395000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       395000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  13540268939                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  13540268939                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  13540268939                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  13540268939                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147158057500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147158057500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data  42257629539                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  42257629539                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189415687039                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 189415687039                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.026363                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.026363                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.024294                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.024294                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.041525                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.041525                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000060                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000060                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.025511                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.025511                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.025511                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.025511                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12798.522494                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12798.522494                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34521.947615                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34521.947615                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11677.776876                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11677.776876                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 23235.294118                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 23235.294118                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21313.826384                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 21313.826384                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21313.826384                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 21313.826384                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks       607543                       # number of writebacks
+system.cpu.dcache.writebacks::total            607543                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       379767                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       379767                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      2744505                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      2744505                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         1453                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total         1453                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      3124272                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      3124272                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      3124272                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      3124272                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       385485                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       385485                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       248806                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       248806                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        12312                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total        12312                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data           19                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total           19                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       634291                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       634291                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       634291                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       634291                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6242554097                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   6242554097                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   9246380950                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   9246380950                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    164108000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    164108000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       341500                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       341500                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  15488935047                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  15488935047                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  15488935047                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  15488935047                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147082070000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147082070000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data  41215087708                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  41215087708                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 188297157708                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 188297157708                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.026278                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.026278                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.024273                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.024273                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.041370                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.041370                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000067                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000067                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.025453                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.025453                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.025453                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.025453                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16194.025960                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16194.025960                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37163.014357                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37163.014357                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13329.109812                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13329.109812                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17973.684211                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17973.684211                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24419.288697                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 24419.288697                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24419.288697                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 24419.288697                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -922,16 +918,16 @@ system.iocache.avg_blocked_cycles::no_mshrs          nan                       #
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1290934638893                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1290934638893                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1290934638893                       # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1290934638893                       # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1298563544001                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1298563544001                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1298563544001                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1298563544001                       # number of overall MSHR uncacheable cycles
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                    88048                       # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce                    88049                       # number of quiesce instructions executed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
index 1c6d485f3..43a81f743 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
@@ -935,7 +935,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=true
-width=64
+width=8
 default=system.pc.pciconfig.pio
 master=system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
 slave=system.bridge.master system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master
@@ -997,7 +997,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 default=system.membus.badaddr_responder.pio
 master=system.physmem.port[0] system.bridge.slave system.cpu.interrupts.pio system.cpu.interrupts.int_slave
 slave=system.apicbridge.master system.system_port system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.int_master
@@ -1477,7 +1477,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.l2c.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walker_cache.mem_side system.cpu.dtb_walker_cache.mem_side
 
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
index fefd6bd25..c8a74a70a 100755
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:08:09
-gem5 started Jun 29 2012 00:25:59
+gem5 compiled Jul  2 2012 08:58:39
+gem5 started Jul  2 2012 14:54:43
 gem5 executing on zizzer
 command line: build/X86/gem5.fast -d build/X86/tests/fast/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/fast/long/fs/10.linux-boot/x86/linux/pc-o3-timing
 warning: add_child('terminal'): child 'terminal' already has parent
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 5147413032500 because m5_exit instruction encountered
+Exiting @ tick 5173840734500 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
index 674b1d778..4862f54d8 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
@@ -1,186 +1,186 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  5.147413                       # Number of seconds simulated
-sim_ticks                                5147413032500                       # Number of ticks simulated
-final_tick                               5147413032500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  5.173841                       # Number of seconds simulated
+sim_ticks                                5173840734500                       # Number of ticks simulated
+final_tick                               5173840734500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 192321                       # Simulator instruction rate (inst/s)
-host_op_rate                                   378987                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2320932369                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 367552                       # Number of bytes of host memory used
-host_seconds                                  2217.82                       # Real time elapsed on the host
-sim_insts                                   426532736                       # Number of instructions simulated
-sim_ops                                     840526050                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::pc.south_bridge.ide      2503168                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker         3392                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker          384                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           1073280                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          10624512                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             14204736                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1073280                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1073280                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      9409088                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           9409088                       # Number of bytes written to this memory
-system.physmem.num_reads::pc.south_bridge.ide        39112                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker           53                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker            6                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              16770                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             166008                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                221949                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          147017                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               147017                       # Number of write requests responded to by this memory
-system.physmem.bw_read::pc.south_bridge.ide       486296                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker            659                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker             75                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               208509                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              2064049                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2759587                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          208509                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             208509                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1827926                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1827926                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1827926                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide       486296                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker           659                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker            75                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              208509                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             2064049                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4587513                       # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements                        110659                       # number of replacements
-system.l2c.tagsinuse                     64846.009272                       # Cycle average of tags in use
-system.l2c.total_refs                         3990913                       # Total number of references to valid blocks.
-system.l2c.sampled_refs                        174907                       # Sample count of references to valid blocks.
-system.l2c.avg_refs                         22.817343                       # Average number of references to valid blocks.
+host_inst_rate                                 158571                       # Simulator instruction rate (inst/s)
+host_op_rate                                   312487                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1923470418                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 368528                       # Number of bytes of host memory used
+host_seconds                                  2689.85                       # Real time elapsed on the host
+sim_insts                                   426531587                       # Number of instructions simulated
+sim_ops                                     840543055                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::pc.south_bridge.ide      2458496                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker         3200                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker          448                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           1064640                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          10449152                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             13975936                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1064640                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1064640                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      9180480                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           9180480                       # Number of bytes written to this memory
+system.physmem.num_reads::pc.south_bridge.ide        38414                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker           50                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker            7                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              16635                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             163268                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                218374                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          143445                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               143445                       # Number of write requests responded to by this memory
+system.physmem.bw_read::pc.south_bridge.ide       475178                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker            618                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker             87                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               205774                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              2019612                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2701269                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          205774                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             205774                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1774403                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1774403                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1774403                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide       475178                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker           618                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker            87                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              205774                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             2019612                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                4475672                       # Total bandwidth to/from this memory (bytes/s)
+system.l2c.replacements                        107079                       # number of replacements
+system.l2c.tagsinuse                     64844.194000                       # Cycle average of tags in use
+system.l2c.total_refs                         3995584                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                        171337                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                         23.320030                       # Average number of references to valid blocks.
 system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks        50048.797239                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.dtb.walker       13.777958                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.itb.walker        0.155980                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.inst           3384.461133                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.data          11398.816962                       # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks           0.763684                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.dtb.walker       0.000210                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.itb.walker       0.000002                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.inst             0.051643                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.data             0.173932                       # Average percentage of cache occupancy
-system.l2c.occ_percent::total                0.989472                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu.dtb.walker        111705                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.itb.walker          9478                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.inst             1055456                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.data             1342066                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                2518705                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks         1610504                       # number of Writeback hits
-system.l2c.Writeback_hits::total              1610504                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu.data              315                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                 315                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu.data            161822                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               161822                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu.dtb.walker         111705                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.itb.walker           9478                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.inst              1055456                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.data              1503888                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2680527                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu.dtb.walker        111705                       # number of overall hits
-system.l2c.overall_hits::cpu.itb.walker          9478                       # number of overall hits
-system.l2c.overall_hits::cpu.inst             1055456                       # number of overall hits
-system.l2c.overall_hits::cpu.data             1503888                       # number of overall hits
-system.l2c.overall_hits::total                2680527                       # number of overall hits
-system.l2c.ReadReq_misses::cpu.dtb.walker           53                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu.itb.walker            6                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu.inst             16771                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu.data             36056                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                52886                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu.data           1746                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              1746                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu.data          130897                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             130897                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu.dtb.walker           53                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu.itb.walker            6                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu.inst              16771                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu.data             166953                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                183783                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu.dtb.walker           53                       # number of overall misses
-system.l2c.overall_misses::cpu.itb.walker            6                       # number of overall misses
-system.l2c.overall_misses::cpu.inst             16771                       # number of overall misses
-system.l2c.overall_misses::cpu.data            166953                       # number of overall misses
-system.l2c.overall_misses::total               183783                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu.dtb.walker      2763500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu.itb.walker       312000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu.inst    876462500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu.data   1897742000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total     2777280000                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu.data     38052500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total     38052500                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu.data   6815913500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   6815913500                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu.dtb.walker      2763500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.itb.walker       312000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.inst    876462500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.data   8713655500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total      9593193500                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu.dtb.walker      2763500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu.itb.walker       312000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu.inst    876462500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu.data   8713655500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total     9593193500                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu.dtb.walker       111758                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.itb.walker         9484                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.inst         1072227                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.data         1378122                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2571591                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks      1610504                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total          1610504                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu.data         2061                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            2061                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu.data        292719                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           292719                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu.dtb.walker       111758                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.itb.walker         9484                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.inst          1072227                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.data          1670841                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2864310                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu.dtb.walker       111758                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.itb.walker         9484                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.inst         1072227                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.data         1670841                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2864310                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu.dtb.walker     0.000474                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.itb.walker     0.000633                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.inst       0.015641                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.data       0.026163                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.020565                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu.data     0.847162                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.847162                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu.data     0.447176                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.447176                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu.dtb.walker     0.000474                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.itb.walker     0.000633                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.inst        0.015641                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.data        0.099922                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.064163                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu.dtb.walker     0.000474                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.itb.walker     0.000633                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.inst       0.015641                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.data       0.099922                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.064163                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52141.509434                       # average ReadReq miss latency
+system.l2c.occ_blocks::writebacks        50153.806815                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.dtb.walker       12.883885                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.itb.walker        0.168545                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.inst           3383.279361                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.data          11294.055394                       # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks           0.765286                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.dtb.walker       0.000197                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.itb.walker       0.000003                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.inst             0.051625                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.data             0.172334                       # Average percentage of cache occupancy
+system.l2c.occ_percent::total                0.989444                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu.dtb.walker        110015                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.itb.walker          8879                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.inst             1055721                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.data             1346083                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                2520698                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks         1613450                       # number of Writeback hits
+system.l2c.Writeback_hits::total              1613450                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu.data              329                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                 329                       # number of UpgradeReq hits
+system.l2c.ReadExReq_hits::cpu.data            163813                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               163813                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu.dtb.walker         110015                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.itb.walker           8879                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.inst              1055721                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.data              1509896                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 2684511                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu.dtb.walker        110015                       # number of overall hits
+system.l2c.overall_hits::cpu.itb.walker          8879                       # number of overall hits
+system.l2c.overall_hits::cpu.inst             1055721                       # number of overall hits
+system.l2c.overall_hits::cpu.data             1509896                       # number of overall hits
+system.l2c.overall_hits::total                2684511                       # number of overall hits
+system.l2c.ReadReq_misses::cpu.dtb.walker           50                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.itb.walker            7                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.inst             16637                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.data             34998                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                51692                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu.data           1514                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              1514                       # number of UpgradeReq misses
+system.l2c.ReadExReq_misses::cpu.data          129215                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             129215                       # number of ReadExReq misses
+system.l2c.demand_misses::cpu.dtb.walker           50                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.itb.walker            7                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.inst              16637                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.data             164213                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                180907                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu.dtb.walker           50                       # number of overall misses
+system.l2c.overall_misses::cpu.itb.walker            7                       # number of overall misses
+system.l2c.overall_misses::cpu.inst             16637                       # number of overall misses
+system.l2c.overall_misses::cpu.data            164213                       # number of overall misses
+system.l2c.overall_misses::total               180907                       # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu.dtb.walker      2626500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.itb.walker       364000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.inst    883116000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.data   1863608490                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total     2749714990                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu.data     39367500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total     39367500                       # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu.data   6737631498                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   6737631498                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu.dtb.walker      2626500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.itb.walker       364000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.inst    883116000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.data   8601239988                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total      9487346488                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu.dtb.walker      2626500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu.itb.walker       364000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu.inst    883116000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu.data   8601239988                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total     9487346488                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu.dtb.walker       110065                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.itb.walker         8886                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.inst         1072358                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.data         1381081                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            2572390                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks      1613450                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total          1613450                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu.data         1843                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            1843                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu.data        293028                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           293028                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu.dtb.walker       110065                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.itb.walker         8886                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.inst          1072358                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.data          1674109                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             2865418                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu.dtb.walker       110065                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.itb.walker         8886                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.inst         1072358                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.data         1674109                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            2865418                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu.dtb.walker     0.000454                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.itb.walker     0.000788                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.inst       0.015514                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.data       0.025341                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.020095                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu.data     0.821487                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.821487                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu.data     0.440965                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.440965                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu.dtb.walker     0.000454                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.itb.walker     0.000788                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.inst        0.015514                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.data        0.098090                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.063135                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu.dtb.walker     0.000454                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.itb.walker     0.000788                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.inst       0.015514                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.data       0.098090                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.063135                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker        52530                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker        52000                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu.inst 52260.598652                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu.data 52633.181717                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 52514.465076                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu.data 21794.100802                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 21794.100802                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu.data 52070.815221                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 52070.815221                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52141.509434                       # average overall miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.inst 53081.444972                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.data 53248.999657                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 53194.207808                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu.data 26002.311757                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 26002.311757                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu.data 52142.796873                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 52142.796873                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu.dtb.walker        52530                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu.itb.walker        52000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu.inst 52260.598652                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu.data 52192.266686                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 52198.481361                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52141.509434                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.inst 53081.444972                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.data 52378.557045                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 52443.224906                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.dtb.walker        52530                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu.itb.walker        52000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.inst 52260.598652                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.data 52192.266686                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 52198.481361                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.inst 53081.444972                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.data 52378.557045                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 52443.224906                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -189,99 +189,99 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks              100350                       # number of writebacks
-system.l2c.writebacks::total                   100350                       # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu.inst              1                       # number of ReadReq MSHR hits
+system.l2c.writebacks::writebacks               96778                       # number of writebacks
+system.l2c.writebacks::total                    96778                       # number of writebacks
+system.l2c.ReadReq_mshr_hits::cpu.inst              2                       # number of ReadReq MSHR hits
 system.l2c.ReadReq_mshr_hits::cpu.data              1                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total                 2                       # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits::cpu.inst               1                       # number of demand (read+write) MSHR hits
+system.l2c.ReadReq_mshr_hits::total                 3                       # number of ReadReq MSHR hits
+system.l2c.demand_mshr_hits::cpu.inst               2                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_hits::cpu.data               1                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                  2                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu.inst              1                       # number of overall MSHR hits
+system.l2c.demand_mshr_hits::total                  3                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu.inst              2                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::cpu.data              1                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                 2                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu.dtb.walker           53                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu.itb.walker            6                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu.inst        16770                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu.data        36055                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total           52884                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu.data         1746                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total         1746                       # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu.data       130897                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        130897                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu.dtb.walker           53                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu.itb.walker            6                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu.inst         16770                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu.data        166952                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           183781                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu.dtb.walker           53                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu.itb.walker            6                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu.inst        16770                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu.data       166952                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          183781                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker      2121000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker       240000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu.inst    671584500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu.data   1456546000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total   2130491500                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu.data     70212000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total     70212000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu.data   5237071500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   5237071500                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.dtb.walker      2121000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.itb.walker       240000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.inst    671584500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.data   6693617500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total   7367563000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.dtb.walker      2121000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.itb.walker       240000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.inst    671584500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.data   6693617500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total   7367563000                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data  59976004500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total  59976004500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data   1230258000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   1230258000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu.data  61206262500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  61206262500                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000474                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000633                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.015640                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.026162                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.020565                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.847162                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.847162                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.447176                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.447176                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu.dtb.walker     0.000474                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu.itb.walker     0.000633                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu.inst     0.015640                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu.data     0.099921                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.064162                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu.dtb.walker     0.000474                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu.itb.walker     0.000633                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu.inst     0.015640                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu.data     0.099921                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.064162                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40018.867925                       # average ReadReq mshr miss latency
+system.l2c.overall_mshr_hits::total                 3                       # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses::cpu.dtb.walker           50                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.itb.walker            7                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.inst        16635                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.data        34997                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total           51689                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu.data         1514                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total         1514                       # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu.data       129215                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        129215                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu.dtb.walker           50                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu.itb.walker            7                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu.inst         16635                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu.data        164212                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           180904                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu.dtb.walker           50                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu.itb.walker            7                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu.inst        16635                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu.data       164212                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          180904                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker      2020500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker       280000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.inst    680227000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.data   1435916999                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total   2118444499                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu.data     60967500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total     60967500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu.data   5181066001                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   5181066001                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.dtb.walker      2020500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.itb.walker       280000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.inst    680227000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.data   6616983000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   7299510500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.dtb.walker      2020500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.itb.walker       280000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.inst    680227000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.data   6616983000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   7299510500                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data  59191869564                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total  59191869564                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data   1211082000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   1211082000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu.data  60402951564                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  60402951564                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000454                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000788                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.015513                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.025340                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.020094                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.821487                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.821487                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.440965                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.440965                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu.dtb.walker     0.000454                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.itb.walker     0.000788                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.inst     0.015513                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.data     0.098089                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.063134                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu.dtb.walker     0.000454                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.itb.walker     0.000788                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.inst     0.015513                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.data     0.098089                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.063134                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker        40410                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        40000                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40046.779964                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40397.892109                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 40286.126239                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40213.058419                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40213.058419                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40009.102577                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 40009.102577                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40018.867925                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40891.313496                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 41029.716804                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 40984.435741                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40269.154557                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40269.154557                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40096.474875                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 40096.474875                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker        40410                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker        40000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40046.779964                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.data 40093.065672                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 40088.817669                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40018.867925                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40891.313496                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.data 40295.368183                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 40350.188498                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker        40410                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker        40000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40046.779964                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.data 40093.065672                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 40088.817669                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40891.313496                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.data 40295.368183                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 40350.188498                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -289,39 +289,39 @@ system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.iocache.replacements                     47569                       # number of replacements
-system.iocache.tagsinuse                     0.147452                       # Cycle average of tags in use
+system.iocache.replacements                     47568                       # number of replacements
+system.iocache.tagsinuse                     0.202980                       # Cycle average of tags in use
 system.iocache.total_refs                           0                       # Total number of references to valid blocks.
-system.iocache.sampled_refs                     47585                       # Sample count of references to valid blocks.
+system.iocache.sampled_refs                     47584                       # Sample count of references to valid blocks.
 system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
-system.iocache.warmup_cycle              4996357767000                       # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::pc.south_bridge.ide     0.147452                       # Average occupied blocks per requestor
-system.iocache.occ_percent::pc.south_bridge.ide     0.009216                       # Average percentage of cache occupancy
-system.iocache.occ_percent::total            0.009216                       # Average percentage of cache occupancy
-system.iocache.ReadReq_misses::pc.south_bridge.ide          904                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              904                       # number of ReadReq misses
+system.iocache.warmup_cycle              5000598826000                       # Cycle when the warmup percentage was hit.
+system.iocache.occ_blocks::pc.south_bridge.ide     0.202980                       # Average occupied blocks per requestor
+system.iocache.occ_percent::pc.south_bridge.ide     0.012686                       # Average percentage of cache occupancy
+system.iocache.occ_percent::total            0.012686                       # Average percentage of cache occupancy
+system.iocache.ReadReq_misses::pc.south_bridge.ide          903                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              903                       # number of ReadReq misses
 system.iocache.WriteReq_misses::pc.south_bridge.ide        46720                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total           46720                       # number of WriteReq misses
-system.iocache.demand_misses::pc.south_bridge.ide        47624                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             47624                       # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide        47624                       # number of overall misses
-system.iocache.overall_misses::total            47624                       # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    113343932                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total    113343932                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::pc.south_bridge.ide   6309295160                       # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total   6309295160                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide   6422639092                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   6422639092                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide   6422639092                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   6422639092                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide          904                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            904                       # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::pc.south_bridge.ide        47623                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             47623                       # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide        47623                       # number of overall misses
+system.iocache.overall_misses::total            47623                       # number of overall misses
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    135810932                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total    135810932                       # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::pc.south_bridge.ide   6905757160                       # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total   6905757160                       # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide   7041568092                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   7041568092                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide   7041568092                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   7041568092                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::pc.south_bridge.ide          903                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            903                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::pc.south_bridge.ide        46720                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total         46720                       # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide        47624                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           47624                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide        47624                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          47624                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::pc.south_bridge.ide        47623                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           47623                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide        47623                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          47623                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteReq accesses
@@ -330,40 +330,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 125380.455752                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 125380.455752                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 135044.845034                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 135044.845034                       # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 134861.395347                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 134861.395347                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 134861.395347                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 134861.395347                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs      66555216                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 150399.703212                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 150399.703212                       # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 147811.583048                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 147811.583048                       # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 147860.657497                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 147860.657497                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 147860.657497                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 147860.657497                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs        269004                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                11227                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                   25                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs  5928.138951                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 10760.160000                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           46667                       # number of writebacks
 system.iocache.writebacks::total                46667                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          904                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          904                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          903                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          903                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total        46720                       # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide        47624                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total        47624                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide        47624                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total        47624                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     66312982                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     66312982                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide   3879551568                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total   3879551568                       # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide   3945864550                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   3945864550                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide   3945864550                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   3945864550                       # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::pc.south_bridge.ide        47623                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total        47623                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide        47623                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total        47623                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     88823000                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     88823000                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide   4476002926                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total   4476002926                       # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide   4564825926                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   4564825926                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide   4564825926                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   4564825926                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteReq accesses
@@ -372,14 +372,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 73355.068584                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 73355.068584                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 83038.346918                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 83038.346918                       # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 82854.538678                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 82854.538678                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 82854.538678                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 82854.538678                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 98364.341085                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 98364.341085                       # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 95804.857149                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 95804.857149                       # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 95853.388615                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 95853.388615                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 95853.388615                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 95853.388615                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
@@ -393,413 +393,413 @@ system.pc.south_bridge.ide.disks1.dma_read_txs            0
 system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
-system.cpu.numCycles                        459902894                       # number of cpu cycles simulated
+system.cpu.numCycles                        473010428                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                 90033870                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted           90033870                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect            1172024                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups              84304215                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                 81702749                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                 90027775                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           90027775                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect            1176793                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              84224638                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                 81706962                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
 system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles           29359737                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      447000113                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    90033870                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           81702749                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     169792580                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 5290860                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                     149776                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles               97806900                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                37530                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles         36600                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles          214                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                   9375679                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                523969                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                    5232                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          301265833                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.919513                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.390338                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           31360026                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      446936699                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    90027775                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           81706962                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     169789390                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 5321789                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                     167863                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles              104601282                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                37271                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles         44086                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles          447                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                   9371006                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                537925                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                    5262                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          310106612                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.836098                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.376721                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                131910949     43.79%     43.79% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  1767278      0.59%     44.37% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 72780383     24.16%     68.53% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                   988082      0.33%     68.86% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  1637864      0.54%     69.40% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  3667894      1.22%     70.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  1147346      0.38%     71.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1446143      0.48%     71.48% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 85919894     28.52%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                140752877     45.39%     45.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  1771842      0.57%     45.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 72784841     23.47%     69.43% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                   985545      0.32%     69.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  1639332      0.53%     70.28% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  3672529      1.18%     71.46% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  1138013      0.37%     71.83% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1446532      0.47%     72.29% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 85915101     27.71%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            301265833                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.195767                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.971945                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 34474494                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              93907388                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 163990791                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               4810664                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                4082496                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts              876264710                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                   919                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                4082496                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 38727929                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                39278399                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       10114969                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 164053704                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              45008336                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              872424503                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                  9763                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents               34576608                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               3790570                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents         31863881                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands          1394114241                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            2488384373                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       2488383477                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups               896                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps            1347565425                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 46548809                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts             469868                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts         476809                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  46309775                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             18907776                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            10445518                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1298255                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          1025454                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  865635268                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             1719822                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 864337626                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            112774                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        25913081                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     53108345                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         204185                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     301265833                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.869020                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.387854                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            310106612                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.190329                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.944877                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 36504487                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             100689087                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 164100014                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               4706777                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                4106247                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts              876222772                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                   974                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                4106247                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 40918052                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                44290154                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       10988643                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 163783570                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              46019946                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              872439032                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                  9880                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               35250675                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               3950071                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents         31995010                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands          1394183444                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            2488413838                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       2488413278                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups               560                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps            1347594272                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 46589165                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts             469708                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts         477213                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  48119615                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             18916713                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            10445823                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1292985                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          1005726                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  865744936                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             1721292                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 864337925                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            123293                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        26001434                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     53514506                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         205573                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     310106612                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.787228                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.396179                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            94932773     31.51%     31.51% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            22142074      7.35%     38.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            18888671      6.27%     45.13% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             7860945      2.61%     47.74% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            80656411     26.77%     74.51% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             3302785      1.10%     75.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            72810465     24.17%     99.78% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              540656      0.18%     99.96% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              131053      0.04%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           102391332     33.02%     33.02% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            23760486      7.66%     40.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            19024925      6.13%     46.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             7818761      2.52%     49.34% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            80618326     26.00%     75.33% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             3106091      1.00%     76.34% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            72752494     23.46%     99.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              520993      0.17%     99.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              113204      0.04%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       301265833                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       310106612                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  170381      8.07%      8.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      8.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      8.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      8.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      8.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      8.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      8.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      8.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      8.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      8.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      8.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      8.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      8.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      8.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      8.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      8.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      8.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      8.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      8.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      8.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      8.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      8.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      8.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      8.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      8.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      8.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      8.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      8.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      8.07% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                1776523     84.09%     92.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                165648      7.84%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  162823      7.80%      7.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      7.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      7.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      7.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      7.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      7.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      7.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      7.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      7.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      7.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      7.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      7.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      7.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      7.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      7.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      7.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      7.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      7.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      7.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      7.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      7.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      7.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      7.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      7.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      7.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      7.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      7.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      7.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      7.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                1765220     84.55%     92.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                159742      7.65%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass            297256      0.03%      0.03% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             829421724     95.96%     95.99% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    0      0.00%     95.99% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     95.99% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     95.99% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     95.99% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     95.99% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     95.99% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     95.99% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     95.99% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     95.99% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     95.99% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     95.99% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     95.99% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     95.99% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     95.99% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     95.99% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     95.99% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     95.99% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     95.99% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     95.99% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     95.99% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     95.99% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     95.99% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     95.99% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     95.99% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     95.99% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     95.99% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     95.99% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     95.99% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             25169917      2.91%     98.91% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             9448729      1.09%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass            296671      0.03%      0.03% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             829442170     95.96%     96.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    0      0.00%     96.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     96.00% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     96.00% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     96.00% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     96.00% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     96.00% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     96.00% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     96.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     96.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     96.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     96.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     96.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     96.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     96.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     96.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     96.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     96.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     96.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     96.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     96.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     96.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     96.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     96.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     96.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     96.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     96.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     96.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             25162510      2.91%     98.91% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             9436574      1.09%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              864337626                       # Type of FU issued
-system.cpu.iq.rate                           1.879392                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     2112552                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.002444                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         2032304206                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         893278706                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    853918308                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 381                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                418                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses           98                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              866152744                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     178                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          1572054                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              864337925                       # Type of FU issued
+system.cpu.iq.rate                           1.827313                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2087785                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.002415                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         2041131934                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         893478671                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    853934886                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 231                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                260                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses           63                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              866128931                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     108                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1577690                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      3603717                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        21501                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        11898                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      2033136                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      3621025                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        20103                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        12189                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      2042088                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads      7821637                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          2389                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads      7821421                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          4286                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                4082496                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                25489851                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               1396862                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           867355090                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            297196                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              18907776                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             10445518                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts             881207                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 698514                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 12367                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          11898                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         698869                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       624345                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1323214                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             862415633                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              24733940                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           1921992                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                4106247                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                27916479                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               1927801                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           867466228                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            303428                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              18916713                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             10445834                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts             882766                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 975199                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 15962                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          12189                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         699297                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       625213                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              1324510                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             862446659                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              24735217                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1891265                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                     33937040                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 86496224                       # Number of branches executed
-system.cpu.iew.exec_stores                    9203100                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.875212                       # Inst execution rate
-system.cpu.iew.wb_sent                      861954133                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     853918406                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 669978264                       # num instructions producing a value
-system.cpu.iew.wb_consumers                1919317191                       # num instructions consuming a value
+system.cpu.iew.exec_refs                     33929559                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 86496146                       # Number of branches executed
+system.cpu.iew.exec_stores                    9194342                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.823314                       # Inst execution rate
+system.cpu.iew.wb_sent                      861961974                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     853934949                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 669649521                       # num instructions producing a value
+system.cpu.iew.wb_consumers                1918783501                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.856736                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.349071                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.805319                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.348997                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts      426532736                       # The number of committed instructions
-system.cpu.commit.commitCommittedOps        840526050                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts        26723975                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls         1515635                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           1176103                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    297198870                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.828160                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.864352                       # Number of insts commited each cycle
+system.cpu.commit.commitCommittedInsts      426531587                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps        840543055                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts        26818803                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         1515717                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts           1181719                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    306015924                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.746730                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.861261                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    116541377     39.21%     39.21% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     14339767      4.82%     44.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      4295097      1.45%     45.48% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     76671720     25.80%     71.28% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      3910835      1.32%     72.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1786901      0.60%     73.20% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      1117084      0.38%     73.57% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     71988132     24.22%     97.80% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      6547957      2.20%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    125070317     40.87%     40.87% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     14726015      4.81%     45.68% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      4257326      1.39%     47.07% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     76646045     25.05%     72.12% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      3895754      1.27%     73.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1793252      0.59%     73.98% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      1102852      0.36%     74.34% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     71997039     23.53%     97.87% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      6527324      2.13%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    297198870                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            426532736                       # Number of instructions committed
-system.cpu.commit.committedOps              840526050                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    306015924                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            426531587                       # Number of instructions committed
+system.cpu.commit.committedOps              840543055                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       23716438                       # Number of memory references committed
-system.cpu.commit.loads                      15304056                       # Number of loads committed
-system.cpu.commit.membars                      781569                       # Number of memory barriers committed
-system.cpu.commit.branches                   85505804                       # Number of branches committed
+system.cpu.commit.refs                       23699431                       # Number of memory references committed
+system.cpu.commit.loads                      15295685                       # Number of loads committed
+system.cpu.commit.membars                      781577                       # Number of memory barriers committed
+system.cpu.commit.branches                   85508404                       # Number of branches committed
 system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 768351683                       # Number of committed integer instructions.
+system.cpu.commit.int_insts                 768361520                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                    0                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events               6547957                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events               6527324                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   1157821631                       # The number of ROB reads
-system.cpu.rob.rob_writes                  1738597524                       # The number of ROB writes
-system.cpu.timesIdled                         2901104                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                       158637061                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   9834920608                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                   426532736                       # Number of Instructions Simulated
-system.cpu.committedOps                     840526050                       # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total             426532736                       # Number of Instructions Simulated
-system.cpu.cpi                               1.078236                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.078236                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.927441                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.927441                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               2163268420                       # number of integer regfile reads
-system.cpu.int_regfile_writes              1362711366                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                        98                       # number of floating regfile reads
-system.cpu.misc_regfile_reads               281060274                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                 403581                       # number of misc regfile writes
-system.cpu.icache.replacements                1071746                       # number of replacements
-system.cpu.icache.tagsinuse                509.688073                       # Cycle average of tags in use
-system.cpu.icache.total_refs                  8235470                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                1072258                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                   7.680493                       # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle            56594855000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     509.688073                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.995485                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.995485                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst      8235470                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total         8235470                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst       8235470                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total          8235470                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst      8235470                       # number of overall hits
-system.cpu.icache.overall_hits::total         8235470                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1140205                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1140205                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1140205                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1140205                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1140205                       # number of overall misses
-system.cpu.icache.overall_misses::total       1140205                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  16916733991                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  16916733991                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  16916733991                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  16916733991                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  16916733991                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  16916733991                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst      9375675                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total      9375675                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst      9375675                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total      9375675                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst      9375675                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total      9375675                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.121613                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.121613                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.121613                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.121613                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.121613                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.121613                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14836.572363                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 14836.572363                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 14836.572363                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 14836.572363                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 14836.572363                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 14836.572363                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs      2216492                       # number of cycles access was blocked
+system.cpu.rob.rob_reads                   1166770942                       # The number of ROB reads
+system.cpu.rob.rob_writes                  1738844954                       # The number of ROB writes
+system.cpu.timesIdled                         2997386                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                       162903816                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   9874668492                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                   426531587                       # Number of Instructions Simulated
+system.cpu.committedOps                     840543055                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total             426531587                       # Number of Instructions Simulated
+system.cpu.cpi                               1.108969                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.108969                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.901738                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.901738                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               2163215430                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1362691420                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                        63                       # number of floating regfile reads
+system.cpu.misc_regfile_reads               281069935                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                 403791                       # number of misc regfile writes
+system.cpu.icache.replacements                1071897                       # number of replacements
+system.cpu.icache.tagsinuse                510.429584                       # Cycle average of tags in use
+system.cpu.icache.total_refs                  8228054                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                1072409                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                   7.672496                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle            56932855000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::cpu.inst     510.429584                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.996933                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.996933                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst      8228054                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total         8228054                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst       8228054                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total          8228054                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst      8228054                       # number of overall hits
+system.cpu.icache.overall_hits::total         8228054                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1142948                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1142948                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1142948                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1142948                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1142948                       # number of overall misses
+system.cpu.icache.overall_misses::total       1142948                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  18865193488                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  18865193488                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  18865193488                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  18865193488                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  18865193488                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  18865193488                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst      9371002                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total      9371002                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst      9371002                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total      9371002                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst      9371002                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total      9371002                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.121966                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.121966                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.121966                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.121966                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.121966                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.121966                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16505.732096                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 16505.732096                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 16505.732096                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 16505.732096                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 16505.732096                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 16505.732096                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs      3301994                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               241                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               399                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs  9197.062241                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs  8275.674185                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks         1572                       # number of writebacks
-system.cpu.icache.writebacks::total              1572                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        67614                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        67614                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        67614                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        67614                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        67614                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        67614                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1072591                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      1072591                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      1072591                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      1072591                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      1072591                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      1072591                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12848213492                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  12848213492                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12848213492                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  12848213492                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12848213492                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  12848213492                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.114401                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.114401                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.114401                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.114401                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.114401                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.114401                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11978.669868                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11978.669868                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11978.669868                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11978.669868                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11978.669868                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11978.669868                       # average overall mshr miss latency
+system.cpu.icache.writebacks::writebacks         1600                       # number of writebacks
+system.cpu.icache.writebacks::total              1600                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        70415                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        70415                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        70415                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        70415                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        70415                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        70415                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1072533                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total      1072533                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst      1072533                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total      1072533                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst      1072533                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total      1072533                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  14734319994                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  14734319994                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  14734319994                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  14734319994                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  14734319994                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  14734319994                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.114452                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.114452                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.114452                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.114452                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.114452                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.114452                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13737.870997                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13737.870997                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13737.870997                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 13737.870997                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13737.870997                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 13737.870997                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.itb_walker_cache.replacements        12981                       # number of replacements
-system.cpu.itb_walker_cache.tagsinuse        6.013322                       # Cycle average of tags in use
-system.cpu.itb_walker_cache.total_refs          25373                       # Total number of references to valid blocks.
-system.cpu.itb_walker_cache.sampled_refs        12993                       # Sample count of references to valid blocks.
-system.cpu.itb_walker_cache.avg_refs         1.952821                       # Average number of references to valid blocks.
-system.cpu.itb_walker_cache.warmup_cycle 5123561713000                       # Cycle when the warmup percentage was hit.
-system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker     6.013322                       # Average occupied blocks per requestor
-system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker     0.375833                       # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.occ_percent::total     0.375833                       # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        25418                       # number of ReadReq hits
-system.cpu.itb_walker_cache.ReadReq_hits::total        25418                       # number of ReadReq hits
+system.cpu.itb_walker_cache.replacements        11177                       # number of replacements
+system.cpu.itb_walker_cache.tagsinuse        6.030365                       # Cycle average of tags in use
+system.cpu.itb_walker_cache.total_refs          31227                       # Total number of references to valid blocks.
+system.cpu.itb_walker_cache.sampled_refs        11191                       # Sample count of references to valid blocks.
+system.cpu.itb_walker_cache.avg_refs         2.790367                       # Average number of references to valid blocks.
+system.cpu.itb_walker_cache.warmup_cycle 5136145388000                       # Cycle when the warmup percentage was hit.
+system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker     6.030365                       # Average occupied blocks per requestor
+system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker     0.376898                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.occ_percent::total     0.376898                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        31228                       # number of ReadReq hits
+system.cpu.itb_walker_cache.ReadReq_hits::total        31228                       # number of ReadReq hits
 system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            3                       # number of WriteReq hits
 system.cpu.itb_walker_cache.WriteReq_hits::total            3                       # number of WriteReq hits
-system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker        25421                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.demand_hits::total        25421                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker        25421                       # number of overall hits
-system.cpu.itb_walker_cache.overall_hits::total        25421                       # number of overall hits
-system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker        13864                       # number of ReadReq misses
-system.cpu.itb_walker_cache.ReadReq_misses::total        13864                       # number of ReadReq misses
-system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker        13864                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.demand_misses::total        13864                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker        13864                       # number of overall misses
-system.cpu.itb_walker_cache.overall_misses::total        13864                       # number of overall misses
-system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker    165480500                       # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.ReadReq_miss_latency::total    165480500                       # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker    165480500                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::total    165480500                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker    165480500                       # number of overall miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::total    165480500                       # number of overall miss cycles
-system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        39282                       # number of ReadReq accesses(hits+misses)
-system.cpu.itb_walker_cache.ReadReq_accesses::total        39282                       # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker        31231                       # number of demand (read+write) hits
+system.cpu.itb_walker_cache.demand_hits::total        31231                       # number of demand (read+write) hits
+system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker        31231                       # number of overall hits
+system.cpu.itb_walker_cache.overall_hits::total        31231                       # number of overall hits
+system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker        12057                       # number of ReadReq misses
+system.cpu.itb_walker_cache.ReadReq_misses::total        12057                       # number of ReadReq misses
+system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker        12057                       # number of demand (read+write) misses
+system.cpu.itb_walker_cache.demand_misses::total        12057                       # number of demand (read+write) misses
+system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker        12057                       # number of overall misses
+system.cpu.itb_walker_cache.overall_misses::total        12057                       # number of overall misses
+system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker    192652500                       # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.ReadReq_miss_latency::total    192652500                       # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker    192652500                       # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::total    192652500                       # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker    192652500                       # number of overall miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::total    192652500                       # number of overall miss cycles
+system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        43285                       # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.ReadReq_accesses::total        43285                       # number of ReadReq accesses(hits+misses)
 system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            3                       # number of WriteReq accesses(hits+misses)
 system.cpu.itb_walker_cache.WriteReq_accesses::total            3                       # number of WriteReq accesses(hits+misses)
-system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        39285                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.demand_accesses::total        39285                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        39285                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::total        39285                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.352935                       # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.352935                       # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.352908                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_miss_rate::total     0.352908                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.352908                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_miss_rate::total     0.352908                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11935.985286                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11935.985286                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11935.985286                       # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11935.985286                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11935.985286                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11935.985286                       # average overall miss latency
+system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        43288                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.demand_accesses::total        43288                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        43288                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::total        43288                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.278549                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.278549                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.278530                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_miss_rate::total     0.278530                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.278530                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_miss_rate::total     0.278530                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 15978.477233                       # average ReadReq miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 15978.477233                       # average ReadReq miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 15978.477233                       # average overall miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::total 15978.477233                       # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 15978.477233                       # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::total 15978.477233                       # average overall miss latency
 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -808,78 +808,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.itb_walker_cache.writebacks::writebacks         1460                       # number of writebacks
-system.cpu.itb_walker_cache.writebacks::total         1460                       # number of writebacks
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker        13864                       # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::total        13864                       # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker        13864                       # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::total        13864                       # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker        13864                       # number of overall MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::total        13864                       # number of overall MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker    123445500                       # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total    123445500                       # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker    123445500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::total    123445500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker    123445500                       # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::total    123445500                       # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.352935                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.352935                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.352908                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.352908                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.352908                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.352908                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  8904.032025                       # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  8904.032025                       # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  8904.032025                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  8904.032025                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  8904.032025                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  8904.032025                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.writebacks::writebacks         1620                       # number of writebacks
+system.cpu.itb_walker_cache.writebacks::total         1620                       # number of writebacks
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker        12057                       # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::total        12057                       # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker        12057                       # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::total        12057                       # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker        12057                       # number of overall MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::total        12057                       # number of overall MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker    155859527                       # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total    155859527                       # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker    155859527                       # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::total    155859527                       # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker    155859527                       # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::total    155859527                       # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.278549                       # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.278549                       # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.278530                       # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.278530                       # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.278530                       # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.278530                       # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 12926.891184                       # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 12926.891184                       # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 12926.891184                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 12926.891184                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 12926.891184                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 12926.891184                       # average overall mshr miss latency
 system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.dtb_walker_cache.replacements       120380                       # number of replacements
-system.cpu.dtb_walker_cache.tagsinuse       12.933344                       # Cycle average of tags in use
-system.cpu.dtb_walker_cache.total_refs         133363                       # Total number of references to valid blocks.
-system.cpu.dtb_walker_cache.sampled_refs       120396                       # Sample count of references to valid blocks.
-system.cpu.dtb_walker_cache.avg_refs         1.107703                       # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.warmup_cycle 5104613509000                       # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker    12.933344                       # Average occupied blocks per requestor
-system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker     0.808334                       # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.occ_percent::total     0.808334                       # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker       133363                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.ReadReq_hits::total       133363                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker       133363                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::total       133363                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker       133363                       # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::total       133363                       # number of overall hits
-system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker       121457                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.ReadReq_misses::total       121457                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker       121457                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::total       121457                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker       121457                       # number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::total       121457                       # number of overall misses
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker   1679660000                       # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::total   1679660000                       # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker   1679660000                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::total   1679660000                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker   1679660000                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::total   1679660000                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       254820                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.ReadReq_accesses::total       254820                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       254820                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::total       254820                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       254820                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::total       254820                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.476638                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.476638                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.476638                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::total     0.476638                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.476638                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::total     0.476638                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 13829.256445                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 13829.256445                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 13829.256445                       # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 13829.256445                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 13829.256445                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 13829.256445                       # average overall miss latency
+system.cpu.dtb_walker_cache.replacements       116226                       # number of replacements
+system.cpu.dtb_walker_cache.tagsinuse       12.942586                       # Cycle average of tags in use
+system.cpu.dtb_walker_cache.total_refs         138119                       # Total number of references to valid blocks.
+system.cpu.dtb_walker_cache.sampled_refs       116242                       # Sample count of references to valid blocks.
+system.cpu.dtb_walker_cache.avg_refs         1.188202                       # Average number of references to valid blocks.
+system.cpu.dtb_walker_cache.warmup_cycle 5112881220000                       # Cycle when the warmup percentage was hit.
+system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker    12.942586                       # Average occupied blocks per requestor
+system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker     0.808912                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.occ_percent::total     0.808912                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker       138119                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.ReadReq_hits::total       138119                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker       138119                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.demand_hits::total       138119                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker       138119                       # number of overall hits
+system.cpu.dtb_walker_cache.overall_hits::total       138119                       # number of overall hits
+system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker       117277                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.ReadReq_misses::total       117277                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker       117277                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.demand_misses::total       117277                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker       117277                       # number of overall misses
+system.cpu.dtb_walker_cache.overall_misses::total       117277                       # number of overall misses
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker   2115105000                       # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::total   2115105000                       # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker   2115105000                       # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::total   2115105000                       # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker   2115105000                       # number of overall miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::total   2115105000                       # number of overall miss cycles
+system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       255396                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.ReadReq_accesses::total       255396                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       255396                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.demand_accesses::total       255396                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       255396                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::total       255396                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.459197                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.459197                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.459197                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::total     0.459197                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.459197                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::total     0.459197                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 18035.121976                       # average ReadReq miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 18035.121976                       # average ReadReq miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 18035.121976                       # average overall miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 18035.121976                       # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 18035.121976                       # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 18035.121976                       # average overall miss latency
 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -888,146 +888,146 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.dtb_walker_cache.writebacks::writebacks        37082                       # number of writebacks
-system.cpu.dtb_walker_cache.writebacks::total        37082                       # number of writebacks
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker       121457                       # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total       121457                       # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker       121457                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::total       121457                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker       121457                       # number of overall MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::total       121457                       # number of overall MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker   1312360500                       # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total   1312360500                       # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker   1312360500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total   1312360500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker   1312360500                       # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total   1312360500                       # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.476638                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.476638                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.476638                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.476638                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.476638                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.476638                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10805.145031                       # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10805.145031                       # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10805.145031                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10805.145031                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10805.145031                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10805.145031                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.writebacks::writebacks        36600                       # number of writebacks
+system.cpu.dtb_walker_cache.writebacks::total        36600                       # number of writebacks
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker       117277                       # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total       117277                       # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker       117277                       # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::total       117277                       # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker       117277                       # number of overall MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::total       117277                       # number of overall MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker   1760668506                       # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total   1760668506                       # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker   1760668506                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total   1760668506                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker   1760668506                       # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total   1760668506                       # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.459197                       # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.459197                       # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.459197                       # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.459197                       # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.459197                       # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.459197                       # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 15012.905395                       # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 15012.905395                       # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 15012.905395                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 15012.905395                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 15012.905395                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 15012.905395                       # average overall mshr miss latency
 system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                1670972                       # number of replacements
-system.cpu.dcache.tagsinuse                511.998179                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 19056575                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                1671484                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  11.400992                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle               34328000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data     511.998179                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.999996                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.999996                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data     10967822                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        10967822                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      8085914                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        8085914                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      19053736                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         19053736                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     19053736                       # number of overall hits
-system.cpu.dcache.overall_hits::total        19053736                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      2407391                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       2407391                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       317109                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       317109                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      2724500                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2724500                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      2724500                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2724500                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  35545734500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  35545734500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  10083377990                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  10083377990                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  45629112490                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  45629112490                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  45629112490                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  45629112490                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     13375213                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     13375213                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      8403023                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      8403023                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     21778236                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     21778236                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     21778236                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     21778236                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.179989                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.179989                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037737                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.037737                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.125102                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.125102                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.125102                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.125102                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14765.251885                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14765.251885                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31797.829737                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 31797.829737                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 16747.701409                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 16747.701409                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 16747.701409                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 16747.701409                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs     19144990                       # number of cycles access was blocked
+system.cpu.dcache.replacements                1674194                       # number of replacements
+system.cpu.dcache.tagsinuse                511.997520                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 19015880                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                1674706                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  11.354757                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle               36854000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data     511.997520                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.999995                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.999995                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     10936415                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        10936415                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      8076863                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        8076863                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      19013278                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         19013278                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     19013278                       # number of overall hits
+system.cpu.dcache.overall_hits::total        19013278                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      2432524                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       2432524                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       317516                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       317516                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      2750040                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2750040                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2750040                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2750040                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  45245018000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  45245018000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  10626959991                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  10626959991                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  55871977991                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  55871977991                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  55871977991                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  55871977991                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     13368939                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     13368939                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      8394379                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      8394379                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     21763318                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     21763318                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     21763318                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     21763318                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.181953                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.181953                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037825                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.037825                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.126361                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.126361                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.126361                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.126361                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18600.029434                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 18600.029434                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33469.053500                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 33469.053500                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 20316.787389                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 20316.787389                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 20316.787389                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 20316.787389                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs     26625491                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs              3356                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              4915                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs  5704.705006                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  5417.190437                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      1570390                       # number of writebacks
-system.cpu.dcache.writebacks::total           1570390                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      1028077                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      1028077                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        22422                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        22422                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1050499                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1050499                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1050499                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1050499                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1379314                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1379314                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       294687                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       294687                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1674001                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1674001                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1674001                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1674001                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  17753874500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  17753874500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8876538990                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   8876538990                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  26630413490                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  26630413490                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  26630413490                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  26630413490                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  85208379000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  85208379000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   1393915000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   1393915000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  86602294000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  86602294000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.103125                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.103125                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.035069                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.035069                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.076866                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.076866                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.076866                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.076866                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12871.524903                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12871.524903                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30121.922548                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30121.922548                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15908.242283                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 15908.242283                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15908.242283                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 15908.242283                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks      1573630                       # number of writebacks
+system.cpu.dcache.writebacks::total           1573630                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      1050273                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      1050273                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        22706                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        22706                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      1072979                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1072979                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1072979                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1072979                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1382251                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1382251                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       294810                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       294810                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1677061                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1677061                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1677061                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1677061                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  23310362534                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  23310362534                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   9362745997                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   9362745997                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  32673108531                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  32673108531                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  32673108531                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  32673108531                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  85207340500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  85207340500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   1386118500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   1386118500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  86593459000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  86593459000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.103393                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.103393                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.035120                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.035120                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.077059                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.077059                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.077059                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.077059                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16864.059085                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16864.059085                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31758.576700                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31758.576700                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19482.361423                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 19482.361423                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19482.361423                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 19482.361423                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini
index c9fc9d3a5..d219b0faf 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini
@@ -1190,7 +1190,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=true
-width=64
+width=8
 default=system.pc.pciconfig.pio
 master=system.physmem.port[0] system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.cpu0.interrupts.pio system.cpu0.interrupts.int_slave system.cpu1.interrupts.pio system.cpu1.interrupts.int_slave
 slave=system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master system.l1_cntrl0.sequencer.pio_port system.l1_cntrl1.sequencer.pio_port system.cpu0.interrupts.int_master system.cpu1.interrupts.int_master
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout
index d6cb455f2..9c27e2eb7 100755
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout
@@ -1,13 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun  4 2012 13:44:12
-gem5 started Jun  4 2012 17:11:29
+gem5 compiled Jul  2 2012 09:03:01
+gem5 started Jul  2 2012 15:09:17
 gem5 executing on zizzer
-command line: build/X86_MESI_CMP_directory/gem5.opt -d build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory
+command line: build/X86_MESI_CMP_directory/gem5.fast -d build/X86_MESI_CMP_directory/tests/fast/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/X86_MESI_CMP_directory/tests/fast/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory
 warning: add_child('terminal'): child 'terminal' already has parent
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9.smp
-      0: rtc: Real-time clock set to Sun Jan  1 00:00:00 2012
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 5304689685500 because m5_exit instruction encountered
+Exiting @ tick 5305568291500 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt
index b7d143468..b9331fa8f 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt
@@ -1,77 +1,77 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  5.304690                       # Number of seconds simulated
-sim_ticks                                5304689685500                       # Number of ticks simulated
-final_tick                               5304689685500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  5.305568                       # Number of seconds simulated
+sim_ticks                                5305568291500                       # Number of ticks simulated
+final_tick                               5305568291500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 163049                       # Simulator instruction rate (inst/s)
-host_op_rate                                   333085                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             6301127704                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 481488                       # Number of bytes of host memory used
-host_seconds                                   841.86                       # Real time elapsed on the host
-sim_insts                                   137264752                       # Number of instructions simulated
-sim_ops                                     280412254                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::pc.south_bridge.ide        35144                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker       126800                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker        64416                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst        827772912                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         39626426                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker       100784                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker        45696                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst        470347440                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data         53905938                       # Number of bytes read from this memory
-system.physmem.bytes_read::total           1392025556                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst    827772912                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst    470347440                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total      1298120352                       # Number of instructions bytes read from this memory
+host_inst_rate                                 254586                       # Simulator instruction rate (inst/s)
+host_op_rate                                   522269                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             9722568027                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 466304                       # Number of bytes of host memory used
+host_seconds                                   545.70                       # Real time elapsed on the host
+sim_insts                                   138926459                       # Number of instructions simulated
+sim_ops                                     285000258                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::pc.south_bridge.ide        35160                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker       131880                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker        65368                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst        843624624                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         40107648                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker        91872                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker        42696                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst        468878472                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data         53485285                       # Number of bytes read from this memory
+system.physmem.bytes_read::total           1406463005                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst    843624624                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst    468878472                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total      1312503096                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::pc.south_bridge.ide      2991104                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.itb.walker           16                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data      32173132                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data      35738580                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          70902832                       # Number of bytes written to this memory
-system.physmem.num_reads::pc.south_bridge.ide          809                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker        15850                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         8052                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst         103471614                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data           6642662                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker        12598                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker         5712                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst          58793430                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data           9050935                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total             178001662                       # Number of read requests responded to by this memory
+system.physmem.bytes_written::cpu0.data      32434308                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data      35512736                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          70938164                       # Number of bytes written to this memory
+system.physmem.num_reads::pc.south_bridge.ide          811                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker        16485                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         8171                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst         105453078                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data           6721984                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker        11484                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker         5337                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst          58609809                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data           8980290                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total             179807449                       # Number of read requests responded to by this memory
 system.physmem.num_writes::pc.south_bridge.ide        46736                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.itb.walker            2                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data          4837067                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data          4982709                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              9866514                       # Number of write requests responded to by this memory
-system.physmem.bw_read::pc.south_bridge.ide         6625                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker         23903                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker         12143                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst           156045492                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             7470074                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker         18999                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker          8614                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst            88666344                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data            10161940                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               262414135                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst      156045492                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst       88666344                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          244711836                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::pc.south_bridge.ide       563860                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::cpu0.data          4872641                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data          4951979                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              9871358                       # Number of write requests responded to by this memory
+system.physmem.bw_read::pc.south_bridge.ide         6627                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker         24857                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker         12321                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst           159007401                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             7559539                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker         17316                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker          8047                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst            88374788                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data            10080972                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               265091867                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst      159007401                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst       88374788                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          247382189                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::pc.south_bridge.ide       563767                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.itb.walker            3                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data            6065036                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data            6737167                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               13366066                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide       570485                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker        23903                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker        12146                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst          156045492                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           13535110                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker        18999                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker         8614                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst           88666344                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data           16899107                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              275780201                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data            6113258                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data            6693484                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               13370512                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide       570394                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker        24857                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker        12324                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst          159007401                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           13672797                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker        17316                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker         8047                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst           88374788                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data           16774456                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              278462379                       # Total bandwidth to/from this memory (bytes/s)
 system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_bytes        32768                       # Number of bytes transfered via DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_txs           30                       # Number of DMA read transactions (not PRD).
@@ -84,52 +84,52 @@ system.pc.south_bridge.ide.disks1.dma_read_txs            0
 system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
-system.cpu0.numCycles                     10608177450                       # number of cpu cycles simulated
+system.cpu0.numCycles                     10611136583                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   88690468                       # Number of instructions committed
-system.cpu0.committedOps                    187060545                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses            168469813                       # Number of integer alu accesses
+system.cpu0.committedInsts                   90467543                       # Number of instructions committed
+system.cpu0.committedOps                    191745753                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses            172320951                       # Number of integer alu accesses
 system.cpu0.num_fp_alu_accesses                     0                       # Number of float alu accesses
 system.cpu0.num_func_calls                          0                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts     17923925                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                   168469813                       # number of integer instructions
+system.cpu0.num_conditional_control_insts     18433460                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                   172320951                       # number of integer instructions
 system.cpu0.num_fp_insts                            0                       # number of float instructions
-system.cpu0.num_int_register_reads          517963630                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes         280483339                       # number of times the integer registers were written
+system.cpu0.num_int_register_reads          529440727                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes         286411795                       # number of times the integer registers were written
 system.cpu0.num_fp_register_reads                   0                       # number of times the floating registers were read
 system.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                     19132508                       # number of memory refs
-system.cpu0.num_load_insts                   14284566                       # Number of load instructions
-system.cpu0.num_store_insts                   4847942                       # Number of store instructions
-system.cpu0.num_idle_cycles              10086452980.871330                       # Number of idle cycles
-system.cpu0.num_busy_cycles              521724469.128670                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.049181                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.950819                       # Percentage of idle cycles
+system.cpu0.num_mem_refs                     19683524                       # number of memory refs
+system.cpu0.num_load_insts                   14800104                       # Number of load instructions
+system.cpu0.num_store_insts                   4883420                       # Number of store instructions
+system.cpu0.num_idle_cycles              10087380547.886099                       # Number of idle cycles
+system.cpu0.num_busy_cycles              523756035.113901                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.049359                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.950641                       # Percentage of idle cycles
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu0.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu1.numCycles                     10609379371                       # number of cpu cycles simulated
+system.cpu1.numCycles                     10608184508                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   48574284                       # Number of instructions committed
-system.cpu1.committedOps                     93351709                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             89110416                       # Number of integer alu accesses
+system.cpu1.committedInsts                   48458916                       # Number of instructions committed
+system.cpu1.committedOps                     93254505                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             88898001                       # Number of integer alu accesses
 system.cpu1.num_fp_alu_accesses                     0                       # Number of float alu accesses
 system.cpu1.num_func_calls                          0                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      8197841                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    89110416                       # number of integer instructions
+system.cpu1.num_conditional_control_insts      8156206                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    88898001                       # number of integer instructions
 system.cpu1.num_fp_insts                            0                       # number of float instructions
-system.cpu1.num_int_register_reads          273178604                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes         138760228                       # number of times the integer registers were written
+system.cpu1.num_int_register_reads          272266493                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes         138281277                       # number of times the integer registers were written
 system.cpu1.num_fp_register_reads                   0                       # number of times the floating registers were read
 system.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                     14426742                       # number of memory refs
-system.cpu1.num_load_insts                    9181010                       # Number of load instructions
-system.cpu1.num_store_insts                   5245732                       # Number of store instructions
-system.cpu1.num_idle_cycles              10273661233.326063                       # Number of idle cycles
-system.cpu1.num_busy_cycles              335718137.673937                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.031644                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.968356                       # Percentage of idle cycles
+system.cpu1.num_mem_refs                     14383510                       # number of memory refs
+system.cpu1.num_load_insts                    9129721                       # Number of load instructions
+system.cpu1.num_store_insts                   5253789                       # Number of store instructions
+system.cpu1.num_idle_cycles              10274260882.632458                       # Number of idle cycles
+system.cpu1.num_busy_cycles              333923625.367543                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.031478                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.968522                       # Percentage of idle cycles
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
 
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini
index 201ee02a7..0e8616cf5 100644
--- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini
@@ -181,7 +181,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
@@ -213,7 +213,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout
index 4b4f6933d..282b60660 100755
--- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:05:18
-gem5 started Jun 28 2012 22:10:24
+gem5 compiled Jul  2 2012 08:30:56
+gem5 started Jul  2 2012 09:09:56
 gem5 executing on zizzer
 command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing
 Global frequency set at 1000000000000 ticks per second
@@ -39,4 +39,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 271948359500 because target called exit()
+Exiting @ tick 274137499500 because target called exit()
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt
index c0f2578f2..5b9902e79 100644
--- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.271948                       # Number of seconds simulated
-sim_ticks                                271948359500                       # Number of ticks simulated
-final_tick                               271948359500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.274137                       # Number of seconds simulated
+sim_ticks                                274137499500                       # Number of ticks simulated
+final_tick                               274137499500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 167086                       # Simulator instruction rate (inst/s)
-host_op_rate                                   167086                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               75497413                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 219024                       # Number of bytes of host memory used
-host_seconds                                  3602.09                       # Real time elapsed on the host
+host_inst_rate                                 167497                       # Simulator instruction rate (inst/s)
+host_op_rate                                   167497                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               76292716                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 218988                       # Number of bytes of host memory used
+host_seconds                                  3593.23                       # Real time elapsed on the host
 sim_insts                                   601856964                       # Number of instructions simulated
 sim_ops                                     601856964                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             53824                       # Number of bytes read from this memory
@@ -23,37 +23,37 @@ system.physmem.num_reads::cpu.data              25316                       # Nu
 system.physmem.num_reads::total                 26157                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks             891                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                  891                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               197920                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              5957837                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 6155757                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          197920                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             197920                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks            209687                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                 209687                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks            209687                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              197920                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             5957837                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6365444                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               196339                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              5910260                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 6106600                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          196339                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             196339                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks            208012                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                 208012                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks            208012                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              196339                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             5910260                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                6314612                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    114517207                       # DTB read hits
+system.cpu.dtb.read_hits                    114518785                       # DTB read hits
 system.cpu.dtb.read_misses                       2631                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                114519838                       # DTB read accesses
-system.cpu.dtb.write_hits                    39661898                       # DTB write hits
+system.cpu.dtb.read_accesses                114521416                       # DTB read accesses
+system.cpu.dtb.write_hits                    39662429                       # DTB write hits
 system.cpu.dtb.write_misses                      2302                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                39664200                       # DTB write accesses
-system.cpu.dtb.data_hits                    154179105                       # DTB hits
+system.cpu.dtb.write_accesses                39664731                       # DTB write accesses
+system.cpu.dtb.data_hits                    154181214                       # DTB hits
 system.cpu.dtb.data_misses                       4933                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                154184038                       # DTB accesses
-system.cpu.itb.fetch_hits                    25013413                       # ITB hits
+system.cpu.dtb.data_accesses                154186147                       # DTB accesses
+system.cpu.itb.fetch_hits                    25086764                       # ITB hits
 system.cpu.itb.fetch_misses                        22                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                25013435                       # ITB accesses
+system.cpu.itb.fetch_accesses                25086786                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -67,42 +67,42 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   17                       # Number of system calls
-system.cpu.numCycles                        543896720                       # number of cpu cycles simulated
+system.cpu.numCycles                        548275000                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.branch_predictor.lookups          86316674                       # Number of BP lookups
-system.cpu.branch_predictor.condPredicted     81371545                       # Number of conditional branches predicted
-system.cpu.branch_predictor.condIncorrect     36360802                       # Number of conditional branches incorrect
-system.cpu.branch_predictor.BTBLookups       52676212                       # Number of BTB lookups
-system.cpu.branch_predictor.BTBHits          34326876                       # Number of BTB hits
+system.cpu.branch_predictor.lookups          86322538                       # Number of BP lookups
+system.cpu.branch_predictor.condPredicted     81377487                       # Number of conditional branches predicted
+system.cpu.branch_predictor.condIncorrect     36366052                       # Number of conditional branches incorrect
+system.cpu.branch_predictor.BTBLookups       52958494                       # Number of BTB lookups
+system.cpu.branch_predictor.BTBHits          34331818                       # Number of BTB hits
 system.cpu.branch_predictor.usedRAS           1197609                       # Number of times the RAS was used to get a target.
 system.cpu.branch_predictor.RASInCorrect            6                       # Number of incorrect RAS predictions.
-system.cpu.branch_predictor.BTBHitPct       65.165802                       # BTB Hit Percentage
-system.cpu.branch_predictor.predictedTaken     36904283                       # Number of Branches Predicted As Taken (True).
-system.cpu.branch_predictor.predictedNotTaken     49412391                       # Number of Branches Predicted As Not Taken (False).
-system.cpu.regfile_manager.intRegFileReads    541655345                       # Number of Reads from Int. Register File
+system.cpu.branch_predictor.BTBHitPct       64.827784                       # BTB Hit Percentage
+system.cpu.branch_predictor.predictedTaken     36908227                       # Number of Branches Predicted As Taken (True).
+system.cpu.branch_predictor.predictedNotTaken     49414311                       # Number of Branches Predicted As Not Taken (False).
+system.cpu.regfile_manager.intRegFileReads    541561070                       # Number of Reads from Int. Register File
 system.cpu.regfile_manager.intRegFileWrites    463854846                       # Number of Writes to Int. Register File
-system.cpu.regfile_manager.intRegFileAccesses   1005510191                       # Total Accesses (Read+Write) to the Int. Register File
-system.cpu.regfile_manager.floatRegFileReads          161                       # Number of Reads from FP Register File
+system.cpu.regfile_manager.intRegFileAccesses   1005415916                       # Total Accesses (Read+Write) to the Int. Register File
+system.cpu.regfile_manager.floatRegFileReads          162                       # Number of Reads from FP Register File
 system.cpu.regfile_manager.floatRegFileWrites           42                       # Number of Writes to FP Register File
-system.cpu.regfile_manager.floatRegFileAccesses          203                       # Total Accesses (Read+Write) to the FP Register File
-system.cpu.regfile_manager.regForwards      254971320                       # Number of Registers Read Through Forwarding Logic
-system.cpu.agen_unit.agens                  155049936                       # Number of Address Generations
-system.cpu.execution_unit.predictedTakenIncorrect     33767521                       # Number of Branches Incorrectly Predicted As Taken.
-system.cpu.execution_unit.predictedNotTakenIncorrect      2588294                       # Number of Branches Incorrectly Predicted As Not Taken).
-system.cpu.execution_unit.mispredicted       36355815                       # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.predicted          26192089                       # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.mispredictPct     58.124753                       # Percentage of Incorrect Branches Predicts
-system.cpu.execution_unit.executions        412333421                       # Number of Instructions Executed.
+system.cpu.regfile_manager.floatRegFileAccesses          204                       # Total Accesses (Read+Write) to the FP Register File
+system.cpu.regfile_manager.regForwards      255070177                       # Number of Registers Read Through Forwarding Logic
+system.cpu.agen_unit.agens                  155050348                       # Number of Address Generations
+system.cpu.execution_unit.predictedTakenIncorrect     33771595                       # Number of Branches Incorrectly Predicted As Taken.
+system.cpu.execution_unit.predictedNotTakenIncorrect      2589470                       # Number of Branches Incorrectly Predicted As Not Taken).
+system.cpu.execution_unit.mispredicted       36361065                       # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.predicted          26186838                       # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.mispredictPct     58.133148                       # Percentage of Incorrect Branches Predicts
+system.cpu.execution_unit.executions        412334459                       # Number of Instructions Executed.
 system.cpu.mult_div_unit.multiplies              6482                       # Number of Multipy Operations Executed
 system.cpu.mult_div_unit.divides                    0                       # Number of Divide Operations Executed
 system.cpu.contextSwitches                          1                       # Number of context switches
-system.cpu.threadCycles                     538321020                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles                     539843930                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
 system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled                          407697                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        54736228                       # Number of cycles cpu's stages were not processed
-system.cpu.runCycles                        489160492                       # Number of cycles cpu stages are processed.
-system.cpu.activity                         89.936283                       # Percentage of cycles cpu is active
+system.cpu.timesIdled                          672410                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        59138192                       # Number of cycles cpu's stages were not processed
+system.cpu.runCycles                        489136808                       # Number of cycles cpu stages are processed.
+system.cpu.activity                         89.213772                       # Percentage of cycles cpu is active
 system.cpu.comLoads                         114514042                       # Number of Load instructions committed
 system.cpu.comStores                         39451321                       # Number of Store instructions committed
 system.cpu.comBranches                       62547159                       # Number of Branches instructions committed
@@ -114,144 +114,144 @@ system.cpu.committedInsts                   601856964                       # Nu
 system.cpu.committedOps                     601856964                       # Number of Ops committed (Per-Thread)
 system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
 system.cpu.committedInsts_total             601856964                       # Number of Instructions committed (Total)
-system.cpu.cpi                               0.903698                       # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi                               0.910972                       # CPI: Cycles Per Instruction (Per-Thread)
 system.cpu.smt_cpi                                nan                       # CPI: Total SMT-CPI
-system.cpu.cpi_total                         0.903698                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.106565                       # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.cpi_total                         0.910972                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.097728                       # IPC: Instructions Per Cycle (Per-Thread)
 system.cpu.smt_ipc                                nan                       # IPC: Total SMT-IPC
-system.cpu.ipc_total                         1.106565                       # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles                205017879                       # Number of cycles 0 instructions are processed.
-system.cpu.stage0.runCycles                 338878841                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization               62.305734                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles                233023029                       # Number of cycles 0 instructions are processed.
-system.cpu.stage1.runCycles                 310873691                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization               57.156750                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles                202072445                       # Number of cycles 0 instructions are processed.
-system.cpu.stage2.runCycles                 341824275                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization               62.847276                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles                432365235                       # Number of cycles 0 instructions are processed.
-system.cpu.stage3.runCycles                 111531485                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization               20.506004                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles                196896047                       # Number of cycles 0 instructions are processed.
-system.cpu.stage4.runCycles                 347000673                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization               63.799001                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.ipc_total                         1.097728                       # IPC: Total IPC of All Threads
+system.cpu.stage0.idleCycles                209383014                       # Number of cycles 0 instructions are processed.
+system.cpu.stage0.runCycles                 338891986                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.utilization               61.810585                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles                237433241                       # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles                 310841759                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization               56.694498                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles                206489440                       # Number of cycles 0 instructions are processed.
+system.cpu.stage2.runCycles                 341785560                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage2.utilization               62.338345                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles                436702963                       # Number of cycles 0 instructions are processed.
+system.cpu.stage3.runCycles                 111572037                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage3.utilization               20.349649                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles                201266098                       # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles                 347008902                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization               63.291031                       # Percentage of cycles stage was utilized (processing insts).
 system.cpu.icache.replacements                     30                       # number of replacements
-system.cpu.icache.tagsinuse                728.555018                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 25012389                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                728.512372                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 25085741                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    855                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs               29254.256140                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs               29340.047953                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     728.555018                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.355740                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.355740                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst     25012389                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        25012389                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      25012389                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         25012389                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     25012389                       # number of overall hits
-system.cpu.icache.overall_hits::total        25012389                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         1022                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          1022                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         1022                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           1022                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         1022                       # number of overall misses
-system.cpu.icache.overall_misses::total          1022                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     56014500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     56014500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     56014500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     56014500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     56014500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     56014500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     25013411                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     25013411                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     25013411                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     25013411                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     25013411                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     25013411                       # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::cpu.inst     728.512372                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.355719                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.355719                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst     25085741                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        25085741                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      25085741                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         25085741                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     25085741                       # number of overall hits
+system.cpu.icache.overall_hits::total        25085741                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1021                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1021                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1021                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1021                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1021                       # number of overall misses
+system.cpu.icache.overall_misses::total          1021                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     57700000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     57700000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     57700000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     57700000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     57700000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     57700000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     25086762                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     25086762                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     25086762                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     25086762                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     25086762                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     25086762                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000041                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000041                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000041                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000041                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000041                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000041                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54808.708415                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 54808.708415                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 54808.708415                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 54808.708415                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 54808.708415                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 54808.708415                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56513.222331                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 56513.222331                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 56513.222331                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 56513.222331                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 56513.222331                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 56513.222331                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets        87500                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets        43500                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               3                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               2                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets 29166.666667                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets        21750                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          167                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          167                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          167                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          167                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          167                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          167                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          166                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          166                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          166                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          166                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          166                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          166                       # number of overall MSHR hits
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          855                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total          855                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst          855                       # number of demand (read+write) MSHR misses
 system.cpu.icache.demand_mshr_misses::total          855                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          855                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          855                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     45159500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     45159500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     45159500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     45159500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     45159500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     45159500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     46832500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     46832500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     46832500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     46832500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     46832500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     46832500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000034                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000034                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000034                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000034                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000034                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000034                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52818.128655                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52818.128655                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52818.128655                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 52818.128655                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52818.128655                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 52818.128655                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54774.853801                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54774.853801                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54774.853801                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 54774.853801                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54774.853801                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 54774.853801                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                 451299                       # number of replacements
-system.cpu.dcache.tagsinuse               4094.146809                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                152406141                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse               4093.836595                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                152406041                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                 455395                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                 334.668016                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              260481000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4094.146809                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.999548                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.999548                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data    114120507                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       114120507                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     38285634                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       38285634                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data     152406141                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        152406141                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    152406141                       # number of overall hits
-system.cpu.dcache.overall_hits::total       152406141                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       393535                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        393535                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1165687                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1165687                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      1559222                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1559222                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1559222                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1559222                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   5944936500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   5944936500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  18222826500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  18222826500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  24167763000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  24167763000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  24167763000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  24167763000                       # number of overall miss cycles
+system.cpu.dcache.avg_refs                 334.667796                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              294657000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4093.836595                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.999472                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.999472                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data    114120497                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       114120497                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     38285544                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       38285544                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     152406041                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        152406041                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    152406041                       # number of overall hits
+system.cpu.dcache.overall_hits::total       152406041                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       393545                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        393545                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1165777                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1165777                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      1559322                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1559322                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1559322                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1559322                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   7771987500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   7771987500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  30228669000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  30228669000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  38000656500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  38000656500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  38000656500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  38000656500                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data    114514042                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total    114514042                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     39451321                       # number of WriteReq accesses(hits+misses)
@@ -262,38 +262,38 @@ system.cpu.dcache.overall_accesses::cpu.data    153965363
 system.cpu.dcache.overall_accesses::total    153965363                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.003437                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.003437                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.029547                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.029547                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.010127                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.010127                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.010127                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.010127                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15106.500057                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 15106.500057                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15632.692567                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 15632.692567                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 15499.885841                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 15499.885841                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 15499.885841                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 15499.885841                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs     10505000                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets   2188634000                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs              2561                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets          211460                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs  4101.913315                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 10350.108768                       # average number of cycles each access was blocked
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.029550                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.029550                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.010128                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.010128                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.010128                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.010128                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19748.662796                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 19748.662796                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25930.061238                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 25930.061238                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 24369.986763                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 24369.986763                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 24369.986763                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 24369.986763                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs     28255500                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets   3255084000                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              3561                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets          211493                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  7934.709351                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 15390.977479                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       436902                       # number of writebacks
 system.cpu.dcache.writebacks::total            436902                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       192303                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       192303                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       911524                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       911524                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1103827                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1103827                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1103827                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1103827                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       192313                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       192313                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       911614                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       911614                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      1103927                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1103927                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1103927                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1103927                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data       201232                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total       201232                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data       254163                       # number of WriteReq MSHR misses
@@ -302,14 +302,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data       455395
 system.cpu.dcache.demand_mshr_misses::total       455395                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data       455395                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total       455395                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   2433186000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   2433186000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   3829787500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   3829787500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data   6262973500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total   6262973500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data   6262973500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total   6262973500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   2683978500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   2683978500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5136800000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   5136800000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   7820778500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   7820778500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data   7820778500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   7820778500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.001757                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.001757                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006442                       # mshr miss rate for WriteReq accesses
@@ -318,35 +318,35 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002958
 system.cpu.dcache.demand_mshr_miss_rate::total     0.002958                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002958                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.002958                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12091.446688                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12091.446688                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15068.233771                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15068.233771                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13752.837646                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 13752.837646                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13752.837646                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 13752.837646                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13337.732070                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13337.732070                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20210.652219                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20210.652219                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17173.615213                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 17173.615213                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17173.615213                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 17173.615213                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                   917                       # number of replacements
-system.cpu.l2cache.tagsinuse             22852.415153                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                  538842                       # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse             22837.818259                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                  538848                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                 23142                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                 23.284159                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                 23.284418                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 21652.224350                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst    719.469676                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data    480.721127                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.660773                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst     0.021956                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.014670                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.697400                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::writebacks 21635.297134                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst    719.415397                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    483.105728                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.660257                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.021955                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.014743                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.696955                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst           14                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data       197093                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total         197107                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data       197099                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         197113                       # number of ReadReq hits
 system.cpu.l2cache.Writeback_hits::writebacks       436902                       # number of Writeback hits
 system.cpu.l2cache.Writeback_hits::total       436902                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       232986                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       232986                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       232980                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       232980                       # number of ReadExReq hits
 system.cpu.l2cache.demand_hits::cpu.inst           14                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.data       430079                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::total          430093                       # number of demand (read+write) hits
@@ -364,24 +364,24 @@ system.cpu.l2cache.demand_misses::total         26157                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          841                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data        25316                       # number of overall misses
 system.cpu.l2cache.overall_misses::total        26157                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     44029000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data    214315000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    258344000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   1104963500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   1104963500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     44029000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data   1319278500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total   1363307500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     44029000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data   1319278500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total   1363307500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     45384000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data    214860500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    260244500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   1215316500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   1215316500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     45384000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   1430177000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   1475561000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     45384000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   1430177000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   1475561000                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst          855                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data       201213                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total       202068                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data       201219                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       202074                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::writebacks       436902                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::total       436902                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       254182                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       254182                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       254176                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       254176                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.inst          855                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data       455395                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::total       456250                       # number of demand (read+write) accesses
@@ -389,32 +389,32 @@ system.cpu.l2cache.overall_accesses::cpu.inst          855
 system.cpu.l2cache.overall_accesses::cpu.data       455395                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total       456250                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.983626                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.020476                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.024551                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.083389                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.083389                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.020475                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.024550                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.083391                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.083391                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.983626                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.055591                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::total     0.057330                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.983626                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.055591                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.057330                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52353.151011                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52018.203883                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 52074.984882                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52130.755803                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52130.755803                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52353.151011                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52112.438774                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52120.178155                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52353.151011                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52112.438774                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52120.178155                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs       766500                       # number of cycles access was blocked
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53964.328181                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52150.606796                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 52458.072969                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 57337.068315                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 57337.068315                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53964.328181                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56493.008374                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 56411.706235                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53964.328181                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56493.008374                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 56411.706235                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs      3459500                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs               81                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs              116                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs  9462.962963                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs 29823.275862                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
@@ -431,39 +431,39 @@ system.cpu.l2cache.demand_mshr_misses::total        26157
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          841                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data        25316                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total        26157                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     33775500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    164851000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    198626500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    849849500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    849849500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     33775500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   1014700500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   1048476000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     33775500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   1014700500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   1048476000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     35146000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    165361000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    200507000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    954428500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    954428500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     35146000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   1119789500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   1154935500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     35146000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   1119789500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   1154935500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.983626                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.020476                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.024551                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.083389                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.083389                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.020475                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.024550                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.083391                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.083391                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.983626                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.055591                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.057330                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.983626                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.055591                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.057330                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40161.117717                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40012.378641                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40037.593227                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40094.805624                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40094.805624                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40161.117717                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40081.391215                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40083.954582                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40161.117717                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40081.391215                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40083.954582                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41790.725327                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40136.165049                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40416.649869                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 45028.708247                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 45028.708247                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41790.725327                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44232.481435                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44153.974080                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41790.725327                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44232.481435                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44153.974080                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini
index 53e4b73f0..5bc85930f 100644
--- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini
@@ -479,7 +479,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
@@ -511,7 +511,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout
index 21003a7f0..ddf76222f 100755
--- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:05:18
-gem5 started Jun 28 2012 22:10:29
+gem5 compiled Jul  2 2012 08:30:56
+gem5 started Jul  2 2012 09:10:10
 gem5 executing on zizzer
 command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
@@ -39,4 +39,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 133563007500 because target called exit()
+Exiting @ tick 135504709500 because target called exit()
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
index 38226af10..9f9fc3c8f 100644
--- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,59 +1,59 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.133563                       # Number of seconds simulated
-sim_ticks                                133563007500                       # Number of ticks simulated
-final_tick                               133563007500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.135505                       # Number of seconds simulated
+sim_ticks                                135504709500                       # Number of ticks simulated
+final_tick                               135504709500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 301381                       # Simulator instruction rate (inst/s)
-host_op_rate                                   301381                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               71175252                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 220044                       # Number of bytes of host memory used
-host_seconds                                  1876.54                       # Real time elapsed on the host
+host_inst_rate                                 302966                       # Simulator instruction rate (inst/s)
+host_op_rate                                   302966                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               72589653                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 220016                       # Number of bytes of host memory used
+host_seconds                                  1866.72                       # Real time elapsed on the host
 sim_insts                                   565552443                       # Number of instructions simulated
 sim_ops                                     565552443                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst             61120                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           1627392                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              1688512                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        61120                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           61120                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks        58688                       # Number of bytes written to this memory
-system.physmem.bytes_written::total             58688                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst                955                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data              25428                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                 26383                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks             917                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                  917                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               457612                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             12184452                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                12642063                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          457612                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             457612                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks            439403                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                 439403                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks            439403                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              457612                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            12184452                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               13081466                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst             61760                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           1627200                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              1688960                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        61760                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           61760                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks        58880                       # Number of bytes written to this memory
+system.physmem.bytes_written::total             58880                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst                965                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data              25425                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                 26390                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks             920                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                  920                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               455778                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             12008439                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                12464216                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          455778                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             455778                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks            434524                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                 434524                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks            434524                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              455778                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            12008439                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               12898740                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    123849413                       # DTB read hits
-system.cpu.dtb.read_misses                      20691                       # DTB read misses
+system.cpu.dtb.read_hits                    123973202                       # DTB read hits
+system.cpu.dtb.read_misses                      28801                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                123870104                       # DTB read accesses
-system.cpu.dtb.write_hits                    40835064                       # DTB write hits
-system.cpu.dtb.write_misses                     30091                       # DTB write misses
+system.cpu.dtb.read_accesses                124002003                       # DTB read accesses
+system.cpu.dtb.write_hits                    40826098                       # DTB write hits
+system.cpu.dtb.write_misses                     43038                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                40865155                       # DTB write accesses
-system.cpu.dtb.data_hits                    164684477                       # DTB hits
-system.cpu.dtb.data_misses                      50782                       # DTB misses
+system.cpu.dtb.write_accesses                40869136                       # DTB write accesses
+system.cpu.dtb.data_hits                    164799300                       # DTB hits
+system.cpu.dtb.data_misses                      71839                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                164735259                       # DTB accesses
-system.cpu.itb.fetch_hits                    66492910                       # ITB hits
-system.cpu.itb.fetch_misses                        38                       # ITB misses
+system.cpu.dtb.data_accesses                164871139                       # DTB accesses
+system.cpu.itb.fetch_hits                    66654125                       # ITB hits
+system.cpu.itb.fetch_misses                        39                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                66492948                       # ITB accesses
+system.cpu.itb.fetch_accesses                66654164                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -67,247 +67,247 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   17                       # Number of system calls
-system.cpu.numCycles                        267126016                       # number of cpu cycles simulated
+system.cpu.numCycles                        271009420                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                 78502606                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted           72859176                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect            3048930                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups              42879233                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                 41644328                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                 78550084                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           72909802                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect            3049618                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              42960098                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                 41697412                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                  1629564                       # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect                 215                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles           68435581                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      710898129                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    78502606                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           43273892                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     119207604                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                12936161                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles               69569484                       # Number of cycles fetch has spent blocked
+system.cpu.BPredUnit.usedRAS                  1627945                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect                 225                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles           68633140                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      712310900                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    78550084                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           43325357                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     119402153                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                13096957                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               72942972                       # Number of cycles fetch has spent blocked
 system.cpu.fetch.MiscStallCycles                   29                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles           914                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                  66492910                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                942940                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          267090859                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.661634                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.464377                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.PendingTrapStallCycles          1077                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                  66654125                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                952316                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          270973447                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.628711                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.455670                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                147883255     55.37%     55.37% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 10367188      3.88%     59.25% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 11844651      4.43%     63.68% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 10612793      3.97%     67.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  6990815      2.62%     70.28% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  2667876      1.00%     71.27% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  3494727      1.31%     72.58% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  3104174      1.16%     73.74% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 70125380     26.26%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                151571294     55.94%     55.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 10370513      3.83%     59.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 11843929      4.37%     64.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 10611726      3.92%     68.05% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  6997698      2.58%     70.63% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  2669321      0.99%     71.62% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  3542857      1.31%     72.92% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  3106060      1.15%     74.07% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 70260049     25.93%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            267090859                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.293879                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.661284                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 85625908                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              53897418                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 104721883                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              12969411                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                9876239                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              3910148                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                  1104                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              702131172                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                  4692                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                9876239                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 93864195                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                11132886                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           1433                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 104174566                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              48041540                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              690226135                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                    13                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents               36911224                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               4900299                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands           527321421                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             906904042                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        906901104                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups              2938                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            270973447                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.289843                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.628362                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 86239898                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              56889648                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 104078394                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              13772489                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                9993018                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              3907857                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                  1149                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              703284399                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                  4152                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                9993018                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 94515684                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                12291800                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           1567                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 104313558                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              49857820                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              691204157                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                  5604                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               37465189                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               6251536                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands           527653035                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             907560525                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        907557502                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups              3023                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             463854889                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 63466532                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                108                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            116                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 106984731                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            129019631                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            42434130                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          14712304                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          9648397                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  626510721                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                  98                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 608418192                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            334492                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        60261200                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     33473416                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             81                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     267090859                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.277945                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.835634                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                 63798146                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                 98                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            109                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 110554649                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            129201281                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            42494660                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          14706454                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          9724071                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  626942555                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                  88                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 608726605                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            349964                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        60693556                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     33842727                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             71                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     270973447                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.246444                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.833475                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            52595450     19.69%     19.69% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            54748440     20.50%     40.19% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            53400082     19.99%     60.18% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            36696955     13.74%     73.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            30804090     11.53%     85.46% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            24162728      9.05%     94.50% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            10693904      4.00%     98.51% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             3328381      1.25%     99.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              660829      0.25%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            55588929     20.51%     20.51% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            55068872     20.32%     40.84% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            54063102     19.95%     60.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            36829632     13.59%     74.38% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            31174989     11.50%     85.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            23761374      8.77%     94.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            10484912      3.87%     98.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             3386761      1.25%     99.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              614876      0.23%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       267090859                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       270973447                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 2950080     75.40%     75.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                     39      0.00%     75.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     75.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     75.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     75.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     75.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     75.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     75.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     75.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     75.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     75.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     75.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     75.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     75.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     75.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     75.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     75.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     75.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     75.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     75.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     75.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     75.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     75.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     75.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     75.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     75.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     75.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     75.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     75.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                 582636     14.89%     90.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                379789      9.71%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 2718607     75.19%     75.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                     33      0.00%     75.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     75.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     75.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     75.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     75.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     75.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     75.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     75.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     75.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     75.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     75.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     75.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     75.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     75.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     75.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     75.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     75.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     75.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     75.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     75.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     75.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     75.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     75.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     75.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     75.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     75.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     75.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     75.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 573635     15.86%     91.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                323505      8.95%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             441018930     72.49%     72.49% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                 7345      0.00%     72.49% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     72.49% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                  27      0.00%     72.49% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   5      0.00%     72.49% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   5      0.00%     72.49% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  4      0.00%     72.49% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     72.49% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     72.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     72.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     72.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     72.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     72.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     72.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     72.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     72.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     72.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     72.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     72.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     72.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     72.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     72.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     72.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     72.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     72.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     72.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     72.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     72.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     72.49% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            126131577     20.73%     93.22% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            41260299      6.78%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             441168683     72.47%     72.47% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                 7348      0.00%     72.48% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     72.48% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                  30      0.00%     72.48% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   5      0.00%     72.48% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   5      0.00%     72.48% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  4      0.00%     72.48% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     72.48% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     72.48% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     72.48% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     72.48% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     72.48% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     72.48% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     72.48% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     72.48% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     72.48% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     72.48% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     72.48% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     72.48% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     72.48% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     72.48% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     72.48% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     72.48% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     72.48% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     72.48% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     72.48% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     72.48% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     72.48% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     72.48% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            126287390     20.75%     93.22% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            41263140      6.78%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              608418192                       # Type of FU issued
-system.cpu.iq.rate                           2.277645                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     3912544                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.006431                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         1488170355                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         686774500                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    598832188                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                3924                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes               2359                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses         1719                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              612328769                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                    1967                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         12182137                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              608726605                       # Type of FU issued
+system.cpu.iq.rate                           2.246146                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     3615780                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.005940                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         1492388483                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         687638825                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    598965859                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                3918                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes               2476                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses         1713                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              612340430                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                    1955                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         12180256                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     14505589                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        34191                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation         4885                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      2982809                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     14687239                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        33196                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation         5150                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      3043339                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads         6785                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked         71183                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads         6743                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        162277                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                9876239                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                  295412                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                 42917                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           670453714                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts           1691855                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             129019631                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             42434130                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                 98                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                    899                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                  7278                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents           4885                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        1348504                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      2206028                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              3554532                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             602596052                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             123870207                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           5822140                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                9993018                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                  593522                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                 81920                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           671227772                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           1733098                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             129201281                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             42494660                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                 88                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                   9721                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                   904                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents           5150                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        1349008                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      2205914                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              3554922                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             602873827                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             124002105                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           5852778                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                      43942895                       # number of nop insts executed
-system.cpu.iew.exec_refs                    164752686                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 67005259                       # Number of branches executed
-system.cpu.iew.exec_stores                   40882479                       # Number of stores executed
-system.cpu.iew.exec_rate                     2.255849                       # Inst execution rate
-system.cpu.iew.wb_sent                      600080079                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     598833907                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 417539542                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 531416482                       # num instructions consuming a value
+system.cpu.iew.exec_nop                      44285129                       # number of nop insts executed
+system.cpu.iew.exec_refs                    164888589                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 67046898                       # Number of branches executed
+system.cpu.iew.exec_stores                   40886484                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.224549                       # Inst execution rate
+system.cpu.iew.wb_sent                      600233130                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     598967572                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 417280903                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 532263406                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       2.241766                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.785711                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       2.210136                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.783974                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts      601856963                       # The number of committed instructions
 system.cpu.commit.commitCommittedOps        601856963                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts        68437583                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts        69254422                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              17                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           3047922                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    257214620                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.339902                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.706449                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           3048560                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    260980429                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.306138                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.692981                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     78375558     30.47%     30.47% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     72865724     28.33%     58.80% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     26619590     10.35%     69.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      8074736      3.14%     72.29% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     10311668      4.01%     76.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     20443429      7.95%     84.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      6319286      2.46%     86.70% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      3488714      1.36%     88.06% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     30715915     11.94%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     82002311     31.42%     31.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     72802901     27.90%     59.32% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     26180796     10.03%     69.35% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      8233037      3.15%     72.50% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     10839669      4.15%     76.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     20863917      7.99%     84.65% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      6243794      2.39%     87.04% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      3659698      1.40%     88.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     30154306     11.55%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    257214620                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    260980429                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            601856963                       # Number of instructions committed
 system.cpu.commit.committedOps              601856963                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -318,70 +318,70 @@ system.cpu.commit.branches                   62547159                       # Nu
 system.cpu.commit.fp_insts                       1520                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                 563954763                       # Number of committed integer instructions.
 system.cpu.commit.function_calls              1197610                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events              30715915                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events              30154306                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    896728862                       # The number of ROB reads
-system.cpu.rob.rob_writes                  1350487768                       # The number of ROB writes
-system.cpu.timesIdled                             758                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           35157                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                    901873119                       # The number of ROB reads
+system.cpu.rob.rob_writes                  1352238413                       # The number of ROB writes
+system.cpu.timesIdled                             924                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           35973                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   565552443                       # Number of Instructions Simulated
 system.cpu.committedOps                     565552443                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total             565552443                       # Number of Instructions Simulated
-system.cpu.cpi                               0.472328                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.472328                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               2.117175                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         2.117175                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                848664377                       # number of integer regfile reads
-system.cpu.int_regfile_writes               492741272                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                       384                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                       47                       # number of floating regfile writes
+system.cpu.cpi                               0.479194                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.479194                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               2.086837                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         2.086837                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                848955638                       # number of integer regfile reads
+system.cpu.int_regfile_writes               492807399                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                       373                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                       51                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                       1                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.icache.replacements                     44                       # number of replacements
-system.cpu.icache.tagsinuse                827.496665                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 66491540                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                    975                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs               68196.451282                       # Average number of references to valid blocks.
+system.cpu.icache.replacements                     45                       # number of replacements
+system.cpu.icache.tagsinuse                834.184340                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 66652701                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    988                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               67462.247976                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     827.496665                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.404051                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.404051                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst     66491540                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        66491540                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      66491540                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         66491540                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     66491540                       # number of overall hits
-system.cpu.icache.overall_hits::total        66491540                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         1370                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          1370                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         1370                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           1370                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         1370                       # number of overall misses
-system.cpu.icache.overall_misses::total          1370                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     47830500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     47830500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     47830500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     47830500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     47830500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     47830500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     66492910                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     66492910                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     66492910                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     66492910                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     66492910                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     66492910                       # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::cpu.inst     834.184340                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.407317                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.407317                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst     66652701                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        66652701                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      66652701                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         66652701                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     66652701                       # number of overall hits
+system.cpu.icache.overall_hits::total        66652701                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1424                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1424                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1424                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1424                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1424                       # number of overall misses
+system.cpu.icache.overall_misses::total          1424                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     52187000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     52187000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     52187000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     52187000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     52187000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     52187000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     66654125                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     66654125                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     66654125                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     66654125                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     66654125                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     66654125                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000021                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000021                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000021                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000021                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000021                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000021                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34912.773723                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 34912.773723                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 34912.773723                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 34912.773723                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 34912.773723                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 34912.773723                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36648.174157                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 36648.174157                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 36648.174157                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 36648.174157                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 36648.174157                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 36648.174157                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -390,296 +390,296 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          395                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          395                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          395                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          395                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          395                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          395                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          975                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          975                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          975                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          975                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          975                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          975                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     34096000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     34096000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     34096000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     34096000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     34096000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     34096000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          436                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          436                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          436                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          436                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          436                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          436                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          988                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          988                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          988                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          988                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          988                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          988                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     37189000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     37189000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     37189000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     37189000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     37189000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     37189000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000015                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000015                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000015                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000015                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000015                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000015                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34970.256410                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34970.256410                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34970.256410                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 34970.256410                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34970.256410                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 34970.256410                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37640.688259                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37640.688259                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37640.688259                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 37640.688259                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37640.688259                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 37640.688259                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                 460470                       # number of replacements
-system.cpu.dcache.tagsinuse               4093.773805                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                149240040                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                 464566                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                 321.246152                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              124982000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4093.773805                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.999456                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.999456                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data    111034129                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       111034129                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     38205852                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       38205852                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data           59                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total           59                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data     149239981                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        149239981                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    149239981                       # number of overall hits
-system.cpu.dcache.overall_hits::total       149239981                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       620415                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        620415                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1245469                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1245469                       # number of WriteReq misses
+system.cpu.dcache.replacements                 460628                       # number of replacements
+system.cpu.dcache.tagsinuse               4093.382195                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                148766128                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 464724                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 320.117162                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              141133000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4093.382195                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.999361                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.999361                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data    111085210                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       111085210                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     37680869                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       37680869                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data           49                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total           49                       # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits::cpu.data     148766079                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        148766079                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    148766079                       # number of overall hits
+system.cpu.dcache.overall_hits::total       148766079                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       577881                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        577881                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1770452                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1770452                       # number of WriteReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            2                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            2                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      1865884                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1865884                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1865884                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1865884                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   4714177500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   4714177500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  12635422233                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  12635422233                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data         7000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total         7000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  17349599733                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  17349599733                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  17349599733                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  17349599733                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    111654544                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    111654544                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data      2348333                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2348333                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2348333                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2348333                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   8220967500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   8220967500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  45275400067                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  45275400067                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        31000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total        31000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  53496367567                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  53496367567                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  53496367567                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  53496367567                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    111663091                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    111663091                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     39451321                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     39451321                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data           61                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total           61                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    151105865                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    151105865                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    151105865                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    151105865                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.005557                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.005557                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.031570                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.031570                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.032787                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.032787                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.012348                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.012348                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.012348                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.012348                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data  7598.426054                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total  7598.426054                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10145.111788                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 10145.111788                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data         3500                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total         3500                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data  9298.327084                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total  9298.327084                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data  9298.327084                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total  9298.327084                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs       113496                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets       187500                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                23                       # number of cycles access was blocked
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data           51                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total           51                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    151114412                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    151114412                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    151114412                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    151114412                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.005175                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.005175                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.044877                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.044877                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.039216                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.039216                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.015540                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.015540                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.015540                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.015540                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14226.056057                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14226.056057                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25572.791619                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 25572.791619                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        15500                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        15500                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 22780.571396                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 22780.571396                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 22780.571396                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 22780.571396                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       267496                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets       204500                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               117                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets              10                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs  4934.608696                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets        18750                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  2286.290598                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets        20450                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       444730                       # number of writebacks
-system.cpu.dcache.writebacks::total            444730                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       410277                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       410277                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       991041                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       991041                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks       444923                       # number of writebacks
+system.cpu.dcache.writebacks::total            444923                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       367661                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       367661                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1515948                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      1515948                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            2                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total            2                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1401318                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1401318                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1401318                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1401318                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       210138                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       210138                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       254428                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       254428                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       464566                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       464566                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       464566                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       464566                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    739150000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total    739150000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1881373462                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   1881373462                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data   2620523462                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total   2620523462                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data   2620523462                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total   2620523462                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.001882                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.001882                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006449                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006449                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.003074                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.003074                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.003074                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.003074                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  3517.450437                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  3517.450437                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  7394.522073                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  7394.522073                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  5640.799073                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total  5640.799073                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  5640.799073                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total  5640.799073                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_hits::cpu.data      1883609                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1883609                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1883609                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1883609                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       210220                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       210220                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       254504                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       254504                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       464724                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       464724                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       464724                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       464724                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   1663922500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   1663922500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5123963342                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   5123963342                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   6787885842                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   6787885842                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data   6787885842                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   6787885842                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.001883                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.001883                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006451                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006451                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.003075                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.003075                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.003075                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.003075                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  7915.148416                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  7915.148416                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20133.134811                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20133.134811                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14606.273491                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 14606.273491                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14606.273491                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 14606.273491                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.replacements                   947                       # number of replacements
-system.cpu.l2cache.tagsinuse             22959.894157                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                  555227                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                 23376                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                 23.752011                       # Average number of references to valid blocks.
+system.cpu.l2cache.replacements                   949                       # number of replacements
+system.cpu.l2cache.tagsinuse             22947.355822                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                  555465                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                 23383                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                 23.755078                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 21522.130893                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst    820.682242                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data    617.081022                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.656803                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst     0.025045                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.018832                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.700680                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst           20                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data       205851                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total         205871                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       444730                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       444730                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       233287                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       233287                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst           20                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       439138                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          439158                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst           20                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       439138                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         439158                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          955                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data         4287                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         5242                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data        21141                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total        21141                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          955                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data        25428                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total         26383                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          955                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data        25428                       # number of overall misses
-system.cpu.l2cache.overall_misses::total        26383                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     32795000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data    146960500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    179755500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    733664500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    733664500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     32795000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    880625000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    913420000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     32795000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    880625000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    913420000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          975                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data       210138                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total       211113                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       444730                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       444730                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       254428                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       254428                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          975                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       464566                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       465541                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          975                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       464566                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       465541                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.979487                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.020401                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.024830                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.083092                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.083092                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.979487                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.054735                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.056672                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.979487                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.054735                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.056672                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34340.314136                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34280.499184                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 34291.396414                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34703.396244                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34703.396244                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34340.314136                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34632.098474                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 34621.536596                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34340.314136                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34632.098474                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 34621.536596                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs        45500                       # number of cycles access was blocked
+system.cpu.l2cache.occ_blocks::writebacks 21503.111139                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst    828.347740                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    615.896944                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.656223                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.025279                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.018796                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.700298                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst           23                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data       205921                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         205944                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       444923                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       444923                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       233378                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       233378                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst           23                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       439299                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          439322                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst           23                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       439299                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         439322                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          965                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data         4295                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total         5260                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data        21130                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total        21130                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          965                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data        25425                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total         26390                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          965                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data        25425                       # number of overall misses
+system.cpu.l2cache.overall_misses::total        26390                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     34622500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data    149004000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    183626500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    818980496                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    818980496                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     34622500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    967984496                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   1002606996                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     34622500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    967984496                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   1002606996                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          988                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data       210216                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       211204                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       444923                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       444923                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       254508                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       254508                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          988                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       464724                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       465712                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          988                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       464724                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       465712                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.976721                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.020431                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.024905                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.083023                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.083023                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.976721                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.054710                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.056666                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.976721                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.054710                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.056666                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35878.238342                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34692.433062                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 34909.980989                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 38759.133743                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 38759.133743                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35878.238342                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 38072.153235                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 37991.928609                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35878.238342                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 38072.153235                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 37991.928609                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs        81496                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs                7                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                8                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs         6500                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs        10187                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks          917                       # number of writebacks
-system.cpu.l2cache.writebacks::total              917                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          955                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data         4287                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         5242                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        21141                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total        21141                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          955                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data        25428                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total        26383                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          955                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data        25428                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total        26383                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     29726000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    133026000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    162752000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    668424000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    668424000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     29726000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    801450000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    831176000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     29726000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    801450000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    831176000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.979487                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.020401                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.024830                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.083092                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.083092                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.979487                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.054735                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.056672                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.979487                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.054735                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.056672                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31126.701571                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31030.090973                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31047.691721                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31617.425855                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31617.425855                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31126.701571                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31518.404908                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31504.226206                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31126.701571                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31518.404908                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31504.226206                       # average overall mshr miss latency
+system.cpu.l2cache.writebacks::writebacks          920                       # number of writebacks
+system.cpu.l2cache.writebacks::total              920                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          965                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data         4295                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         5260                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        21130                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        21130                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          965                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data        25425                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        26390                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          965                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data        25425                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total        26390                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     31552000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    135966500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    167518500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    754186996                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    754186996                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     31552000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    890153496                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    921705496                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     31552000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    890153496                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    921705496                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.976721                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.020431                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.024905                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.083023                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.083023                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.976721                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.054710                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.056666                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.976721                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.054710                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.056666                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32696.373057                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31656.926659                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31847.623574                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35692.711595                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35692.711595                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32696.373057                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35010.953628                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34926.316635                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32696.373057                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35010.953628                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34926.316635                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini
index 265a2a956..a9c226ca1 100644
--- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini
@@ -148,7 +148,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
@@ -180,7 +180,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout
index be37b32c1..fcee711f2 100755
--- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:05:18
-gem5 started Jun 28 2012 22:10:37
+gem5 compiled Jul  2 2012 08:30:56
+gem5 started Jul  2 2012 09:11:02
 gem5 executing on zizzer
 command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
@@ -39,4 +39,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 762853846000 because target called exit()
+Exiting @ tick 764109115000 because target called exit()
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
index a7b4a0a92..6b056dd7e 100644
--- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.762854                       # Number of seconds simulated
-sim_ticks                                762853846000                       # Number of ticks simulated
-final_tick                               762853846000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.764109                       # Number of seconds simulated
+sim_ticks                                764109115000                       # Number of ticks simulated
+final_tick                               764109115000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2331221                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2331221                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2954822927                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 219024                       # Number of bytes of host memory used
-host_seconds                                   258.17                       # Real time elapsed on the host
+host_inst_rate                                2465110                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2465110                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             3129668646                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 218984                       # Number of bytes of host memory used
+host_seconds                                   244.15                       # Real time elapsed on the host
 sim_insts                                   601856964                       # Number of instructions simulated
 sim_ops                                     601856964                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             50112                       # Number of bytes read from this memory
@@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data              25315                       # Nu
 system.physmem.num_reads::total                 26098                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks             883                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                  883                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                65690                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              2123814                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2189505                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           65690                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              65690                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks             74080                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                  74080                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks             74080                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               65690                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             2123814                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2263584                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst                65582                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              2120325                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2185908                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           65582                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              65582                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks             73958                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                  73958                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks             73958                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               65582                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             2120325                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2259866                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -67,7 +67,7 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   17                       # Number of system calls
-system.cpu.numCycles                       1525707692                       # number of cpu cycles simulated
+system.cpu.numCycles                       1528218230                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   601856964                       # Number of instructions committed
@@ -86,18 +86,18 @@ system.cpu.num_mem_refs                     153970296                       # nu
 system.cpu.num_load_insts                   114516673                       # Number of load instructions
 system.cpu.num_store_insts                   39453623                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                 1525707692                       # Number of busy cycles
+system.cpu.num_busy_cycles                 1528218230                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                     24                       # number of replacements
-system.cpu.icache.tagsinuse                673.359193                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                673.286058                       # Cycle average of tags in use
 system.cpu.icache.total_refs                601861103                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    795                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               757057.991195                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     673.359193                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.328789                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.328789                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst     673.286058                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.328753                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.328753                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst    601861103                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total       601861103                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst     601861103                       # number of demand (read+write) hits
@@ -110,12 +110,12 @@ system.cpu.icache.demand_misses::cpu.inst          795                       # n
 system.cpu.icache.demand_misses::total            795                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          795                       # number of overall misses
 system.cpu.icache.overall_misses::total           795                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     44016000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     44016000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     44016000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     44016000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     44016000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     44016000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     44165000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     44165000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     44165000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     44165000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     44165000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     44165000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst    601861898                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total    601861898                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst    601861898                       # number of demand (read+write) accesses
@@ -128,12 +128,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000001
 system.cpu.icache.demand_miss_rate::total     0.000001                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000001                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000001                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55366.037736                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 55366.037736                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 55366.037736                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 55366.037736                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 55366.037736                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 55366.037736                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55553.459119                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 55553.459119                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 55553.459119                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 55553.459119                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 55553.459119                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 55553.459119                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -148,34 +148,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          795
 system.cpu.icache.demand_mshr_misses::total          795                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          795                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          795                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     41631000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     41631000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     41631000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     41631000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     41631000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     41631000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     41780000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     41780000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     41780000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     41780000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     41780000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     41780000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000001                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000001                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000001                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000001                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000001                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000001                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52366.037736                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52366.037736                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52366.037736                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 52366.037736                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52366.037736                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 52366.037736                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52553.459119                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52553.459119                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52553.459119                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 52553.459119                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52553.459119                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 52553.459119                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                 451299                       # number of replacements
-system.cpu.dcache.tagsinuse               4094.177385                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               4094.128141                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                153509968                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                 455395                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                 337.091905                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              571210000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4094.177385                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.999555                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.999555                       # Average percentage of cache occupancy
+system.cpu.dcache.warmup_cycle              590218000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4094.128141                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.999543                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.999543                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data    114312810                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total       114312810                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     39197158                       # number of WriteReq hits
@@ -192,14 +192,14 @@ system.cpu.dcache.demand_misses::cpu.data       455395                       # n
 system.cpu.dcache.demand_misses::total         455395                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data       455395                       # number of overall misses
 system.cpu.dcache.overall_misses::total        455395                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   2990372000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   2990372000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   4448388000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   4448388000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data   7438760000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total   7438760000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data   7438760000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total   7438760000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   2991812000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   2991812000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   4452609000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   4452609000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data   7444421000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total   7444421000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data   7444421000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total   7444421000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data    114514042                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total    114514042                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     39451321                       # number of WriteReq accesses(hits+misses)
@@ -216,14 +216,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.002958
 system.cpu.dcache.demand_miss_rate::total     0.002958                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.002958                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.002958                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14860.320426                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14860.320426                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17502.106916                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 17502.106916                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 16334.742367                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 16334.742367                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 16334.742367                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 16334.742367                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14867.476346                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14867.476346                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17518.714368                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 17518.714368                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 16347.173333                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 16347.173333                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 16347.173333                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 16347.173333                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -242,14 +242,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data       455395
 system.cpu.dcache.demand_mshr_misses::total       455395                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data       455395                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total       455395                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   2386676000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   2386676000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   3685899000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   3685899000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data   6072575000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total   6072575000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data   6072575000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total   6072575000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   2388116000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   2388116000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   3690120000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   3690120000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   6078236000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   6078236000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data   6078236000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   6078236000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.001757                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.001757                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006442                       # mshr miss rate for WriteReq accesses
@@ -258,28 +258,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002958
 system.cpu.dcache.demand_mshr_miss_rate::total     0.002958                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002958                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.002958                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11860.320426                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11860.320426                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14502.106916                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14502.106916                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13334.742367                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 13334.742367                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13334.742367                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 13334.742367                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11867.476346                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11867.476346                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14518.714368                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14518.714368                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13347.173333                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 13347.173333                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13347.173333                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 13347.173333                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                   903                       # number of replacements
-system.cpu.l2cache.tagsinuse             22842.001450                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse             22839.375690                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                  538870                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                 23085                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                 23.342863                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 21648.658638                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst    668.310399                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data    525.032413                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.660665                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst     0.020395                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.016023                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.697083                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::writebacks 21645.673483                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst    668.235332                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    525.466875                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.660574                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.020393                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.016036                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.697002                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst           12                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data       197110                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total         197122                       # number of ReadReq hits
diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini
index d26a36061..3e3a921c2 100644
--- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini
@@ -497,7 +497,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
@@ -529,7 +529,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout
index 2a1e3a459..71d01f629 100755
--- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:10:14
-gem5 started Jun 29 2012 00:37:13
+gem5 compiled Jul  2 2012 09:08:16
+gem5 started Jul  2 2012 15:22:13
 gem5 executing on zizzer
 command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
@@ -38,4 +38,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 163291004000 because target called exit()
+Exiting @ tick 164812294500 because target called exit()
diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt
index 4e7834f0d..ad067cb13 100644
--- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt
@@ -1,39 +1,39 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.163291                       # Number of seconds simulated
-sim_ticks                                163291004000                       # Number of ticks simulated
-final_tick                               163291004000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.164812                       # Number of seconds simulated
+sim_ticks                                164812294500                       # Number of ticks simulated
+final_tick                               164812294500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 225808                       # Simulator instruction rate (inst/s)
-host_op_rate                                   238605                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               64682367                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 234804                       # Number of bytes of host memory used
-host_seconds                                  2524.51                       # Real time elapsed on the host
-sim_insts                                   570052735                       # Number of instructions simulated
-sim_ops                                     602360941                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst             47872                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           1770240                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              1818112                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        47872                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           47872                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks       203264                       # Number of bytes written to this memory
-system.physmem.bytes_written::total            203264                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst                748                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data              27660                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                 28408                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks            3176                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                 3176                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               293170                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             10841014                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                11134183                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          293170                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             293170                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1244796                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1244796                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1244796                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              293170                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            10841014                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               12378980                       # Total bandwidth to/from this memory (bytes/s)
+host_inst_rate                                 186522                       # Simulator instruction rate (inst/s)
+host_op_rate                                   197094                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               53926880                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 234728                       # Number of bytes of host memory used
+host_seconds                                  3056.22                       # Real time elapsed on the host
+sim_insts                                   570052720                       # Number of instructions simulated
+sim_ops                                     602360926                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst             48192                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           1770688                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              1818880                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        48192                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           48192                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks       203712                       # Number of bytes written to this memory
+system.physmem.bytes_written::total            203712                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst                753                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data              27667                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                 28420                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks            3183                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                 3183                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               292405                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             10743665                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                11036070                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          292405                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             292405                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1236024                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1236024                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1236024                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              292405                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            10743665                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               12272094                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -77,141 +77,141 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                   48                       # Number of system calls
-system.cpu.numCycles                        326582009                       # number of cpu cycles simulated
+system.cpu.numCycles                        329624590                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                 85496783                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted           80297868                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect            2361759                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups              47129611                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                 46810915                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                 85521151                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           80320824                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect            2362426                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              47149352                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                 46837857                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                  1442822                       # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect                 939                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles           68930661                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      669745010                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    85496783                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           48253737                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     130048027                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                13475244                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles              116341672                       # Number of cycles fetch has spent blocked
+system.cpu.BPredUnit.usedRAS                  1443093                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect                 967                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles           68941793                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      669884423                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    85521151                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           48280950                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     130081078                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                13500418                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles              119459363                       # Number of cycles fetch has spent blocked
 system.cpu.fetch.MiscStallCycles                    2                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles           687                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                  67499108                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                807540                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          326356874                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.186850                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.203825                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.PendingTrapStallCycles           639                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                  67507706                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                807322                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          329533342                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.166395                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.195647                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                196309073     60.15%     60.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 20957347      6.42%     66.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  4946491      1.52%     68.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 14317000      4.39%     72.48% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  8978746      2.75%     75.23% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  9407391      2.88%     78.11% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  4385745      1.34%     79.45% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  5814869      1.78%     81.24% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 61240212     18.76%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                199452502     60.53%     60.53% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 20948711      6.36%     66.88% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  4950582      1.50%     68.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 14318865      4.35%     72.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  8979173      2.72%     75.46% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  9434613      2.86%     78.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  4385548      1.33%     79.65% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  5816824      1.77%     81.41% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 61246524     18.59%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            326356874                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.261793                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.050771                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 93064197                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              93574356                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 108736934                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              19947205                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               11034182                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              4784985                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                  1738                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              706036905                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                  6288                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles               11034182                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                107346412                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                13092326                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          46822                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 114338400                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              80498732                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              697255622                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                   101                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents               59224108                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents              19051405                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents              625                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           723858007                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            3241539667                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       3241539539                       # Number of integer rename lookups
+system.cpu.fetch.rateDist::total            329533342                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.259450                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.032265                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 93614628                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              96158900                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 108189069                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              20521940                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               11048805                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              4786965                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                  1741                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              706200361                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                  6232                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               11048805                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                107837275                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                14152380                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          49672                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 114426981                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              82018229                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              697376779                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                   154                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               59681814                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents              20119568                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents              658                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           723981883                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            3242139777                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       3242139649                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups               128                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             627419213                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 96438794                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               6501                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts           6457                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 169431016                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            172916819                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            80629893                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          21434071                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         27751379                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  682016489                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                4774                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 646845145                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           1424192                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        79472523                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    197906343                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved           1840                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     326356874                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.982018                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.741007                       # Number of insts issued each cycle
+system.cpu.rename.CommittedMaps             627419189                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 96562694                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               6452                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           6400                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 169999822                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            172950765                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            80642212                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          21622434                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         28168591                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  682111188                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                4787                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 646911424                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           1425738                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        79572817                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    198257861                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           1856                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     329533342                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.963114                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.727328                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            67525997     20.69%     20.69% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            84702389     25.95%     46.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            74951613     22.97%     69.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            40526195     12.42%     82.03% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            28606192      8.77%     90.79% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            15221367      4.66%     95.46% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             5979021      1.83%     97.29% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             6497584      1.99%     99.28% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             2346516      0.72%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            69109124     20.97%     20.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            85502964     25.95%     46.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            75902592     23.03%     69.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            41003361     12.44%     82.39% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            28586147      8.67%     91.07% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            15096087      4.58%     95.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             5691070      1.73%     97.38% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             6514226      1.98%     99.35% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             2127771      0.65%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       326356874                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       329533342                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  204976      4.99%      4.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      4.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      4.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      4.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      4.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      4.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      4.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      4.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      4.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      4.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      4.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      4.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      4.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      4.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      4.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      4.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      4.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      4.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      4.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      4.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      4.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      4.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      4.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      4.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      4.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      4.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      4.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      4.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      4.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                2983992     72.63%     77.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                919347     22.38%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  205938      5.35%      5.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      5.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      5.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      5.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      5.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      5.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      5.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      5.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      5.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      5.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      5.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      5.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      5.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      5.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      5.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      5.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      5.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      5.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      5.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      5.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      5.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      5.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      5.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      5.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      5.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      5.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      5.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      5.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      5.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                2629007     68.31%     73.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               1013747     26.34%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             403923414     62.45%     62.45% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                 6566      0.00%     62.45% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             403964135     62.45%     62.45% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                 6565      0.00%     62.45% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     62.45% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     62.45% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     62.45% # Type of FU issued
@@ -239,159 +239,159 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.00%     62.45% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     62.45% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     62.45% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     62.45% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            166112206     25.68%     88.13% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            76802956     11.87%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            166144548     25.68%     88.13% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            76796173     11.87%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              646845145                       # Type of FU issued
-system.cpu.iq.rate                           1.980651                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     4108315                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.006351                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         1625579635                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         761505232                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    638567907                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total              646911424                       # Type of FU issued
+system.cpu.iq.rate                           1.962570                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     3848692                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.005949                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         1628630584                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         761700595                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    638589501                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                  36                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                 16                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              650953440                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses              650760096                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                      20                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         30447417                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads         30444381                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     23963996                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses       129674                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        11684                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     10408650                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     23997945                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       128330                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        12058                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     10420972                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        12812                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked         13814                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        12743                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked         33964                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               11034182                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                  314683                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                 40041                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           682087415                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            655237                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             172916819                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             80629893                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               3420                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  12514                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                  1466                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          11684                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        1312850                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      1582780                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              2895630                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             642706502                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             163991051                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           4138643                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles               11048805                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                  670880                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                 80193                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           682182162                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            671811                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             172950765                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             80642212                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               3436                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  21821                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                  3936                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          12058                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        1313101                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      1582689                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              2895790                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             642749974                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             164016211                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           4161450                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                         66152                       # number of nop insts executed
-system.cpu.iew.exec_refs                    240011876                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 74666851                       # Number of branches executed
-system.cpu.iew.exec_stores                   76020825                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.967979                       # Inst execution rate
-system.cpu.iew.wb_sent                      640060409                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     638567923                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 420584081                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 656222195                       # num instructions consuming a value
+system.cpu.iew.exec_nop                         66187                       # number of nop insts executed
+system.cpu.iew.exec_refs                    240022824                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 74673150                       # Number of branches executed
+system.cpu.iew.exec_stores                   76006613                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.949945                       # Inst execution rate
+system.cpu.iew.wb_sent                      640083965                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     638589517                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 419034564                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 650591569                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.955306                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.640917                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.937324                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.644082                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts      570052786                       # The number of committed instructions
-system.cpu.commit.commitCommittedOps        602360992                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts        79735934                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls            2934                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           2422217                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    315322693                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.910300                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.242360                       # Number of insts commited each cycle
+system.cpu.commit.commitCommittedInsts      570052771                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps        602360977                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts        79830456                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls            2931                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts           2422889                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    318484538                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.891335                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.233401                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     91618801     29.06%     29.06% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    103774162     32.91%     61.97% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     42992063     13.63%     75.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      8898067      2.82%     78.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     25658030      8.14%     86.56% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     13146506      4.17%     90.73% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      7589457      2.41%     93.14% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      1157745      0.37%     93.50% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     20487862      6.50%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     93876011     29.48%     29.48% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    104566020     32.83%     62.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     43293403     13.59%     75.90% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      8795442      2.76%     78.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     26035150      8.17%     86.84% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     12750697      4.00%     90.84% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      7572699      2.38%     93.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      1269382      0.40%     93.62% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     20325734      6.38%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    315322693                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            570052786                       # Number of instructions committed
-system.cpu.commit.committedOps              602360992                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    318484538                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            570052771                       # Number of instructions committed
+system.cpu.commit.committedOps              602360977                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                      219174066                       # Number of memory references committed
-system.cpu.commit.loads                     148952823                       # Number of loads committed
+system.cpu.commit.refs                      219174060                       # Number of memory references committed
+system.cpu.commit.loads                     148952820                       # Number of loads committed
 system.cpu.commit.membars                        1328                       # Number of memory barriers committed
-system.cpu.commit.branches                   70828830                       # Number of branches committed
+system.cpu.commit.branches                   70828827                       # Number of branches committed
 system.cpu.commit.fp_insts                         16                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 533523551                       # Number of committed integer instructions.
+system.cpu.commit.int_insts                 533523539                       # Number of committed integer instructions.
 system.cpu.commit.function_calls               997573                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events              20487862                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events              20325734                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    976931145                       # The number of ROB reads
-system.cpu.rob.rob_writes                  1375260810                       # The number of ROB writes
-system.cpu.timesIdled                            9894                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          225135                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                   570052735                       # Number of Instructions Simulated
-system.cpu.committedOps                     602360941                       # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total             570052735                       # Number of Instructions Simulated
-system.cpu.cpi                               0.572898                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.572898                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.745512                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.745512                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               3210543463                       # number of integer regfile reads
-system.cpu.int_regfile_writes               664223214                       # number of integer regfile writes
+system.cpu.rob.rob_reads                    980349625                       # The number of ROB reads
+system.cpu.rob.rob_writes                  1375464218                       # The number of ROB writes
+system.cpu.timesIdled                            6594                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           91248                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                   570052720                       # Number of Instructions Simulated
+system.cpu.committedOps                     602360926                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total             570052720                       # Number of Instructions Simulated
+system.cpu.cpi                               0.578235                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.578235                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.729400                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.729400                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               3210711882                       # number of integer regfile reads
+system.cpu.int_regfile_writes               664273083                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
-system.cpu.misc_regfile_reads               905101471                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                   3116                       # number of misc regfile writes
-system.cpu.icache.replacements                     67                       # number of replacements
-system.cpu.icache.tagsinuse                689.277263                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 67498009                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                    823                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs               82014.591738                       # Average number of references to valid blocks.
+system.cpu.misc_regfile_reads               905231466                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                   3110                       # number of misc regfile writes
+system.cpu.icache.replacements                     57                       # number of replacements
+system.cpu.icache.tagsinuse                692.699547                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 67506606                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    819                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               82425.648352                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     689.277263                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.336561                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.336561                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst     67498009                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        67498009                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      67498009                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         67498009                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     67498009                       # number of overall hits
-system.cpu.icache.overall_hits::total        67498009                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         1099                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          1099                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         1099                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           1099                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         1099                       # number of overall misses
-system.cpu.icache.overall_misses::total          1099                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     36702500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     36702500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     36702500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     36702500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     36702500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     36702500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     67499108                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     67499108                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     67499108                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     67499108                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     67499108                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     67499108                       # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::cpu.inst     692.699547                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.338232                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.338232                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst     67506606                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        67506606                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      67506606                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         67506606                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     67506606                       # number of overall hits
+system.cpu.icache.overall_hits::total        67506606                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1100                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1100                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1100                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1100                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1100                       # number of overall misses
+system.cpu.icache.overall_misses::total          1100                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     38665000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     38665000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     38665000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     38665000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     38665000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     38665000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     67507706                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     67507706                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     67507706                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     67507706                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     67507706                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     67507706                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000016                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000016                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000016                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000016                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000016                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000016                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33396.269336                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 33396.269336                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 33396.269336                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 33396.269336                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 33396.269336                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 33396.269336                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst        35150                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total        35150                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst        35150                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total        35150                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst        35150                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total        35150                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -400,309 +400,309 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          276                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          276                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          276                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          276                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          276                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          276                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          823                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          823                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          823                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          823                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          823                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          823                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     26927500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     26927500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     26927500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     26927500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     26927500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     26927500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          281                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          281                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          281                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          281                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          281                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          281                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          819                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          819                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          819                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          819                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          819                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          819                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     28673500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     28673500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     28673500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     28673500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     28673500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     28673500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000012                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000012                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000012                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000012                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000012                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000012                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 32718.712029                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 32718.712029                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 32718.712029                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 32718.712029                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 32718.712029                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 32718.712029                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35010.378510                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35010.378510                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35010.378510                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 35010.378510                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35010.378510                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 35010.378510                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                 440493                       # number of replacements
-system.cpu.dcache.tagsinuse               4094.665054                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                200200644                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                 444589                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                 450.304987                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle               87327000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4094.665054                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.999674                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.999674                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data    132070479                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       132070479                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     68126925                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       68126925                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data         1683                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total         1683                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data         1557                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total         1557                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     200197404                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        200197404                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    200197404                       # number of overall hits
-system.cpu.dcache.overall_hits::total       200197404                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       228400                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        228400                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1290606                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1290606                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data           22                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total           22                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      1519006                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1519006                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1519006                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1519006                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   1639819000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   1639819000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  12328996350                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  12328996350                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       168000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total       168000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  13968815350                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  13968815350                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  13968815350                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  13968815350                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    132298879                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    132298879                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.replacements                 440349                       # number of replacements
+system.cpu.dcache.tagsinuse               4094.167847                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                198867214                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 444445                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 447.450672                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              114097000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4094.167847                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.999553                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.999553                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data    132006402                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       132006402                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     66857562                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       66857562                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data         1696                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total         1696                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data         1554                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total         1554                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data     198863964                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        198863964                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    198863964                       # number of overall hits
+system.cpu.dcache.overall_hits::total       198863964                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       301447                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        301447                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      2559969                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      2559969                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data           21                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total           21                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data      2861416                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2861416                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2861416                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2861416                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   3693455500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   3693455500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  40398908535                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  40398908535                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       237000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total       237000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  44092364035                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  44092364035                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  44092364035                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  44092364035                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    132307849                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    132307849                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     69417531                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     69417531                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data         1705                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total         1705                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data         1557                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total         1557                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    201716410                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    201716410                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    201716410                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    201716410                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.001726                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.001726                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.018592                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.018592                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.012903                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.012903                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.007530                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.007530                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.007530                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.007530                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data  7179.592820                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total  7179.592820                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data  9552.873883                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total  9552.873883                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data  7636.363636                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total  7636.363636                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data  9196.023814                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total  9196.023814                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data  9196.023814                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total  9196.023814                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs      9916851                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs              2339                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs  4239.782386                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data         1717                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total         1717                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data         1554                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total         1554                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    201725380                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    201725380                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    201725380                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    201725380                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.002278                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.002278                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.036878                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.036878                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.012231                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.012231                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.014185                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.014185                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.014185                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.014185                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12252.420824                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 12252.420824                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15781.014745                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 15781.014745                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 11285.714286                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 11285.714286                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 15409.281291                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 15409.281291                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 15409.281291                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 15409.281291                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs     30249535                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets        47000                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              3035                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               2                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  9966.897858                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets        23500                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       421148                       # number of writebacks
-system.cpu.dcache.writebacks::total            421148                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data        30933                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        30933                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1043483                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      1043483                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           22                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total           22                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1074416                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1074416                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1074416                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1074416                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       197467                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       197467                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       247123                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       247123                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       444590                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       444590                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       444590                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       444590                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    754200000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total    754200000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1366160851                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   1366160851                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data   2120360851                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total   2120360851                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data   2120360851                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total   2120360851                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.001493                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.001493                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.writebacks::writebacks       420982                       # number of writebacks
+system.cpu.dcache.writebacks::total            420982                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       104126                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       104126                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      2312844                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      2312844                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           21                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total           21                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      2416970                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      2416970                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      2416970                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      2416970                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       197321                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       197321                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       247125                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       247125                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       444446                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       444446                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       444446                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       444446                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   1545858000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   1545858000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2729554035                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   2729554035                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   4275412035                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   4275412035                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data   4275412035                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   4275412035                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.001491                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.001491                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.003560                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.003560                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002204                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.002204                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002204                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.002204                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  3819.372351                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  3819.372351                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  5528.262651                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  5528.262651                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  4769.249985                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total  4769.249985                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  4769.249985                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total  4769.249985                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002203                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.002203                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002203                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.002203                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  7834.229504                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  7834.229504                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 11045.236358                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 11045.236358                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  9619.643410                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total  9619.643410                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  9619.643410                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total  9619.643410                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.replacements                  4232                       # number of replacements
-system.cpu.l2cache.tagsinuse             21916.989023                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                  505361                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                 25263                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                 20.003998                       # Average number of references to valid blocks.
+system.cpu.l2cache.replacements                  4243                       # number of replacements
+system.cpu.l2cache.tagsinuse             21902.752747                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                  504961                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                 25275                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                 19.978675                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 20776.737847                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst    177.343583                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data    962.907593                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.634056                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst     0.005412                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.029386                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.668853                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst           74                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data       191964                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total         192038                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       421148                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       421148                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       224955                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       224955                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst           74                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       416919                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          416993                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst           74                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       416919                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         416993                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          749                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data         5501                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         6250                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data        22170                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total        22170                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          749                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data        27671                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total         28420                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          749                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data        27671                       # number of overall misses
-system.cpu.l2cache.overall_misses::total        28420                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     25729000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data    189531000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    215260000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    766936500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    766936500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     25729000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    956467500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    982196500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     25729000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    956467500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    982196500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          823                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data       197465                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total       198288                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       421148                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       421148                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       247125                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       247125                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          823                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       444590                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       445413                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          823                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       444590                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       445413                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.910085                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.027858                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.031520                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.089712                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.089712                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.910085                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.062239                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.063806                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.910085                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.062239                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.063806                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34351.134846                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34453.917470                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 34441.600000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34593.437077                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34593.437077                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34351.134846                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34565.700553                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 34560.045742                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34351.134846                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34565.700553                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 34560.045742                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs      2032500                       # number of cycles access was blocked
+system.cpu.l2cache.occ_blocks::writebacks 20758.350420                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst    181.193003                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    963.209324                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.633495                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.005530                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.029395                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.668419                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst           63                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data       191816                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         191879                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       420982                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       420982                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       224953                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       224953                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst           63                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       416769                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          416832                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst           63                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       416769                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         416832                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          756                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data         5500                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total         6256                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data        22177                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total        22177                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          756                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data        27677                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total         28433                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          756                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data        27677                       # number of overall misses
+system.cpu.l2cache.overall_misses::total        28433                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     27067500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data    193993000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    221060500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    879298285                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    879298285                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     27067500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   1073291285                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   1100358785                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     27067500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   1073291285                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   1100358785                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          819                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data       197316                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       198135                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       420982                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       420982                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       247130                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       247130                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          819                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       444446                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       445265                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          819                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       444446                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       445265                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.923077                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.027874                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.031574                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.089738                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.089738                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.923077                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.062273                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.063856                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.923077                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.062273                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.063856                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35803.571429                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 35271.454545                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 35335.757673                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39649.108761                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39649.108761                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35803.571429                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 38779.177115                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 38700.059262                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35803.571429                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 38779.177115                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 38700.059262                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs      5679785                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs              322                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs              478                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs  6312.111801                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs 11882.395397                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks         3176                       # number of writebacks
-system.cpu.l2cache.writebacks::total             3176                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            1                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           11                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total           12                       # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data           11                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           12                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data           11                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           12                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          748                       # number of ReadReq MSHR misses
+system.cpu.l2cache.writebacks::writebacks         3183                       # number of writebacks
+system.cpu.l2cache.writebacks::total             3183                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            3                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           10                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total           13                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst            3                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data           10                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           13                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst            3                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data           10                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total           13                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          753                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data         5490                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         6238                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        22170                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total        22170                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          748                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data        27660                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total        28408                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          748                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data        27660                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total        28408                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     23297500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    171301000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    194598500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    698565000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    698565000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     23297500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    869866000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    893163500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     23297500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    869866000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    893163500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.908870                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.027802                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.031459                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.089712                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.089712                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.908870                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.062215                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.063779                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.908870                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.062215                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.063779                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31146.390374                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31202.367942                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31195.655659                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31509.472260                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31509.472260                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31146.390374                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31448.517715                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31440.562518                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31146.390374                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31448.517715                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31440.562518                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_mshr_misses::total         6243                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        22177                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        22177                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          753                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data        27667                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        28420                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          753                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data        27667                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total        28420                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     24642000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    175481000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    200123000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    812123285                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    812123285                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     24642000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    987604285                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   1012246285                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     24642000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    987604285                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   1012246285                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.919414                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.027823                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.031509                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.089738                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.089738                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.919414                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.062251                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.063827                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.919414                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.062251                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.063827                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32725.099602                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31963.752277                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32055.582252                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36620.069667                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36620.069667                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32725.099602                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35696.110348                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35617.392153                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32725.099602                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35696.110348                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35617.392153                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini
index 02db72141..a10276e4b 100644
--- a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini
@@ -166,7 +166,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
@@ -198,7 +198,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout
index b63306c7d..149dba9b1 100755
--- a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:10:14
-gem5 started Jun 29 2012 00:38:23
+gem5 compiled Jul  2 2012 09:08:16
+gem5 started Jul  2 2012 15:28:47
 gem5 executing on zizzer
 command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
@@ -38,4 +38,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 794147534000 because target called exit()
+Exiting @ tick 795270546000 because target called exit()
diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt
index 759b7639a..79ebe936b 100644
--- a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.794148                       # Number of seconds simulated
-sim_ticks                                794147534000                       # Number of ticks simulated
-final_tick                               794147534000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.795271                       # Number of seconds simulated
+sim_ticks                                795270546000                       # Number of ticks simulated
+final_tick                               795270546000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1549107                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1635914                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2163825213                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 232760                       # Number of bytes of host memory used
-host_seconds                                   367.01                       # Real time elapsed on the host
+host_inst_rate                                 873454                       # Simulator instruction rate (inst/s)
+host_op_rate                                   922399                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1221783566                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 232680                       # Number of bytes of host memory used
+host_seconds                                   650.91                       # Real time elapsed on the host
 sim_insts                                   568539335                       # Number of instructions simulated
 sim_ops                                     600398272                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             39104                       # Number of bytes read from this memory
@@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data              27110                       # Nu
 system.physmem.num_reads::total                 27721                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks            3043                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                 3043                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                49240                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              2184783                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2234023                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           49240                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              49240                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks            245234                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                 245234                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks            245234                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               49240                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             2184783                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2479257                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst                49171                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              2181698                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2230868                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           49171                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              49171                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks            244888                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                 244888                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks            244888                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               49171                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             2181698                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2475756                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -77,7 +77,7 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                   48                       # Number of system calls
-system.cpu.numCycles                       1588295068                       # number of cpu cycles simulated
+system.cpu.numCycles                       1590541092                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   568539335                       # Number of instructions committed
@@ -96,18 +96,18 @@ system.cpu.num_mem_refs                     219173606                       # nu
 system.cpu.num_load_insts                   148952593                       # Number of load instructions
 system.cpu.num_store_insts                   70221013                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                 1588295068                       # Number of busy cycles
+system.cpu.num_busy_cycles                 1590541092                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                     12                       # number of replacements
-system.cpu.icache.tagsinuse                577.753136                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                577.715333                       # Cycle average of tags in use
 system.cpu.icache.total_refs                570073883                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    643                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               886584.576983                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     577.753136                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.282106                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.282106                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst     577.715333                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.282088                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.282088                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst    570073883                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total       570073883                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst     570073883                       # number of demand (read+write) hits
@@ -120,12 +120,12 @@ system.cpu.icache.demand_misses::cpu.inst          643                       # n
 system.cpu.icache.demand_misses::total            643                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          643                       # number of overall misses
 system.cpu.icache.overall_misses::total           643                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     34664000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     34664000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     34664000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     34664000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     34664000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     34664000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     34792000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     34792000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     34792000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     34792000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     34792000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     34792000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst    570074526                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total    570074526                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst    570074526                       # number of demand (read+write) accesses
@@ -138,12 +138,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000001
 system.cpu.icache.demand_miss_rate::total     0.000001                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000001                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000001                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53909.797823                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 53909.797823                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 53909.797823                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 53909.797823                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 53909.797823                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 53909.797823                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54108.864697                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 54108.864697                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 54108.864697                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 54108.864697                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 54108.864697                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 54108.864697                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -158,34 +158,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          643
 system.cpu.icache.demand_mshr_misses::total          643                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          643                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          643                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     32735000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     32735000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     32735000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     32735000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     32735000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     32735000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     32863000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     32863000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     32863000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     32863000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     32863000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     32863000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000001                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000001                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000001                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000001                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000001                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000001                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50909.797823                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50909.797823                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50909.797823                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 50909.797823                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50909.797823                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 50909.797823                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51108.864697                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51108.864697                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51108.864697                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 51108.864697                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51108.864697                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 51108.864697                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                 433468                       # number of replacements
-system.cpu.dcache.tagsinuse               4094.217417                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               4094.191707                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                216774472                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                 437564                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                 495.412036                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              536853000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4094.217417                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.999565                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.999565                       # Average percentage of cache occupancy
+system.cpu.dcache.warmup_cycle              547974000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4094.191707                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.999559                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.999559                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data    147602035                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total       147602035                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     69169783                       # number of WriteReq hits
@@ -206,14 +206,14 @@ system.cpu.dcache.demand_misses::cpu.data       437564                       # n
 system.cpu.dcache.demand_misses::total         437564                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data       437564                       # number of overall misses
 system.cpu.dcache.overall_misses::total        437564                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   2865114000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   2865114000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   4399402000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   4399402000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data   7264516000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total   7264516000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data   7264516000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total   7264516000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   2866972000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   2866972000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   4400884000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   4400884000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data   7267856000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total   7267856000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data   7267856000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total   7267856000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data    147791851                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total    147791851                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     69417531                       # number of WriteReq accesses(hits+misses)
@@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.002014
 system.cpu.dcache.demand_miss_rate::total     0.002014                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.002014                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.002014                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15094.164875                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 15094.164875                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17757.568174                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 17757.568174                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 16602.179338                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 16602.179338                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 16602.179338                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 16602.179338                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15103.953302                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 15103.953302                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17763.550059                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 17763.550059                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 16609.812507                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 16609.812507                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 16609.812507                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 16609.812507                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data       437564
 system.cpu.dcache.demand_mshr_misses::total       437564                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data       437564                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total       437564                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   2295666000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   2295666000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   3656158000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   3656158000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data   5951824000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total   5951824000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data   5951824000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total   5951824000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   2297524000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   2297524000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   3657640000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   3657640000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   5955164000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   5955164000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data   5955164000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   5955164000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.001284                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.001284                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.003569                       # mshr miss rate for WriteReq accesses
@@ -276,28 +276,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002014
 system.cpu.dcache.demand_mshr_miss_rate::total     0.002014                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002014                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.002014                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12094.164875                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12094.164875                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14757.568174                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14757.568174                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13602.179338                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 13602.179338                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13602.179338                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 13602.179338                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12103.953302                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12103.953302                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14763.550059                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14763.550059                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13609.812507                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 13609.812507                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13609.812507                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 13609.812507                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                  3963                       # number of replacements
-system.cpu.l2cache.tagsinuse             21581.956920                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse             21579.150724                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                  495400                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                 24559                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                 20.171831                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 20942.700989                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst    130.076740                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data    509.179191                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.639121                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst     0.003970                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::writebacks 20939.895204                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst    130.071130                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    509.184390                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.639035                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.003969                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.data     0.015539                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.658629                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.658543                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst           32                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data       184871                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total         184903                       # number of ReadReq hits
diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini
index 3fe84dba1..647cf0cf8 100644
--- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini
+++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini
@@ -479,7 +479,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
@@ -511,7 +511,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout
index 476c2fbae..196024f42 100755
--- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout
+++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:06:58
-gem5 started Jun 28 2012 22:54:22
+gem5 compiled Jul  2 2012 08:54:18
+gem5 started Jul  2 2012 11:32:18
 gem5 executing on zizzer
 command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
@@ -38,4 +38,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 387353399000 because target called exit()
+Exiting @ tick 389181871500 because target called exit()
diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt
index aefb16cc5..09d53c6a6 100644
--- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt
+++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt
@@ -1,173 +1,173 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.387353                       # Number of seconds simulated
-sim_ticks                                387353399000                       # Number of ticks simulated
-final_tick                               387353399000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.389182                       # Number of seconds simulated
+sim_ticks                                389181871500                       # Number of ticks simulated
+final_tick                               389181871500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 249730                       # Simulator instruction rate (inst/s)
-host_op_rate                                   250517                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               69036992                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 223172                       # Number of bytes of host memory used
-host_seconds                                  5610.81                       # Real time elapsed on the host
+host_inst_rate                                 233275                       # Simulator instruction rate (inst/s)
+host_op_rate                                   234010                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               64792479                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 223132                       # Number of bytes of host memory used
+host_seconds                                  6006.59                       # Real time elapsed on the host
 sim_insts                                  1401188958                       # Number of instructions simulated
 sim_ops                                    1405604152                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst             78784                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           1679296                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              1758080                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        78784                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           78784                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks       163648                       # Number of bytes written to this memory
-system.physmem.bytes_written::total            163648                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               1231                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data              26239                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                 27470                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks            2557                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                 2557                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               203390                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              4335307                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 4538698                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          203390                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             203390                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks            422477                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                 422477                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks            422477                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              203390                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             4335307                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4961175                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst             78592                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           1679360                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              1757952                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        78592                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           78592                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks       163456                       # Number of bytes written to this memory
+system.physmem.bytes_written::total            163456                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               1228                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data              26240                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                 27468                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks            2554                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                 2554                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               201942                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              4315103                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 4517045                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          201942                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             201942                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks            419999                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                 419999                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks            419999                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              201942                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             4315103                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                4937044                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   49                       # Number of system calls
-system.cpu.numCycles                        774706799                       # number of cpu cycles simulated
+system.cpu.numCycles                        778363744                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                 98185703                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted           88410338                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect            3780922                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups              66067142                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                 65660680                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                 98202538                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           88418167                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect            3786555                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              66007710                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                 65666961                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                     1350                       # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect                 222                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles          165873006                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     1648740209                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    98185703                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           65662030                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     330401804                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                21677633                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles              260655576                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                  134                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          2710                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                 162813671                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                754240                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          774625436                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.134374                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.150186                       # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS                     1332                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect                 219                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles          165889798                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1648919647                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    98202538                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           65668293                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     330430884                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                21692843                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles              264292230                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                  125                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles          2686                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                 162826473                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                754831                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          778319405                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.124393                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.146166                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                444223632     57.35%     57.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 74371089      9.60%     66.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 37975725      4.90%     71.85% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  9081691      1.17%     73.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 28157593      3.63%     76.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 18825345      2.43%     79.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 11518334      1.49%     80.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  3870567      0.50%     81.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                146601460     18.93%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                447888521     57.55%     57.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 74380250      9.56%     67.10% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 37976870      4.88%     71.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  9085355      1.17%     73.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 28165073      3.62%     76.77% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 18828553      2.42%     79.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 11512004      1.48%     80.67% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  3871007      0.50%     81.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                146611772     18.84%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            774625436                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.126739                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.128212                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                217582243                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             211191171                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 285367331                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              42792485                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               17692206                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts             1642537043                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles               17692206                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                241610870                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                34893000                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       51906533                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 303032306                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles             125490521                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             1631238728                       # Number of instructions processed by rename
-system.cpu.rename.IQFullEvents               30863889                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents              72608286                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents          3100712                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands          1360952696                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            2755863339                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       2721765470                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups          34097869                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            778319405                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.126165                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.118444                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                217790097                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             214638982                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 285156910                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              43029734                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               17703682                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts             1642636299                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles               17703682                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                241734353                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                36955708                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       51946820                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 303044657                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             126934185                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             1631312586                       # Number of instructions processed by rename
+system.cpu.rename.IQFullEvents               31546408                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents              73332264                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents          3116970                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands          1360939473                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            2755912805                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       2722068159                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups          33844646                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps            1244770452                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                116182244                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts            2679261                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts        2694678                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 271420357                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            438695813                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           180248477                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads         255317958                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         83005231                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 1517026367                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             2634412                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1460842230                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued             78451                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       113716292                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    136734652                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         390741                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     774625436                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.885869                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.429732                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                116169021                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            2679381                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts        2694981                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 272918574                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            438732735                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           180262547                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads         255381650                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         82499363                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 1517064379                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             2634738                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1460855259                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued             54931                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       113760463                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    136767182                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         391067                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     778319405                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.876935                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.427664                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           145113160     18.73%     18.73% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           184290714     23.79%     42.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           210981910     27.24%     69.76% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           131056815     16.92%     86.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            70797961      9.14%     95.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            20401058      2.63%     98.45% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             7831654      1.01%     99.46% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             3987119      0.51%     99.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              165045      0.02%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           147026932     18.89%     18.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           186493885     23.96%     42.85% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           211074443     27.12%     69.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           130841076     16.81%     86.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            70678954      9.08%     95.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            20414805      2.62%     98.49% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             7717737      0.99%     99.48% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             3979587      0.51%     99.99% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8               91986      0.01%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       774625436                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       778319405                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                   85311      4.91%      4.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      4.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      4.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                160602      9.25%     14.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     14.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     14.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     14.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     14.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     14.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     14.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     14.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     14.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     14.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     14.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     14.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     14.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     14.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     14.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     14.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     14.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     14.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     14.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     14.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     14.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     14.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     14.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     14.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     14.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     14.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                1164457     67.05%     81.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                326416     18.79%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  100522      6.26%      6.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      6.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      6.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                166576     10.38%     16.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     16.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     16.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     16.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     16.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     16.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     16.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     16.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     16.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     16.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     16.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     16.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     16.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     16.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     16.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     16.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     16.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     16.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     16.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     16.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     16.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     16.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     16.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     16.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     16.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     16.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                1142590     71.19%     87.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                195193     12.16%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             867158495     59.36%     59.36% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             867158324     59.36%     59.36% # Type of FU issued
 system.cpu.iq.FU_type_0::IntMult                    0      0.00%     59.36% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     59.36% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd             2649765      0.18%     59.54% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd             2642655      0.18%     59.54% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     59.54% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     59.54% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     59.54% # Type of FU issued
@@ -193,86 +193,86 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     59.54% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     59.54% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     59.54% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     59.54% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            419768740     28.73%     88.28% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           171265230     11.72%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            419786972     28.74%     88.28% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           171267308     11.72%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1460842230                       # Type of FU issued
-system.cpu.iq.rate                           1.885671                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     1736786                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.001189                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         3680238914                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        1624378157                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1444420049                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads            17886219                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes            9235235                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses      8548145                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             1453389871                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                 9189145                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads        215326368                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             1460855259                       # Type of FU issued
+system.cpu.iq.rate                           1.876829                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     1604881                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.001099                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         3684016874                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        1624580550                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1444446185                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads            17672861                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes            9115596                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses      8537125                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             1453449423                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 9010717                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads        215321766                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     36182969                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        54134                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       244807                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     13400335                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     36219891                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        54743                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       244893                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     13414405                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads         3669                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked         64278                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads         3575                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked         58855                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               17692206                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                  786779                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                100697                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          1613841065                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts           4120499                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             438695813                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            180248477                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            2548675                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  22528                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 11302                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         244807                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        2356307                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      1558704                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              3915011                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            1455294659                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             417049506                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           5547571                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles               17703682                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 1537187                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                135114                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          1613898993                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           4122313                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             438732735                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            180262547                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            2549072                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  88195                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                  3279                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         244893                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        2354936                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      1566356                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              3921292                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1455308115                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             417068435                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           5547144                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                      94180286                       # number of nop insts executed
-system.cpu.iew.exec_refs                    587622925                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 89107301                       # Number of branches executed
-system.cpu.iew.exec_stores                  170573419                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.878510                       # Inst execution rate
-system.cpu.iew.wb_sent                     1453892295                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    1452968194                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1154379658                       # num instructions producing a value
-system.cpu.iew.wb_consumers                1205415324                       # num instructions consuming a value
+system.cpu.iew.exec_nop                      94199876                       # number of nop insts executed
+system.cpu.iew.exec_refs                    587640720                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 89112594                       # Number of branches executed
+system.cpu.iew.exec_stores                  170572285                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.869702                       # Inst execution rate
+system.cpu.iew.wb_sent                     1453906115                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1452983310                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1154403216                       # num instructions producing a value
+system.cpu.iew.wb_consumers                1205257004                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.875507                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.957661                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.866715                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.957807                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts     1485108101                       # The number of committed instructions
 system.cpu.commit.commitCommittedOps       1489523295                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts       124212585                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       124289069                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls         2243671                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           3780922                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    756933841                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.967838                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.506392                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           3786555                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    760616334                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.958311                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.503558                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    238474723     31.51%     31.51% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    276385043     36.51%     68.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     43107077      5.69%     73.71% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     54927770      7.26%     80.97% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     19677668      2.60%     83.57% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     13341628      1.76%     85.33% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     30470034      4.03%     89.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     10497412      1.39%     90.75% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     70052486      9.25%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    241729742     31.78%     31.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    276918822     36.41%     68.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     43178321      5.68%     73.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     54835847      7.21%     81.07% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     19622698      2.58%     83.65% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     13346857      1.75%     85.41% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     30466514      4.01%     89.41% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     10424135      1.37%     90.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     70093398      9.22%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    756933841                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    760616334                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts           1485108101                       # Number of instructions committed
 system.cpu.commit.committedOps             1489523295                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -283,70 +283,70 @@ system.cpu.commit.branches                   86248929                       # Nu
 system.cpu.commit.fp_insts                    8452036                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                1319476388                       # Number of committed integer instructions.
 system.cpu.commit.function_calls              1206914                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events              70052486                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events              70093398                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   2300552365                       # The number of ROB reads
-system.cpu.rob.rob_writes                  3245186964                       # The number of ROB writes
-system.cpu.timesIdled                            3424                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           81363                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                   2304270430                       # The number of ROB reads
+system.cpu.rob.rob_writes                  3245352893                       # The number of ROB writes
+system.cpu.timesIdled                            1469                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           44339                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                  1401188958                       # Number of Instructions Simulated
 system.cpu.committedOps                    1405604152                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total            1401188958                       # Number of Instructions Simulated
-system.cpu.cpi                               0.552892                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.552892                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.808670                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.808670                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               1980590719                       # number of integer regfile reads
-system.cpu.int_regfile_writes              1276263729                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                  16980710                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                 10502370                       # number of floating regfile writes
-system.cpu.misc_regfile_reads               593296241                       # number of misc regfile reads
+system.cpu.cpi                               0.555502                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.555502                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.800172                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.800172                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               1980619061                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1276279795                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                  16952700                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                 10491726                       # number of floating regfile writes
+system.cpu.misc_regfile_reads               593312421                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                2190883                       # number of misc regfile writes
-system.cpu.icache.replacements                    213                       # number of replacements
-system.cpu.icache.tagsinuse               1045.821443                       # Cycle average of tags in use
-system.cpu.icache.total_refs                162811755                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                   1361                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs               119626.565026                       # Average number of references to valid blocks.
+system.cpu.icache.replacements                    216                       # number of replacements
+system.cpu.icache.tagsinuse               1046.067933                       # Cycle average of tags in use
+system.cpu.icache.total_refs                162824561                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                   1364                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               119372.845308                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst    1045.821443                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.510655                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.510655                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst    162811755                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       162811755                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     162811755                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        162811755                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    162811755                       # number of overall hits
-system.cpu.icache.overall_hits::total       162811755                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         1916                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          1916                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         1916                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           1916                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         1916                       # number of overall misses
-system.cpu.icache.overall_misses::total          1916                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     62211500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     62211500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     62211500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     62211500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     62211500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     62211500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    162813671                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    162813671                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    162813671                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    162813671                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    162813671                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    162813671                       # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::cpu.inst    1046.067933                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.510775                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.510775                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst    162824561                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       162824561                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     162824561                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        162824561                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    162824561                       # number of overall hits
+system.cpu.icache.overall_hits::total       162824561                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1912                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1912                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1912                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1912                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1912                       # number of overall misses
+system.cpu.icache.overall_misses::total          1912                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     62993000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     62993000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     62993000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     62993000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     62993000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     62993000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    162826473                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    162826473                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    162826473                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    162826473                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    162826473                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    162826473                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000012                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000012                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000012                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000012                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000012                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000012                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 32469.467641                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 32469.467641                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 32469.467641                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 32469.467641                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 32469.467641                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 32469.467641                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 32946.129707                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 32946.129707                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 32946.129707                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 32946.129707                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 32946.129707                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 32946.129707                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -355,144 +355,144 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          554                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          554                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          554                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          554                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          554                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          554                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         1362                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         1362                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         1362                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         1362                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         1362                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         1362                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     43838000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     43838000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     43838000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     43838000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     43838000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     43838000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          547                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          547                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          547                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          547                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          547                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          547                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         1365                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         1365                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         1365                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         1365                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         1365                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         1365                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     44905000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     44905000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     44905000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     44905000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     44905000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     44905000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000008                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000008                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000008                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000008                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000008                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000008                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 32186.490455                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 32186.490455                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 32186.490455                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 32186.490455                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 32186.490455                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 32186.490455                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 32897.435897                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 32897.435897                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 32897.435897                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 32897.435897                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 32897.435897                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 32897.435897                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                 458023                       # number of replacements
-system.cpu.dcache.tagsinuse               4095.115270                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                365885511                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                 462119                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                 791.756043                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              131340000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4095.115270                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.999784                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.999784                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data    200904892                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       200904892                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    164979300                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      164979300                       # number of WriteReq hits
+system.cpu.dcache.replacements                 458041                       # number of replacements
+system.cpu.dcache.tagsinuse               4094.912001                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                365776449                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 462137                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 791.489210                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              160490000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4094.912001                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.999734                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.999734                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data    200799973                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       200799973                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    164975157                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      164975157                       # number of WriteReq hits
 system.cpu.dcache.SwapReq_hits::cpu.data         1319                       # number of SwapReq hits
 system.cpu.dcache.SwapReq_hits::total            1319                       # number of SwapReq hits
-system.cpu.dcache.demand_hits::cpu.data     365884192                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        365884192                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    365884192                       # number of overall hits
-system.cpu.dcache.overall_hits::total       365884192                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       767087                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        767087                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1867516                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1867516                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data     365775130                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        365775130                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    365775130                       # number of overall hits
+system.cpu.dcache.overall_hits::total       365775130                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       900450                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        900450                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1871659                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1871659                       # number of WriteReq misses
 system.cpu.dcache.SwapReq_misses::cpu.data            7                       # number of SwapReq misses
 system.cpu.dcache.SwapReq_misses::total             7                       # number of SwapReq misses
-system.cpu.dcache.demand_misses::cpu.data      2634603                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2634603                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      2634603                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2634603                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   5082670000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   5082670000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  23201861832                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  23201861832                       # number of WriteReq miss cycles
-system.cpu.dcache.SwapReq_miss_latency::cpu.data        69000                       # number of SwapReq miss cycles
-system.cpu.dcache.SwapReq_miss_latency::total        69000                       # number of SwapReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  28284531832                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  28284531832                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  28284531832                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  28284531832                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    201671979                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    201671979                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data      2772109                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2772109                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2772109                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2772109                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  11941437000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  11941437000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  57464288206                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  57464288206                       # number of WriteReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency::cpu.data        69500                       # number of SwapReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency::total        69500                       # number of SwapReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  69405725206                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  69405725206                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  69405725206                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  69405725206                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    201700423                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    201700423                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    166846816                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    166846816                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SwapReq_accesses::cpu.data         1326                       # number of SwapReq accesses(hits+misses)
 system.cpu.dcache.SwapReq_accesses::total         1326                       # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    368518795                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    368518795                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    368518795                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    368518795                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.003804                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.003804                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.011193                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.011193                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_accesses::cpu.data    368547239                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    368547239                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    368547239                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    368547239                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.004464                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.004464                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.011218                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.011218                       # miss rate for WriteReq accesses
 system.cpu.dcache.SwapReq_miss_rate::cpu.data     0.005279                       # miss rate for SwapReq accesses
 system.cpu.dcache.SwapReq_miss_rate::total     0.005279                       # miss rate for SwapReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.007149                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.007149                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.007149                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.007149                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data  6625.936823                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total  6625.936823                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12423.915957                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 12423.915957                       # average WriteReq miss latency
-system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data  9857.142857                       # average SwapReq miss latency
-system.cpu.dcache.SwapReq_avg_miss_latency::total  9857.142857                       # average SwapReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 10735.785176                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 10735.785176                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 10735.785176                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 10735.785176                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs         5000                       # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data     0.007522                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.007522                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.007522                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.007522                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13261.632517                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 13261.632517                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30702.327831                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 30702.327831                       # average WriteReq miss latency
+system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data  9928.571429                       # average SwapReq miss latency
+system.cpu.dcache.SwapReq_avg_miss_latency::total  9928.571429                       # average SwapReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 25037.155900                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 25037.155900                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 25037.155900                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 25037.155900                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs         4500                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 2                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs         2500                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs         2250                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       442952                       # number of writebacks
-system.cpu.dcache.writebacks::total            442952                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       567019                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       567019                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1605472                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      1605472                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      2172491                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      2172491                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      2172491                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      2172491                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       200068                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       200068                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       262044                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       262044                       # number of WriteReq MSHR misses
+system.cpu.dcache.writebacks::writebacks       442976                       # number of writebacks
+system.cpu.dcache.writebacks::total            442976                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       700359                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       700359                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1609620                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      1609620                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      2309979                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      2309979                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      2309979                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      2309979                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       200091                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       200091                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       262039                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       262039                       # number of WriteReq MSHR misses
 system.cpu.dcache.SwapReq_mshr_misses::cpu.data            7                       # number of SwapReq MSHR misses
 system.cpu.dcache.SwapReq_mshr_misses::total            7                       # number of SwapReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       462112                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       462112                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       462112                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       462112                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    667617500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total    667617500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2577100353                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   2577100353                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data        48000                       # number of SwapReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_latency::total        48000                       # number of SwapReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data   3244717853                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total   3244717853                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data   3244717853                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total   3244717853                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data       462130                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       462130                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       462130                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       462130                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    927899000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total    927899000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5906951258                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   5906951258                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data        47000                       # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency::total        47000                       # number of SwapReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   6834850258                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   6834850258                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data   6834850258                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   6834850258                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000992                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000992                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.001571                       # mshr miss rate for WriteReq accesses
@@ -503,100 +503,100 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.001254
 system.cpu.dcache.demand_mshr_miss_rate::total     0.001254                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.001254                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.001254                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  3336.952936                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  3336.952936                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  9834.609276                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  9834.609276                       # average WriteReq mshr miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data  6857.142857                       # average SwapReq mshr miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total  6857.142857                       # average SwapReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  7021.496635                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total  7021.496635                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  7021.496635                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total  7021.496635                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  4637.384990                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  4637.384990                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22542.259961                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22542.259961                       # average WriteReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data  6714.285714                       # average SwapReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total  6714.285714                       # average SwapReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14789.886521                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 14789.886521                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14789.886521                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 14789.886521                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.replacements                  2687                       # number of replacements
-system.cpu.l2cache.tagsinuse             22389.093569                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                  541770                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                 24316                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                 22.280392                       # Average number of references to valid blocks.
+system.cpu.l2cache.replacements                  2683                       # number of replacements
+system.cpu.l2cache.tagsinuse             22381.394167                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                  541833                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                 24313                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                 22.285732                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 20749.065354                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst    997.527040                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data    642.501175                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.633211                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst     0.030442                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.019608                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.683261                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst          131                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data       195628                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total         195759                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       442952                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       442952                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       240252                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       240252                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst          131                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       435880                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          436011                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst          131                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       435880                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         436011                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         1231                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data         4439                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         5670                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data        21800                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total        21800                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         1231                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data        26239                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total         27470                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         1231                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data        26239                       # number of overall misses
-system.cpu.l2cache.overall_misses::total        27470                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     42142000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data    151082000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    193224000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    748717000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    748717000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     42142000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    899799000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    941941000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     42142000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    899799000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    941941000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst         1362                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data       200067                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total       201429                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       442952                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       442952                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       262052                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       262052                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         1362                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       462119                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       463481                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         1362                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       462119                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       463481                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.903818                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.022188                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.028149                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.083190                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.083190                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.903818                       # miss rate for demand accesses
+system.cpu.l2cache.occ_blocks::writebacks 20744.483714                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst    995.293943                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    641.616510                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.633071                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.030374                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.019581                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.683026                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst          137                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data       195649                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         195786                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       442976                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       442976                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       240248                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       240248                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst          137                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       435897                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          436034                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst          137                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       435897                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         436034                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         1228                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data         4437                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total         5665                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data        21803                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total        21803                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         1228                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data        26240                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total         27468                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         1228                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data        26240                       # number of overall misses
+system.cpu.l2cache.overall_misses::total        27468                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     42725500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data    151899500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    194625000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    842839500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    842839500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     42725500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    994739000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   1037464500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     42725500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    994739000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   1037464500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst         1365                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data       200086                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       201451                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       442976                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       442976                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       262051                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       262051                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         1365                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       462137                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       463502                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         1365                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       462137                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       463502                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.899634                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.022175                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.028121                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.083201                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.083201                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.899634                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.056780                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.059269                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.903818                       # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::total     0.059262                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.899634                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.056780                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.059269                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34233.956133                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34035.143050                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 34078.306878                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34344.816514                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34344.816514                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34233.956133                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34292.427303                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 34289.807062                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34233.956133                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34292.427303                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 34289.807062                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total     0.059262                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34792.752443                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34234.730674                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 34355.692851                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 38657.042609                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 38657.042609                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34792.752443                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 37909.260671                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 37769.932285                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34792.752443                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 37909.260671                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 37769.932285                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -605,52 +605,52 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks         2557                       # number of writebacks
-system.cpu.l2cache.writebacks::total             2557                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         1231                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data         4439                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         5670                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        21800                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total        21800                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         1231                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data        26239                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total        27470                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         1231                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data        26239                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total        27470                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     38155500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    137662500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    175818000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    681082000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    681082000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     38155500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    818744500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    856900000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     38155500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    818744500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    856900000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.903818                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.022188                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.028149                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.083190                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.083190                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.903818                       # mshr miss rate for demand accesses
+system.cpu.l2cache.writebacks::writebacks         2554                       # number of writebacks
+system.cpu.l2cache.writebacks::total             2554                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         1228                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data         4437                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         5665                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        21803                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        21803                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         1228                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data        26240                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        27468                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         1228                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data        26240                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total        27468                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     38798500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    138491500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    177290000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    776754500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    776754500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     38798500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    915246000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    954044500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     38798500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    915246000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    954044500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.899634                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.022175                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.028121                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.083201                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.083201                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.899634                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.056780                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.059269                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.903818                       # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.059262                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.899634                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.056780                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.059269                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 30995.532088                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31012.052264                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31008.465608                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31242.293578                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31242.293578                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 30995.532088                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31203.342353                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31194.029851                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 30995.532088                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31203.342353                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31194.029851                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.059262                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31594.869707                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31212.869056                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31295.675199                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35626.037701                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35626.037701                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31594.869707                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34879.801829                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34732.943789                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31594.869707                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34879.801829                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34732.943789                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini
index e273f1b51..ed5d7509c 100644
--- a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini
@@ -148,7 +148,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
@@ -180,7 +180,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout
index a6ed8a59a..7b12cccb1 100755
--- a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:06:58
-gem5 started Jun 28 2012 22:54:27
+gem5 compiled Jul  2 2012 08:54:18
+gem5 started Jul  2 2012 12:13:11
 gem5 executing on zizzer
 command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
@@ -38,4 +38,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 2061521023000 because target called exit()
+Exiting @ tick 2063177751000 because target called exit()
diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt
index 921624c02..607412a81 100644
--- a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.061521                       # Number of seconds simulated
-sim_ticks                                2061521023000                       # Number of ticks simulated
-final_tick                               2061521023000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.063178                       # Number of seconds simulated
+sim_ticks                                2063177751000                       # Number of ticks simulated
+final_tick                               2063177751000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2065708                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2071849                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2867468443                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 221124                       # Number of bytes of host memory used
-host_seconds                                   718.93                       # Real time elapsed on the host
+host_inst_rate                                1349558                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1353570                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1874864984                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 222108                       # Number of bytes of host memory used
+host_seconds                                  1100.44                       # Real time elapsed on the host
 sim_insts                                  1485108101                       # Number of instructions simulated
 sim_ops                                    1489523295                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             65728                       # Number of bytes read from this memory
@@ -23,19 +23,19 @@ system.physmem.num_reads::cpu.data              26134                       # Nu
 system.physmem.num_reads::total                 27161                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks            2523                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                 2523                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                31883                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data               811331                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                  843214                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           31883                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              31883                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks             78327                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                  78327                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks             78327                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               31883                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data              811331                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                 921541                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst                31858                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data               810680                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                  842537                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           31858                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              31858                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks             78264                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                  78264                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks             78264                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               31858                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data              810680                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                 920801                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   49                       # Number of system calls
-system.cpu.numCycles                       4123042046                       # number of cpu cycles simulated
+system.cpu.numCycles                       4126355502                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                  1485108101                       # Number of instructions committed
@@ -54,18 +54,18 @@ system.cpu.num_mem_refs                     569365767                       # nu
 system.cpu.num_load_insts                   402515346                       # Number of load instructions
 system.cpu.num_store_insts                  166850421                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                 4123042046                       # Number of busy cycles
+system.cpu.num_busy_cycles                 4126355502                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                    118                       # number of replacements
-system.cpu.icache.tagsinuse                906.456939                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                906.409372                       # Cycle average of tags in use
 system.cpu.icache.total_refs               1485111905                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                   1107                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               1341564.503162                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     906.456939                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.442606                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.442606                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst     906.409372                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.442583                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.442583                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst   1485111905                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total      1485111905                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst    1485111905                       # number of demand (read+write) hits
@@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst         1107                       # n
 system.cpu.icache.demand_misses::total           1107                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst         1107                       # number of overall misses
 system.cpu.icache.overall_misses::total          1107                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     58632000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     58632000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     58632000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     58632000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     58632000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     58632000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     58777000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     58777000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     58777000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     58777000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     58777000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     58777000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst   1485113012                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total   1485113012                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst   1485113012                       # number of demand (read+write) accesses
@@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000001
 system.cpu.icache.demand_miss_rate::total     0.000001                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000001                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000001                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52964.769648                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 52964.769648                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 52964.769648                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 52964.769648                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 52964.769648                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 52964.769648                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53095.754291                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 53095.754291                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 53095.754291                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 53095.754291                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 53095.754291                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 53095.754291                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -116,34 +116,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst         1107
 system.cpu.icache.demand_mshr_misses::total         1107                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst         1107                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total         1107                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     55311000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     55311000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     55311000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     55311000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     55311000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     55311000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     55456000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     55456000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     55456000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     55456000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     55456000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     55456000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000001                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000001                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000001                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000001                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000001                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000001                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49964.769648                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49964.769648                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49964.769648                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 49964.769648                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49964.769648                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 49964.769648                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50095.754291                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50095.754291                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50095.754291                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 50095.754291                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50095.754291                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 50095.754291                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                 449125                       # number of replacements
-system.cpu.dcache.tagsinuse               4095.226004                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               4095.205153                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                568907765                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                 453221                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                1255.254644                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              566952000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4095.226004                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.999811                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.999811                       # Average percentage of cache occupancy
+system.cpu.dcache.warmup_cycle              588945000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4095.205153                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.999806                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.999806                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data    402319358                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total       402319358                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data    166587088                       # number of WriteReq hits
@@ -164,16 +164,16 @@ system.cpu.dcache.demand_misses::cpu.data       453214                       # n
 system.cpu.dcache.demand_misses::total         453214                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data       453214                       # number of overall misses
 system.cpu.dcache.overall_misses::total        453214                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   2888312000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   2888312000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   4554270000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   4554270000                       # number of WriteReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   2888728000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   2888728000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   4554574000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   4554574000                       # number of WriteReq miss cycles
 system.cpu.dcache.SwapReq_miss_latency::cpu.data       140000                       # number of SwapReq miss cycles
 system.cpu.dcache.SwapReq_miss_latency::total       140000                       # number of SwapReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data   7442582000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total   7442582000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data   7442582000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total   7442582000                       # number of overall miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data   7443302000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total   7443302000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data   7443302000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total   7443302000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data    402512844                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total    402512844                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    166846816                       # number of WriteReq accesses(hits+misses)
@@ -194,16 +194,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.000796
 system.cpu.dcache.demand_miss_rate::total     0.000796                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.000796                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.000796                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14927.757047                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14927.757047                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17534.767141                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 17534.767141                       # average WriteReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14929.907073                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14929.907073                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17535.937596                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 17535.937596                       # average WriteReq miss latency
 system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data        20000                       # average SwapReq miss latency
 system.cpu.dcache.SwapReq_avg_miss_latency::total        20000                       # average SwapReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 16421.783087                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 16421.783087                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 16421.783087                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 16421.783087                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 16423.371741                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 16423.371741                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 16423.371741                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 16423.371741                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -224,16 +224,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data       453214
 system.cpu.dcache.demand_mshr_misses::total       453214                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data       453214                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total       453214                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   2307854000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   2307854000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   3775086000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   3775086000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   2308270000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   2308270000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   3775390000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   3775390000                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data       119000                       # number of SwapReq MSHR miss cycles
 system.cpu.dcache.SwapReq_mshr_miss_latency::total       119000                       # number of SwapReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data   6082940000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total   6082940000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data   6082940000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total   6082940000                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   6083660000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   6083660000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data   6083660000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   6083660000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000481                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000481                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.001557                       # mshr miss rate for WriteReq accesses
@@ -244,30 +244,30 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000796
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000796                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000796                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000796                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11927.757047                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11927.757047                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14534.767141                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14534.767141                       # average WriteReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11929.907073                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11929.907073                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14535.937596                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14535.937596                       # average WriteReq mshr miss latency
 system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data        17000                       # average SwapReq mshr miss latency
 system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total        17000                       # average SwapReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13421.783087                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 13421.783087                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13421.783087                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 13421.783087                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13423.371741                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 13423.371741                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13423.371741                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 13423.371741                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                  2614                       # number of replacements
-system.cpu.l2cache.tagsinuse             22186.870278                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse             22185.384662                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                  527657                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                 23998                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                 21.987541                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 20830.127393                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst    857.488075                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data    499.254810                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.635685                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst     0.026168                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.015236                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.677090                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::writebacks 20828.536366                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst    857.441703                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    499.406594                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.635636                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.026167                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.015241                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.677044                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst           80                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data       189212                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total         189292                       # number of ReadReq hits
diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini
index 994a9cc44..9d85601cf 100644
--- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini
@@ -500,7 +500,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
@@ -532,7 +532,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
 slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
 
diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout
index 486e549a7..e9fade7f1 100755
--- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout
+++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:08:09
-gem5 started Jun 28 2012 23:06:37
+gem5 compiled Jul  2 2012 08:58:39
+gem5 started Jul  2 2012 12:44:41
 gem5 executing on zizzer
 command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
@@ -24,6 +24,7 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Compressing Input Data, level 5
+info: Increasing stack size by one page.
 Compressed data 83382 bytes in length
 Uncompressing Data
 Uncompressed data 1048576 bytes in length
@@ -39,4 +40,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 636762784500 because target called exit()
+Exiting @ tick 636963896500 because target called exit()
diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt
index 608862386..5a09d9960 100644
--- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt
@@ -1,171 +1,171 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.636763                       # Number of seconds simulated
-sim_ticks                                636762784500                       # Number of ticks simulated
-final_tick                               636762784500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.636964                       # Number of seconds simulated
+sim_ticks                                636963896500                       # Number of ticks simulated
+final_tick                               636963896500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 102830                       # Simulator instruction rate (inst/s)
-host_op_rate                                   189469                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               74404788                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 230588                       # Number of bytes of host memory used
-host_seconds                                  8558.09                       # Real time elapsed on the host
+host_inst_rate                                  94339                       # Simulator instruction rate (inst/s)
+host_op_rate                                   173825                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               68282764                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 230548                       # Number of bytes of host memory used
+host_seconds                                  9328.33                       # Real time elapsed on the host
 sim_insts                                   880025312                       # Number of instructions simulated
 sim_ops                                    1621493982                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst             58816                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           1694912                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              1753728                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        58816                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           58816                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks       162944                       # Number of bytes written to this memory
-system.physmem.bytes_written::total            162944                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst                919                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data              26483                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                 27402                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks            2546                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                 2546                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                92367                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              2661764                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2754131                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           92367                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              92367                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks            255894                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                 255894                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks            255894                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               92367                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             2661764                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3010025                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst             59072                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           1694720                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              1753792                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        59072                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           59072                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks       162752                       # Number of bytes written to this memory
+system.physmem.bytes_written::total            162752                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst                923                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data              26480                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                 27403                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks            2543                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                 2543                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst                92740                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              2660622                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2753362                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           92740                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              92740                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks            255512                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                 255512                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks            255512                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               92740                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             2660622                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3008874                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   48                       # Number of system calls
-system.cpu.numCycles                       1273525570                       # number of cpu cycles simulated
+system.cpu.numCycles                       1273927794                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                155344135                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted          155344135                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect           26655607                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups              77245204                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                 76889704                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                155476696                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted          155476696                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect           26665974                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              76215157                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                 75849392                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
 system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles          180802236                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     1488442027                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   155344135                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           76889704                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     402274046                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                93385401                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles              623851243                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                  135                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          1029                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                 186094276                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               8755292                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples         1273499648                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.998943                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.233820                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          180766435                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1491872316                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   155476696                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           75849392                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     402325403                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                93614087                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles              624018674                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                  140                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles          1031                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                 185889439                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               8548075                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples         1273900868                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.002953                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.238276                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                878442365     68.98%     68.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 24602632      1.93%     70.91% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 15260428      1.20%     72.11% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 18256548      1.43%     73.54% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 26724815      2.10%     75.64% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 18280477      1.44%     77.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 29063774      2.28%     79.36% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 39873032      3.13%     82.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                222995577     17.51%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                878792706     68.98%     68.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 24409433      1.92%     70.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 14960209      1.17%     72.07% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 18025508      1.41%     73.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 26731742      2.10%     75.59% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 18277101      1.43%     77.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 28493019      2.24%     79.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 39802935      3.12%     82.38% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                224408215     17.62%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1273499648                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.121980                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.168757                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                300474409                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             536583689                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 281514067                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              88356524                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               66570959                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts             2368586772                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles               66570959                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                352813558                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles               123796819                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           1672                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 302654861                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles             427661779                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             2273830132                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                     2                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents              293323791                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents             102919235                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents               68                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands          3464511326                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            7120107939                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       7120100187                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups              7752                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total           1273900868                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.122045                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.171081                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                300130332                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             537055352                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 281851498                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              88074501                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               66789185                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts             2370363864                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles               66789185                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                352614235                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               124117956                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           1807                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 302560946                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             427816739                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             2274265358                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                     5                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents              293377579                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents             103041568                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents              112                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands          3464406080                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            7122244281                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       7122237233                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups              7048                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps            2493860970                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                970650356                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                 98                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts             98                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 745542263                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            545308074                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           222233244                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads         351719357                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores        147016761                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 2026127683                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                 554                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1785922004                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            133826                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       404499601                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined   1046828617                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            504                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples    1273499648                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.402373                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.312278                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                970545110                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                 88                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts             88                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 745535849                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            545979333                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           222242756                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads         352158228                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores        146951837                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 2027253751                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                 556                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1785885865                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            143298                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       405620982                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined   1049961378                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            506                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    1273900868                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.401903                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.311945                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           346409167     27.20%     27.20% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           447658448     35.15%     62.35% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           243252093     19.10%     81.45% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           151077765     11.86%     93.32% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            40789672      3.20%     96.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            32618177      2.56%     99.08% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             9933898      0.78%     99.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             1410310      0.11%     99.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              350118      0.03%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           346798223     27.22%     27.22% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           447596849     35.14%     62.36% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           243149127     19.09%     81.45% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           151409869     11.89%     93.33% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            40759247      3.20%     96.53% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            32504128      2.55%     99.08% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             9931846      0.78%     99.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             1400181      0.11%     99.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              351398      0.03%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      1273499648                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1273900868                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  252918      9.83%      9.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      9.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      9.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      9.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      9.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      9.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      9.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      9.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      9.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      9.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      9.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      9.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      9.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      9.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      9.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      9.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      9.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      9.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      9.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      9.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      9.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      9.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      9.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      9.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      9.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      9.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      9.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      9.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      9.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                2142956     83.30%     93.13% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                176798      6.87%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  262837     10.20%     10.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     10.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     10.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     10.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     10.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     10.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     10.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     10.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     10.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     10.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     10.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     10.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     10.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     10.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     10.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     10.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     10.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     10.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     10.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     10.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     10.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     10.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     10.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     10.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     10.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     10.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     10.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     10.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     10.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                2136217     82.89%     93.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                178017      6.91%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass          46813783      2.62%      2.62% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1067070411     59.75%     62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass          46812745      2.62%      2.62% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1067077874     59.75%     62.37% # Type of FU issued
 system.cpu.iq.FU_type_0::IntMult                    0      0.00%     62.37% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     62.37% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     62.37% # Type of FU issued
@@ -194,86 +194,86 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     62.37% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     62.37% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     62.37% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     62.37% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            479563179     26.85%     89.22% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           192474631     10.78%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            479524386     26.85%     89.22% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           192470860     10.78%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1785922004                       # Type of FU issued
-system.cpu.iq.rate                           1.402345                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     2572672                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.001441                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         4848049464                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        2430808619                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1727155501                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 690                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes               2256                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses           76                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             1741680668                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     225                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads        208913373                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             1785885865                       # Type of FU issued
+system.cpu.iq.rate                           1.401874                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2577071                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.001443                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         4848392282                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        2433055974                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1727031567                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 685                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes               2066                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses           68                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             1741649976                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     215                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads        208887212                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    126265949                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        36209                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       190191                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     34047187                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads    126937208                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        36775                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       189921                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     34056699                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads         1764                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads         2072                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked           462                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               66570959                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                  346337                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                 84829                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          2026128237                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts          63751416                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             545308074                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            222233244                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                 86                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  49329                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                   412                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         190191                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        2137841                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect     24642910                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             26780751                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            1767814472                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             473818516                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          18107532                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles               66789185                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                  397482                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                 85620                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          2027254307                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts          63893728                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             545979333                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            222242756                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                 83                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  48032                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                   669                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         189921                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        2137684                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect     24653436                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             26791120                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1767797184                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             473889834                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          18088681                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                    665662363                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                109724389                       # Number of branches executed
-system.cpu.iew.exec_stores                  191843847                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.388126                       # Inst execution rate
-system.cpu.iew.wb_sent                     1728501294                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    1727155577                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1262384078                       # num instructions producing a value
-system.cpu.iew.wb_consumers                2985492726                       # num instructions consuming a value
+system.cpu.iew.exec_refs                    665730625                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                109718993                       # Number of branches executed
+system.cpu.iew.exec_stores                  191840791                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.387675                       # Inst execution rate
+system.cpu.iew.wb_sent                     1728379028                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1727031635                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1262282896                       # num instructions producing a value
+system.cpu.iew.wb_consumers                2985352291                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.356200                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.422839                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.355675                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.422825                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts      880025312                       # The number of committed instructions
 system.cpu.commit.commitCommittedOps       1621493982                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts       404636626                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       405765098                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              50                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts          26655738                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples   1206928689                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.343488                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.659364                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts          26666115                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   1207111683                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.343284                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.660206                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    436768152     36.19%     36.19% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    432905754     35.87%     72.06% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     93527824      7.75%     79.81% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3    134952786     11.18%     90.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     35694459      2.96%     93.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     23721563      1.97%     95.91% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     25354378      2.10%     98.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      8867881      0.73%     98.75% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     15135892      1.25%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    437166011     36.22%     36.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    432802967     35.85%     72.07% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     93484629      7.74%     79.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3    134841213     11.17%     90.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     35727207      2.96%     93.95% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     23483214      1.95%     95.89% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     25551681      2.12%     98.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      8874954      0.74%     98.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     15179807      1.26%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   1206928689                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total   1207111683                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            880025312                       # Number of instructions committed
 system.cpu.commit.committedOps             1621493982                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -284,68 +284,68 @@ system.cpu.commit.branches                  107161579                       # Nu
 system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                1621354492                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                    0                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events              15135892                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events              15179807                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   3217923405                       # The number of ROB reads
-system.cpu.rob.rob_writes                  4118849074                       # The number of ROB writes
-system.cpu.timesIdled                             528                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           25922                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                   3219190956                       # The number of ROB reads
+system.cpu.rob.rob_writes                  4121324121                       # The number of ROB writes
+system.cpu.timesIdled                             604                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           26926                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   880025312                       # Number of Instructions Simulated
 system.cpu.committedOps                    1621493982                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total             880025312                       # Number of Instructions Simulated
-system.cpu.cpi                               1.447147                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.447147                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.691015                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.691015                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               4473867691                       # number of integer regfile reads
-system.cpu.int_regfile_writes              2590130278                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                        76                       # number of floating regfile reads
-system.cpu.misc_regfile_reads               911455321                       # number of misc regfile reads
-system.cpu.icache.replacements                     19                       # number of replacements
-system.cpu.icache.tagsinuse                827.665584                       # Cycle average of tags in use
-system.cpu.icache.total_refs                186092930                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                    926                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs               200964.287257                       # Average number of references to valid blocks.
+system.cpu.cpi                               1.447604                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.447604                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.690797                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.690797                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               4473882728                       # number of integer regfile reads
+system.cpu.int_regfile_writes              2589957068                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                        68                       # number of floating regfile reads
+system.cpu.misc_regfile_reads               911502074                       # number of misc regfile reads
+system.cpu.icache.replacements                     17                       # number of replacements
+system.cpu.icache.tagsinuse                828.056964                       # Cycle average of tags in use
+system.cpu.icache.total_refs                185888078                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    930                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               199879.653763                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     827.665584                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.404134                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.404134                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst    186092930                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       186092930                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     186092930                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        186092930                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    186092930                       # number of overall hits
-system.cpu.icache.overall_hits::total       186092930                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         1346                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          1346                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         1346                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           1346                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         1346                       # number of overall misses
-system.cpu.icache.overall_misses::total          1346                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     45797000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     45797000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     45797000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     45797000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     45797000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     45797000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    186094276                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    186094276                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    186094276                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    186094276                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    186094276                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    186094276                       # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::cpu.inst     828.056964                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.404325                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.404325                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst    185888078                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       185888078                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     185888078                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        185888078                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    185888078                       # number of overall hits
+system.cpu.icache.overall_hits::total       185888078                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1361                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1361                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1361                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1361                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1361                       # number of overall misses
+system.cpu.icache.overall_misses::total          1361                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     47861000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     47861000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     47861000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     47861000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     47861000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     47861000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    185889439                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    185889439                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    185889439                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    185889439                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    185889439                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    185889439                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000007                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000007                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000007                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000007                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000007                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000007                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34024.517088                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 34024.517088                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 34024.517088                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 34024.517088                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 34024.517088                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 34024.517088                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35166.054372                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 35166.054372                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 35166.054372                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 35166.054372                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 35166.054372                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 35166.054372                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -354,94 +354,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          420                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          420                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          420                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          420                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          420                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          420                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          926                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          926                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          926                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          926                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          926                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          926                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     32563500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     32563500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     32563500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     32563500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     32563500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     32563500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          431                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          431                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          431                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          431                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          431                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          431                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          930                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          930                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          930                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          930                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          930                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          930                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     34220000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     34220000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     34220000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     34220000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     34220000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     34220000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000005                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000005                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000005                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000005                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000005                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000005                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35165.766739                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35165.766739                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35165.766739                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 35165.766739                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35165.766739                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 35165.766739                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36795.698925                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36795.698925                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36795.698925                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 36795.698925                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36795.698925                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 36795.698925                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                 445434                       # number of replacements
-system.cpu.dcache.tagsinuse               4093.513761                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                452635366                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                 449530                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                1006.908028                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              723815000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4093.513761                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.999393                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.999393                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data    264695512                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       264695512                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    187939854                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      187939854                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data     452635366                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        452635366                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    452635366                       # number of overall hits
-system.cpu.dcache.overall_hits::total       452635366                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       206467                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        206467                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       246203                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       246203                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data       452670                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         452670                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       452670                       # number of overall misses
-system.cpu.dcache.overall_misses::total        452670                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   1238244500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   1238244500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   2014411000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   2014411000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data   3252655500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total   3252655500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data   3252655500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total   3252655500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    264901979                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    264901979                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.replacements                 445433                       # number of replacements
+system.cpu.dcache.tagsinuse               4093.428364                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                452731874                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 449529                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                1007.124955                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              738592000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4093.428364                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.999372                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.999372                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data    264792027                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       264792027                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    187939847                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      187939847                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     452731874                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        452731874                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    452731874                       # number of overall hits
+system.cpu.dcache.overall_hits::total       452731874                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       206669                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        206669                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       246210                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       246210                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data       452879                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         452879                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       452879                       # number of overall misses
+system.cpu.dcache.overall_misses::total        452879                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   1300622500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   1300622500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   2040839000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   2040839000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data   3341461500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total   3341461500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data   3341461500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total   3341461500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    264998696                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    264998696                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    188186057                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    188186057                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    453088036                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    453088036                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    453088036                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    453088036                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000779                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.000779                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data    453184753                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    453184753                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    453184753                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    453184753                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000780                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.000780                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001308                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.001308                       # miss rate for WriteReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.000999                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     0.000999                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.000999                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.000999                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data  5997.299811                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total  5997.299811                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data  8181.910862                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total  8181.910862                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data  7185.489429                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total  7185.489429                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data  7185.489429                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total  7185.489429                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data  6293.263624                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total  6293.263624                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data  8289.017505                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total  8289.017505                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data  7378.265497                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total  7378.265497                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data  7378.265497                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total  7378.265497                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -450,132 +450,132 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       428484                       # number of writebacks
-system.cpu.dcache.writebacks::total            428484                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data         3123                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total         3123                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data           15                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total           15                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data         3138                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total         3138                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data         3138                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total         3138                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       203344                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       203344                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       246188                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       246188                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       449532                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       449532                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       449532                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       449532                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    611389500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total    611389500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1275715500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   1275715500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data   1887105000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total   1887105000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data   1887105000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total   1887105000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000768                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000768                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.writebacks::writebacks       428496                       # number of writebacks
+system.cpu.dcache.writebacks::total            428496                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data         3328                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total         3328                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data           20                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total           20                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data         3348                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total         3348                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data         3348                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total         3348                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       203341                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       203341                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       246190                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       246190                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       449531                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       449531                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       449531                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       449531                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    607771500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total    607771500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1249776500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   1249776500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   1857548000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   1857548000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data   1857548000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   1857548000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000767                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000767                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.001308                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.001308                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000992                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000992                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000992                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000992                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  3006.675879                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  3006.675879                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  5181.875234                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  5181.875234                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  4197.932516                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total  4197.932516                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  4197.932516                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total  4197.932516                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  2988.927467                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  2988.927467                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  5076.471425                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  5076.471425                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  4132.191106                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total  4132.191106                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  4132.191106                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total  4132.191106                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.replacements                  2662                       # number of replacements
-system.cpu.l2cache.tagsinuse             22222.846443                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                  517815                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                 24238                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                 21.363768                       # Average number of references to valid blocks.
+system.cpu.l2cache.replacements                  2658                       # number of replacements
+system.cpu.l2cache.tagsinuse             22224.770293                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                  517694                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                 24236                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                 21.360538                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 20810.359304                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst    736.556866                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data    675.930273                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.635082                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst     0.022478                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.020628                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.678187                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::writebacks 20809.314009                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst    737.283312                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    678.172973                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.635050                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.022500                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.020696                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.678246                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst            7                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data       198774                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total         198781                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       428484                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       428484                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       224275                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       224275                       # number of ReadExReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data       198771                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         198778                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       428496                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       428496                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       224280                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       224280                       # number of ReadExReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            7                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       423049                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          423056                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       423051                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          423058                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst            7                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       423049                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         423056                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          919                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data         4560                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         5479                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data        21923                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total        21923                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          919                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data        26483                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total         27402                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          919                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data        26483                       # number of overall misses
-system.cpu.l2cache.overall_misses::total        27402                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     31495500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data    157147500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    188643000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    753146000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    753146000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     31495500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    910293500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    941789000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     31495500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    910293500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    941789000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          926                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data       203334                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total       204260                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       428484                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       428484                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       246198                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       246198                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          926                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       449532                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       450458                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          926                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       449532                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       450458                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.992441                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.022426                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.026824                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.089046                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.089046                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.992441                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.058912                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.060831                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.992441                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.058912                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.060831                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34271.490751                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34462.171053                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 34430.187991                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34354.148611                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34354.148611                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34271.490751                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34372.748556                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 34369.352602                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34271.490751                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34372.748556                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 34369.352602                       # average overall miss latency
+system.cpu.l2cache.overall_hits::cpu.data       423051                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         423058                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          923                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data         4558                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total         5481                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data        21922                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total        21922                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          923                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data        26480                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total         27403                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          923                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data        26480                       # number of overall misses
+system.cpu.l2cache.overall_misses::total        27403                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     32677500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data    156724000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    189401500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    752017500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    752017500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     32677500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    908741500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    941419000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     32677500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    908741500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    941419000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          930                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data       203329                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       204259                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       428496                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       428496                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       246202                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       246202                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          930                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       449531                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       450461                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          930                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       449531                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       450461                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.992473                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.022417                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.026834                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.089041                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.089041                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.992473                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.058906                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.060833                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.992473                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.058906                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.060833                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35403.575298                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34384.379114                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 34556.011677                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34304.237752                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34304.237752                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35403.575298                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34318.032477                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 34354.596212                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35403.575298                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34318.032477                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 34354.596212                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -584,52 +584,52 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks         2546                       # number of writebacks
-system.cpu.l2cache.writebacks::total             2546                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          919                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data         4560                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         5479                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        21923                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total        21923                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          919                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data        26483                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total        27402                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          919                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data        26483                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total        27402                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     28532500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    141346000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    169878500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    679632500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    679632500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     28532500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    820978500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    849511000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     28532500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    820978500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    849511000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.992441                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.022426                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.026824                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.089046                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.089046                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.992441                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.058912                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.060831                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.992441                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.058912                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.060831                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31047.334059                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30996.929825                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31005.384194                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.889477                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31000.889477                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31047.334059                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31000.207680                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31001.788191                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31047.334059                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31000.207680                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31001.788191                       # average overall mshr miss latency
+system.cpu.l2cache.writebacks::writebacks         2543                       # number of writebacks
+system.cpu.l2cache.writebacks::total             2543                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          923                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data         4558                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         5481                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        21922                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        21922                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          923                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data        26480                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        27403                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          923                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data        26480                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total        27403                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     29745000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    141788500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    171533500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    679883500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    679883500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     29745000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    821672000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    851417000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     29745000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    821672000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    851417000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.992473                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.022417                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.026834                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.089041                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.089041                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.992473                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.058906                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.060833                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.992473                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.058906                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.060833                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32226.435536                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31107.612988                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31296.022624                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31013.753307                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31013.753307                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32226.435536                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31029.909366                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31070.211291                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32226.435536                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31029.909366                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31070.211291                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini
index 3c1333558..2eec436ef 100644
--- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini
@@ -169,7 +169,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
@@ -201,7 +201,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
 slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
 
diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout
index 9e79ba165..d6878297d 100755
--- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout
+++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:08:09
-gem5 started Jun 28 2012 23:10:36
+gem5 compiled Jul  2 2012 08:58:39
+gem5 started Jul  2 2012 13:03:08
 gem5 executing on zizzer
 command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
@@ -39,4 +39,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 1800635309000 because target called exit()
+Exiting @ tick 1801979727000 because target called exit()
diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt
index a3d141ce0..79bdadab4 100644
--- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.800635                       # Number of seconds simulated
-sim_ticks                                1800635309000                       # Number of ticks simulated
-final_tick                               1800635309000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.801980                       # Number of seconds simulated
+sim_ticks                                1801979727000                       # Number of ticks simulated
+final_tick                               1801979727000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 904173                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1665987                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1850044030                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 228536                       # Number of bytes of host memory used
-host_seconds                                   973.29                       # Real time elapsed on the host
+host_inst_rate                                 622629                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1147227                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1274922997                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 228496                       # Number of bytes of host memory used
+host_seconds                                  1413.40                       # Real time elapsed on the host
 sim_insts                                   880025313                       # Number of instructions simulated
 sim_ops                                    1621493983                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             46208                       # Number of bytes read from this memory
@@ -23,19 +23,19 @@ system.physmem.num_reads::cpu.data              26287                       # Nu
 system.physmem.num_reads::total                 27009                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks            2510                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                 2510                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                25662                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data               934319                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                  959981                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           25662                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              25662                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks             89213                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                  89213                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks             89213                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               25662                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data              934319                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                1049194                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst                25643                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data               933622                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                  959265                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           25643                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              25643                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks             89146                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                  89146                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks             89146                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               25643                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data              933622                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                1048411                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   48                       # Number of system calls
-system.cpu.numCycles                       3601270618                       # number of cpu cycles simulated
+system.cpu.numCycles                       3603959454                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   880025313                       # Number of instructions committed
@@ -54,18 +54,18 @@ system.cpu.num_mem_refs                     607228182                       # nu
 system.cpu.num_load_insts                   419042125                       # Number of load instructions
 system.cpu.num_store_insts                  188186057                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                 3601270618                       # Number of busy cycles
+system.cpu.num_busy_cycles                 3603959454                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                      4                       # number of replacements
-system.cpu.icache.tagsinuse                660.189072                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                660.169533                       # Cycle average of tags in use
 system.cpu.icache.total_refs               1186516018                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    722                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               1643373.986150                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     660.189072                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.322358                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.322358                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst     660.169533                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.322348                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.322348                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst   1186516018                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total      1186516018                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst    1186516018                       # number of demand (read+write) hits
@@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst          722                       # n
 system.cpu.icache.demand_misses::total            722                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          722                       # number of overall misses
 system.cpu.icache.overall_misses::total           722                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     40432000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     40432000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     40432000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     40432000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     40432000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     40432000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     40521000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     40521000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     40521000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     40521000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     40521000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     40521000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst   1186516740                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total   1186516740                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst   1186516740                       # number of demand (read+write) accesses
@@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000001
 system.cpu.icache.demand_miss_rate::total     0.000001                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000001                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000001                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst        56000                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total        56000                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst        56000                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total        56000                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst        56000                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total        56000                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56123.268698                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 56123.268698                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 56123.268698                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 56123.268698                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 56123.268698                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 56123.268698                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -116,34 +116,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          722
 system.cpu.icache.demand_mshr_misses::total          722                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          722                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          722                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     38266000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     38266000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     38266000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     38266000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     38266000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     38266000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     38355000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     38355000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     38355000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     38355000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     38355000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     38355000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000001                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000001                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000001                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000001                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000001                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000001                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst        53000                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total        53000                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst        53000                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst        53000                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53123.268698                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53123.268698                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53123.268698                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 53123.268698                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53123.268698                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 53123.268698                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                 437952                       # number of replacements
-system.cpu.dcache.tagsinuse               4094.895332                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               4094.884021                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                606786134                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                 442048                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                1372.670239                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              778540000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4094.895332                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.999730                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.999730                       # Average percentage of cache occupancy
+system.cpu.dcache.warmup_cycle              788858000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4094.884021                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.999728                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.999728                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data    418844799                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total       418844799                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data    187941335                       # number of WriteReq hits
@@ -160,14 +160,14 @@ system.cpu.dcache.demand_misses::cpu.data       442048                       # n
 system.cpu.dcache.demand_misses::total         442048                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data       442048                       # number of overall misses
 system.cpu.dcache.overall_misses::total        442048                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   2943878000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   2943878000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   4348848000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   4348848000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data   7292726000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total   7292726000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data   7292726000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total   7292726000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   2948308000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   2948308000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   4362877000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   4362877000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data   7311185000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total   7311185000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data   7311185000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total   7311185000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data    419042125                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total    419042125                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    188186057                       # number of WriteReq accesses(hits+misses)
@@ -184,14 +184,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.000728
 system.cpu.dcache.demand_miss_rate::total     0.000728                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.000728                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.000728                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14918.855093                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14918.855093                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17770.564150                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 17770.564150                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 16497.588497                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 16497.588497                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 16497.588497                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 16497.588497                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14941.305251                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14941.305251                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17827.890423                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 17827.890423                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 16539.346406                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 16539.346406                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 16539.346406                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 16539.346406                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -210,14 +210,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data       442048
 system.cpu.dcache.demand_mshr_misses::total       442048                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data       442048                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total       442048                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   2351900000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   2351900000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   3614682000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   3614682000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data   5966582000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total   5966582000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data   5966582000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total   5966582000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   2356330000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   2356330000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   3628711000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   3628711000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   5985041000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   5985041000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data   5985041000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   5985041000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000471                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000471                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.001300                       # mshr miss rate for WriteReq accesses
@@ -226,28 +226,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000728
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000728                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000728                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000728                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11918.855093                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11918.855093                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14770.564150                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14770.564150                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13497.588497                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 13497.588497                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13497.588497                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 13497.588497                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11941.305251                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11941.305251                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14827.890423                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14827.890423                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13539.346406                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 13539.346406                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13539.346406                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 13539.346406                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                  2581                       # number of replacements
-system.cpu.l2cache.tagsinuse             22163.019096                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse             22161.849584                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                  506758                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                 23832                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                 21.263763                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 21019.596332                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst    596.850673                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data    546.572092                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.641467                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::writebacks 21018.400125                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst    596.832039                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    546.617420                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.641431                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.inst     0.018214                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.016680                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.676362                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.016681                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.676326                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.data       193009                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total         193009                       # number of ReadReq hits
 system.cpu.l2cache.Writeback_hits::writebacks       422980                       # number of Writeback hits
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
index 354c87304..a0763b2c7 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
@@ -497,7 +497,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
@@ -529,7 +529,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
index e2beccd27..48d145b85 100755
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:10:14
-gem5 started Jun 29 2012 00:41:22
+gem5 compiled Jul  2 2012 09:08:16
+gem5 started Jul  2 2012 15:39:45
 gem5 executing on zizzer
 command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
@@ -23,4 +23,4 @@ simplex iterations         : 2663
 flow value                 : 3080014995
 checksum                   : 68389
 optimal
-Exiting @ tick 25878583500 because target called exit()
+Exiting @ tick 28553466500 because target called exit()
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
index 507566fcc..8d85ceff7 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
@@ -1,32 +1,32 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.025879                       # Number of seconds simulated
-sim_ticks                                 25878583500                       # Number of ticks simulated
-final_tick                                25878583500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.028553                       # Number of seconds simulated
+sim_ticks                                 28553466500                       # Number of ticks simulated
+final_tick                                28553466500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 220420                       # Simulator instruction rate (inst/s)
-host_op_rate                                   222002                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               62960153                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 367872                       # Number of bytes of host memory used
-host_seconds                                   411.03                       # Real time elapsed on the host
-sim_insts                                    90599358                       # Number of instructions simulated
-sim_ops                                      91249911                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst             45504                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data            947456                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               992960                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        45504                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           45504                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                711                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data              14804                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                 15515                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              1758365                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             36611587                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                38369952                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         1758365                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1758365                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             1758365                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            36611587                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               38369952                       # Total bandwidth to/from this memory (bytes/s)
+host_inst_rate                                 181848                       # Simulator instruction rate (inst/s)
+host_op_rate                                   183154                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               57311644                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 367800                       # Number of bytes of host memory used
+host_seconds                                   498.21                       # Real time elapsed on the host
+sim_insts                                    90599368                       # Number of instructions simulated
+sim_ops                                      91249921                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst             45312                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data            947584                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               992896                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        45312                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           45312                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                708                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data              14806                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                 15514                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              1586918                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             33186303                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                34773221                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1586918                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1586918                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             1586918                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            33186303                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               34773221                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -70,322 +70,322 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  442                       # Number of system calls
-system.cpu.numCycles                         51757168                       # number of cpu cycles simulated
+system.cpu.numCycles                         57106934                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                 26984015                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted           22232491                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect             888214                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups              11580024                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                 11447482                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                 27012699                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           22277532                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect             889694                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              11653286                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                 11426819                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                    71474                       # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect                 416                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles           14414928                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      129560918                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    26984015                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           11518956                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      24378433                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 4928329                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles                8911472                       # Number of cycles fetch has spent blocked
+system.cpu.BPredUnit.usedRAS                    72452                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect                 358                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles           14542606                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      129803697                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    27012699                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           11499271                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      24399920                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 5015488                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               14039908                       # Number of cycles fetch has spent blocked
 system.cpu.fetch.MiscStallCycles                    1                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles            24                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                  14076190                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                379999                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples           51715551                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.525564                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.245999                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.PendingTrapStallCycles            27                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                  14144138                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                347071                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples           57042317                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.294103                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.179417                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 27375149     52.93%     52.93% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  3448740      6.67%     59.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  2025913      3.92%     63.52% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  1592010      3.08%     66.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  1693129      3.27%     69.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  2969374      5.74%     75.61% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  1533811      2.97%     78.58% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1107315      2.14%     80.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                  9970110     19.28%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 32680363     57.29%     57.29% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  3435885      6.02%     63.31% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  2022812      3.55%     66.86% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  1588688      2.79%     69.65% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  1698003      2.98%     72.62% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  3014546      5.28%     77.91% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  1479172      2.59%     80.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1109191      1.94%     82.45% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 10013657     17.55%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total             51715551                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.521358                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.503246                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 17151536                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles               6845661                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  22836822                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                879705                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                4001827                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              4473928                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                  9005                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              127743952                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                 42919                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                4001827                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 18918146                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 2041479                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         194552                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  21908799                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               4650748                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              124387508                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                    37                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 285864                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               3910791                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents              369                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           145115578                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             541729246                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        541723014                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups              6232                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             107429482                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 37686096                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts              18180                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts          18178                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  11273342                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             29662115                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores             5564551                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           2120620                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          1233720                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  118944023                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded               22020                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 105456921                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued             87203                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        27512358                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     68343356                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved          11890                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples      51715551                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.039172                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.917652                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total             57042317                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.473020                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.272994                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 17762369                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              11471319                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  22339470                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               1418238                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                4050921                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              4486769                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                  9087                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              127953392                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                 42856                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                4050921                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 19506799                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 5508085                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         206847                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  21544530                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               6225135                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              124612804                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                  1000                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 540301                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               4835980                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents            10850                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           145164650                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             542855215                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        542847680                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups              7535                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             107429498                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 37735152                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts              18216                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts          18214                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  14341922                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             29837938                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores             5556896                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           2142306                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          1236219                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  119143027                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               22051                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 105690693                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued             78779                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        27699280                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     68606056                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved          11919                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples      57042317                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.852847                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.854849                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            13904878     26.89%     26.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            11456546     22.15%     49.04% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             7969137     15.41%     64.45% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             6724396     13.00%     77.45% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             5314058     10.28%     87.73% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             2865211      5.54%     93.27% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             2534987      4.90%     98.17% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              474000      0.92%     99.09% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              472338      0.91%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            17381718     30.47%     30.47% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            13049544     22.88%     53.35% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             8518143     14.93%     68.28% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             6991208     12.26%     80.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             5292177      9.28%     89.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             2744999      4.81%     94.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             2144277      3.76%     98.39% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              490134      0.86%     99.25% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              430117      0.75%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total        51715551                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        57042317                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                   33403      5.02%      5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                     27      0.00%      5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      5.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                 354808     53.31%     58.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                277311     41.67%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   40944      6.13%      6.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                     27      0.00%      6.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      6.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      6.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      6.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      6.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      6.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      6.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      6.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      6.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      6.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      6.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      6.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      6.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      6.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      6.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      6.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      6.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      6.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      6.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      6.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      6.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      6.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      6.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      6.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      6.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      6.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      6.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      6.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 349072     52.27%     58.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                277751     41.59%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              74629419     70.77%     70.77% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                10524      0.01%     70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               2      0.00%     70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt             188      0.00%     70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc            232      0.00%     70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            2      0.00%     70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             25677872     24.35%     95.13% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             5138682      4.87%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              74708862     70.69%     70.69% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                10518      0.01%     70.70% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     70.70% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     70.70% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     70.70% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     70.70% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     70.70% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     70.70% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     70.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     70.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     70.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     70.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     70.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     70.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     70.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     70.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     70.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     70.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     70.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     70.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     70.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     70.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               2      0.00%     70.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt             221      0.00%     70.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     70.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc            275      0.00%     70.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     70.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            3      0.00%     70.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     70.70% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             25829491     24.44%     95.14% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             5141321      4.86%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              105456921                       # Type of FU issued
-system.cpu.iq.rate                           2.037533                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                      665549                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.006311                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          263381228                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         146480266                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    102833498                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 917                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes               1333                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses          399                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              106122017                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     453                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads           424644                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              105690693                       # Type of FU issued
+system.cpu.iq.rate                           1.850751                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                      667794                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.006318                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          269169203                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         146866507                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    102954305                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                1073                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes               1626                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses          453                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              106357959                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     528                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads           425504                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      7086237                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         8981                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation         4129                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores       817795                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      7262058                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         7178                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation         4608                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores       810138                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            2                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked         39333                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked        165527                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                4001827                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                  198669                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                 33921                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           119002430                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            339181                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              29662115                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts              5564551                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts              18117                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  13618                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                  1230                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents           4129                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         473445                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       489320                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               962765                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             104433557                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              25350982                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           1023364                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                4050921                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                  893670                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                117044                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           119201460                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            342636                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              29837938                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts              5556896                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts              18147                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  49262                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 15777                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents           4608                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         477903                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       486113                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               964016                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             104633146                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              25499061                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1057547                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                         36387                       # number of nop insts executed
-system.cpu.iew.exec_refs                     30425523                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 21334984                       # Number of branches executed
-system.cpu.iew.exec_stores                    5074541                       # Number of stores executed
-system.cpu.iew.exec_rate                     2.017760                       # Inst execution rate
-system.cpu.iew.wb_sent                      103141450                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     102833897                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  62142858                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 103855994                       # num instructions consuming a value
+system.cpu.iew.exec_nop                         36382                       # number of nop insts executed
+system.cpu.iew.exec_refs                     30575453                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 21352915                       # Number of branches executed
+system.cpu.iew.exec_stores                    5076392                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.832232                       # Inst execution rate
+system.cpu.iew.wb_sent                      103240911                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     102954758                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  61949538                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 102898807                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.986853                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.598356                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.802842                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.602043                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts       90611967                       # The number of committed instructions
-system.cpu.commit.commitCommittedOps         91262520                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts        27741223                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls           10130                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            891236                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples     47713725                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.912710                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.511102                       # Number of insts commited each cycle
+system.cpu.commit.commitCommittedInsts       90611977                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps         91262530                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts        27941572                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls           10132                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            892650                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples     52991397                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.722214                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.475842                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     17393373     36.45%     36.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     13510296     28.32%     64.77% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      4501215      9.43%     74.20% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      3866271      8.10%     82.31% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1517173      3.18%     85.49% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5       785983      1.65%     87.13% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       854820      1.79%     88.92% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       253298      0.53%     89.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      5031296     10.54%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     23013346     43.43%     43.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     13498664     25.47%     68.90% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      4267920      8.05%     76.96% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      3605539      6.80%     83.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1555941      2.94%     86.70% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5       706178      1.33%     88.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       916105      1.73%     89.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       261507      0.49%     90.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      5166197      9.75%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total     47713725                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts             90611967                       # Number of instructions committed
-system.cpu.commit.committedOps               91262520                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total     52991397                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts             90611977                       # Number of instructions committed
+system.cpu.commit.committedOps               91262530                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       27322634                       # Number of memory references committed
-system.cpu.commit.loads                      22575878                       # Number of loads committed
+system.cpu.commit.refs                       27322638                       # Number of memory references committed
+system.cpu.commit.loads                      22575880                       # Number of loads committed
 system.cpu.commit.membars                        3888                       # Number of memory barriers committed
-system.cpu.commit.branches                   18722472                       # Number of branches committed
+system.cpu.commit.branches                   18722474                       # Number of branches committed
 system.cpu.commit.fp_insts                         48                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                  72533322                       # Number of committed integer instructions.
+system.cpu.commit.int_insts                  72533330                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                56148                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events               5031296                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events               5166197                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    161680438                       # The number of ROB reads
-system.cpu.rob.rob_writes                   242031234                       # The number of ROB writes
-system.cpu.timesIdled                            1832                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           41617                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                    90599358                       # Number of Instructions Simulated
-system.cpu.committedOps                      91249911                       # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total              90599358                       # Number of Instructions Simulated
-system.cpu.cpi                               0.571275                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.571275                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.750470                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.750470                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                496537855                       # number of integer regfile reads
-system.cpu.int_regfile_writes               120784900                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                       199                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                      517                       # number of floating regfile writes
-system.cpu.misc_regfile_reads               183129525                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                  11608                       # number of misc regfile writes
-system.cpu.icache.replacements                      2                       # number of replacements
-system.cpu.icache.tagsinuse                635.708091                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 14075225                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                    737                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs               19097.998643                       # Average number of references to valid blocks.
+system.cpu.rob.rob_reads                    167023568                       # The number of ROB reads
+system.cpu.rob.rob_writes                   242480145                       # The number of ROB writes
+system.cpu.timesIdled                           16985                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           64617                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                    90599368                       # Number of Instructions Simulated
+system.cpu.committedOps                      91249921                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total              90599368                       # Number of Instructions Simulated
+system.cpu.cpi                               0.630324                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.630324                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.586486                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.586486                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                497500268                       # number of integer regfile reads
+system.cpu.int_regfile_writes               120842597                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                       229                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                      593                       # number of floating regfile writes
+system.cpu.misc_regfile_reads               183620284                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                  11612                       # number of misc regfile writes
+system.cpu.icache.replacements                      3                       # number of replacements
+system.cpu.icache.tagsinuse                638.455928                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 14143171                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    734                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               19268.625341                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     635.708091                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.310404                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.310404                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst     14075225                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        14075225                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      14075225                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         14075225                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     14075225                       # number of overall hits
-system.cpu.icache.overall_hits::total        14075225                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          965                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           965                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          965                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            965                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          965                       # number of overall misses
-system.cpu.icache.overall_misses::total           965                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     33626500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     33626500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     33626500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     33626500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     33626500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     33626500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     14076190                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     14076190                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     14076190                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     14076190                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     14076190                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     14076190                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000069                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000069                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000069                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000069                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000069                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000069                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34846.113990                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 34846.113990                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 34846.113990                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 34846.113990                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 34846.113990                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 34846.113990                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     638.455928                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.311746                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.311746                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst     14143171                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        14143171                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      14143171                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         14143171                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     14143171                       # number of overall hits
+system.cpu.icache.overall_hits::total        14143171                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          967                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           967                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          967                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            967                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          967                       # number of overall misses
+system.cpu.icache.overall_misses::total           967                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     35020500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     35020500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     35020500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     35020500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     35020500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     35020500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     14144138                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     14144138                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     14144138                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     14144138                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     14144138                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     14144138                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000068                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000068                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000068                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000068                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000068                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000068                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36215.615305                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 36215.615305                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 36215.615305                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 36215.615305                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 36215.615305                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 36215.615305                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -394,246 +394,246 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          228                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          228                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          228                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          228                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          228                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          228                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          737                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          737                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          737                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          737                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          737                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          737                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     25265000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     25265000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     25265000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     25265000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     25265000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     25265000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          233                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          233                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          233                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          233                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          233                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          233                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          734                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          734                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          734                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          734                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          734                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          734                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     26444000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     26444000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     26444000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     26444000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     26444000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     26444000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000052                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000052                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000052                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000052                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000052                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000052                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34280.868385                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34280.868385                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34280.868385                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 34280.868385                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34280.868385                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 34280.868385                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36027.247956                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36027.247956                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36027.247956                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 36027.247956                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36027.247956                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 36027.247956                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                 943587                       # number of replacements
-system.cpu.dcache.tagsinuse               3648.438272                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 28413602                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                 947683                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  29.982180                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle             8139620000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    3648.438272                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.890732                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.890732                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data     23842486                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        23842486                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      4559459                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        4559459                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data         5858                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total         5858                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data         5799                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total         5799                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      28401945                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         28401945                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     28401945                       # number of overall hits
-system.cpu.dcache.overall_hits::total        28401945                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1005618                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1005618                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       175522                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       175522                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data            7                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total            7                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      1181140                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1181140                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1181140                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1181140                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   5786835500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   5786835500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   4609409990                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   4609409990                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       130000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total       130000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  10396245490                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  10396245490                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  10396245490                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  10396245490                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     24848104                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     24848104                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.replacements                 943512                       # number of replacements
+system.cpu.dcache.tagsinuse               3689.791275                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 28381642                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 947608                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  29.950826                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle             8154700000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    3689.791275                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.900828                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.900828                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     23801988                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        23801988                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      4567984                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        4567984                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data         5869                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total         5869                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data         5801                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total         5801                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      28369972                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         28369972                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     28369972                       # number of overall hits
+system.cpu.dcache.overall_hits::total        28369972                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1060525                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1060525                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       166997                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       166997                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data            8                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total            8                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data      1227522                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1227522                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1227522                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1227522                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  21965060500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  21965060500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   6217004264                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   6217004264                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       153500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total       153500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  28182064764                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  28182064764                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  28182064764                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  28182064764                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     24862513                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     24862513                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data      4734981                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total      4734981                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data         5865                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total         5865                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data         5799                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total         5799                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     29583085                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     29583085                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     29583085                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     29583085                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.040471                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.040471                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037069                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.037069                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.001194                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.001194                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.039926                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.039926                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.039926                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.039926                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data  5754.506681                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total  5754.506681                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26261.152391                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 26261.152391                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18571.428571                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18571.428571                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data  8801.874028                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total  8801.874028                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data  8801.874028                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total  8801.874028                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs     23117548                       # number of cycles access was blocked
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data         5877                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total         5877                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data         5801                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total         5801                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     29597494                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     29597494                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     29597494                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     29597494                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.042656                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.042656                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.035269                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.035269                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.001361                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.001361                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.041474                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.041474                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.041474                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.041474                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20711.497136                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 20711.497136                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37228.239214                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 37228.239214                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19187.500000                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19187.500000                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 22958.500755                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 22958.500755                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 22958.500755                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 22958.500755                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs     78852438                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs              8084                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              9147                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs  2859.666997                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  8620.579206                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       942950                       # number of writebacks
-system.cpu.dcache.writebacks::total            942950                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       101118                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       101118                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       132339                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       132339                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            7                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total            7                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       233457                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       233457                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       233457                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       233457                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       904500                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       904500                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data        43183                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total        43183                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       947683                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       947683                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       947683                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       947683                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   2400819500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   2400819500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1075610609                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   1075610609                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data   3476430109                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total   3476430109                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data   3476430109                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total   3476430109                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.036401                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.036401                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009120                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009120                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.032035                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.032035                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.032035                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.032035                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  2654.305694                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  2654.305694                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24908.195563                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24908.195563                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  3668.347020                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total  3668.347020                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  3668.347020                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total  3668.347020                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks       942869                       # number of writebacks
+system.cpu.dcache.writebacks::total            942869                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       148009                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       148009                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       131905                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       131905                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            8                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total            8                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       279914                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       279914                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       279914                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       279914                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       912516                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       912516                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data        35092                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total        35092                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       947608                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       947608                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       947608                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       947608                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  16755802500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  16755802500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1751499399                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   1751499399                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  18507301899                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  18507301899                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  18507301899                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  18507301899                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.036702                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.036702                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.007411                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.007411                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.032016                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.032016                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.032016                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.032016                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18362.201320                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18362.201320                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49911.643651                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49911.643651                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19530.546280                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 19530.546280                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19530.546280                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 19530.546280                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse             10511.051990                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 1830916                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                 15498                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                118.138857                       # Average number of references to valid blocks.
+system.cpu.l2cache.tagsinuse             10958.956435                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 1839863                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                 15497                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                118.723818                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks  9660.066682                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst    620.063738                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data    230.921571                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.294802                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst     0.018923                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.007047                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.320772                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst           25                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data       903058                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total         903083                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       942950                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       942950                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data        29811                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total        29811                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst           25                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       932869                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          932894                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst           25                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       932869                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         932894                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          712                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data          278                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total          990                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data        14536                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total        14536                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          712                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data        14814                       # number of demand (read+write) misses
+system.cpu.l2cache.occ_blocks::writebacks 10102.128367                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst    622.173685                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    234.654384                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.308292                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.018987                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.007161                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.334441                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst           24                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data       912088                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         912112                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       942869                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       942869                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data        20704                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total        20704                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst           24                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       932792                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          932816                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst           24                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       932792                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         932816                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          710                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data          281                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total          991                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data        14535                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total        14535                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          710                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data        14816                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::total         15526                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          712                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data        14814                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.inst          710                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data        14816                       # number of overall misses
 system.cpu.l2cache.overall_misses::total        15526                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     24404500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      9520000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     33924500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    499194500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    499194500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     24404500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    508714500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    533119000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     24404500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    508714500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    533119000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          737                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data       903336                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total       904073                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       942950                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       942950                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data        44347                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total        44347                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          737                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       947683                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       948420                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          737                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       947683                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       948420                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.966079                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     25363000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     10310000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     35673000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    499681500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    499681500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     25363000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    509991500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    535354500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     25363000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    509991500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    535354500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          734                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data       912369                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       913103                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       942869                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       942869                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data        35239                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total        35239                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          734                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       947608                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       948342                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          734                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       947608                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       948342                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.967302                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.000308                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.001095                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.327779                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.327779                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.966079                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.015632                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.016370                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.966079                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.015632                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.016370                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34275.983146                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34244.604317                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 34267.171717                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34341.944139                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34341.944139                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34275.983146                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34340.117456                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 34337.176349                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34275.983146                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34340.117456                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 34337.176349                       # average overall miss latency
+system.cpu.l2cache.ReadReq_miss_rate::total     0.001085                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.412469                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.412469                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.967302                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.015635                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.016372                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.967302                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.015635                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.016372                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35722.535211                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 36690.391459                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 35996.972755                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34377.812178                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34377.812178                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35722.535211                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34421.672516                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 34481.160634                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35722.535211                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34421.672516                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 34481.160634                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -642,59 +642,59 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            1                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            2                       # number of ReadReq MSHR hits
 system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           10                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total           11                       # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total           12                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst            2                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.data           10                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           11                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           12                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst            2                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.data           10                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           11                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          711                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          268                       # number of ReadReq MSHR misses
+system.cpu.l2cache.overall_mshr_hits::total           12                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          708                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          271                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::total          979                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        14536                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total        14536                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          711                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data        14804                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total        15515                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          711                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data        14804                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total        15515                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     22107000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      8364000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     30471000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    452118500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    452118500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     22107000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    460482500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    482589500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     22107000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    460482500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    482589500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.964722                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        14535                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        14535                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          708                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data        14806                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        15514                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          708                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data        14806                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total        15514                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     23086000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      9134000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     32220000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    453439000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    453439000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     23086000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    462573000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    485659000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     23086000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    462573000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    485659000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.964578                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.000297                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.001083                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.327779                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.327779                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.964722                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.015621                       # mshr miss rate for demand accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.001072                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.412469                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.412469                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.964578                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.015625                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.016359                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.964722                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.015621                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.964578                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.015625                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.016359                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31092.827004                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31208.955224                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31124.616956                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31103.364062                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31103.364062                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31092.827004                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31105.275601                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31104.705124                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31092.827004                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31105.275601                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31104.705124                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32607.344633                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33704.797048                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32911.133810                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31196.353629                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31196.353629                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32607.344633                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31242.266649                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31304.563620                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32607.344633                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31242.266649                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31304.563620                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini
index 8e4e9dec7..172c79802 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini
@@ -166,7 +166,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
@@ -198,7 +198,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout
index 78b502a64..092850ece 100755
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:10:14
-gem5 started Jun 29 2012 00:44:41
+gem5 compiled Jul  2 2012 09:08:16
+gem5 started Jul  2 2012 15:40:44
 gem5 executing on zizzer
 command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
@@ -23,4 +23,4 @@ simplex iterations         : 2663
 flow value                 : 3080014995
 checksum                   : 68389
 optimal
-Exiting @ tick 148083373000 because target called exit()
+Exiting @ tick 148267705000 because target called exit()
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
index 63806d746..4b16c09c3 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.148083                       # Number of seconds simulated
-sim_ticks                                148083373000                       # Number of ticks simulated
-final_tick                               148083373000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.148268                       # Number of seconds simulated
+sim_ticks                                148267705000                       # Number of ticks simulated
+final_tick                               148267705000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1433979                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1444261                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2344399916                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 365828                       # Number of bytes of host memory used
-host_seconds                                    63.16                       # Real time elapsed on the host
+host_inst_rate                                1021914                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1029241                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1672798092                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 365748                       # Number of bytes of host memory used
+host_seconds                                    88.63                       # Real time elapsed on the host
 sim_insts                                    90576861                       # Number of instructions simulated
 sim_ops                                      91226312                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             36992                       # Number of bytes read from this memory
@@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total           36992                       # Nu
 system.physmem.num_reads::cpu.inst                578                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data              14762                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                 15340                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst               249805                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              6379974                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 6629779                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          249805                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             249805                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              249805                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             6379974                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6629779                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               249495                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              6372042                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 6621536                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          249495                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             249495                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              249495                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             6372042                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                6621536                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -70,7 +70,7 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  442                       # Number of system calls
-system.cpu.numCycles                        296166746                       # number of cpu cycles simulated
+system.cpu.numCycles                        296535410                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                    90576861                       # Number of instructions committed
@@ -89,18 +89,18 @@ system.cpu.num_mem_refs                      27318810                       # nu
 system.cpu.num_load_insts                    22573966                       # Number of load instructions
 system.cpu.num_store_insts                    4744844                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  296166746                       # Number of busy cycles
+system.cpu.num_busy_cycles                  296535410                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                      2                       # number of replacements
-system.cpu.icache.tagsinuse                510.334547                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                510.369252                       # Cycle average of tags in use
 system.cpu.icache.total_refs                107830172                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    599                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               180016.981636                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     510.334547                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.249187                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.249187                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst     510.369252                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.249204                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.249204                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst    107830172                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total       107830172                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst     107830172                       # number of demand (read+write) hits
@@ -113,12 +113,12 @@ system.cpu.icache.demand_misses::cpu.inst          599                       # n
 system.cpu.icache.demand_misses::total            599                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          599                       # number of overall misses
 system.cpu.icache.overall_misses::total           599                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     32662000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     32662000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     32662000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     32662000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     32662000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     32662000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     32709000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     32709000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     32709000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     32709000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     32709000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     32709000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst    107830771                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total    107830771                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst    107830771                       # number of demand (read+write) accesses
@@ -131,12 +131,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000006
 system.cpu.icache.demand_miss_rate::total     0.000006                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000006                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000006                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54527.545910                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 54527.545910                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 54527.545910                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 54527.545910                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 54527.545910                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 54527.545910                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54606.010017                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 54606.010017                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 54606.010017                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 54606.010017                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 54606.010017                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 54606.010017                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -151,34 +151,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          599
 system.cpu.icache.demand_mshr_misses::total          599                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          599                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          599                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     30865000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     30865000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     30865000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     30865000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     30865000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     30865000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     30912000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     30912000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     30912000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     30912000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     30912000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     30912000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000006                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000006                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000006                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000006                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000006                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000006                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51527.545910                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51527.545910                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51527.545910                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 51527.545910                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51527.545910                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 51527.545910                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51606.010017                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51606.010017                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51606.010017                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 51606.010017                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51606.010017                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 51606.010017                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                 942702                       # number of replacements
-system.cpu.dcache.tagsinuse               3568.539568                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               3568.972050                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                 26345364                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                 946798                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                  27.825750                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle            54479146000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    3568.539568                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.871225                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.871225                       # Average percentage of cache occupancy
+system.cpu.dcache.warmup_cycle            54491057000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    3568.972050                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.871331                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.871331                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data     21649218                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        21649218                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data      4688372                       # number of WriteReq hits
@@ -199,14 +199,14 @@ system.cpu.dcache.demand_misses::cpu.data       946798                       # n
 system.cpu.dcache.demand_misses::total         946798                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data       946798                       # number of overall misses
 system.cpu.dcache.overall_misses::total        946798                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  12611634000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  12611634000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   1263542000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   1263542000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  13875176000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  13875176000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  13875176000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  13875176000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  12648933000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  12648933000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   1288595000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   1288595000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  13937528000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  13937528000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  13937528000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  13937528000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data     22549407                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total     22549407                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data      4734981                       # number of WriteReq accesses(hits+misses)
@@ -227,14 +227,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.034701
 system.cpu.dcache.demand_miss_rate::total     0.034701                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.034701                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.034701                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14009.984570                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14009.984570                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27109.399472                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 27109.399472                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 14654.842955                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 14654.842955                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 14654.842955                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 14654.842955                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14051.419202                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14051.419202                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27646.913686                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 27646.913686                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 14720.698607                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 14720.698607                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 14720.698607                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 14720.698607                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -253,14 +253,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data       946798
 system.cpu.dcache.demand_mshr_misses::total       946798                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data       946798                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total       946798                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   9911067000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   9911067000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1123715000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   1123715000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  11034782000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  11034782000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  11034782000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  11034782000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   9948366000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   9948366000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1148768000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   1148768000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  11097134000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  11097134000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  11097134000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  11097134000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.039921                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.039921                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009844                       # mshr miss rate for WriteReq accesses
@@ -269,28 +269,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.034701
 system.cpu.dcache.demand_mshr_miss_rate::total     0.034701                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.034701                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.034701                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11009.984570                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11009.984570                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24109.399472                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24109.399472                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11654.842955                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 11654.842955                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11654.842955                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 11654.842955                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11051.419202                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11051.419202                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24646.913686                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24646.913686                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11720.698607                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 11720.698607                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11720.698607                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 11720.698607                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse              9598.880462                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse              9602.986186                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                 1827210                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                 15323                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                119.246231                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks  8910.241595                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst    495.387120                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data    193.251747                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.271919                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst     0.015118                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::writebacks  8914.312589                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst    495.421771                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    193.251826                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.272043                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.015119                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.data     0.005898                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.292935                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.293060                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst           21                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data       899975                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total         899996                       # number of ReadReq hits
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
index 8e6bba913..2ba8ced6e 100644
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
@@ -148,7 +148,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
@@ -180,7 +180,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
index 8432da315..f34d81d26 100755
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:06:58
-gem5 started Jun 28 2012 22:55:42
+gem5 compiled Jul  2 2012 08:54:18
+gem5 started Jul  2 2012 12:31:43
 gem5 executing on zizzer
 command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
@@ -23,4 +23,4 @@ simplex iterations         : 2663
 flow value                 : 3080014995
 checksum                   : 68389
 optimal
-Exiting @ tick 362428997000 because target called exit()
+Exiting @ tick 362481577000 because target called exit()
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
index 75faf8d15..5f77178bc 100644
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.362429                       # Number of seconds simulated
-sim_ticks                                362428997000                       # Number of ticks simulated
-final_tick                               362428997000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.362482                       # Number of seconds simulated
+sim_ticks                                362481577000                       # Number of ticks simulated
+final_tick                               362481577000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1801112                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1801186                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2677225778                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 354292                       # Number of bytes of host memory used
-host_seconds                                   135.37                       # Real time elapsed on the host
+host_inst_rate                                1217197                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1217247                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1809539933                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 354248                       # Number of bytes of host memory used
+host_seconds                                   200.32                       # Real time elapsed on the host
 sim_insts                                   243825163                       # Number of instructions simulated
 sim_ops                                     243835278                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             56256                       # Number of bytes read from this memory
@@ -19,16 +19,16 @@ system.physmem.bytes_inst_read::total           56256                       # Nu
 system.physmem.num_reads::cpu.inst                879                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data              14724                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                 15603                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst               155219                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              2600057                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2755276                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          155219                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             155219                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              155219                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             2600057                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2755276                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               155197                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              2599680                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2754877                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          155197                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             155197                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              155197                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             2599680                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2754877                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                  443                       # Number of system calls
-system.cpu.numCycles                        724857994                       # number of cpu cycles simulated
+system.cpu.numCycles                        724963154                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   243825163                       # Number of instructions committed
@@ -47,18 +47,18 @@ system.cpu.num_mem_refs                     105711442                       # nu
 system.cpu.num_load_insts                    82803522                       # Number of load instructions
 system.cpu.num_store_insts                   22907920                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  724857994                       # Number of busy cycles
+system.cpu.num_busy_cycles                  724963154                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                     25                       # number of replacements
-system.cpu.icache.tagsinuse                725.567220                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                725.564686                       # Cycle average of tags in use
 system.cpu.icache.total_refs                244420630                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    882                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               277120.895692                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     725.567220                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.354281                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.354281                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst     725.564686                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.354280                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.354280                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst    244420630                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total       244420630                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst     244420630                       # number of demand (read+write) hits
@@ -71,12 +71,12 @@ system.cpu.icache.demand_misses::cpu.inst          882                       # n
 system.cpu.icache.demand_misses::total            882                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          882                       # number of overall misses
 system.cpu.icache.overall_misses::total           882                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     49266000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     49266000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     49266000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     49266000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     49266000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     49266000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     49333000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     49333000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     49333000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     49333000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     49333000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     49333000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst    244421512                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total    244421512                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst    244421512                       # number of demand (read+write) accesses
@@ -89,12 +89,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000004
 system.cpu.icache.demand_miss_rate::total     0.000004                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000004                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000004                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55857.142857                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 55857.142857                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 55857.142857                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 55857.142857                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 55857.142857                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 55857.142857                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55933.106576                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 55933.106576                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 55933.106576                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 55933.106576                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 55933.106576                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 55933.106576                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -109,34 +109,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          882
 system.cpu.icache.demand_mshr_misses::total          882                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          882                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          882                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     46620000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     46620000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     46620000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     46620000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     46620000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     46620000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     46687000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     46687000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     46687000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     46687000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     46687000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     46687000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000004                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000004                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000004                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000004                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000004                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000004                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52857.142857                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52857.142857                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52857.142857                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 52857.142857                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52857.142857                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 52857.142857                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52933.106576                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52933.106576                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52933.106576                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 52933.106576                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52933.106576                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 52933.106576                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                 935475                       # number of replacements
-system.cpu.dcache.tagsinuse               3563.821484                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               3563.804804                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                104186700                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                 939571                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                 110.887522                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle           134373316000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    3563.821484                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.870074                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.870074                       # Average percentage of cache occupancy
+system.cpu.dcache.warmup_cycle           134384281000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    3563.804804                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.870070                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.870070                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data     81327577                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        81327577                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     22855241                       # number of WriteReq hits
@@ -157,16 +157,16 @@ system.cpu.dcache.demand_misses::cpu.data       939567                       # n
 system.cpu.dcache.demand_misses::total         939567                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data       939567                       # number of overall misses
 system.cpu.dcache.overall_misses::total        939567                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  12506592000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  12506592000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   1265712000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   1265712000                       # number of WriteReq miss cycles
-system.cpu.dcache.SwapReq_miss_latency::cpu.data        98000                       # number of SwapReq miss cycles
-system.cpu.dcache.SwapReq_miss_latency::total        98000                       # number of SwapReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  13772304000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  13772304000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  13772304000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  13772304000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  12510586000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  12510586000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   1267548000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   1267548000                       # number of WriteReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency::cpu.data       101000                       # number of SwapReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency::total       101000                       # number of SwapReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  13778134000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  13778134000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  13778134000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  13778134000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data     82220434                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total     82220434                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     22901951                       # number of WriteReq accesses(hits+misses)
@@ -187,16 +187,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.008938
 system.cpu.dcache.demand_miss_rate::total     0.008938                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.008938                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.008938                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14007.385281                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14007.385281                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27097.238279                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 27097.238279                       # average WriteReq miss latency
-system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data        24500                       # average SwapReq miss latency
-system.cpu.dcache.SwapReq_avg_miss_latency::total        24500                       # average SwapReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 14658.139334                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 14658.139334                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 14658.139334                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 14658.139334                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14011.858562                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14011.858562                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27136.544637                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 27136.544637                       # average WriteReq miss latency
+system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data        25250                       # average SwapReq miss latency
+system.cpu.dcache.SwapReq_avg_miss_latency::total        25250                       # average SwapReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 14664.344320                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 14664.344320                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 14664.344320                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 14664.344320                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -217,16 +217,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data       939567
 system.cpu.dcache.demand_mshr_misses::total       939567                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data       939567                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total       939567                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   9828021000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   9828021000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1125582000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   1125582000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data        86000                       # number of SwapReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_latency::total        86000                       # number of SwapReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  10953603000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  10953603000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  10953603000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  10953603000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   9832015000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   9832015000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1127418000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   1127418000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data        89000                       # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency::total        89000                       # number of SwapReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  10959433000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  10959433000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  10959433000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  10959433000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.010859                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.010859                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.002040                       # mshr miss rate for WriteReq accesses
@@ -237,30 +237,30 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.008938
 system.cpu.dcache.demand_mshr_miss_rate::total     0.008938                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.008938                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.008938                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11007.385281                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11007.385281                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24097.238279                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24097.238279                       # average WriteReq mshr miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data        21500                       # average SwapReq mshr miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total        21500                       # average SwapReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11658.139334                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 11658.139334                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11658.139334                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 11658.139334                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11011.858562                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11011.858562                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24136.544637                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24136.544637                       # average WriteReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data        22250                       # average SwapReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total        22250                       # average SwapReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11664.344320                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 11664.344320                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11664.344320                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 11664.344320                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse              9744.405217                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse              9744.633089                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                 1813121                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                 15586                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                116.330104                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks  8861.272475                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst    738.802087                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data    144.330654                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.270425                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::writebacks  8861.504688                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst    738.799807                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    144.328594                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.270432                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.inst     0.022546                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.data     0.004405                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.297376                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.297383                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst            3                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data       892700                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total         892703                       # number of ReadReq hits
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
index 4ff330a09..02825e2f4 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
@@ -500,7 +500,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
@@ -532,7 +532,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
 slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
 
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
index ec0229a1c..dec2c9148 100755
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:08:09
-gem5 started Jun 28 2012 23:13:04
+gem5 compiled Jul  2 2012 08:58:39
+gem5 started Jul  2 2012 13:12:36
 gem5 executing on zizzer
 command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/10.mcf/x86/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
@@ -21,7 +21,8 @@ new implicit arcs          : 23867
 active arcs                : 25772
 simplex iterations         : 2663
 flow value                 : 3080014995
-info: Increasing stack size by one page.
 checksum                   : 68389
 optimal
-Exiting @ tick 66545720000 because target called exit()
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+Exiting @ tick 68340167000 because target called exit()
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
index 1baa4dbca..4e7a26f12 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
@@ -1,279 +1,279 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.066546                       # Number of seconds simulated
-sim_ticks                                 66545720000                       # Number of ticks simulated
-final_tick                                66545720000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.068340                       # Number of seconds simulated
+sim_ticks                                 68340167000                       # Number of ticks simulated
+final_tick                                68340167000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 128459                       # Simulator instruction rate (inst/s)
-host_op_rate                                   226196                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               54107733                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 365700                       # Number of bytes of host memory used
-host_seconds                                  1229.87                       # Real time elapsed on the host
+host_inst_rate                                 107513                       # Simulator instruction rate (inst/s)
+host_op_rate                                   189313                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               46506224                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 365660                       # Number of bytes of host memory used
+host_seconds                                  1469.48                       # Real time elapsed on the host
 sim_insts                                   157988582                       # Number of instructions simulated
 sim_ops                                     278192519                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst             68352                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           1892992                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              1961344                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        68352                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           68352                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks        20032                       # Number of bytes written to this memory
-system.physmem.bytes_written::total             20032                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               1068                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data              29578                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                 30646                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks             313                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                  313                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst              1027143                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             28446488                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                29473631                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         1027143                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1027143                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks            301026                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                 301026                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks            301026                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             1027143                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            28446488                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               29774657                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst             68608                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           1893120                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              1961728                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        68608                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           68608                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks        20288                       # Number of bytes written to this memory
+system.physmem.bytes_written::total             20288                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               1072                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data              29580                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                 30652                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks             317                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                  317                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst              1003919                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             27701425                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                28705344                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1003919                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1003919                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks            296868                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                 296868                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks            296868                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             1003919                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            27701425                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               29002212                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                  444                       # Number of system calls
-system.cpu.numCycles                        133091441                       # number of cpu cycles simulated
+system.cpu.numCycles                        136680335                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                 36127369                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted           36127369                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect            1087558                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups              25661122                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                 25550646                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                 36129289                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           36129289                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect            1086629                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              25668657                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                 25566381                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
 system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles           27995643                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      196446977                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    36127369                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           25550646                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      59425857                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 8408654                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles               38346383                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                   25                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles           123                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                  27275955                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                142407                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          133058866                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.595223                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.362713                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           28038648                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      196448149                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    36129289                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           25566381                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      59446336                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 8437809                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               41835148                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                   32                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles           182                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                  27320717                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                151811                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          136641889                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.527241                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.343736                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 76373838     57.40%     57.40% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  2167538      1.63%     59.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  2997061      2.25%     61.28% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  4104688      3.08%     64.36% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  8024100      6.03%     70.40% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  5043618      3.79%     74.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  2895035      2.18%     76.36% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1466845      1.10%     77.46% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 29986143     22.54%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 79944033     58.51%     58.51% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  2167208      1.59%     60.09% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  2997757      2.19%     62.29% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  4111297      3.01%     65.29% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  8027988      5.88%     71.17% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  5053640      3.70%     74.87% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  2897429      2.12%     76.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1474644      1.08%     78.07% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 29967893     21.93%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            133058866                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.271448                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.476030                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 40459991                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              29238616                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  46513629                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               9555795                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                7290835                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts              341218691                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles                7290835                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 45832356                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 4342736                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           9009                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  50371616                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              25212314                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              337359064                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                    16                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                   3751                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents              23039182                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents            70135                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           414697998                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1009810700                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1009808348                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups              2352                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            136641889                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.264334                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.437282                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 40756149                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              32464330                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  46271327                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               9828540                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                7321543                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts              341364323                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles                7321543                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 46061495                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 6368629                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           8995                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  50367831                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              26513396                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              337564097                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                    23                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                   5026                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents              24245573                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents            73928                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           414895608                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1010438546                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1010435932                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups              2614                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             341010940                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 73687058                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps                 73884668                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts                483                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            476                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  55957632                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            108146065                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            37162932                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          46284047                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          7887005                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  331670931                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                2660                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 311367761                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            187011                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        53218475                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     92468498                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved           2214                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     133058866                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.340075                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.723307                       # Number of insts issued each cycle
+system.cpu.rename.tempSerializingInsts            475                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  57387793                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            108215751                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            37227533                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          46388866                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          7855106                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  331925513                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                2461                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 311467723                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            186069                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        53480941                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     93052835                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           2015                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     136641889                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.279445                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.722907                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            27262165     20.49%     20.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            17087897     12.84%     33.33% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            25427949     19.11%     52.44% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            31141299     23.40%     75.85% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            17714013     13.31%     89.16% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             9070422      6.82%     95.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             3766330      2.83%     98.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             1516401      1.14%     99.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8               72390      0.05%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            29493706     21.58%     21.58% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            18268502     13.37%     34.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            26067174     19.08%     54.03% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            31248056     22.87%     76.90% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            17426975     12.75%     89.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             8824728      6.46%     96.11% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             3769643      2.76%     98.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             1473533      1.08%     99.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8               69572      0.05%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       133058866                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       136641889                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                   23137      1.10%      1.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      1.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      1.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      1.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      1.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      1.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      1.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      1.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      1.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      1.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      1.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      1.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      1.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      1.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      1.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      1.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      1.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      1.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      1.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      1.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      1.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      1.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      1.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      1.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      1.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      1.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      1.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      1.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      1.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                1959411     92.81%     93.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                128735      6.10%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   22788      1.09%      1.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      1.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      1.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      1.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      1.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      1.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      1.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      1.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      1.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      1.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      1.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      1.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      1.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      1.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      1.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      1.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      1.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      1.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      1.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      1.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      1.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      1.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      1.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      1.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      1.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      1.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      1.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      1.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      1.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                1944579     92.77%     93.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                128653      6.14%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass             31371      0.01%      0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             177167866     56.90%     56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    0      0.00%     56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                 103      0.00%     56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     56.91% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             99703270     32.02%     88.93% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            34465151     11.07%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass             29247      0.01%      0.01% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             177257579     56.91%     56.92% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    0      0.00%     56.92% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     56.92% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                 116      0.00%     56.92% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     56.92% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     56.92% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     56.92% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     56.92% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     56.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     56.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     56.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     56.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     56.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     56.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     56.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     56.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     56.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     56.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     56.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     56.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     56.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     56.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     56.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     56.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     56.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     56.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     56.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     56.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     56.92% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             99693088     32.01%     88.93% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            34487693     11.07%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              311367761                       # Type of FU issued
-system.cpu.iq.rate                           2.339503                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     2111283                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.006781                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          758091805                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         384922588                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    308230879                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 877                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes               1235                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses          288                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              313447268                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     405                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         52556752                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              311467723                       # Type of FU issued
+system.cpu.iq.rate                           2.278804                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2096020                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.006729                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          761858485                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         385440526                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    308377955                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 939                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes               1362                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses          296                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              313534078                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     418                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         52563213                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     17366677                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        97430                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        32398                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      5723181                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     17436363                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        94862                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        33518                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      5787782                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads         3328                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          3855                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads         3294                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked           766                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                7290835                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                  316808                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                 29284                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           331673591                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts             45940                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             108146065                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             37162932                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                478                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                    230                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                  5075                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          32398                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         615271                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       578255                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1193526                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             309404440                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              99168969                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           1963321                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                7321543                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                  823106                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                106434                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           331927974                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts             49382                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             108215751                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             37227533                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                475                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                   1169                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 29139                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          33518                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         614396                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       578149                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              1192545                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             309546199                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              99164124                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1921524                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                    133248637                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 31530009                       # Number of branches executed
-system.cpu.iew.exec_stores                   34079668                       # Number of stores executed
-system.cpu.iew.exec_rate                     2.324751                       # Inst execution rate
-system.cpu.iew.wb_sent                      308773966                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     308231167                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 227547609                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 467201547                       # num instructions consuming a value
+system.cpu.iew.exec_refs                    133270548                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 31554842                       # Number of branches executed
+system.cpu.iew.exec_stores                   34106424                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.264746                       # Inst execution rate
+system.cpu.iew.wb_sent                      308908711                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     308378251                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 227159905                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 466461304                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       2.315935                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.487044                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       2.256201                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.486986                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts      157988582                       # The number of committed instructions
 system.cpu.commit.commitCommittedOps        278192519                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts        53483171                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts        53739498                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             446                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           1087573                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    125768031                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.211949                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.676987                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           1086653                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    129320346                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.151189                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.664667                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     45423361     36.12%     36.12% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     24208560     19.25%     55.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     16905668     13.44%     68.81% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     12615481     10.03%     78.84% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      3337463      2.65%     81.49% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      3557456      2.83%     84.32% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      2707212      2.15%     86.47% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      1156864      0.92%     87.39% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     15855966     12.61%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     48978430     37.87%     37.87% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     24328173     18.81%     56.69% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     16731567     12.94%     69.62% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     12545678      9.70%     79.33% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      3454921      2.67%     82.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      3553253      2.75%     84.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      2757236      2.13%     86.88% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      1133891      0.88%     87.75% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     15837197     12.25%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    125768031                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    129320346                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            157988582                       # Number of instructions committed
 system.cpu.commit.committedOps              278192519                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -284,69 +284,69 @@ system.cpu.commit.branches                   29309710                       # Nu
 system.cpu.commit.fp_insts                         40                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                 278186227                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                    0                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events              15855966                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events              15837197                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    441587755                       # The number of ROB reads
-system.cpu.rob.rob_writes                   670650798                       # The number of ROB writes
-system.cpu.timesIdled                             771                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           32575                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                    445415166                       # The number of ROB reads
+system.cpu.rob.rob_writes                   671194708                       # The number of ROB writes
+system.cpu.timesIdled                            2012                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           38446                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   157988582                       # Number of Instructions Simulated
 system.cpu.committedOps                     278192519                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total             157988582                       # Number of Instructions Simulated
-system.cpu.cpi                               0.842412                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.842412                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.187068                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.187068                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                705256530                       # number of integer regfile reads
-system.cpu.int_regfile_writes               373197329                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                       323                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                      179                       # number of floating regfile writes
-system.cpu.misc_regfile_reads               197910485                       # number of misc regfile reads
-system.cpu.icache.replacements                     89                       # number of replacements
-system.cpu.icache.tagsinuse                845.508761                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 27274550                       # Total number of references to valid blocks.
+system.cpu.cpi                               0.865128                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.865128                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.155898                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.155898                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                705405399                       # number of integer regfile reads
+system.cpu.int_regfile_writes               373270395                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                       345                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                      188                       # number of floating regfile writes
+system.cpu.misc_regfile_reads               197984504                       # number of misc regfile reads
+system.cpu.icache.replacements                     90                       # number of replacements
+system.cpu.icache.tagsinuse                845.686115                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 27319306                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                   1079                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs               25277.618165                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs               25319.097312                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     845.508761                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.412846                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.412846                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst     27274554                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        27274554                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      27274554                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         27274554                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     27274554                       # number of overall hits
-system.cpu.icache.overall_hits::total        27274554                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         1401                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          1401                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         1401                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           1401                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         1401                       # number of overall misses
-system.cpu.icache.overall_misses::total          1401                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     49669500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     49669500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     49669500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     49669500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     49669500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     49669500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     27275955                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     27275955                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     27275955                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     27275955                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     27275955                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     27275955                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000051                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000051                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000051                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000051                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000051                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000051                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35452.890792                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 35452.890792                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 35452.890792                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 35452.890792                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 35452.890792                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 35452.890792                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     845.686115                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.412933                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.412933                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst     27319307                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        27319307                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      27319307                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         27319307                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     27319307                       # number of overall hits
+system.cpu.icache.overall_hits::total        27319307                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1410                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1410                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1410                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1410                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1410                       # number of overall misses
+system.cpu.icache.overall_misses::total          1410                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     52106500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     52106500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     52106500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     52106500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     52106500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     52106500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     27320717                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     27320717                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     27320717                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     27320717                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     27320717                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     27320717                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000052                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000052                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000052                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000052                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000052                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000052                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36954.964539                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 36954.964539                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 36954.964539                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 36954.964539                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 36954.964539                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 36954.964539                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -355,94 +355,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          317                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          317                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          317                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          317                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          317                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          317                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         1084                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         1084                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         1084                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         1084                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         1084                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         1084                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     37853000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     37853000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     37853000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     37853000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     37853000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     37853000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          328                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          328                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          328                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          328                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          328                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          328                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         1082                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         1082                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         1082                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         1082                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         1082                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         1082                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     39682000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     39682000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     39682000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     39682000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     39682000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     39682000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000040                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000040                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000040                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000040                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000040                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000040                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34919.741697                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34919.741697                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34919.741697                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 34919.741697                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34919.741697                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 34919.741697                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36674.676525                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36674.676525                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36674.676525                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 36674.676525                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36674.676525                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 36674.676525                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                2072094                       # number of replacements
-system.cpu.dcache.tagsinuse               4072.411380                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 75633227                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                2076190                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  36.428856                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle            22601159000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4072.411380                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.994241                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.994241                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data     44275835                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        44275835                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     31357376                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       31357376                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      75633211                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         75633211                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     75633211                       # number of overall hits
-system.cpu.dcache.overall_hits::total        75633211                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      2285631                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       2285631                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data        82375                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total        82375                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      2368006                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2368006                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      2368006                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2368006                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  12197942000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  12197942000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   1391130788                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   1391130788                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  13589072788                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  13589072788                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  13589072788                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  13589072788                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     46561466                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     46561466                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.replacements                2072150                       # number of replacements
+system.cpu.dcache.tagsinuse               4072.380318                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 75593684                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                2076246                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  36.408828                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle            22734551000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4072.380318                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.994233                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.994233                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     44236411                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        44236411                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     31357262                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       31357262                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      75593673                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         75593673                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     75593673                       # number of overall hits
+system.cpu.dcache.overall_hits::total        75593673                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      2315078                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       2315078                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data        82489                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        82489                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      2397567                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2397567                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2397567                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2397567                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  16784018500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  16784018500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   1571310000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   1571310000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  18355328500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  18355328500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  18355328500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  18355328500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     46551489                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     46551489                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     31439751                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     31439751                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     78001217                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     78001217                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     78001217                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     78001217                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.049088                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.049088                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.002620                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.002620                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.030359                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.030359                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.030359                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.030359                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data  5336.794084                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total  5336.794084                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16887.778914                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 16887.778914                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data  5738.614171                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total  5738.614171                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data  5738.614171                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total  5738.614171                       # average overall miss latency
+system.cpu.dcache.demand_accesses::cpu.data     77991240                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     77991240                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     77991240                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     77991240                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.049732                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.049732                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.002624                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.002624                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.030741                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.030741                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.030741                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.030741                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data  7249.871711                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total  7249.871711                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 19048.721648                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 19048.721648                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data  7655.814624                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total  7655.814624                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data  7655.814624                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total  7655.814624                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -451,140 +451,140 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      2064779                       # number of writebacks
-system.cpu.dcache.writebacks::total           2064779                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       291515                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       291515                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data          294                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total          294                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       291809                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       291809                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       291809                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       291809                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1994116                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1994116                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data        82081                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total        82081                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      2076197                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      2076197                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      2076197                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      2076197                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   4625699000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   4625699000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1142906788                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   1142906788                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data   5768605788                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total   5768605788                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data   5768605788                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total   5768605788                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.042828                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.042828                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.002611                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.002611                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.026617                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.026617                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.026617                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.026617                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  2319.673981                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  2319.673981                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 13924.133332                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 13924.133332                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  2778.448186                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total  2778.448186                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  2778.448186                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total  2778.448186                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks      2064802                       # number of writebacks
+system.cpu.dcache.writebacks::total           2064802                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       320846                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       320846                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data          469                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total          469                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       321315                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       321315                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       321315                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       321315                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1994232                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1994232                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data        82020                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total        82020                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      2076252                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      2076252                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      2076252                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      2076252                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6184007000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   6184007000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1313707000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   1313707000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   7497714000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   7497714000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data   7497714000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   7497714000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.042839                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.042839                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.002609                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.002609                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.026622                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.026622                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.026622                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.026622                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  3100.946630                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  3100.946630                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16016.910510                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16016.910510                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  3611.177256                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total  3611.177256                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  3611.177256                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total  3611.177256                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.replacements                  1461                       # number of replacements
-system.cpu.l2cache.tagsinuse             19902.779056                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 4027062                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                 30627                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                131.487315                       # Average number of references to valid blocks.
+system.cpu.l2cache.replacements                  1468                       # number of replacements
+system.cpu.l2cache.tagsinuse             20085.228280                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 4027172                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                 30631                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                131.473736                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 19403.134879                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst    269.722529                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data    229.921648                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.592137                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst     0.008231                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.007017                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.607385                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst           11                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data      1993423                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1993434                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      2064779                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      2064779                       # number of Writeback hits
+system.cpu.l2cache.occ_blocks::writebacks 19589.019970                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst    262.767533                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    233.440777                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.597809                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.008019                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.007124                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.612953                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst            7                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data      1993528                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        1993535                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      2064802                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      2064802                       # number of Writeback hits
 system.cpu.l2cache.UpgradeReq_hits::cpu.data            1                       # number of UpgradeReq hits
 system.cpu.l2cache.UpgradeReq_hits::total            1                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data        53191                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total        53191                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst           11                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      2046614                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2046625                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst           11                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      2046614                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2046625                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         1068                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data          585                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         1653                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data            4                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total            4                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data        28993                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total        28993                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         1068                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data        29578                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total         30646                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         1068                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data        29578                       # number of overall misses
-system.cpu.l2cache.overall_misses::total        30646                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     36597500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     20018000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     56615500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    988202000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    988202000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     36597500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data   1008220000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total   1044817500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     36597500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data   1008220000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total   1044817500                       # number of overall miss cycles
+system.cpu.l2cache.ReadExReq_hits::cpu.data        53141                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total        53141                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst            7                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      2046669                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2046676                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst            7                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      2046669                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2046676                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         1072                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data          588                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total         1660                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data            2                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total            2                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data        28992                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total        28992                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         1072                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data        29580                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total         30652                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         1072                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data        29580                       # number of overall misses
+system.cpu.l2cache.overall_misses::total        30652                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     38191500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     20878500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     59070000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    989300500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    989300500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     38191500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   1010179000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   1048370500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     38191500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   1010179000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   1048370500                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst         1079                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      1994008                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      1995087                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      2064779                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      2064779                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data            5                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total            5                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data        82184                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total        82184                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      1994116                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      1995195                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      2064802                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      2064802                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data            3                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total            3                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data        82133                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total        82133                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.inst         1079                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      2076192                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2077271                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      2076249                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2077328                       # number of demand (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.inst         1079                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      2076192                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2077271                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.989805                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.000293                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.000829                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.800000                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.800000                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.352782                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.352782                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.989805                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.014246                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.014753                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.989805                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.014246                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.014753                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34267.322097                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34218.803419                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 34250.151240                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34084.158245                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34084.158245                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34267.322097                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34086.821286                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 34093.111662                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34267.322097                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34086.821286                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 34093.111662                       # average overall miss latency
+system.cpu.l2cache.overall_accesses::cpu.data      2076249                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2077328                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.993513                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.000295                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.000832                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.666667                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.666667                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.352988                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.352988                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.993513                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.014247                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.014755                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.993513                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.014247                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.014755                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35626.399254                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 35507.653061                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 35584.337349                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34123.223648                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34123.223648                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35626.399254                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34150.743746                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 34202.352212                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35626.399254                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34150.743746                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 34202.352212                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -593,60 +593,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks          313                       # number of writebacks
-system.cpu.l2cache.writebacks::total              313                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         1068                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          585                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         1653                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            4                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total            4                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        28993                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total        28993                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         1068                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data        29578                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total        30646                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         1068                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data        29578                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total        30646                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     33172000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     18151500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     51323500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       124000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       124000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    898797500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    898797500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     33172000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    916949000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    950121000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     33172000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    916949000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    950121000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.989805                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.000293                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.000829                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.800000                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.800000                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.352782                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.352782                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.989805                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.014246                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.014753                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.989805                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.014246                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.014753                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31059.925094                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31028.205128                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31048.699335                       # average ReadReq mshr miss latency
+system.cpu.l2cache.writebacks::writebacks          317                       # number of writebacks
+system.cpu.l2cache.writebacks::total              317                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         1072                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          588                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         1660                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            2                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total            2                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        28992                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        28992                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         1072                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data        29580                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        30652                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         1072                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data        29580                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total        30652                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     34797000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     19023000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     53820000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        62000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        62000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    899044500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    899044500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     34797000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    918067500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    952864500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     34797000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    918067500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    952864500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.993513                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.000295                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.000832                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.666667                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.666667                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.352988                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.352988                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.993513                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.014247                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.014755                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.993513                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.014247                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.014755                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32459.888060                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32352.040816                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32421.686747                       # average ReadReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        31000                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        31000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.500121                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31000.500121                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31059.925094                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31001.048076                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31003.099915                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31059.925094                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31001.048076                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31003.099915                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31010.088990                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31010.088990                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32459.888060                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31036.764706                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31086.535952                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32459.888060                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31036.764706                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31086.535952                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
index 4b59eaf01..44c2b2c0a 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
@@ -169,7 +169,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
@@ -201,7 +201,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
 slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
 
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
index 894e40d36..85144f91b 100755
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:08:09
-gem5 started Jun 28 2012 23:17:22
+gem5 compiled Jul  2 2012 08:58:39
+gem5 started Jul  2 2012 13:28:56
 gem5 executing on zizzer
 command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
@@ -23,4 +23,4 @@ simplex iterations         : 2663
 flow value                 : 3080014995
 checksum                   : 68389
 optimal
-Exiting @ tick 368062166000 because target called exit()
+Exiting @ tick 368209254000 because target called exit()
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
index 896f57262..cca34d6d0 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.368062                       # Number of seconds simulated
-sim_ticks                                368062166000                       # Number of ticks simulated
-final_tick                               368062166000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.368209                       # Number of seconds simulated
+sim_ticks                                368209254000                       # Number of ticks simulated
+final_tick                               368209254000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 915530                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1612102                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2132888263                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 362628                       # Number of bytes of host memory used
-host_seconds                                   172.57                       # Real time elapsed on the host
+host_inst_rate                                 606195                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1067413                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1412802854                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 363612                       # Number of bytes of host memory used
+host_seconds                                   260.62                       # Real time elapsed on the host
 sim_insts                                   157988583                       # Number of instructions simulated
 sim_ops                                     278192520                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             51712                       # Number of bytes read from this memory
@@ -23,19 +23,19 @@ system.physmem.num_reads::cpu.data              29370                       # Nu
 system.physmem.num_reads::total                 30178                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks             227                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                  227                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               140498                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              5106963                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 5247461                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          140498                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             140498                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks             39472                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                  39472                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks             39472                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              140498                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             5106963                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                5286933                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               140442                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              5104923                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 5245365                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          140442                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             140442                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks             39456                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                  39456                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks             39456                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              140442                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             5104923                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                5284821                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                  444                       # Number of system calls
-system.cpu.numCycles                        736124332                       # number of cpu cycles simulated
+system.cpu.numCycles                        736418508                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   157988583                       # Number of instructions committed
@@ -54,16 +54,16 @@ system.cpu.num_mem_refs                     122219139                       # nu
 system.cpu.num_load_insts                    90779388                       # Number of load instructions
 system.cpu.num_store_insts                   31439751                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  736124332                       # Number of busy cycles
+system.cpu.num_busy_cycles                  736418508                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                     24                       # number of replacements
-system.cpu.icache.tagsinuse                665.896557                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                665.897663                       # Cycle average of tags in use
 system.cpu.icache.total_refs                217695401                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    808                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               269425.001238                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     665.896557                       # Average occupied blocks per requestor
+system.cpu.icache.occ_blocks::cpu.inst     665.897663                       # Average occupied blocks per requestor
 system.cpu.icache.occ_percent::cpu.inst      0.325145                       # Average percentage of cache occupancy
 system.cpu.icache.occ_percent::total         0.325145                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst    217695401                       # number of ReadReq hits
@@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst          808                       # n
 system.cpu.icache.demand_misses::total            808                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          808                       # number of overall misses
 system.cpu.icache.overall_misses::total           808                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     45248000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     45248000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     45248000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     45248000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     45248000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     45248000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     45336000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     45336000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     45336000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     45336000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     45336000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     45336000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst    217696209                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total    217696209                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst    217696209                       # number of demand (read+write) accesses
@@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000004
 system.cpu.icache.demand_miss_rate::total     0.000004                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000004                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000004                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst        56000                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total        56000                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst        56000                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total        56000                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst        56000                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total        56000                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56108.910891                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 56108.910891                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 56108.910891                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 56108.910891                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 56108.910891                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 56108.910891                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -116,34 +116,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          808
 system.cpu.icache.demand_mshr_misses::total          808                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          808                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          808                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     42824000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     42824000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     42824000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     42824000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     42824000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     42824000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     42912000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     42912000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     42912000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     42912000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     42912000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     42912000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000004                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000004                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000004                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000004                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000004                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000004                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst        53000                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total        53000                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst        53000                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst        53000                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53108.910891                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53108.910891                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53108.910891                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 53108.910891                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53108.910891                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 53108.910891                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                2062733                       # number of replacements
-system.cpu.dcache.tagsinuse               4076.559519                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               4076.463091                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                120152372                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                2066829                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                  58.133678                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle           126200130000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4076.559519                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.995254                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.995254                       # Average percentage of cache occupancy
+system.cpu.dcache.warmup_cycle           126234114000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4076.463091                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.995230                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.995230                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data     88818730                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        88818730                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     31333642                       # number of WriteReq hits
@@ -160,14 +160,14 @@ system.cpu.dcache.demand_misses::cpu.data      2066829                       # n
 system.cpu.dcache.demand_misses::total        2066829                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data      2066829                       # number of overall misses
 system.cpu.dcache.overall_misses::total       2066829                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  27464486000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  27464486000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   2704691000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   2704691000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  30169177000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  30169177000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  30169177000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  30169177000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  27487330000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  27487330000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   2708348000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   2708348000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  30195678000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  30195678000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  30195678000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  30195678000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data     90779450                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total     90779450                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     31439751                       # number of WriteReq accesses(hits+misses)
@@ -184,14 +184,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.016911
 system.cpu.dcache.demand_miss_rate::total     0.016911                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.016911                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.016911                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14007.347301                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14007.347301                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25489.741681                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 25489.741681                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 14596.842313                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 14596.842313                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 14596.842313                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 14596.842313                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14018.998123                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14018.998123                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25524.206241                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 25524.206241                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 14609.664370                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 14609.664370                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 14609.664370                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 14609.664370                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -210,14 +210,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data      2066829
 system.cpu.dcache.demand_mshr_misses::total      2066829                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data      2066829                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total      2066829                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  21582326000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  21582326000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2386362500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   2386362500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  23968688500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  23968688500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  23968688500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  23968688500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  21605170000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  21605170000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2390019500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   2390019500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  23995189500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  23995189500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  23995189500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  23995189500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.021599                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.021599                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.003375                       # mshr miss rate for WriteReq accesses
@@ -226,28 +226,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016911
 system.cpu.dcache.demand_mshr_miss_rate::total     0.016911                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.016911                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.016911                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11007.347301                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11007.347301                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22489.727544                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22489.727544                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11596.841587                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 11596.841587                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11596.841587                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 11596.841587                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11018.998123                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11018.998123                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22524.192104                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22524.192104                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11609.663644                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 11609.663644                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11609.663644                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 11609.663644                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                  1081                       # number of replacements
-system.cpu.l2cache.tagsinuse             19721.209952                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse             19722.096664                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                 3991053                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                 30157                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                132.342508                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 19369.116114                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst    209.759091                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data    142.334747                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.591099                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst     0.006401                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::writebacks 19370.042647                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst    209.723692                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    142.330324                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.591127                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.006400                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.data     0.004344                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.601844                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.601871                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.data      1960377                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total        1960377                       # number of ReadReq hits
 system.cpu.l2cache.Writeback_hits::writebacks      2061794                       # number of Writeback hits
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
index 5e05f1621..79d4aa555 100644
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
@@ -497,7 +497,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
@@ -529,7 +529,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr
index 374965c0a..b4d96e4ea 100755
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr
@@ -1,4 +1,3 @@
 warn: Sockets disabled, not accepting gdb connections
 warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4]
-warn: CP14 unimplemented crn[15], opc1[7], crm[5], opc2[7]
 hack: be nice to actually delete the event here
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
index 5a5a625da..19d21974e 100755
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:10:14
-gem5 started Jun 29 2012 00:45:14
+gem5 compiled Jul  2 2012 09:08:16
+gem5 started Jul  2 2012 15:42:24
 gem5 executing on zizzer
 command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
@@ -67,4 +67,4 @@ info: Increasing stack size by one page.
   about 2 million people attended 
   the five best costumes got prizes 
 No errors!
-Exiting @ tick 210036334500 because target called exit()
+Exiting @ tick 213265939500 because target called exit()
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
index 43f7dedd0..e448a6379 100644
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
@@ -1,39 +1,39 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.210036                       # Number of seconds simulated
-sim_ticks                                210036334500                       # Number of ticks simulated
-final_tick                               210036334500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.213266                       # Number of seconds simulated
+sim_ticks                                213265939500                       # Number of ticks simulated
+final_tick                               213265939500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 177312                       # Simulator instruction rate (inst/s)
-host_op_rate                                   199743                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               73173320                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 239056                       # Number of bytes of host memory used
-host_seconds                                  2870.40                       # Real time elapsed on the host
-sim_insts                                   508955243                       # Number of instructions simulated
-sim_ops                                     573341803                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst            219136                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          10020416                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             10239552                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       219136                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          219136                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      6682560                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6682560                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               3424                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             156569                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                159993                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          104415                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               104415                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst              1043324                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             47708012                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                48751336                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         1043324                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1043324                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          31816209                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               31816209                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          31816209                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             1043324                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            47708012                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               80567546                       # Total bandwidth to/from this memory (bytes/s)
+host_inst_rate                                 150954                       # Simulator instruction rate (inst/s)
+host_op_rate                                   170051                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               63253971                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 238980                       # Number of bytes of host memory used
+host_seconds                                  3371.58                       # Real time elapsed on the host
+sim_insts                                   508955143                       # Number of instructions simulated
+sim_ops                                     573341703                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst            218944                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          10016576                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             10235520                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       218944                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          218944                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      6679616                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           6679616                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               3421                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             156509                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                159930                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          104369                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               104369                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst              1026624                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             46967537                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                47994162                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1026624                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1026624                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          31320594                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               31320594                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          31320594                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             1026624                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            46967537                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               79314756                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -77,143 +77,143 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  548                       # Number of system calls
-system.cpu.numCycles                        420072670                       # number of cpu cycles simulated
+system.cpu.numCycles                        426531880                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                180017694                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted          142687184                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect            7729396                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups              94339767                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                 87293897                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                180717428                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted          143299693                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect            7745708                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              94822680                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                 87599174                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                 12415335                       # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect              116774                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles          120382403                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      794428106                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   180017694                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           99709232                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     176656328                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                41234330                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles               91071148                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                   14                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles           358                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                 113830042                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               2509224                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          418577617                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.181681                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.031530                       # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS                 12446842                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect              117258                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles          120998369                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      797263404                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   180717428                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          100046016                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     177300353                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                41685655                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               95764916                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                   19                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles           750                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                 114346660                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               2503858                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          424958022                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.156047                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.022518                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                241934136     57.80%     57.80% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 14312407      3.42%     61.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 20602450      4.92%     66.14% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 22857238      5.46%     71.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 20951996      5.01%     76.61% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 13135363      3.14%     79.74% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 13267726      3.17%     82.91% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 12107850      2.89%     85.81% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 59408451     14.19%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                247670464     58.28%     58.28% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 14397332      3.39%     61.67% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 20689751      4.87%     66.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 22947722      5.40%     71.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 21025298      4.95%     76.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 13188609      3.10%     79.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 13288793      3.13%     83.12% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 12167829      2.86%     85.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 59582224     14.02%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            418577617                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.428539                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.891168                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                132749600                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              85626153                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 165029361                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               4780262                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               30392241                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             26480489                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 78151                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              870641905                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                312699                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles               30392241                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                142822329                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 6003622                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       66002577                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 159587024                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              13769824                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              815822534                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                   858                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                2869085                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               7326440                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents               62                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           963278183                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            3562240909                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       3562236360                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups              4549                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             672200323                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                291077860                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts            5318003                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts        5317721                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  67395600                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            171954811                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            74969765                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          27370082                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         14835909                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  760687253                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             6768595                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 671184661                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           1545827                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       191893024                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    487573539                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved        3047459                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     418577617                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.603489                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.725201                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            424958022                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.423690                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.869177                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                133827033                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              89884158                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 165222726                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               5205901                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               30818204                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             26548087                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 78411                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              873467434                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                311843                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               30818204                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                144286364                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 8884116                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       66224882                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 159795223                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              14949233                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              818684887                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                  1541                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                2838925                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               8204276                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents              192                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           966602186                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            3574693177                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       3574688542                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups              4635                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             672200163                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                294402023                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            5323897                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts        5323528                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  70458787                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            172688867                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            75177672                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          27536611                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         15452316                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  763600148                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             6775253                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 672568642                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           1541380                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       194741611                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    494202077                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved        3054137                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     424958022                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.582671                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.715070                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           157194444     37.55%     37.55% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            77339610     18.48%     56.03% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            70514833     16.85%     72.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            51630225     12.33%     85.21% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            31661646      7.56%     92.78% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            16095104      3.85%     96.62% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             9461042      2.26%     98.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             3409350      0.81%     99.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             1271363      0.30%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           161198015     37.93%     37.93% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            79163376     18.63%     56.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            71154341     16.74%     73.31% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            52720722     12.41%     85.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            30628875      7.21%     92.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            16032619      3.77%     96.69% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             9417662      2.22%     98.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             3389445      0.80%     99.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             1252967      0.29%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       418577617                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       424958022                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  446687      4.54%      4.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      4.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      4.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      4.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      4.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      4.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      4.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      4.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      4.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      4.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      4.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      4.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      4.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      4.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      4.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      4.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      4.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      4.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      4.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      4.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      4.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      4.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      4.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      4.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      4.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      4.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      4.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      4.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      4.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                6731982     68.43%     72.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               2658540     27.03%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  469414      4.82%      4.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      4.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      4.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      4.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      4.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      4.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      4.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      4.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      4.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      4.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      4.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      4.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      4.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      4.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      4.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      4.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      4.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      4.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      4.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      4.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      4.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      4.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      4.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      4.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      4.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      4.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      4.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      4.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      4.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                6674941     68.55%     73.37% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               2592845     26.63%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             450868550     67.18%     67.18% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               385779      0.06%     67.23% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             451773589     67.17%     67.17% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               385931      0.06%     67.23% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.23% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                 220      0.00%     67.23% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                 236      0.00%     67.23% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.23% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.23% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.23% # Type of FU issued
@@ -239,159 +239,159 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.00%     67.23% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.23% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.23% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.23% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            154882510     23.08%     90.31% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            65047599      9.69%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            155280491     23.09%     90.32% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            65128392      9.68%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              671184661                       # Type of FU issued
-system.cpu.iq.rate                           1.597782                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     9837209                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.014656                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         1772329499                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         960150284                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    650772394                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 476                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                942                       # Number of floating instruction queue writes
+system.cpu.iq.FU_type_0::total              672568642                       # Type of FU issued
+system.cpu.iq.rate                           1.576831                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     9737200                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.014478                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         1781373379                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         965920498                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    652179695                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 507                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                988                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              681021630                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     240                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          8403522                       # Number of loads that had data forwarded from stores
+system.cpu.iq.int_alu_accesses              682305587                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     255                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          8455481                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     45181752                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        43422                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       806126                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     17365784                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     45915828                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        43410                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       808399                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     17573711                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        19422                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          1337                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        19491                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          1190                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               30392241                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 2471437                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                146089                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           773606723                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts           1210159                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             171954811                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             74969765                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            5279868                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  67842                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                  6482                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         806126                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        4698240                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      6420025                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             11118265                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             661214126                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             151365480                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           9970535                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles               30818204                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 4164130                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                269264                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           776544403                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           1215899                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             172688867                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             75177672                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            5286544                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 138154                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                  7994                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         808399                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        4709852                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      6436476                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             11146328                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             662608710                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             151741633                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           9959932                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                       6150875                       # number of nop insts executed
-system.cpu.iew.exec_refs                    214988835                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                137027568                       # Number of branches executed
-system.cpu.iew.exec_stores                   63623355                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.574047                       # Inst execution rate
-system.cpu.iew.wb_sent                      655977937                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     650772410                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 374973371                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 645025945                       # num instructions consuming a value
+system.cpu.iew.exec_nop                       6169002                       # number of nop insts executed
+system.cpu.iew.exec_refs                    215464084                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                137322673                       # Number of branches executed
+system.cpu.iew.exec_stores                   63722451                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.553480                       # Inst execution rate
+system.cpu.iew.wb_sent                      657371500                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     652179711                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 375708324                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 644520569                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.549190                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.581331                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.529029                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.582927                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts      510299127                       # The number of committed instructions
-system.cpu.commit.commitCommittedOps        574685687                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts       198937259                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls         3721136                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           9897053                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    388185377                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.480441                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.160280                       # Number of insts commited each cycle
+system.cpu.commit.commitCommittedInsts      510299027                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps        574685587                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts       201878689                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         3721116                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts           9919991                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    394139819                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.458075                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.151494                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    174260848     44.89%     44.89% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    102323189     26.36%     71.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     36274304      9.34%     80.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     18231179      4.70%     85.29% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     17368323      4.47%     89.77% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      8208578      2.11%     91.88% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      6882791      1.77%     93.65% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      3781895      0.97%     94.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     20854270      5.37%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    179649221     45.58%     45.58% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    103014328     26.14%     71.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     36282541      9.21%     80.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     18903013      4.80%     85.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     16466891      4.18%     89.90% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      8169845      2.07%     91.97% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      6904317      1.75%     93.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      3742857      0.95%     94.67% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     21006806      5.33%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    388185377                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            510299127                       # Number of instructions committed
-system.cpu.commit.committedOps              574685687                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    394139819                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            510299027                       # Number of instructions committed
+system.cpu.commit.committedOps              574685587                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                      184377040                       # Number of memory references committed
-system.cpu.commit.loads                     126773059                       # Number of loads committed
+system.cpu.commit.refs                      184377000                       # Number of memory references committed
+system.cpu.commit.loads                     126773039                       # Number of loads committed
 system.cpu.commit.membars                     1488542                       # Number of memory barriers committed
-system.cpu.commit.branches                  120192244                       # Number of branches committed
+system.cpu.commit.branches                  120192224                       # Number of branches committed
 system.cpu.commit.fp_insts                         16                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 473701709                       # Number of committed integer instructions.
+system.cpu.commit.int_insts                 473701629                       # Number of committed integer instructions.
 system.cpu.commit.function_calls              9757362                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events              20854270                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events              21006806                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   1140946915                       # The number of ROB reads
-system.cpu.rob.rob_writes                  1577778936                       # The number of ROB writes
-system.cpu.timesIdled                           55077                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         1495053                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                   508955243                       # Number of Instructions Simulated
-system.cpu.committedOps                     573341803                       # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total             508955243                       # Number of Instructions Simulated
-system.cpu.cpi                               0.825363                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.825363                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.211589                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.211589                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               3085576786                       # number of integer regfile reads
-system.cpu.int_regfile_writes               758984284                       # number of integer regfile writes
+system.cpu.rob.rob_reads                   1149690151                       # The number of ROB reads
+system.cpu.rob.rob_writes                  1584089992                       # The number of ROB writes
+system.cpu.timesIdled                           76999                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         1573858                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                   508955143                       # Number of Instructions Simulated
+system.cpu.committedOps                     573341703                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total             508955143                       # Number of Instructions Simulated
+system.cpu.cpi                               0.838054                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.838054                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.193241                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.193241                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               3092178369                       # number of integer regfile reads
+system.cpu.int_regfile_writes               760489659                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
-system.cpu.misc_regfile_reads              1021861854                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                4464092                       # number of misc regfile writes
-system.cpu.icache.replacements                  15860                       # number of replacements
-system.cpu.icache.tagsinuse               1099.172767                       # Cycle average of tags in use
-system.cpu.icache.total_refs                113810641                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                  17722                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                6421.997574                       # Average number of references to valid blocks.
+system.cpu.misc_regfile_reads              1025175182                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                4464052                       # number of misc regfile writes
+system.cpu.icache.replacements                  15943                       # number of replacements
+system.cpu.icache.tagsinuse               1097.454054                       # Cycle average of tags in use
+system.cpu.icache.total_refs                114326971                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                  17802                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                6422.141950                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst    1099.172767                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.536705                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.536705                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst    113810641                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       113810641                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     113810641                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        113810641                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    113810641                       # number of overall hits
-system.cpu.icache.overall_hits::total       113810641                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        19401                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         19401                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        19401                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          19401                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        19401                       # number of overall misses
-system.cpu.icache.overall_misses::total         19401                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    248637000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    248637000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    248637000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    248637000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    248637000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    248637000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    113830042                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    113830042                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    113830042                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    113830042                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    113830042                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    113830042                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000170                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000170                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000170                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000170                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000170                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000170                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12815.679604                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 12815.679604                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 12815.679604                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 12815.679604                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 12815.679604                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 12815.679604                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst    1097.454054                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.535866                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.535866                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst    114326971                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       114326971                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     114326971                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        114326971                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    114326971                       # number of overall hits
+system.cpu.icache.overall_hits::total       114326971                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        19689                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         19689                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        19689                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          19689                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        19689                       # number of overall misses
+system.cpu.icache.overall_misses::total         19689                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    281738500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    281738500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    281738500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    281738500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    281738500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    281738500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    114346660                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    114346660                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    114346660                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    114346660                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    114346660                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    114346660                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000172                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000172                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000172                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000172                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000172                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000172                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14309.436741                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 14309.436741                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 14309.436741                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 14309.436741                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 14309.436741                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 14309.436741                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -400,254 +400,256 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1635                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         1635                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         1635                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         1635                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         1635                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         1635                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        17766                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        17766                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        17766                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        17766                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        17766                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        17766                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    157002000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    157002000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    157002000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    157002000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    157002000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    157002000                       # number of overall MSHR miss cycles
+system.cpu.icache.writebacks::writebacks            1                       # number of writebacks
+system.cpu.icache.writebacks::total                 1                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1829                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         1829                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         1829                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         1829                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         1829                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         1829                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        17860                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        17860                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        17860                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        17860                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        17860                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        17860                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    184743000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    184743000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    184743000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    184743000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    184743000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    184743000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000156                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000156                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000156                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000156                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000156                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000156                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  8837.217156                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  8837.217156                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  8837.217156                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total  8837.217156                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  8837.217156                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total  8837.217156                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10343.952968                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10343.952968                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10343.952968                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 10343.952968                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10343.952968                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 10343.952968                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                1187572                       # number of replacements
-system.cpu.dcache.tagsinuse               4054.018588                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                194536167                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                1191668                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                 163.246950                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle             4842467000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4054.018588                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.989751                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.989751                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data    137268360                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       137268360                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     52802735                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       52802735                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data      2232908                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total      2232908                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data      2232045                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total      2232045                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     190071095                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        190071095                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    190071095                       # number of overall hits
-system.cpu.dcache.overall_hits::total       190071095                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1261511                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1261511                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1436571                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1436571                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data           44                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total           44                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      2698082                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2698082                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      2698082                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2698082                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  11193325500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  11193325500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  24423594500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  24423594500                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       430500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total       430500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  35616920000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  35616920000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  35616920000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  35616920000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    138529871                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    138529871                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.replacements                1188340                       # number of replacements
+system.cpu.dcache.tagsinuse               4054.521086                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                194732293                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                1192436                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 163.306285                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle             4858281000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4054.521086                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.989873                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.989873                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data    137583731                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       137583731                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     52683552                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       52683552                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data      2232862                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total      2232862                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data      2232025                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total      2232025                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data     190267283                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        190267283                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    190267283                       # number of overall hits
+system.cpu.dcache.overall_hits::total       190267283                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1266916                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1266916                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1555754                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1555754                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data           41                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total           41                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data      2822670                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2822670                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2822670                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2822670                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  15542571000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  15542571000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  33103572500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  33103572500                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       516500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total       516500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  48646143500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  48646143500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  48646143500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  48646143500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    138850647                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    138850647                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     54239306                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     54239306                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data      2232952                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total      2232952                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data      2232045                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total      2232045                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    192769177                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    192769177                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    192769177                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    192769177                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.009106                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.009106                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.026486                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.026486                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000020                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000020                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.013996                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.013996                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.013996                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.013996                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data  8872.951167                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total  8872.951167                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17001.313893                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 17001.313893                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data  9784.090909                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total  9784.090909                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 13200.829330                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 13200.829330                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 13200.829330                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 13200.829330                       # average overall miss latency
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data      2232903                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total      2232903                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data      2232025                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total      2232025                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    193089953                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    193089953                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    193089953                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    193089953                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.009124                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.009124                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.028683                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.028683                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000018                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000018                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.014618                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.014618                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.014618                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.014618                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12268.035923                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 12268.035923                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21278.153551                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 21278.153551                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12597.560976                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12597.560976                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 17234.088115                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 17234.088115                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 17234.088115                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 17234.088115                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets      3248500                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets      3299000                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets             559                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets  5811.270125                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets  5901.610018                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      1101877                       # number of writebacks
-system.cpu.dcache.writebacks::total           1101877                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       417972                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       417972                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1088398                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      1088398                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           44                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total           44                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1506370                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1506370                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1506370                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1506370                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       843539                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       843539                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       348173                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       348173                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1191712                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1191712                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1191712                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1191712                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   3801302500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   3801302500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   4208028500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   4208028500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data   8009331000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total   8009331000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data   8009331000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total   8009331000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006089                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006089                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.writebacks::writebacks      1102764                       # number of writebacks
+system.cpu.dcache.writebacks::total           1102764                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       422570                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       422570                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1207611                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      1207611                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           41                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total           41                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      1630181                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1630181                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1630181                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1630181                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       844346                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       844346                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       348143                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       348143                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1192489                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1192489                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1192489                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1192489                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   4793812500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   4793812500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   4284005501                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   4284005501                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   9077818001                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   9077818001                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data   9077818001                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   9077818001                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006081                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006081                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006419                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006419                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006182                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.006182                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006182                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.006182                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  4506.374335                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  4506.374335                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 12086.027636                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 12086.027636                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  6720.861248                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total  6720.861248                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  6720.861248                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total  6720.861248                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006176                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.006176                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006176                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.006176                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  5677.545106                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  5677.545106                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 12305.304145                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 12305.304145                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  7612.496217                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total  7612.496217                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  7612.496217                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total  7612.496217                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.replacements                128814                       # number of replacements
-system.cpu.l2cache.tagsinuse             26521.071882                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 1726136                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                160049                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                 10.785047                       # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle          108383253000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 22699.952079                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst    308.453582                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data   3512.666221                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.692748                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst     0.009413                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.107198                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.809359                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst        14292                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data       789500                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total         803792                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      1101877                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      1101877                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data           38                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total           38                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       245577                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       245577                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        14292                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      1035077                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         1049369                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst        14292                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      1035077                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        1049369                       # number of overall hits
+system.cpu.l2cache.replacements                128738                       # number of replacements
+system.cpu.l2cache.tagsinuse             26549.866286                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 1724393                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                159968                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                 10.779612                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle          109550112000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::writebacks 22721.325025                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst    308.211644                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data   3520.329617                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.693400                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.009406                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.107432                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.810238                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst        14375                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data       787281                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         801656                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      1102765                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      1102765                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data           44                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total           44                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       248622                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       248622                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst        14375                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      1035903                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         1050278                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst        14375                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      1035903                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        1050278                       # number of overall hits
 system.cpu.l2cache.ReadReq_misses::cpu.inst         3428                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data        53156                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        56584                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data            5                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total            5                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       103436                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       103436                       # number of ReadExReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data        53041                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        56469                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data            6                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total            6                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       103489                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       103489                       # number of ReadExReq misses
 system.cpu.l2cache.demand_misses::cpu.inst         3428                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       156592                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        160020                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       156530                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        159958                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst         3428                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       156592                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       160020                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    117618500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1820625500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total   1938244000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   3542483500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   3542483500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    117618500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data   5363109000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total   5480727500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    117618500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data   5363109000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total   5480727500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst        17720                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data       842656                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total       860376                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      1101877                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      1101877                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data           43                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total           43                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       349013                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       349013                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        17720                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      1191669                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      1209389                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        17720                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      1191669                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      1209389                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.193454                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.063081                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.065767                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.116279                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.116279                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.296367                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.296367                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.193454                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.131406                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.132315                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.193454                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.131406                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.132315                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34311.114352                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34250.611408                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 34254.276827                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34248.071271                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34248.071271                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34311.114352                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34248.933534                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 34250.265592                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34311.114352                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34248.933534                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 34250.265592                       # average overall miss latency
+system.cpu.l2cache.overall_misses::cpu.data       156530                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       159958                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    121134500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1832266000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   1953400500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   3547601500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   3547601500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    121134500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   5379867500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   5501002000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    121134500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   5379867500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   5501002000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst        17803                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data       840322                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       858125                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      1102765                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      1102765                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data           50                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total           50                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       352111                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       352111                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        17803                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      1192433                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      1210236                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        17803                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      1192433                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      1210236                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.192552                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.063120                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.065805                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.120000                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.120000                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.293910                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.293910                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.192552                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.131269                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.132171                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.192552                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.131269                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.132171                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35336.785298                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34544.333629                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 34592.440100                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34279.986279                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34279.986279                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35336.785298                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34369.561745                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 34390.289951                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35336.785298                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34369.561745                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 34390.289951                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -656,69 +658,69 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       104415                       # number of writebacks
-system.cpu.l2cache.writebacks::total           104415                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            4                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           22                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total           26                       # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst            4                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data           22                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           26                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst            4                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data           22                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           26                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3424                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        53134                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        56558                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            5                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total            5                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       103436                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       103436                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3424                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       156570                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       159994                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3424                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       156570                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       159994                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    106506000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1650725500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1757231500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       155000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       155000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   3207102500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   3207102500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    106506000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   4857828000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   4964334000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    106506000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   4857828000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   4964334000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.193228                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.063055                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.065736                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.116279                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.116279                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.296367                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.296367                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.193228                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.131387                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.132293                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.193228                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.131387                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.132293                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31105.724299                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31067.216848                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31069.548075                       # average ReadReq mshr miss latency
+system.cpu.l2cache.writebacks::writebacks       104369                       # number of writebacks
+system.cpu.l2cache.writebacks::total           104369                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            7                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           20                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total           27                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst            7                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data           20                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           27                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst            7                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data           20                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total           27                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3421                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        53021                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        56442                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            6                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total            6                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       103489                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       103489                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3421                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       156510                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       159931                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3421                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       156510                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       159931                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    110230000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1664605500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1774835500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       186000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       186000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   3213112500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   3213112500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    110230000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   4877718000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   4987948000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    110230000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   4877718000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   4987948000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.192159                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.063096                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.065774                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.120000                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.120000                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.293910                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.293910                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.192159                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.131253                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.132149                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.192159                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.131253                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.132149                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32221.572640                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31395.211331                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31445.297828                       # average ReadReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        31000                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        31000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31005.670173                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31005.670173                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31105.724299                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31026.556812                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31028.251059                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31105.724299                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31026.556812                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31028.251059                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31047.864990                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31047.864990                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32221.572640                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31165.535749                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31188.124879                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32221.572640                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31165.535749                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31188.124879                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
index 6a9499ace..ffe909bf7 100644
--- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
@@ -166,7 +166,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
@@ -198,7 +198,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout
index 64f0d2855..384283516 100755
--- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:10:14
-gem5 started Jun 29 2012 00:48:24
+gem5 compiled Jul  2 2012 09:08:16
+gem5 started Jul  2 2012 15:48:14
 gem5 executing on zizzer
 command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
@@ -67,4 +67,4 @@ info: Increasing stack size by one page.
   about 2 million people attended 
   the five best costumes got prizes 
 No errors!
-Exiting @ tick 718982756000 because target called exit()
+Exiting @ tick 720345914000 because target called exit()
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
index 8439efddd..b8350e4f6 100644
--- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.718983                       # Number of seconds simulated
-sim_ticks                                718982756000                       # Number of ticks simulated
-final_tick                               718982756000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.720346                       # Number of seconds simulated
+sim_ticks                                720345914000                       # Number of ticks simulated
+final_tick                               720345914000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1474104                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1661066                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2098778351                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 237008                       # Number of bytes of host memory used
-host_seconds                                   342.57                       # Real time elapsed on the host
+host_inst_rate                                 808443                       # Simulator instruction rate (inst/s)
+host_op_rate                                   910979                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1153216038                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 236932                       # Number of bytes of host memory used
+host_seconds                                   624.64                       # Real time elapsed on the host
 sim_insts                                   504986853                       # Number of instructions simulated
 sim_ops                                     569034839                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst            178368                       # Number of bytes read from this memory
@@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data             150998                       # Nu
 system.physmem.num_reads::total                153785                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks          102730                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total               102730                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               248084                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             13441034                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                13689118                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          248084                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             248084                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           9144475                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                9144475                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           9144475                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              248084                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            13441034                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               22833594                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               247614                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             13415599                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                13663213                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          247614                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             247614                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           9127171                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                9127171                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           9127171                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              247614                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            13415599                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               22790384                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -77,7 +77,7 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  548                       # Number of system calls
-system.cpu.numCycles                       1437965512                       # number of cpu cycles simulated
+system.cpu.numCycles                       1440691828                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   504986853                       # Number of instructions committed
@@ -96,18 +96,18 @@ system.cpu.num_mem_refs                     182890034                       # nu
 system.cpu.num_load_insts                   126029555                       # Number of load instructions
 system.cpu.num_store_insts                   56860479                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                 1437965512                       # Number of busy cycles
+system.cpu.num_busy_cycles                 1440691828                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                   9788                       # number of replacements
-system.cpu.icache.tagsinuse                983.088334                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                983.378720                       # Cycle average of tags in use
 system.cpu.icache.total_refs                516599855                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                  11521                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               44839.845066                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     983.088334                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.480024                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.480024                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst     983.378720                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.480165                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.480165                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst    516599855                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total       516599855                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst     516599855                       # number of demand (read+write) hits
@@ -120,12 +120,12 @@ system.cpu.icache.demand_misses::cpu.inst        11521                       # n
 system.cpu.icache.demand_misses::total          11521                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst        11521                       # number of overall misses
 system.cpu.icache.overall_misses::total         11521                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    278348000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    278348000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    278348000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    278348000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    278348000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    278348000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    279753000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    279753000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    279753000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    279753000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    279753000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    279753000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst    516611376                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total    516611376                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst    516611376                       # number of demand (read+write) accesses
@@ -138,12 +138,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000022
 system.cpu.icache.demand_miss_rate::total     0.000022                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000022                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000022                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24160.055551                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 24160.055551                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 24160.055551                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 24160.055551                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 24160.055551                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 24160.055551                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24282.006770                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 24282.006770                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 24282.006770                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 24282.006770                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 24282.006770                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 24282.006770                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -158,34 +158,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst        11521
 system.cpu.icache.demand_mshr_misses::total        11521                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst        11521                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total        11521                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    243785000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    243785000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    243785000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    243785000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    243785000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    243785000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    245190000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    245190000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    245190000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    245190000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    245190000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    245190000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000022                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000022                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000022                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000022                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000022                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000022                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21160.055551                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21160.055551                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21160.055551                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 21160.055551                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21160.055551                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 21160.055551                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21282.006770                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21282.006770                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21282.006770                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 21282.006770                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21282.006770                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 21282.006770                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                1134822                       # number of replacements
-system.cpu.dcache.tagsinuse               4065.352134                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               4065.381389                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                179817786                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                1138918                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                 157.884752                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle            11889977000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4065.352134                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.992518                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.992518                       # Average percentage of cache occupancy
+system.cpu.dcache.warmup_cycle            11899663000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4065.381389                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.992525                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.992525                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data    122957658                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total       122957658                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     53883046                       # number of WriteReq hits
@@ -206,14 +206,14 @@ system.cpu.dcache.demand_misses::cpu.data      1138918                       # n
 system.cpu.dcache.demand_misses::total        1138918                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data      1138918                       # number of overall misses
 system.cpu.dcache.overall_misses::total       1138918                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  12960486000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  12960486000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   9326282000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   9326282000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  22286768000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  22286768000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  22286768000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  22286768000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  13181704000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  13181704000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   9327564000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   9327564000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  22509268000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  22509268000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  22509268000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  22509268000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data    123740316                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total    123740316                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     54239306                       # number of WriteReq accesses(hits+misses)
@@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.006399
 system.cpu.dcache.demand_miss_rate::total     0.006399                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.006399                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.006399                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16559.577747                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 16559.577747                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26178.302363                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 26178.302363                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 19568.369277                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 19568.369277                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 19568.369277                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 19568.369277                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16842.227384                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 16842.227384                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26181.900859                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 26181.900859                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 19763.730137                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 19763.730137                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 19763.730137                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 19763.730137                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data      1138918
 system.cpu.dcache.demand_mshr_misses::total      1138918                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data      1138918                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total      1138918                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  10612512000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  10612512000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8257502000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   8257502000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  18870014000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  18870014000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  18870014000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  18870014000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  10833730000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  10833730000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8258784000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   8258784000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  19092514000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  19092514000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  19092514000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  19092514000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006325                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006325                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006568                       # mshr miss rate for WriteReq accesses
@@ -276,28 +276,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006399
 system.cpu.dcache.demand_mshr_miss_rate::total     0.006399                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006399                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.006399                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13559.577747                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13559.577747                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23178.302363                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23178.302363                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16568.369277                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 16568.369277                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16568.369277                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 16568.369277                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13842.227384                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13842.227384                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23181.900859                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23181.900859                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16763.730137                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 16763.730137                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16763.730137                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 16763.730137                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                122482                       # number of replacements
-system.cpu.l2cache.tagsinuse             26935.750905                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse             26939.836590                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                 1623186                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                153644                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                 10.564591                       # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle          344124821000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 23223.605882                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst    246.683502                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data   3465.461521                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.708728                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst     0.007528                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.105757                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.822014                       # Average percentage of cache occupancy
+system.cpu.l2cache.warmup_cycle          344531371000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::writebacks 23226.765026                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst    246.719769                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data   3466.351794                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.708825                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.007529                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.105785                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.822139                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst         8734                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data       734961                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total         743695                       # number of ReadReq hits
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
index 1f04164bf..9aac7b043 100644
--- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
@@ -500,7 +500,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
@@ -532,7 +532,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
 slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
 
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
index 2f3625356..96a3d5c32 100755
--- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
@@ -1,15 +1,15 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:08:09
-gem5 started Jun 28 2012 23:20:26
+gem5 compiled Jul  2 2012 08:58:39
+gem5 started Jul  2 2012 13:33:28
 gem5 executing on zizzer
 command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/20.parser/x86/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
  Reading the dictionary files: ***********************info: Increasing stack size by one page.
-********************info: Increasing stack size by one page.
+***************info: Increasing stack size by one page.
 info: Increasing stack size by one page.
 info: Increasing stack size by one page.
 info: Increasing stack size by one page.
@@ -22,7 +22,7 @@ info: Increasing stack size by one page.
 info: Increasing stack size by one page.
 info: Increasing stack size by one page.
 info: Increasing stack size by one page.
-******
+***********
  58924 words stored in 3784810 bytes
 
 
@@ -80,4 +80,4 @@ Echoing of input sentence turned on.
   about 2 million people attended 
   the five best costumes got prizes 
 No errors!
-Exiting @ tick 455813328500 because target called exit()
+Exiting @ tick 460577560500 because target called exit()
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
index 46181ad4f..96eed0126 100644
--- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
@@ -1,280 +1,280 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.455813                       # Number of seconds simulated
-sim_ticks                                455813328500                       # Number of ticks simulated
-final_tick                               455813328500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.460578                       # Number of seconds simulated
+sim_ticks                                460577560500                       # Number of ticks simulated
+final_tick                               460577560500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 110548                       # Simulator instruction rate (inst/s)
-host_op_rate                                   204416                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               60939389                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 266636                       # Number of bytes of host memory used
-host_seconds                                  7479.78                       # Real time elapsed on the host
+host_inst_rate                                 104932                       # Simulator instruction rate (inst/s)
+host_op_rate                                   194032                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               58448222                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 266596                       # Number of bytes of host memory used
+host_seconds                                  7880.10                       # Real time elapsed on the host
 sim_insts                                   826877144                       # Number of instructions simulated
 sim_ops                                    1528988756                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst            220672                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          27604992                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             27825664                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       220672                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          220672                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     20791296                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          20791296                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               3448                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             431328                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                434776                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          324864                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               324864                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               484128                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             60562055                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                61046183                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          484128                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             484128                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          45613620                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               45613620                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          45613620                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              484128                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            60562055                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              106659803                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst            222400                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          27604032                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             27826432                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       222400                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          222400                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     20791104                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          20791104                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               3475                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             431313                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                434788                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          324861                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               324861                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               482872                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             59933515                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                60416387                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          482872                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             482872                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          45141374                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               45141374                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          45141374                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              482872                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            59933515                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              105557761                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                  551                       # Number of system calls
-system.cpu.numCycles                        911626658                       # number of cpu cycles simulated
+system.cpu.numCycles                        921155122                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                225614318                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted          225614318                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect           14285714                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups             160541063                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                155870604                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                225826893                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted          225826893                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect           14312665                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups             160782597                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                155982448                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
 system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles          191565109                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     1263061891                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   225614318                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          155870604                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     392054994                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                98473885                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles              230412581                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                25920                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        273577                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                 183478574                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               3652581                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          898267437                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.606318                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.392133                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          191746261                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1263371603                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   225826893                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          155982448                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     392161652                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                98608350                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles              239363044                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                24915                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        235054                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                 183579479                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               3670479                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          907575951                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.580457                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.385202                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                510675527     56.85%     56.85% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 25992328      2.89%     59.74% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 29100733      3.24%     62.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 30303597      3.37%     66.36% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 19641643      2.19%     68.54% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 25615145      2.85%     71.40% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 32617140      3.63%     75.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 30849776      3.43%     78.46% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                193471548     21.54%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                519878601     57.28%     57.28% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 25999906      2.86%     60.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 29091750      3.21%     63.35% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 30316480      3.34%     66.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 19610375      2.16%     68.85% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 25620095      2.82%     71.68% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 32648944      3.60%     75.27% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 30886362      3.40%     78.68% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                193523438     21.32%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            898267437                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.247485                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.385503                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                252696641                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             182534450                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 330171612                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              48929478                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               83935256                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts             2290198570                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                     4                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles               83935256                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                289311592                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                40780199                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          14639                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 340344585                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles             143881166                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             2240282902                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                  2186                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents               22940117                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents             103602655                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents            11705                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands          2887046684                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            6493129070                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       6492267923                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups            861147                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            907575951                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.245156                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.371508                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                253842060                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             190511569                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 329127835                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              50049462                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               84045025                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts             2290915196                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                     2                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               84045025                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                290488035                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                45203385                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          15283                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 340026605                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             147797618                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             2240907588                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                  2049                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               24533767                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents             107236940                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents            12284                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands          2887565810                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            6495003002                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       6494129328                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups            873674                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps            1993077484                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                893969200                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               1261                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts           1244                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 345524950                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            540216674                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           217364695                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads         216116185                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         63552241                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 2143188368                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded               61311                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1846653007                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           1596963                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       612532438                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined   1230905034                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved          60758                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     898267437                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.055794                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.806511                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                894488326                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               1298                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           1285                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 351684544                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            540282589                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           217467537                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads         211757951                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         61365379                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 2143556526                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               68297                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1846659599                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           1592599                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       612964134                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined   1231726867                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved          67744                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     907575951                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.034716                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.801175                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           244119309     27.18%     27.18% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           156083539     17.38%     44.55% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           150204364     16.72%     61.27% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           147125554     16.38%     77.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4           103909500     11.57%     89.22% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            58948328      6.56%     95.78% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            27781277      3.09%     98.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             9047752      1.01%     99.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             1047814      0.12%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           248881296     27.42%     27.42% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           159283558     17.55%     44.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           154019271     16.97%     61.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           148934495     16.41%     78.35% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            98823398     10.89%     89.24% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            59633911      6.57%     95.81% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            27979654      3.08%     98.90% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             8970001      0.99%     99.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             1050367      0.12%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       898267437                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       907575951                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 2653512     16.69%     16.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     16.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     16.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     16.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     16.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     16.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     16.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     16.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     16.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     16.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     16.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     16.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     16.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     16.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     16.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     16.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     16.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     16.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     16.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     16.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     16.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     16.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     16.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     16.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     16.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     16.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     16.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     16.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     16.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               10033753     63.11%     79.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               3212720     20.21%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 2635862     18.39%     18.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     18.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     18.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     18.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     18.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     18.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     18.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     18.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     18.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     18.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     18.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     18.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     18.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     18.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     18.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     18.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     18.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     18.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     18.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     18.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     18.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     18.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     18.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     18.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     18.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     18.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     18.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     18.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     18.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                8471298     59.09%     77.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               3228137     22.52%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass           2721869      0.15%      0.15% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1219400147     66.03%     66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    0      0.00%     66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            447092064     24.21%     90.39% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           177438927      9.61%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass           2716270      0.15%      0.15% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1219519641     66.04%     66.19% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    0      0.00%     66.19% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     66.19% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     66.19% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.19% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.19% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     66.19% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     66.19% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     66.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     66.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     66.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     66.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     66.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     66.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     66.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     66.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     66.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     66.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     66.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     66.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     66.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     66.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     66.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     66.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     66.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.19% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            447028129     24.21%     90.39% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           177395559      9.61%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1846653007                       # Type of FU issued
-system.cpu.iq.rate                           2.025668                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    15899985                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.008610                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         4609062574                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        2755747075                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1806129295                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                7825                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes             296338                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses          285                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             1859828366                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                    2757                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads        167960734                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             1846659599                       # Type of FU issued
+system.cpu.iq.rate                           2.004722                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    14335297                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.007763                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         4616815245                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        2756549096                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1806310045                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                7800                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes             300622                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses          277                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             1858275871                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                    2755                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads        168023437                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    156114514                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses       428176                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       272950                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     68204770                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads    156180429                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       430384                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       272150                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     68307598                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads         6724                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked             7                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads         7189                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               83935256                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 5705090                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               1089193                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          2143249679                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts           2772043                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             540216674                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            217364955                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               5665                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 876205                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 14852                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         272950                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect       10085276                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      5239623                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             15324899                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            1818663600                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             438639718                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          27989407                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles               84045025                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 6572333                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               1289879                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          2143624823                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           2858157                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             540282589                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            217467783                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               5279                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 972146                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 66800                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         272150                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect       10086391                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      5256955                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             15343346                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1818812244                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             438622961                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          27847355                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                    610490535                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                170808194                       # Number of branches executed
-system.cpu.iew.exec_stores                  171850817                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.994965                       # Inst execution rate
-system.cpu.iew.wb_sent                     1813450071                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    1806129580                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1379661197                       # num instructions producing a value
-system.cpu.iew.wb_consumers                2939711936                       # num instructions consuming a value
+system.cpu.iew.exec_refs                    610455243                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                170879995                       # Number of branches executed
+system.cpu.iew.exec_stores                  171832282                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.974491                       # Inst execution rate
+system.cpu.iew.wb_sent                     1813575376                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1806310322                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1378798297                       # num instructions producing a value
+system.cpu.iew.wb_consumers                2933608967                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.981216                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.469319                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.960919                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.470001                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts      826877144                       # The number of committed instructions
 system.cpu.commit.commitCommittedOps       1528988756                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts       614283465                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       614662287                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             553                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts          14312346                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    814332181                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.877598                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.330573                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts          14337681                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    823530926                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.856626                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.319528                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    298731075     36.68%     36.68% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    203556250     25.00%     61.68% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     73630894      9.04%     70.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     94876671     11.65%     82.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     30957165      3.80%     86.18% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     28752943      3.53%     89.71% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     16466236      2.02%     91.73% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     11737662      1.44%     93.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     55623285      6.83%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    305238213     37.06%     37.06% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    205541162     24.96%     62.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     74423413      9.04%     71.06% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     96471007     11.71%     82.77% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     29999240      3.64%     86.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     28772955      3.49%     89.91% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     15805357      1.92%     91.83% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     11742762      1.43%     93.26% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     55536817      6.74%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    814332181                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    823530926                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            826877144                       # Number of instructions committed
 system.cpu.commit.committedOps             1528988756                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -285,69 +285,69 @@ system.cpu.commit.branches                  149758588                       # Nu
 system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                1528317614                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                    0                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events              55623285                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events              55536817                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   2901981117                       # The number of ROB reads
-system.cpu.rob.rob_writes                  4370596606                       # The number of ROB writes
-system.cpu.timesIdled                          304669                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        13359221                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                   2911645152                       # The number of ROB reads
+system.cpu.rob.rob_writes                  4371462099                       # The number of ROB writes
+system.cpu.timesIdled                          309415                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        13579171                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   826877144                       # Number of Instructions Simulated
 system.cpu.committedOps                    1528988756                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total             826877144                       # Number of Instructions Simulated
-system.cpu.cpi                               1.102493                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.102493                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.907035                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.907035                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               4004133317                       # number of integer regfile reads
-system.cpu.int_regfile_writes              2286262019                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                       284                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                        1                       # number of floating regfile writes
-system.cpu.misc_regfile_reads              1001892809                       # number of misc regfile reads
-system.cpu.icache.replacements                   5521                       # number of replacements
-system.cpu.icache.tagsinuse               1042.048866                       # Cycle average of tags in use
-system.cpu.icache.total_refs                183243707                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                   7141                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs               25660.790786                       # Average number of references to valid blocks.
+system.cpu.cpi                               1.114017                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.114017                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.897652                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.897652                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               4004251902                       # number of integer regfile reads
+system.cpu.int_regfile_writes              2286361140                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                       274                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                        3                       # number of floating regfile writes
+system.cpu.misc_regfile_reads              1001934144                       # number of misc regfile reads
+system.cpu.icache.replacements                   5528                       # number of replacements
+system.cpu.icache.tagsinuse               1043.833365                       # Cycle average of tags in use
+system.cpu.icache.total_refs                183339964                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                   7144                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               25663.488802                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst    1042.048866                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.508813                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.508813                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst    183260633                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       183260633                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     183260633                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        183260633                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    183260633                       # number of overall hits
-system.cpu.icache.overall_hits::total       183260633                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       217941                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        217941                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       217941                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         217941                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       217941                       # number of overall misses
-system.cpu.icache.overall_misses::total        217941                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   1509664000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   1509664000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   1509664000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   1509664000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   1509664000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   1509664000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    183478574                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    183478574                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    183478574                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    183478574                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    183478574                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    183478574                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.001188                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.001188                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.001188                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.001188                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.001188                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.001188                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  6926.938942                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total  6926.938942                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst  6926.938942                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total  6926.938942                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst  6926.938942                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total  6926.938942                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst    1043.833365                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.509684                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.509684                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst    183356988                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       183356988                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     183356988                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        183356988                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    183356988                       # number of overall hits
+system.cpu.icache.overall_hits::total       183356988                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       222491                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        222491                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       222491                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         222491                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       222491                       # number of overall misses
+system.cpu.icache.overall_misses::total        222491                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   1555664000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   1555664000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   1555664000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   1555664000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   1555664000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   1555664000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    183579479                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    183579479                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    183579479                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    183579479                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    183579479                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    183579479                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.001212                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.001212                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.001212                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.001212                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.001212                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.001212                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  6992.031138                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total  6992.031138                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst  6992.031138                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total  6992.031138                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst  6992.031138                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total  6992.031138                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -358,94 +358,94 @@ system.cpu.icache.fast_writes                       0                       # nu
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks            8                       # number of writebacks
 system.cpu.icache.writebacks::total                 8                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1622                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         1622                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         1622                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         1622                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         1622                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         1622                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       216319                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       216319                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       216319                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       216319                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       216319                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       216319                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    823021000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    823021000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    823021000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    823021000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    823021000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    823021000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.001179                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.001179                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.001179                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.001179                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.001179                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.001179                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  3804.663483                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  3804.663483                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  3804.663483                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total  3804.663483                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  3804.663483                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total  3804.663483                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1714                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         1714                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         1714                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         1714                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         1714                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         1714                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       220777                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       220777                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       220777                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       220777                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       220777                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       220777                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    807311500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    807311500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    807311500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    807311500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    807311500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    807311500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.001203                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.001203                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.001203                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.001203                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.001203                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.001203                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  3656.682988                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  3656.682988                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  3656.682988                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total  3656.682988                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  3656.682988                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total  3656.682988                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                2527069                       # number of replacements
-system.cpu.dcache.tagsinuse               4086.938445                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                415239447                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                2531165                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                 164.050722                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle             2117139000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4086.938445                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.997788                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.997788                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data    266396251                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       266396251                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    148172005                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      148172005                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data     414568256                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        414568256                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    414568256                       # number of overall hits
-system.cpu.dcache.overall_hits::total       414568256                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      2642162                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       2642162                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       988196                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       988196                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      3630358                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3630358                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      3630358                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3630358                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  33785416000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  33785416000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  18850913500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  18850913500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  52636329500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  52636329500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  52636329500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  52636329500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    269038413                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    269038413                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.replacements                2526932                       # number of replacements
+system.cpu.dcache.tagsinuse               4087.002869                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                415155555                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                2531028                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 164.026457                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle             2119650000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4087.002869                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.997803                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.997803                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data    266306304                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       266306304                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    148172784                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      148172784                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     414479088                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        414479088                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    414479088                       # number of overall hits
+system.cpu.dcache.overall_hits::total       414479088                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      2652001                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       2652001                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       987417                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       987417                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      3639418                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3639418                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      3639418                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3639418                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  36687997500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  36687997500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  18991122500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  18991122500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  55679120000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  55679120000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  55679120000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  55679120000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    268958305                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    268958305                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    149160201                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    149160201                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    418198614                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    418198614                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    418198614                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    418198614                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.009821                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.009821                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.006625                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.006625                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.008681                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.008681                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.008681                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.008681                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12787.034255                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 12787.034255                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 19076.087638                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 19076.087638                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 14498.936331                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 14498.936331                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 14498.936331                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 14498.936331                       # average overall miss latency
+system.cpu.dcache.demand_accesses::cpu.data    418118506                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    418118506                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    418118506                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    418118506                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.009860                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.009860                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.006620                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.006620                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.008704                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.008704                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.008704                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.008704                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13834.081322                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 13834.081322                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 19233.133013                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 19233.133013                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 15298.907682                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 15298.907682                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 15298.907682                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 15298.907682                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -454,144 +454,144 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      2302786                       # number of writebacks
-system.cpu.dcache.writebacks::total           2302786                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       881124                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       881124                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data         8927                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total         8927                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       890051                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       890051                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       890051                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       890051                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1761038                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1761038                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       979269                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       979269                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      2740307                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      2740307                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      2740307                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      2740307                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  11264952000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  11264952000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  15850782000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  15850782000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  27115734000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  27115734000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  27115734000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  27115734000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006546                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006546                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006565                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006565                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006553                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.006553                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006553                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.006553                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  6396.768270                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  6396.768270                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16186.341036                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16186.341036                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  9895.144595                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total  9895.144595                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  9895.144595                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total  9895.144595                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks      2302590                       # number of writebacks
+system.cpu.dcache.writebacks::total           2302590                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       891786                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       891786                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data         3028                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total         3028                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       894814                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       894814                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       894814                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       894814                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1760215                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1760215                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       984389                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       984389                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      2744604                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      2744604                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      2744604                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      2744604                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  12497957644                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  12497957644                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  15832587002                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  15832587002                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  28330544646                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  28330544646                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  28330544646                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  28330544646                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006545                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006545                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006600                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006600                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006564                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.006564                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006564                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.006564                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  7100.244938                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  7100.244938                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16083.669161                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16083.669161                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10322.270406                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 10322.270406                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10322.270406                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 10322.270406                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.replacements                408621                       # number of replacements
-system.cpu.l2cache.tagsinuse             29300.466705                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 3609267                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                440961                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  8.185003                       # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle          219912062000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 21087.117194                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst    148.252410                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data   8065.097101                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.643528                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst     0.004524                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.246127                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.894179                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst         3623                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data      1537767                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1541390                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      2302794                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      2302794                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data         1289                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total         1289                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       561962                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       561962                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         3623                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      2099729                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2103352                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         3623                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      2099729                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2103352                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         3448                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data       222182                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total       225630                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data       207844                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total       207844                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       209183                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       209183                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         3448                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       431365                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        434813                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         3448                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       431365                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       434813                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    118183500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data   7588288000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total   7706471500                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     10472000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total     10472000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   7166759500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   7166759500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    118183500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  14755047500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  14873231000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    118183500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  14755047500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  14873231000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst         7071                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      1759949                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      1767020                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      2302794                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      2302794                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data       209133                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total       209133                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       771145                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       771145                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         7071                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      2531094                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2538165                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         7071                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      2531094                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2538165                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.487626                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.126243                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.127690                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.993836                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.993836                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.271263                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.271263                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.487626                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.170426                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.171310                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.487626                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.170426                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.171310                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34275.957077                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34153.477779                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 34155.349466                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data    50.383942                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total    50.383942                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34260.716693                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34260.716693                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34275.957077                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34205.481437                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 34206.040298                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34275.957077                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34205.481437                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 34206.040298                       # average overall miss latency
+system.cpu.l2cache.replacements                408624                       # number of replacements
+system.cpu.l2cache.tagsinuse             29310.882366                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 3608909                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                440968                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  8.184061                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle          220647003000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::writebacks 21083.148834                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst    149.403214                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data   8078.330317                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.643407                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.004559                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.246531                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.894497                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst         3622                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data      1537243                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        1540865                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      2302598                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      2302598                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data         1280                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total         1280                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       562350                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       562350                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst         3622                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      2099593                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2103215                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         3622                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      2099593                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2103215                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         3475                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data       222140                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total       225615                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data       212287                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total       212287                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       209207                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       209207                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         3475                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       431347                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        434822                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         3475                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       431347                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       434822                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    121950500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data   7624838921                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   7746789421                       # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     10608500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total     10608500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   7167281000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   7167281000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    121950500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  14792119921                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  14914070421                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    121950500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  14792119921                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  14914070421                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst         7097                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      1759383                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      1766480                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      2302598                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      2302598                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data       213567                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total       213567                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       771557                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       771557                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         7097                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      2530940                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2538037                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         7097                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      2530940                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2538037                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.489644                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.126260                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.127720                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.994007                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.994007                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.271149                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.271149                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.489644                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.170430                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.171322                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.489644                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.170430                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.171322                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35093.669065                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34324.475200                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 34336.322589                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data    49.972443                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total    49.972443                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34259.279087                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34259.279087                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35093.669065                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34292.854525                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 34299.254456                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35093.669065                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34292.854525                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 34299.254456                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -600,60 +600,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       324864                       # number of writebacks
-system.cpu.l2cache.writebacks::total           324864                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3448                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       222182                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total       225630                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data       207844                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total       207844                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       209183                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       209183                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3448                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       431365                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       434813                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3448                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       431365                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       434813                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    107086500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   6894107000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   7001193500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   6443438500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   6443438500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6484873000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6484873000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    107086500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  13378980000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  13486066500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    107086500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  13378980000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  13486066500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.487626                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.126243                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.127690                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.993836                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.993836                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.271263                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.271263                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.487626                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.170426                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.171310                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.487626                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.170426                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.171310                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31057.569606                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31029.097767                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31029.532864                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31001.320702                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31001.320702                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.956101                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31000.956101                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31057.569606                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31015.450952                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31015.784947                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31057.569606                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31015.450952                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31015.784947                       # average overall mshr miss latency
+system.cpu.l2cache.writebacks::writebacks       324861                       # number of writebacks
+system.cpu.l2cache.writebacks::total           324861                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3475                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       222140                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total       225615                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data       212287                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total       212287                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       209207                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       209207                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3475                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       431347                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       434822                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3475                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       431347                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       434822                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    110937500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   6934880499                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   7045817999                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   6582250000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   6582250000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6487010500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6487010500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    110937500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  13421890999                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  13532828499                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    110937500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  13421890999                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  13532828499                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.489644                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.126260                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.127720                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.994007                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.994007                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.271149                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.271149                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.489644                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.170430                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.171322                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.489644                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.170430                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.171322                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31924.460432                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31218.513095                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31229.386340                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31006.373447                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31006.373447                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31007.616858                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31007.616858                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31924.460432                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31116.226609                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31122.685832                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31924.460432                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31116.226609                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31122.685832                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini
index 2db6fca67..2d97cc0b1 100644
--- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini
@@ -169,7 +169,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
@@ -201,7 +201,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
 slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
 
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout
index 0422a99cd..1335d3658 100755
--- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:08:09
-gem5 started Jun 28 2012 23:33:45
+gem5 compiled Jul  2 2012 08:58:39
+gem5 started Jul  2 2012 13:47:25
 gem5 executing on zizzer
 command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/20.parser/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/20.parser/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
@@ -69,4 +69,4 @@ info: Increasing stack size by one page.
   about 2 million people attended 
   the five best costumes got prizes 
 No errors!
-Exiting @ tick 1652422044000 because target called exit()
+Exiting @ tick 1652606875000 because target called exit()
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
index 246184477..ae8bc7b58 100644
--- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.652422                       # Number of seconds simulated
-sim_ticks                                1652422044000                       # Number of ticks simulated
-final_tick                               1652422044000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.652607                       # Number of seconds simulated
+sim_ticks                                1652606875000                       # Number of ticks simulated
+final_tick                               1652606875000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1001096                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1851139                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2000579398                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 231692                       # Number of bytes of host memory used
-host_seconds                                   825.97                       # Real time elapsed on the host
+host_inst_rate                                 673883                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1246085                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1346830511                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 232676                       # Number of bytes of host memory used
+host_seconds                                  1227.03                       # Real time elapsed on the host
 sim_insts                                   826877145                       # Number of instructions simulated
 sim_ops                                    1528988757                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst            123584                       # Number of bytes read from this memory
@@ -23,19 +23,19 @@ system.physmem.num_reads::cpu.data             427498                       # Nu
 system.physmem.num_reads::total                429429                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks          323570                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total               323570                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                74790                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             16557436                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                16632225                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           74790                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              74790                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          12532198                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               12532198                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          12532198                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               74790                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            16557436                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               29164423                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst                74781                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             16555584                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                16630365                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           74781                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              74781                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          12530796                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               12530796                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          12530796                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               74781                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            16555584                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               29161162                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                  551                       # Number of system calls
-system.cpu.numCycles                       3304844088                       # number of cpu cycles simulated
+system.cpu.numCycles                       3305213750                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   826877145                       # Number of instructions committed
@@ -54,18 +54,18 @@ system.cpu.num_mem_refs                     533262345                       # nu
 system.cpu.num_load_insts                   384102160                       # Number of load instructions
 system.cpu.num_store_insts                  149160185                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                 3304844088                       # Number of busy cycles
+system.cpu.num_busy_cycles                 3305213750                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                   1253                       # number of replacements
-system.cpu.icache.tagsinuse                881.582723                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                881.608185                       # Cycle average of tags in use
 system.cpu.icache.total_refs               1068344296                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                   2814                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               379653.267946                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     881.582723                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.430460                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.430460                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst     881.608185                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.430473                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.430473                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst   1068344296                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total      1068344296                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst    1068344296                       # number of demand (read+write) hits
@@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst         2814                       # n
 system.cpu.icache.demand_misses::total           2814                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst         2814                       # number of overall misses
 system.cpu.icache.overall_misses::total          2814                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    120498000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    120498000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    120498000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    120498000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    120498000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    120498000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    120792000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    120792000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    120792000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    120792000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    120792000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    120792000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst   1068347110                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total   1068347110                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst   1068347110                       # number of demand (read+write) accesses
@@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000003
 system.cpu.icache.demand_miss_rate::total     0.000003                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000003                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000003                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42820.895522                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 42820.895522                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 42820.895522                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 42820.895522                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 42820.895522                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 42820.895522                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42925.373134                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 42925.373134                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 42925.373134                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 42925.373134                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 42925.373134                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 42925.373134                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -116,34 +116,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst         2814
 system.cpu.icache.demand_mshr_misses::total         2814                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst         2814                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total         2814                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    112056000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    112056000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    112056000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    112056000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    112056000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    112056000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    112350000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    112350000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    112350000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    112350000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    112350000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    112350000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000003                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000003                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000003                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000003                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000003                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000003                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39820.895522                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39820.895522                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39820.895522                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 39820.895522                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39820.895522                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 39820.895522                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39925.373134                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39925.373134                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39925.373134                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 39925.373134                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39925.373134                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 39925.373134                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                2514362                       # number of replacements
-system.cpu.dcache.tagsinuse               4086.435686                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               4086.431953                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                530743932                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                2518458                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                 210.741625                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle             8216675000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4086.435686                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.997665                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.997665                       # Average percentage of cache occupancy
+system.cpu.dcache.warmup_cycle             8218697000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4086.431953                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.997664                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.997664                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data    382374775                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total       382374775                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data    148369157                       # number of WriteReq hits
@@ -160,14 +160,14 @@ system.cpu.dcache.demand_misses::cpu.data      2518458                       # n
 system.cpu.dcache.demand_misses::total        2518458                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data      2518458                       # number of overall misses
 system.cpu.dcache.overall_misses::total       2518458                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  33321318000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  33321318000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  19892023500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  19892023500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  53213341500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  53213341500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  53213341500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  53213341500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  33364275000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  33364275000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  19892603500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  19892603500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  53256878500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  53256878500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  53256878500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  53256878500                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data    384102189                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total    384102189                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    149160201                       # number of WriteReq accesses(hits+misses)
@@ -184,14 +184,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.004723
 system.cpu.dcache.demand_miss_rate::total     0.004723                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.004723                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.004723                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19289.711673                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 19289.711673                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25146.544946                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 25146.544946                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 21129.334498                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 21129.334498                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 21129.334498                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 21129.334498                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19314.579481                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 19314.579481                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25147.278154                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 25147.278154                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 21146.621663                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 21146.621663                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 21146.621663                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 21146.621663                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -210,14 +210,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data      2518458
 system.cpu.dcache.demand_mshr_misses::total      2518458                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data      2518458                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total      2518458                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  28139074000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  28139074000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  17518883000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  17518883000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  45657957000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  45657957000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  45657957000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  45657957000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  28182031000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  28182031000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  17519463000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  17519463000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  45701494000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  45701494000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  45701494000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  45701494000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.004497                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.004497                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005303                       # mshr miss rate for WriteReq accesses
@@ -226,28 +226,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.004723
 system.cpu.dcache.demand_mshr_miss_rate::total     0.004723                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.004723                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.004723                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16289.710515                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16289.710515                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22146.534200                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22146.534200                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18129.330328                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 18129.330328                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18129.330328                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 18129.330328                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16314.578323                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16314.578323                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22147.267409                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22147.267409                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18146.617494                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 18146.617494                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18146.617494                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 18146.617494                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                403150                       # number of replacements
-system.cpu.l2cache.tagsinuse             29113.171325                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse             29113.385052                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                 3572765                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                435501                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  8.203804                       # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle          772998682000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 21035.686564                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst     79.698096                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data   7997.786666                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.641958                       # Average percentage of cache occupancy
+system.cpu.l2cache.warmup_cycle          773011530000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::writebacks 21035.861184                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst     79.696348                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data   7997.827520                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.641964                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.inst     0.002432                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.244073                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.888463                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.244074                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.888470                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst          883                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data      1509854                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total        1510737                       # number of ReadReq hits
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini
index fd38a6ce1..d73c26c02 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini
@@ -181,7 +181,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
@@ -213,7 +213,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout
index 8d1e02107..f78d992b7 100755
--- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:05:18
-gem5 started Jun 28 2012 22:10:46
+gem5 compiled Jul  2 2012 08:30:56
+gem5 started Jul  2 2012 09:12:34
 gem5 executing on zizzer
 command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/inorder-timing
 Global frequency set at 1000000000000 ticks per second
@@ -11,4 +11,4 @@ info: Increasing stack size by one page.
 Eon, Version 1.1
 info: Increasing stack size by one page.
 OO-style eon Time= 0.133333
-Exiting @ tick 141174877500 because target called exit()
+Exiting @ tick 141187061500 because target called exit()
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt
index 63af08cbf..c000798eb 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.141175                       # Number of seconds simulated
-sim_ticks                                141174877500                       # Number of ticks simulated
-final_tick                               141174877500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.141187                       # Number of seconds simulated
+sim_ticks                                141187061500                       # Number of ticks simulated
+final_tick                               141187061500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 165783                       # Simulator instruction rate (inst/s)
-host_op_rate                                   165783                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               58706881                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 225068                       # Number of bytes of host memory used
-host_seconds                                  2404.74                       # Real time elapsed on the host
+host_inst_rate                                 158597                       # Simulator instruction rate (inst/s)
+host_op_rate                                   158597                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               56167220                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 225028                       # Number of bytes of host memory used
+host_seconds                                  2513.69                       # Real time elapsed on the host
 sim_insts                                   398664595                       # Number of instructions simulated
 sim_ops                                     398664595                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst            214592                       # Number of bytes read from this memory
@@ -19,34 +19,34 @@ system.physmem.bytes_inst_read::total          214592                       # Nu
 system.physmem.num_reads::cpu.inst               3353                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data               3969                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                  7322                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              1520044                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1799300                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3319344                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         1520044                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1520044                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             1520044                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1799300                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3319344                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst              1519913                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1799145                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 3319058                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1519913                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1519913                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             1519913                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1799145                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3319058                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     94755013                       # DTB read hits
+system.cpu.dtb.read_hits                     94755019                       # DTB read hits
 system.cpu.dtb.read_misses                         21                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                 94755034                       # DTB read accesses
-system.cpu.dtb.write_hits                    73522045                       # DTB write hits
+system.cpu.dtb.read_accesses                 94755040                       # DTB read accesses
+system.cpu.dtb.write_hits                    73522100                       # DTB write hits
 system.cpu.dtb.write_misses                        35                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                73522080                       # DTB write accesses
-system.cpu.dtb.data_hits                    168277058                       # DTB hits
+system.cpu.dtb.write_accesses                73522135                       # DTB write accesses
+system.cpu.dtb.data_hits                    168277119                       # DTB hits
 system.cpu.dtb.data_misses                         56                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                168277114                       # DTB accesses
-system.cpu.itb.fetch_hits                    49111850                       # ITB hits
-system.cpu.itb.fetch_misses                     88782                       # ITB misses
+system.cpu.dtb.data_accesses                168277175                       # DTB accesses
+system.cpu.itb.fetch_hits                    49112134                       # ITB hits
+system.cpu.itb.fetch_misses                     88783                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                49200632                       # ITB accesses
+system.cpu.itb.fetch_accesses                49200917                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -60,42 +60,42 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                  215                       # Number of system calls
-system.cpu.numCycles                        282349756                       # number of cpu cycles simulated
+system.cpu.numCycles                        282374124                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.branch_predictor.lookups          53870351                       # Number of BP lookups
-system.cpu.branch_predictor.condPredicted     30921654                       # Number of conditional branches predicted
-system.cpu.branch_predictor.condIncorrect     16037209                       # Number of conditional branches incorrect
-system.cpu.branch_predictor.BTBLookups       33426940                       # Number of BTB lookups
-system.cpu.branch_predictor.BTBHits          15653987                       # Number of BTB hits
+system.cpu.branch_predictor.lookups          53870034                       # Number of BP lookups
+system.cpu.branch_predictor.condPredicted     30921446                       # Number of conditional branches predicted
+system.cpu.branch_predictor.condIncorrect     16037248                       # Number of conditional branches incorrect
+system.cpu.branch_predictor.BTBLookups       33426490                       # Number of BTB lookups
+system.cpu.branch_predictor.BTBHits          15653868                       # Number of BTB hits
 system.cpu.branch_predictor.usedRAS           8007516                       # Number of times the RAS was used to get a target.
-system.cpu.branch_predictor.RASInCorrect           18                       # Number of incorrect RAS predictions.
-system.cpu.branch_predictor.BTBHitPct       46.830452                       # BTB Hit Percentage
-system.cpu.branch_predictor.predictedTaken     29683846                       # Number of Branches Predicted As Taken (True).
-system.cpu.branch_predictor.predictedNotTaken     24186505                       # Number of Branches Predicted As Not Taken (False).
-system.cpu.regfile_manager.intRegFileReads    280818442                       # Number of Reads from Int. Register File
+system.cpu.branch_predictor.RASInCorrect           19                       # Number of incorrect RAS predictions.
+system.cpu.branch_predictor.BTBHitPct       46.830726                       # BTB Hit Percentage
+system.cpu.branch_predictor.predictedTaken     29683710                       # Number of Branches Predicted As Taken (True).
+system.cpu.branch_predictor.predictedNotTaken     24186324                       # Number of Branches Predicted As Not Taken (False).
+system.cpu.regfile_manager.intRegFileReads    280818505                       # Number of Reads from Int. Register File
 system.cpu.regfile_manager.intRegFileWrites    159335859                       # Number of Writes to Int. Register File
-system.cpu.regfile_manager.intRegFileAccesses    440154301                       # Total Accesses (Read+Write) to the Int. Register File
-system.cpu.regfile_manager.floatRegFileReads    119907697                       # Number of Reads from FP Register File
+system.cpu.regfile_manager.intRegFileAccesses    440154364                       # Total Accesses (Read+Write) to the Int. Register File
+system.cpu.regfile_manager.floatRegFileReads    119907678                       # Number of Reads from FP Register File
 system.cpu.regfile_manager.floatRegFileWrites    100196481                       # Number of Writes to FP Register File
-system.cpu.regfile_manager.floatRegFileAccesses    220104178                       # Total Accesses (Read+Write) to the FP Register File
-system.cpu.regfile_manager.regForwards      100457644                       # Number of Registers Read Through Forwarding Logic
-system.cpu.agen_unit.agens                  168700458                       # Number of Address Generations
-system.cpu.execution_unit.predictedTakenIncorrect     14475221                       # Number of Branches Incorrectly Predicted As Taken.
-system.cpu.execution_unit.predictedNotTakenIncorrect      1561329                       # Number of Branches Incorrectly Predicted As Not Taken).
-system.cpu.execution_unit.mispredicted       16036550                       # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.predicted          28551001                       # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.mispredictPct     35.966429                       # Percentage of Incorrect Branches Predicts
-system.cpu.execution_unit.executions        205750873                       # Number of Instructions Executed.
-system.cpu.mult_div_unit.multiplies           2124330                       # Number of Multipy Operations Executed
+system.cpu.regfile_manager.floatRegFileAccesses    220104159                       # Total Accesses (Read+Write) to the FP Register File
+system.cpu.regfile_manager.regForwards      100457715                       # Number of Registers Read Through Forwarding Logic
+system.cpu.agen_unit.agens                  168700471                       # Number of Address Generations
+system.cpu.execution_unit.predictedTakenIncorrect     14475138                       # Number of Branches Incorrectly Predicted As Taken.
+system.cpu.execution_unit.predictedNotTakenIncorrect      1561451                       # Number of Branches Incorrectly Predicted As Not Taken).
+system.cpu.execution_unit.mispredicted       16036589                       # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.predicted          28550962                       # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.mispredictPct     35.966517                       # Percentage of Incorrect Branches Predicts
+system.cpu.execution_unit.executions        205751085                       # Number of Instructions Executed.
+system.cpu.mult_div_unit.multiplies           2124334                       # Number of Multipy Operations Executed
 system.cpu.mult_div_unit.divides                    0                       # Number of Divide Operations Executed
 system.cpu.contextSwitches                          1                       # Number of context switches
-system.cpu.threadCycles                     281921224                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles                     281932231                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
 system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled                            6799                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        13475470                       # Number of cycles cpu's stages were not processed
-system.cpu.runCycles                        268874286                       # Number of cycles cpu stages are processed.
-system.cpu.activity                         95.227384                       # Percentage of cycles cpu is active
+system.cpu.timesIdled                            9236                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        13499283                       # Number of cycles cpu's stages were not processed
+system.cpu.runCycles                        268874841                       # Number of cycles cpu stages are processed.
+system.cpu.activity                         95.219363                       # Percentage of cycles cpu is active
 system.cpu.comLoads                          94754489                       # Number of Load instructions committed
 system.cpu.comStores                         73520729                       # Number of Store instructions committed
 system.cpu.comBranches                       44587532                       # Number of Branches instructions committed
@@ -107,72 +107,72 @@ system.cpu.committedInsts                   398664595                       # Nu
 system.cpu.committedOps                     398664595                       # Number of Ops committed (Per-Thread)
 system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
 system.cpu.committedInsts_total             398664595                       # Number of Instructions committed (Total)
-system.cpu.cpi                               0.708239                       # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi                               0.708300                       # CPI: Cycles Per Instruction (Per-Thread)
 system.cpu.smt_cpi                                nan                       # CPI: Total SMT-CPI
-system.cpu.cpi_total                         0.708239                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.411953                       # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.cpi_total                         0.708300                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.411831                       # IPC: Instructions Per Cycle (Per-Thread)
 system.cpu.smt_ipc                                nan                       # IPC: Total SMT-IPC
-system.cpu.ipc_total                         1.411953                       # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles                 78535818                       # Number of cycles 0 instructions are processed.
-system.cpu.stage0.runCycles                 203813938                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization               72.184917                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles                108863135                       # Number of cycles 0 instructions are processed.
-system.cpu.stage1.runCycles                 173486621                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization               61.443871                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles                104640369                       # Number of cycles 0 instructions are processed.
-system.cpu.stage2.runCycles                 177709387                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization               62.939451                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles                183568295                       # Number of cycles 0 instructions are processed.
-system.cpu.stage3.runCycles                  98781461                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization               34.985495                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles                 92657161                       # Number of cycles 0 instructions are processed.
-system.cpu.stage4.runCycles                 189692595                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization               67.183552                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.icache.replacements                   1974                       # number of replacements
-system.cpu.icache.tagsinuse               1829.918683                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 49107469                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                   3901                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs               12588.430915                       # Average number of references to valid blocks.
+system.cpu.ipc_total                         1.411831                       # IPC: Total IPC of All Threads
+system.cpu.stage0.idleCycles                 78560366                       # Number of cycles 0 instructions are processed.
+system.cpu.stage0.runCycles                 203813758                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.utilization               72.178624                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles                108887705                       # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles                 173486419                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization               61.438497                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles                104664774                       # Number of cycles 0 instructions are processed.
+system.cpu.stage2.runCycles                 177709350                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage2.utilization               62.934007                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles                183592728                       # Number of cycles 0 instructions are processed.
+system.cpu.stage3.runCycles                  98781396                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage3.utilization               34.982453                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles                 92681683                       # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles                 189692441                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization               67.177700                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.icache.replacements                   1973                       # number of replacements
+system.cpu.icache.tagsinuse               1829.856986                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 49107743                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                   3900                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               12591.728974                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst    1829.918683                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.893515                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.893515                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst     49107469                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        49107469                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      49107469                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         49107469                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     49107469                       # number of overall hits
-system.cpu.icache.overall_hits::total        49107469                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         4380                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          4380                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         4380                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           4380                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         4380                       # number of overall misses
-system.cpu.icache.overall_misses::total          4380                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    214309000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    214309000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    214309000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    214309000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    214309000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    214309000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     49111849                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     49111849                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     49111849                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     49111849                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     49111849                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     49111849                       # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::cpu.inst    1829.856986                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.893485                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.893485                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst     49107743                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        49107743                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      49107743                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         49107743                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     49107743                       # number of overall hits
+system.cpu.icache.overall_hits::total        49107743                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         4390                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          4390                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         4390                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           4390                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         4390                       # number of overall misses
+system.cpu.icache.overall_misses::total          4390                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    220305000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    220305000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    220305000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    220305000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    220305000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    220305000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     49112133                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     49112133                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     49112133                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     49112133                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     49112133                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     49112133                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000089                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000089                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000089                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000089                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000089                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000089                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48928.995434                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 48928.995434                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 48928.995434                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 48928.995434                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 48928.995434                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 48928.995434                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50183.371298                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 50183.371298                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 50183.371298                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 50183.371298                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 50183.371298                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 50183.371298                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets        45000                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -181,70 +181,70 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets        45000                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          479                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          479                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          479                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          479                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          479                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          479                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         3901                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         3901                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         3901                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         3901                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         3901                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         3901                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    185222000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    185222000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    185222000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    185222000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    185222000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    185222000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          490                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          490                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          490                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          490                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          490                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          490                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         3900                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         3900                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         3900                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         3900                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         3900                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         3900                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    190927000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    190927000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    190927000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    190927000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    190927000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    190927000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000079                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000079                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000079                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000079                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000079                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000079                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47480.645988                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47480.645988                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47480.645988                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 47480.645988                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47480.645988                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 47480.645988                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48955.641026                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48955.641026                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48955.641026                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 48955.641026                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48955.641026                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 48955.641026                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                    764                       # number of replacements
-system.cpu.dcache.tagsinuse               3284.843876                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                168261959                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse               3284.708505                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                168261813                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                   4152                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs               40525.519990                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs               40525.484827                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    3284.843876                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.801964                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.801964                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data     94753265                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        94753265                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     73508694                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       73508694                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data     168261959                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        168261959                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    168261959                       # number of overall hits
-system.cpu.dcache.overall_hits::total       168261959                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data         1224                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total          1224                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data        12035                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total        12035                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data        13259                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total          13259                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data        13259                       # number of overall misses
-system.cpu.dcache.overall_misses::total         13259                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     63567000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     63567000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    626556000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    626556000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    690123000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    690123000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    690123000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    690123000                       # number of overall miss cycles
+system.cpu.dcache.occ_blocks::cpu.data    3284.708505                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.801931                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.801931                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     94753261                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        94753261                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     73508552                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       73508552                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     168261813                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        168261813                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    168261813                       # number of overall hits
+system.cpu.dcache.overall_hits::total       168261813                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data         1228                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total          1228                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data        12177                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        12177                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data        13405                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total          13405                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data        13405                       # number of overall misses
+system.cpu.dcache.overall_misses::total         13405                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     68612500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     68612500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    712613500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    712613500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    781226000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    781226000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    781226000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    781226000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data     94754489                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total     94754489                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     73520729                       # number of WriteReq accesses(hits+misses)
@@ -255,38 +255,38 @@ system.cpu.dcache.overall_accesses::cpu.data    168275218
 system.cpu.dcache.overall_accesses::total    168275218                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000013                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.000013                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000164                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.000164                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.000079                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.000079                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.000079                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.000079                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51933.823529                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 51933.823529                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52061.154965                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 52061.154965                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 52049.400407                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 52049.400407                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 52049.400407                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 52049.400407                       # average overall miss latency
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000166                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.000166                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.000080                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.000080                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.000080                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.000080                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55873.371336                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 55873.371336                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 58521.269607                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 58521.269607                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 58278.701977                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 58278.701977                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 58278.701977                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 58278.701977                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets     82410500                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets     86009500                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets            1848                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets            1905                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 44594.426407                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 45149.343832                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks          649                       # number of writebacks
 system.cpu.dcache.writebacks::total               649                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          274                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          274                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data         8833                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total         8833                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data         9107                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total         9107                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data         9107                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total         9107                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          278                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          278                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data         8975                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total         8975                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data         9253                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total         9253                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data         9253                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total         9253                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data          950                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total          950                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data         3202                       # number of WriteReq MSHR misses
@@ -295,14 +295,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data         4152
 system.cpu.dcache.demand_mshr_misses::total         4152                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data         4152                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total         4152                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     45925000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     45925000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    169537000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    169537000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    215462000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    215462000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    215462000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    215462000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     48743500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     48743500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    176149500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    176149500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    224893000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    224893000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    224893000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    224893000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000010                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000010                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000044                       # mshr miss rate for WriteReq accesses
@@ -311,41 +311,41 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000025
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000025                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000025                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000025                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48342.105263                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48342.105263                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52947.220487                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52947.220487                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51893.545279                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 51893.545279                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51893.545279                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 51893.545279                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51308.947368                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51308.947368                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 55012.336040                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 55012.336040                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54164.980732                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 54164.980732                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54164.980732                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 54164.980732                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse              3900.421280                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                     754                       # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse              3900.249221                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                     753                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                  4711                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  0.160051                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.159839                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks   370.518684                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst   2902.345910                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data    627.556686                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::writebacks   370.495467                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst   2902.223601                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    627.530153                       # Average occupied blocks per requestor
 system.cpu.l2cache.occ_percent::writebacks     0.011307                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst     0.088573                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.019152                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.119031                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst          548                       # number of ReadReq hits
+system.cpu.l2cache.occ_percent::cpu.inst     0.088569                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.019151                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.119026                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst          547                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data          123                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total            671                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total            670                       # number of ReadReq hits
 system.cpu.l2cache.Writeback_hits::writebacks          649                       # number of Writeback hits
 system.cpu.l2cache.Writeback_hits::total          649                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data           60                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total           60                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst          548                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst          547                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.data          183                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total             731                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst          548                       # number of overall hits
+system.cpu.l2cache.demand_hits::total             730                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst          547                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.data          183                       # number of overall hits
-system.cpu.l2cache.overall_hits::total            731                       # number of overall hits
+system.cpu.l2cache.overall_hits::total            730                       # number of overall hits
 system.cpu.l2cache.ReadReq_misses::cpu.inst         3353                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.data          824                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::total         4177                       # number of ReadReq misses
@@ -357,52 +357,52 @@ system.cpu.l2cache.demand_misses::total          7322                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst         3353                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data         3969                       # number of overall misses
 system.cpu.l2cache.overall_misses::total         7322                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    175438000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     43307500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    218745500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    164970500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    164970500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    175438000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    208278000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    383716000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    175438000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    208278000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    383716000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst         3901                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    180755000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     45853500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    226608500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    171775500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    171775500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    180755000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    217629000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    398384000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    180755000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    217629000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    398384000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst         3900                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data          947                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total         4848                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total         4847                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::writebacks          649                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::total          649                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data         3205                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total         3205                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         3901                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst         3900                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data         4152                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total         8053                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         3901                       # number of overall (read+write) accesses
+system.cpu.l2cache.demand_accesses::total         8052                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         3900                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data         4152                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total         8053                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.859523                       # miss rate for ReadReq accesses
+system.cpu.l2cache.overall_accesses::total         8052                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.859744                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.870116                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.861592                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.861770                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.981279                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.981279                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.859523                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.859744                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.955925                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.909226                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.859523                       # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::total     0.909339                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.859744                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.955925                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.909226                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52322.696093                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52557.645631                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 52369.044769                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52454.848967                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52454.848967                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52322.696093                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52476.190476                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52405.900027                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52322.696093                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52476.190476                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52405.900027                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total     0.909339                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53908.440203                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55647.451456                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 54251.496289                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54618.600954                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54618.600954                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53908.440203                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54832.199546                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 54409.177820                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53908.440203                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54832.199546                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 54409.177820                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -422,39 +422,39 @@ system.cpu.l2cache.demand_mshr_misses::total         7322
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         3353                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data         3969                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total         7322                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    134591000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     33277500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    167868500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    126757500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    126757500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    134591000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    160035000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    294626000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    134591000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    160035000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    294626000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.859523                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    139951500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     35886500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    175838000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    133424000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    133424000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    139951500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    169310500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    309262000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    139951500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    169310500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    309262000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.859744                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.870116                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.861592                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.861770                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.981279                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.981279                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.859523                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.859744                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.955925                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.909226                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.859523                       # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.909339                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.859744                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.955925                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.909226                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40140.471220                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40385.315534                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40188.771846                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40304.451510                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40304.451510                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40140.471220                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40321.239607                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40238.459437                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40140.471220                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40321.239607                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40238.459437                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.909339                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41739.188786                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43551.577670                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42096.720134                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42424.165342                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42424.165342                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41739.188786                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42658.226253                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42237.366840                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41739.188786                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42658.226253                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42237.366840                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini
index 11313b921..50694257d 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini
@@ -479,7 +479,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
@@ -511,7 +511,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout
index 0f3bb3f65..cf6e41473 100755
--- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:05:18
-gem5 started Jun 28 2012 22:10:52
+gem5 compiled Jul  2 2012 08:30:56
+gem5 started Jul  2 2012 09:15:17
 gem5 executing on zizzer
 command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
@@ -11,4 +11,4 @@ info: Increasing stack size by one page.
 Eon, Version 1.1
 info: Increasing stack size by one page.
 OO-style eon Time= 0.066667
-Exiting @ tick 80278875500 because target called exit()
+Exiting @ tick 80362284000 because target called exit()
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
index c7cbab894..cd4c1620b 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,52 +1,52 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.080279                       # Number of seconds simulated
-sim_ticks                                 80278875500                       # Number of ticks simulated
-final_tick                                80278875500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.080362                       # Number of seconds simulated
+sim_ticks                                 80362284000                       # Number of ticks simulated
+final_tick                                80362284000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 279986                       # Simulator instruction rate (inst/s)
-host_op_rate                                   279986                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               59846889                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 226092                       # Number of bytes of host memory used
-host_seconds                                  1341.40                       # Real time elapsed on the host
+host_inst_rate                                 277812                       # Simulator instruction rate (inst/s)
+host_op_rate                                   277812                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               59443930                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 226052                       # Number of bytes of host memory used
+host_seconds                                  1351.90                       # Real time elapsed on the host
 sim_insts                                   375574808                       # Number of instructions simulated
 sim_ops                                     375574808                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst            222592                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst            222528                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            255296                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               477888                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       222592                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          222592                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               3478                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total               477824                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       222528                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          222528                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               3477                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data               3989                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  7467                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              2772734                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3180114                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 5952849                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         2772734                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            2772734                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             2772734                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             3180114                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                5952849                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_reads::total                  7466                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              2769060                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3176814                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 5945874                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         2769060                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            2769060                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             2769060                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             3176814                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                5945874                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    103395556                       # DTB read hits
-system.cpu.dtb.read_misses                      88623                       # DTB read misses
+system.cpu.dtb.read_hits                    103417276                       # DTB read hits
+system.cpu.dtb.read_misses                      89602                       # DTB read misses
 system.cpu.dtb.read_acv                         48603                       # DTB read access violations
-system.cpu.dtb.read_accesses                103484179                       # DTB read accesses
-system.cpu.dtb.write_hits                    78997481                       # DTB write hits
-system.cpu.dtb.write_misses                      1612                       # DTB write misses
-system.cpu.dtb.write_acv                            4                       # DTB write access violations
-system.cpu.dtb.write_accesses                78999093                       # DTB write accesses
-system.cpu.dtb.data_hits                    182393037                       # DTB hits
-system.cpu.dtb.data_misses                      90235                       # DTB misses
-system.cpu.dtb.data_acv                         48607                       # DTB access violations
-system.cpu.dtb.data_accesses                182483272                       # DTB accesses
-system.cpu.itb.fetch_hits                    52516361                       # ITB hits
-system.cpu.itb.fetch_misses                       462                       # ITB misses
+system.cpu.dtb.read_accesses                103506878                       # DTB read accesses
+system.cpu.dtb.write_hits                    79004376                       # DTB write hits
+system.cpu.dtb.write_misses                      1630                       # DTB write misses
+system.cpu.dtb.write_acv                            2                       # DTB write access violations
+system.cpu.dtb.write_accesses                79006006                       # DTB write accesses
+system.cpu.dtb.data_hits                    182421652                       # DTB hits
+system.cpu.dtb.data_misses                      91232                       # DTB misses
+system.cpu.dtb.data_acv                         48605                       # DTB access violations
+system.cpu.dtb.data_accesses                182512884                       # DTB accesses
+system.cpu.itb.fetch_hits                    52579177                       # ITB hits
+system.cpu.itb.fetch_misses                       445                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                52516823                       # ITB accesses
+system.cpu.itb.fetch_accesses                52579622                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -60,112 +60,112 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                  215                       # Number of system calls
-system.cpu.numCycles                        160557753                       # number of cpu cycles simulated
+system.cpu.numCycles                        160724570                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                 52050833                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted           30287644                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect            1599078                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups              29208422                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                 24276895                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                 52097236                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           30296765                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect            1606699                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              28205553                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                 24320024                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                  9365187                       # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect                1064                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles           53558689                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      462299559                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    52050833                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           33642082                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      81488062                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 7763373                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles               19255908                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                  182                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          8203                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                  52516361                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                627395                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          160436815                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.881505                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.314292                       # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS                  9390300                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect                1099                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles           53639869                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      462587639                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    52097236                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           33710324                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      81534889                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 7793517                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               19277229                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                  188                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles          9332                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                  52579177                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                630275                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          160609062                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.880209                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.314061                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 78948753     49.21%     49.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  4374209      2.73%     51.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  7277181      4.54%     56.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  5613096      3.50%     59.97% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 12419261      7.74%     67.71% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  8092340      5.04%     72.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  5700245      3.55%     76.31% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1902354      1.19%     77.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 36109376     22.51%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 79074173     49.23%     49.23% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  4377828      2.73%     51.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  7270092      4.53%     56.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  5630004      3.51%     59.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 12402470      7.72%     67.71% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  8106533      5.05%     72.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  5708692      3.55%     76.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1929242      1.20%     77.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 36110028     22.48%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            160436815                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.324188                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.879335                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 59087459                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              14718957                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  76680946                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               3827925                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                6121528                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              9736129                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                  4314                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              456834278                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                 12214                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                6121528                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 62371527                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 4787903                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         394179                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  77332259                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               9429419                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              451139499                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                    10                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                  22898                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               7804449                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands           294872724                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             593300368                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        314087845                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups         279212523                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            160609062                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.324140                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.878139                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 59173788                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              14742505                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  76724469                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               3825000                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                6143300                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              9747252                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                  4329                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              457055568                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                 12267                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                6143300                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 62453650                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 4799000                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         401905                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  77381021                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               9430186                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              451385457                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                    27                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                  23697                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               7813364                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands           295061939                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             593486774                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        314314250                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups         279172524                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             259532329                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 35340395                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts              38267                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            351                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  27285549                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            106973750                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            81779740                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           8912420                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          6388901                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  416336746                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                 335                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 407746724                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           1079648                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        40502587                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     19766308                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            120                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     160436815                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.541479                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.007779                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                 35529610                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts              38241                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            341                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  27266716                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            107002651                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            81768344                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           8923759                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          6384538                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  416452671                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                 325                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 407888910                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           1078553                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        40628099                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     19685259                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            110                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     160609062                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.539638                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.007756                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            32040952     19.97%     19.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            26498917     16.52%     36.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            25974021     16.19%     52.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            24801870     15.46%     68.14% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            21558468     13.44%     81.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            15451278      9.63%     91.20% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             8686999      5.41%     96.62% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             4112581      2.56%     99.18% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             1311729      0.82%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            32138937     20.01%     20.01% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            26538030     16.52%     36.53% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            25997150     16.19%     52.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            24815453     15.45%     68.17% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            21510440     13.39%     81.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            15487887      9.64%     91.21% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             8719479      5.43%     96.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             4101336      2.55%     99.19% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             1300350      0.81%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       160436815                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       160609062                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                   35223      0.30%      0.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   35567      0.30%      0.30% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                      0      0.00%      0.30% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                 74176      0.62%      0.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                  4373      0.04%      0.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                  3034      0.03%      0.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult              1856115     15.64%     16.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv               1782113     15.01%     31.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                 73106      0.62%      0.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                  5073      0.04%      0.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                  3115      0.03%      0.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult              1847413     15.60%     16.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv               1780061     15.04%     31.63% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     31.63% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdAdd                      0      0.00%     31.63% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     31.63% # attempts to use FU when none available
@@ -187,120 +187,120 @@ system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     31.63% # at
 system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     31.63% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     31.63% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     31.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                5098643     42.95%     74.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               3017744     25.42%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                5074453     42.86%     74.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               3020406     25.51%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass             33581      0.01%      0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             158007223     38.75%     38.76% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult              2126531      0.52%     39.28% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     39.28% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd            33463416      8.21%     47.49% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp             7846184      1.92%     49.41% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt             2836368      0.70%     50.11% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult           16562414      4.06%     54.17% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv             1592681      0.39%     54.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     54.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     54.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     54.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     54.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     54.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     54.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     54.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     54.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     54.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     54.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     54.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     54.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     54.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     54.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     54.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     54.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     54.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     54.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     54.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     54.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     54.56% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            105279650     25.82%     80.38% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            79998676     19.62%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             158124852     38.77%     38.77% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult              2126520      0.52%     39.30% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     39.30% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd            33455961      8.20%     47.50% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp             7846153      1.92%     49.42% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt             2842255      0.70%     50.12% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult           16560349      4.06%     54.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv             1591354      0.39%     54.57% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     54.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     54.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     54.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     54.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     54.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     54.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     54.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     54.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     54.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     54.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     54.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     54.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     54.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     54.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     54.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     54.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     54.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     54.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     54.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     54.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     54.57% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            105304781     25.82%     80.39% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            80003104     19.61%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              407746724                       # Type of FU issued
-system.cpu.iq.rate                           2.539564                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    11871421                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.029115                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          647615644                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         269617595                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    237690414                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads           341265688                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes          187272317                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses    162935841                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              245304560                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses               174280004                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         14820631                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              407888910                       # Type of FU issued
+system.cpu.iq.rate                           2.537813                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    11839194                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.029026                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          648060515                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         269929713                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    237794597                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads           341244114                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes          187202465                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses    162943481                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              245434368                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses               174260155                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         14844596                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     12219263                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses       125114                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        50286                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      8259011                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     12248164                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       129765                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        51115                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      8247615                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads       260829                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads       260830                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked             3                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                6121528                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 2498871                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                366274                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           441262786                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            203691                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             106973750                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             81779740                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                335                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                    126                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                    17                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          50286                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        1245920                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       565907                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1811827                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             403241961                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             103532839                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           4504763                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                6143300                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 2503230                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                370145                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           441398780                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            177151                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             107002651                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             81768344                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                325                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                    147                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                    68                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          51115                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        1257944                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       570703                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              1828647                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             403351252                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             103555560                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           4537658                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                      24925705                       # number of nop insts executed
-system.cpu.iew.exec_refs                    182531964                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 47208062                       # Number of branches executed
-system.cpu.iew.exec_stores                   78999125                       # Number of stores executed
-system.cpu.iew.exec_rate                     2.511507                       # Inst execution rate
-system.cpu.iew.wb_sent                      401471936                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     400626255                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 195236823                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 273330928                       # num instructions consuming a value
+system.cpu.iew.exec_nop                      24945784                       # number of nop insts executed
+system.cpu.iew.exec_refs                    182561595                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 47229945                       # Number of branches executed
+system.cpu.iew.exec_stores                   79006035                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.509581                       # Inst execution rate
+system.cpu.iew.wb_sent                      401565360                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     400738078                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 195225884                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 273294717                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       2.495216                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.714287                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       2.493322                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.714342                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts      398664583                       # The number of committed instructions
 system.cpu.commit.commitCommittedOps        398664583                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts        42637745                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts        42764408                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             215                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           1594835                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    154315287                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.583442                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.967476                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           1602444                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    154465762                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.580925                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.966951                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     58825621     38.12%     38.12% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     23339762     15.12%     53.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     13270606      8.60%     61.84% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     11657566      7.55%     69.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      8455456      5.48%     74.88% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      5496217      3.56%     78.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      5141868      3.33%     81.77% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      3368734      2.18%     83.96% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     24759457     16.04%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     58951255     38.16%     38.16% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     23354970     15.12%     53.28% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     13285334      8.60%     61.89% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     11679330      7.56%     69.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      8439151      5.46%     74.91% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      5483127      3.55%     78.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      5136953      3.33%     81.79% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      3378138      2.19%     83.97% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     24757504     16.03%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    154315287                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    154465762                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            398664583                       # Number of instructions committed
 system.cpu.commit.committedOps              398664583                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -311,70 +311,70 @@ system.cpu.commit.branches                   44587533                       # Nu
 system.cpu.commit.fp_insts                  155295106                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                 316365839                       # Number of committed integer instructions.
 system.cpu.commit.function_calls              8007752                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events              24759457                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events              24757504                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    570855181                       # The number of ROB reads
-system.cpu.rob.rob_writes                   888739971                       # The number of ROB writes
-system.cpu.timesIdled                            2694                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          120938                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                    571134272                       # The number of ROB reads
+system.cpu.rob.rob_writes                   889015019                       # The number of ROB writes
+system.cpu.timesIdled                            3240                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          115508                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   375574808                       # Number of Instructions Simulated
 system.cpu.committedOps                     375574808                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total             375574808                       # Number of Instructions Simulated
-system.cpu.cpi                               0.427499                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.427499                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               2.339188                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         2.339188                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                402766119                       # number of integer regfile reads
-system.cpu.int_regfile_writes               172550874                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                 158333530                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                105213831                       # number of floating regfile writes
+system.cpu.cpi                               0.427943                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.427943                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               2.336760                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         2.336760                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                402895481                       # number of integer regfile reads
+system.cpu.int_regfile_writes               172638002                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                 158340215                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                105188641                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                  350572                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.icache.replacements                   2221                       # number of replacements
-system.cpu.icache.tagsinuse               1836.833971                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 52510942                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                   4151                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs               12650.190797                       # Average number of references to valid blocks.
+system.cpu.icache.replacements                   2209                       # number of replacements
+system.cpu.icache.tagsinuse               1834.486163                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 52573796                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                   4140                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               12698.984541                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst    1836.833971                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.896892                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.896892                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst     52510942                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        52510942                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      52510942                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         52510942                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     52510942                       # number of overall hits
-system.cpu.icache.overall_hits::total        52510942                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         5419                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          5419                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         5419                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           5419                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         5419                       # number of overall misses
-system.cpu.icache.overall_misses::total          5419                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    170335500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    170335500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    170335500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    170335500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    170335500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    170335500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     52516361                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     52516361                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     52516361                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     52516361                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     52516361                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     52516361                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000103                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000103                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000103                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000103                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000103                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000103                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31433.013471                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 31433.013471                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 31433.013471                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 31433.013471                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 31433.013471                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 31433.013471                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst    1834.486163                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.895745                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.895745                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst     52573796                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        52573796                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      52573796                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         52573796                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     52573796                       # number of overall hits
+system.cpu.icache.overall_hits::total        52573796                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         5381                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          5381                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         5381                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           5381                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         5381                       # number of overall misses
+system.cpu.icache.overall_misses::total          5381                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    173584500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    173584500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    173584500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    173584500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    173584500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    173584500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     52579177                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     52579177                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     52579177                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     52579177                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     52579177                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     52579177                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000102                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000102                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000102                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000102                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000102                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000102                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 32258.780896                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 32258.780896                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 32258.780896                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 32258.780896                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 32258.780896                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 32258.780896                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -383,284 +383,284 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1268                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         1268                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         1268                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         1268                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         1268                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         1268                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4151                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         4151                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         4151                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         4151                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         4151                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         4151                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    125070500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    125070500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    125070500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    125070500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    125070500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    125070500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1241                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         1241                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         1241                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         1241                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         1241                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         1241                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4140                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         4140                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         4140                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         4140                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         4140                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         4140                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    130333500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    130333500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    130333500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    130333500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    130333500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    130333500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000079                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000079                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000079                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000079                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000079                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000079                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 30130.209588                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 30130.209588                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 30130.209588                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 30130.209588                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 30130.209588                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 30130.209588                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 31481.521739                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 31481.521739                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 31481.521739                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 31481.521739                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 31481.521739                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 31481.521739                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                    783                       # number of replacements
-system.cpu.dcache.tagsinuse               3297.903545                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                161813696                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                   4184                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs               38674.401530                       # Average number of references to valid blocks.
+system.cpu.dcache.replacements                    796                       # number of replacements
+system.cpu.dcache.tagsinuse               3296.720309                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                161811337                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                   4197                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs               38554.047415                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    3297.903545                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.805152                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.805152                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data     88312425                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        88312425                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     73501253                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       73501253                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data           18                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total           18                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data     161813678                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        161813678                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    161813678                       # number of overall hits
-system.cpu.dcache.overall_hits::total       161813678                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data         1653                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total          1653                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data        19476                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total        19476                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data        21129                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total          21129                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data        21129                       # number of overall misses
-system.cpu.dcache.overall_misses::total         21129                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     55208500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     55208500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    570020000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    570020000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    625228500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    625228500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    625228500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    625228500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     88314078                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     88314078                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.occ_blocks::cpu.data    3296.720309                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.804863                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.804863                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     88310042                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        88310042                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     73501280                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       73501280                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data           15                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total           15                       # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits::cpu.data     161811322                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        161811322                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    161811322                       # number of overall hits
+system.cpu.dcache.overall_hits::total       161811322                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data         1790                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total          1790                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data        19449                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        19449                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data        21239                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total          21239                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data        21239                       # number of overall misses
+system.cpu.dcache.overall_misses::total         21239                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     68481500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     68481500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    731423000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    731423000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    799904500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    799904500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    799904500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    799904500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     88311832                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     88311832                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     73520729                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     73520729                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data           18                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total           18                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    161834807                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    161834807                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    161834807                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    161834807                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000019                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.000019                       # miss rate for ReadReq accesses
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data           15                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total           15                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    161832561                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    161832561                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    161832561                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    161832561                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000020                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.000020                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000265                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.000265                       # miss rate for WriteReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.000131                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     0.000131                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.000131                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.000131                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33398.971567                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 33398.971567                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29267.816800                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 29267.816800                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 29591.012353                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 29591.012353                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 29591.012353                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 29591.012353                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38257.821229                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 38257.821229                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37607.229163                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 37607.229163                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 37662.060361                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 37662.060361                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 37662.060361                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 37662.060361                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs         7500                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 1                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs         7500                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks          661                       # number of writebacks
-system.cpu.dcache.writebacks::total               661                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          664                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          664                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        16281                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        16281                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data        16945                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total        16945                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data        16945                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total        16945                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data          989                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          989                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data         3195                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total         3195                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data         4184                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total         4184                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data         4184                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total         4184                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     31319000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     31319000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    113198500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    113198500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    144517500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    144517500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    144517500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    144517500                       # number of overall MSHR miss cycles
+system.cpu.dcache.writebacks::writebacks          676                       # number of writebacks
+system.cpu.dcache.writebacks::total               676                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          798                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          798                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        16244                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        16244                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data        17042                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total        17042                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data        17042                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total        17042                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          992                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          992                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         3205                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         3205                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data         4197                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         4197                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data         4197                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         4197                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     36143000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     36143000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    129182000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    129182000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    165325000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    165325000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    165325000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    165325000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000011                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000011                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000043                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000043                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000044                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000044                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000026                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000026                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000026                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000026                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31667.340748                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31667.340748                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35429.890454                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35429.890454                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34540.511472                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 34540.511472                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34540.511472                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 34540.511472                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36434.475806                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 36434.475806                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40306.396256                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40306.396256                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 39391.231832                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 39391.231832                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 39391.231832                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 39391.231832                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse              4030.550390                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                     892                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                  4871                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  0.183125                       # Average number of references to valid blocks.
+system.cpu.l2cache.tagsinuse              4031.271945                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                     894                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                  4870                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.183573                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks   372.758053                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst   2998.208675                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data    659.583662                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.011376                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst     0.091498                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.020129                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.123003                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst          673                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data          131                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total            804                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks          661                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total          661                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data           64                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total           64                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst          673                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data          195                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total             868                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst          673                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data          195                       # number of overall hits
-system.cpu.l2cache.overall_hits::total            868                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         3478                       # number of ReadReq misses
+system.cpu.l2cache.occ_blocks::writebacks   372.726773                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst   3000.006522                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    658.538650                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.011375                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.091553                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.020097                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.123025                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst          663                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data          134                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total            797                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks          676                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total          676                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data           74                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total           74                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst          663                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data          208                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total             871                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst          663                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data          208                       # number of overall hits
+system.cpu.l2cache.overall_hits::total            871                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         3477                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.data          858                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         4336                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total         4335                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data         3131                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total         3131                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         3478                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst         3477                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.data         3989                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total          7467                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         3478                       # number of overall misses
+system.cpu.l2cache.demand_misses::total          7466                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         3477                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data         3989                       # number of overall misses
-system.cpu.l2cache.overall_misses::total         7467                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    119555000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     29668000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    149223000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    108422000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    108422000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    119555000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    138090000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    257645000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    119555000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    138090000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    257645000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst         4151                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data          989                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total         5140                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks          661                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total          661                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data         3195                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total         3195                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         4151                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data         4184                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total         8335                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         4151                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data         4184                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total         8335                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.837870                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.867543                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.843580                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.979969                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.979969                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.837870                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.953394                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.895861                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.837870                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.953394                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.895861                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34374.640598                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34578.088578                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 34414.898524                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34628.553178                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34628.553178                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34374.640598                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34617.698671                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 34504.486407                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34374.640598                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34617.698671                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 34504.486407                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.overall_misses::total         7466                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    124004000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     34532500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    158536500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    124919000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    124919000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    124004000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    159451500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    283455500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    124004000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    159451500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    283455500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst         4140                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data          992                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total         5132                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks          676                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total          676                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data         3205                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total         3205                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         4140                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data         4197                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total         8337                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         4140                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data         4197                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total         8337                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.839855                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.864919                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.844700                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.976911                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.976911                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.839855                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.950441                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.895526                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.839855                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.950441                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.895526                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35664.078228                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 40247.668998                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 36571.280277                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39897.476844                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39897.476844                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35664.078228                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 39972.800201                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 37966.180016                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35664.078228                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 39972.800201                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 37966.180016                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs         3000                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                1                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs         3000                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3478                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3477                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          858                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         4336                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         4335                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         3131                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total         3131                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3478                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3477                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data         3989                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         7467                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3478                       # number of overall MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         7466                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3477                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data         3989                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total         7467                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    108320000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     26958500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    135278500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     98537000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     98537000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    108320000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    125495500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    233815500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    108320000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    125495500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    233815500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.837870                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.867543                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.843580                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.979969                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.979969                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.837870                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.953394                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.895861                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.837870                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.953394                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.895861                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31144.335825                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31420.163170                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31198.916052                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31471.414883                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31471.414883                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31144.335825                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31460.391075                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31313.177983                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31144.335825                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31460.391075                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31313.177983                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_misses::total         7466                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    112721000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     31878000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    144599000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    115138500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    115138500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    112721000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    147016500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    259737500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    112721000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    147016500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    259737500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.839855                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.864919                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.844700                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.976911                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.976911                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.839855                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.950441                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.895526                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.839855                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.950441                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.895526                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32419.039402                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37153.846154                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33356.170704                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36773.714468                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36773.714468                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32419.039402                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36855.477563                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34789.378516                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32419.039402                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36855.477563                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34789.378516                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini
index b7b2de2d4..d4c58b08d 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini
@@ -148,7 +148,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
@@ -180,7 +180,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout
index 535f9cae3..d468809f0 100755
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:05:18
-gem5 started Jun 28 2012 22:12:10
+gem5 compiled Jul  2 2012 08:30:56
+gem5 started Jul  2 2012 09:39:35
 gem5 executing on zizzer
 command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
@@ -11,4 +11,4 @@ info: Increasing stack size by one page.
 Eon, Version 1.1
 info: Increasing stack size by one page.
 OO-style eon Time= 0.566667
-Exiting @ tick 567342918000 because target called exit()
+Exiting @ tick 567365869000 because target called exit()
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
index 049129481..df4992494 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.567343                       # Number of seconds simulated
-sim_ticks                                567342918000                       # Number of ticks simulated
-final_tick                               567342918000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.567366                       # Number of seconds simulated
+sim_ticks                                567365869000                       # Number of ticks simulated
+final_tick                               567365869000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2055836                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2055836                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2925676505                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 224040                       # Number of bytes of host memory used
-host_seconds                                   193.92                       # Real time elapsed on the host
+host_inst_rate                                2066411                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2066411                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2940844836                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 224004                       # Number of bytes of host memory used
+host_seconds                                   192.93                       # Real time elapsed on the host
 sim_insts                                   398664609                       # Number of instructions simulated
 sim_ops                                     398664609                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst            205120                       # Number of bytes read from this memory
@@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total          205120                       # Nu
 system.physmem.num_reads::cpu.inst               3205                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data               3969                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                  7174                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst               361545                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data               447729                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                  809274                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          361545                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             361545                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              361545                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data              447729                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                 809274                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               361530                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data               447711                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                  809241                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          361530                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             361530                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              361530                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data              447711                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                 809241                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -60,7 +60,7 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                  215                       # Number of system calls
-system.cpu.numCycles                       1134685836                       # number of cpu cycles simulated
+system.cpu.numCycles                       1134731738                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   398664609                       # Number of instructions committed
@@ -79,18 +79,18 @@ system.cpu.num_mem_refs                     168275276                       # nu
 system.cpu.num_load_insts                    94754511                       # Number of load instructions
 system.cpu.num_store_insts                   73520765                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                 1134685836                       # Number of busy cycles
+system.cpu.num_busy_cycles                 1134731738                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                   1769                       # number of replacements
-system.cpu.icache.tagsinuse               1795.131072                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse               1795.107538                       # Cycle average of tags in use
 system.cpu.icache.total_refs                398660993                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                   3673                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               108538.250204                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst    1795.131072                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.876529                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.876529                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst    1795.107538                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.876517                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.876517                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst    398660993                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total       398660993                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst     398660993                       # number of demand (read+write) hits
@@ -103,12 +103,12 @@ system.cpu.icache.demand_misses::cpu.inst         3673                       # n
 system.cpu.icache.demand_misses::total           3673                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst         3673                       # number of overall misses
 system.cpu.icache.overall_misses::total          3673                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    186032000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    186032000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    186032000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    186032000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    186032000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    186032000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    186108000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    186108000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    186108000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    186108000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    186108000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    186108000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst    398664666                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total    398664666                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst    398664666                       # number of demand (read+write) accesses
@@ -121,12 +121,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000009
 system.cpu.icache.demand_miss_rate::total     0.000009                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000009                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000009                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50648.516199                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 50648.516199                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 50648.516199                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 50648.516199                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 50648.516199                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 50648.516199                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50669.207732                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 50669.207732                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 50669.207732                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 50669.207732                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 50669.207732                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 50669.207732                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -141,34 +141,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst         3673
 system.cpu.icache.demand_mshr_misses::total         3673                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst         3673                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total         3673                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    175013000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    175013000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    175013000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    175013000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    175013000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    175013000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    175089000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    175089000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    175089000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    175089000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    175089000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    175089000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000009                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000009                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000009                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000009                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000009                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000009                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47648.516199                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47648.516199                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47648.516199                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 47648.516199                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47648.516199                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 47648.516199                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47669.207732                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47669.207732                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47669.207732                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 47669.207732                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47669.207732                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 47669.207732                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                    764                       # number of replacements
-system.cpu.dcache.tagsinuse               3288.912595                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               3288.859436                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                168271068                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                   4152                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs               40527.713873                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    3288.912595                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.802957                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.802957                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::cpu.data    3288.859436                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.802944                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.802944                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data     94753540                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        94753540                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     73517528                       # number of WriteReq hits
@@ -185,14 +185,14 @@ system.cpu.dcache.demand_misses::cpu.data         4152                       # n
 system.cpu.dcache.demand_misses::total           4152                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data         4152                       # number of overall misses
 system.cpu.dcache.overall_misses::total          4152                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     48034000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     48034000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    176792000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    176792000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    224826000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    224826000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    224826000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    224826000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     48094000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     48094000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    176797000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    176797000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    224891000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    224891000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    224891000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    224891000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data     94754490                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total     94754490                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     73520730                       # number of WriteReq accesses(hits+misses)
@@ -209,14 +209,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.000025
 system.cpu.dcache.demand_miss_rate::total     0.000025                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.000025                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.000025                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50562.105263                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 50562.105263                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55212.991880                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 55212.991880                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 54148.843931                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 54148.843931                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 54148.843931                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 54148.843931                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50625.263158                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 50625.263158                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55214.553404                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 55214.553404                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 54164.499037                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 54164.499037                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 54164.499037                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 54164.499037                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -235,14 +235,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data         4152
 system.cpu.dcache.demand_mshr_misses::total         4152                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data         4152                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total         4152                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     45184000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     45184000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    167186000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    167186000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    212370000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    212370000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    212370000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    212370000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     45244000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     45244000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    167191000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    167191000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    212435000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    212435000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    212435000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    212435000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000010                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000010                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000044                       # mshr miss rate for WriteReq accesses
@@ -251,28 +251,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000025
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000025                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000025                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000025                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47562.105263                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47562.105263                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52212.991880                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52212.991880                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51148.843931                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 51148.843931                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51148.843931                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 51148.843931                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47625.263158                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47625.263158                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52214.553404                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52214.553404                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51164.499037                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 51164.499037                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51164.499037                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 51164.499037                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse              3772.462815                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse              3772.396394                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                     674                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                  4566                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.147613                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks   371.536806                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst   2770.454477                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data    630.471532                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::writebacks   371.526936                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst   2770.408528                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    630.460931                       # Average occupied blocks per requestor
 system.cpu.l2cache.occ_percent::writebacks     0.011338                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst     0.084548                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.084546                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.data     0.019240                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.115126                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.115124                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst          468                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data          123                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total            591                       # number of ReadReq hits
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
index 27728d570..e98d14637 100644
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
@@ -497,7 +497,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
@@ -529,7 +529,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout
index e6faeb5f0..7d2acfcbb 100755
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:10:14
-gem5 started Jun 29 2012 00:48:53
+gem5 compiled Jul  2 2012 09:08:16
+gem5 started Jul  2 2012 15:48:29
 gem5 executing on zizzer
 command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/30.eon/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
@@ -13,4 +13,4 @@ info: Increasing stack size by one page.
 info: Increasing stack size by one page.
 info: Increasing stack size by one page.
 OO-style eon Time= 0.070000
-Exiting @ tick 71244143500 because target called exit()
+Exiting @ tick 71229334000 because target called exit()
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
index e982040ed..48ec2839e 100644
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
@@ -1,32 +1,32 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.071244                       # Number of seconds simulated
-sim_ticks                                 71244143500                       # Number of ticks simulated
-final_tick                                71244143500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.071229                       # Number of seconds simulated
+sim_ticks                                 71229334000                       # Number of ticks simulated
+final_tick                                71229334000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 187993                       # Simulator instruction rate (inst/s)
-host_op_rate                                   240337                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               49051248                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 243200                       # Number of bytes of host memory used
-host_seconds                                  1452.44                       # Real time elapsed on the host
-sim_insts                                   273048446                       # Number of instructions simulated
-sim_ops                                     349076170                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst            195520                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data            273792                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               469312                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       195520                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          195520                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               3055                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               4278                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  7333                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              2744366                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3843011                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 6587377                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         2744366                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            2744366                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             2744366                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             3843011                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6587377                       # Total bandwidth to/from this memory (bytes/s)
+host_inst_rate                                 127900                       # Simulator instruction rate (inst/s)
+host_op_rate                                   163512                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               33364795                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 243124                       # Number of bytes of host memory used
+host_seconds                                  2134.87                       # Real time elapsed on the host
+sim_insts                                   273048466                       # Number of instructions simulated
+sim_ops                                     349076190                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst            195712                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data            273280                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               468992                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       195712                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          195712                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               3058                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               4270                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  7328                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              2747632                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3836622                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 6584254                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         2747632                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            2747632                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             2747632                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             3836622                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                6584254                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -70,107 +70,107 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  191                       # Number of system calls
-system.cpu.numCycles                        142488288                       # number of cpu cycles simulated
+system.cpu.numCycles                        142458669                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                 36834655                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted           22011992                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect            2128141                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups              21111775                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                 17921807                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                 36827289                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           22021149                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect            2124112                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              21185272                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                 17907212                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                  7049660                       # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect                9673                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles           41170537                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      330092344                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    36834655                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           24971467                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      74065448                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 8653461                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles               20659218                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                   37                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          3712                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                  39589827                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                662584                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          142371733                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.982100                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.456260                       # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS                  7048127                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect                9776                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles           41164597                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      330015965                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    36827289                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           24955339                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      74037174                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 8640903                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               20677414                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                   46                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles          3984                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                  39570950                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                662120                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          142347473                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.981638                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.456068                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 68999572     48.46%     48.46% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  7443838      5.23%     53.69% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  5890912      4.14%     57.83% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  6290109      4.42%     62.25% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  5018667      3.53%     65.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  4222472      2.97%     68.74% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  3222890      2.26%     71.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  4319860      3.03%     74.04% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 36963413     25.96%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 69001909     48.47%     48.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  7430233      5.22%     53.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  5888428      4.14%     57.83% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  6296154      4.42%     62.25% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  5019761      3.53%     65.78% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  4223315      2.97%     68.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  3223904      2.26%     71.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  4316057      3.03%     74.04% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 36947712     25.96%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            142371733                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.258510                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.316628                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 47920905                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              15947714                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  69670851                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               2428941                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                6403322                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              7589257                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 69989                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              416841547                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                209997                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                6403322                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 53735690                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 1551358                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         361067                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  66219864                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              14100432                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              406248964                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                    31                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                1649610                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents              10115480                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents              773                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           445265070                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            2397426033                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1310073571                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups        1087352462                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             384584954                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 60680116                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts              19505                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts          19502                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  35831958                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            105842469                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            93258241                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           4666139                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          5699487                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  393022623                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded               30465                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 378573033                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           1364119                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        42964941                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    113697743                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved           5987                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     142371733                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.659046                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.045030                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            142347473                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.258512                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.316573                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 47914284                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              15959399                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  69656008                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               2423234                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                6394548                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              7585679                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 70199                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              416758303                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                209359                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                6394548                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 53729037                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 1556343                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         362126                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  66198989                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              14106430                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              406180848                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                    80                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                1648620                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents              10123493                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents             1169                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           445266108                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            2397137405                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1309627482                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups        1087509923                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             384584986                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 60681122                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts              19329                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts          19327                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  35836582                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            105837544                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            93231927                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           4645950                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          5672170                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  392964645                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               30275                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 378555721                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           1363581                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        42910046                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    113514871                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           5793                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     142347473                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.659378                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.045296                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            29238426     20.54%     20.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            20559915     14.44%     34.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            20888687     14.67%     49.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            18235605     12.81%     62.46% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            24142271     16.96%     79.42% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            16046767     11.27%     90.69% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             9027765      6.34%     97.03% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             3298956      2.32%     99.34% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              933341      0.66%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            29227228     20.53%     20.53% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            20574959     14.45%     34.99% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            20845821     14.64%     49.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            18255784     12.82%     62.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            24133952     16.95%     79.41% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            16055098     11.28%     90.69% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             9008550      6.33%     97.02% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             3309478      2.32%     99.34% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              936603      0.66%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       142371733                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       142347473                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                    9050      0.05%      0.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                   4700      0.03%      0.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                    9705      0.05%      0.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                   4696      0.03%      0.08% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.08% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.08% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.08% # attempts to use FU when none available
@@ -189,22 +189,22 @@ system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.08% # at
 system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.08% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.08% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd             48305      0.27%      0.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd             48154      0.27%      0.35% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      0.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp              7771      0.04%      0.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt               390      0.00%      0.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp              7801      0.04%      0.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt               391      0.00%      0.39% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatDiv                 3      0.00%      0.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc           194430      1.08%      1.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult             4896      0.03%      1.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc        241266      1.34%      2.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc           194497      1.08%      1.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult             4577      0.03%      1.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc        241305      1.34%      2.85% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      2.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                9438470     52.59%     55.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               7998776     44.57%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                9433836     52.57%     55.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               7998969     44.58%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             128705433     34.00%     34.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult              2178586      0.58%     34.57% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             128679498     33.99%     33.99% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult              2178469      0.58%     34.57% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     34.57% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     34.57% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     34.57% # Type of FU issued
@@ -215,7 +215,7 @@ system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     34.57% # Ty
 system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     34.57% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     34.57% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     34.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    5      0.00%     34.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    3      0.00%     34.57% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     34.57% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     34.57% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     34.57% # Type of FU issued
@@ -223,169 +223,169 @@ system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     34.57% # Ty
 system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     34.57% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     34.57% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     34.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd         6839771      1.81%     36.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     36.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp         8697995      2.30%     38.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt         3451888      0.91%     39.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv         1605167      0.42%     40.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc       21254253      5.61%     45.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult        7183697      1.90%     47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc      7136969      1.89%     49.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt         175286      0.05%     49.46% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            102677998     27.12%     76.58% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            88665985     23.42%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd         6838580      1.81%     36.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     36.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp         8699925      2.30%     38.67% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt         3453303      0.91%     39.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv         1605459      0.42%     40.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc       21250786      5.61%     45.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult        7183426      1.90%     47.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc      7137674      1.89%     49.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt         175287      0.05%     49.45% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            102689873     27.13%     76.58% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            88663438     23.42%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              378573033                       # Type of FU issued
-system.cpu.iq.rate                           2.656871                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    17948057                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.047410                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          668230837                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         303627249                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    252741444                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads           250599138                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes          132404625                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses    118730959                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              267327381                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses               129193709                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         10789214                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              378555721                       # Type of FU issued
+system.cpu.iq.rate                           2.657302                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    17943934                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.047401                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          668132849                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         303460922                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    252722845                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads           250633581                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes          132457901                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses    118739342                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              267290872                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses               129208783                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         10791540                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     11191376                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses       112013                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        13979                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     10880305                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     11186447                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       112704                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        14184                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     10853987                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads         7857                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked           112                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads         9836                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked           124                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                6403322                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                   34047                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                  1473                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           393102382                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts           1223414                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             105842469                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             93258241                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts              19294                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                    195                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                   174                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          13979                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        1692038                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       558009                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              2250047                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             373788733                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             101161202                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           4784300                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                6394548                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                   40816                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                  2257                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           393044352                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           1233465                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             105837544                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             93231927                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts              19117                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                    279                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                   239                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          14184                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        1686736                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       558131                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              2244867                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             373775544                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             101165584                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           4780177                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                         49294                       # number of nop insts executed
-system.cpu.iew.exec_refs                    188542226                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 32415827                       # Number of branches executed
-system.cpu.iew.exec_stores                   87381024                       # Number of stores executed
-system.cpu.iew.exec_rate                     2.623294                       # Inst execution rate
-system.cpu.iew.wb_sent                      372275263                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     371472403                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 184833323                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 367854017                       # num instructions consuming a value
+system.cpu.iew.exec_nop                         49432                       # number of nop insts executed
+system.cpu.iew.exec_refs                    188551589                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 32411941                       # Number of branches executed
+system.cpu.iew.exec_stores                   87386005                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.623747                       # Inst execution rate
+system.cpu.iew.wb_sent                      372264339                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     371462187                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 184812981                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 367833213                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       2.607038                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.502464                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       2.607508                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.502437                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts      273049058                       # The number of committed instructions
-system.cpu.commit.commitCommittedOps        349076782                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts        44025608                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls           24478                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           2100754                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    135968412                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.567337                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.653672                       # Number of insts commited each cycle
+system.cpu.commit.commitCommittedInsts      273049078                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps        349076802                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts        43967644                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls           24482                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts           2096481                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    135952926                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.567630                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.653370                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     38641813     28.42%     28.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     29058445     21.37%     49.79% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     13534255      9.95%     59.75% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     11222379      8.25%     68.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     13789944     10.14%     78.14% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      7224545      5.31%     83.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      4032637      2.97%     86.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      3910785      2.88%     89.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     14553609     10.70%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     38639864     28.42%     28.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     29020043     21.35%     49.77% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     13541053      9.96%     59.73% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     11234412      8.26%     67.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     13804382     10.15%     78.14% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      7226420      5.32%     83.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      4033022      2.97%     86.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      3906183      2.87%     89.30% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     14547547     10.70%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    135968412                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            273049058                       # Number of instructions committed
-system.cpu.commit.committedOps              349076782                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    135952926                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            273049078                       # Number of instructions committed
+system.cpu.commit.committedOps              349076802                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                      177029029                       # Number of memory references committed
-system.cpu.commit.loads                      94651093                       # Number of loads committed
+system.cpu.commit.refs                      177029037                       # Number of memory references committed
+system.cpu.commit.loads                      94651097                       # Number of loads committed
 system.cpu.commit.membars                       11033                       # Number of memory barriers committed
-system.cpu.commit.branches                   30523988                       # Number of branches committed
+system.cpu.commit.branches                   30523992                       # Number of branches committed
 system.cpu.commit.fp_insts                  114216705                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 279593987                       # Number of committed integer instructions.
+system.cpu.commit.int_insts                 279594003                       # Number of committed integer instructions.
 system.cpu.commit.function_calls              6225112                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events              14553609                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events              14547547                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    514514670                       # The number of ROB reads
-system.cpu.rob.rob_writes                   792612920                       # The number of ROB writes
-system.cpu.timesIdled                            2826                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          116555                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                   273048446                       # Number of Instructions Simulated
-system.cpu.committedOps                     349076170                       # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total             273048446                       # Number of Instructions Simulated
-system.cpu.cpi                               0.521843                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.521843                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.916287                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.916287                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               1784947411                       # number of integer regfile reads
-system.cpu.int_regfile_writes               236351279                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                 189697788                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                133433924                       # number of floating regfile writes
-system.cpu.misc_regfile_reads               991980863                       # number of misc regfile reads
-system.cpu.misc_regfile_writes               34426471                       # number of misc regfile writes
-system.cpu.icache.replacements                  14091                       # number of replacements
-system.cpu.icache.tagsinuse               1855.139503                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 39573076                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                  15985                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                2475.638161                       # Average number of references to valid blocks.
+system.cpu.rob.rob_reads                    514447302                       # The number of ROB reads
+system.cpu.rob.rob_writes                   792488332                       # The number of ROB writes
+system.cpu.timesIdled                            3380                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          111196                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                   273048466                       # Number of Instructions Simulated
+system.cpu.committedOps                     349076190                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total             273048466                       # Number of Instructions Simulated
+system.cpu.cpi                               0.521734                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.521734                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.916686                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.916686                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               1784924885                       # number of integer regfile reads
+system.cpu.int_regfile_writes               236340288                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                 189697402                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                133438574                       # number of floating regfile writes
+system.cpu.misc_regfile_reads               991950959                       # number of misc regfile reads
+system.cpu.misc_regfile_writes               34426479                       # number of misc regfile writes
+system.cpu.icache.replacements                  14092                       # number of replacements
+system.cpu.icache.tagsinuse               1857.122291                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 39554212                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                  15988                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                2473.993745                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst    1855.139503                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.905830                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.905830                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst     39573076                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        39573076                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      39573076                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         39573076                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     39573076                       # number of overall hits
-system.cpu.icache.overall_hits::total        39573076                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        16751                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         16751                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        16751                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          16751                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        16751                       # number of overall misses
-system.cpu.icache.overall_misses::total         16751                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    205369500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    205369500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    205369500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    205369500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    205369500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    205369500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     39589827                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     39589827                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     39589827                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     39589827                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     39589827                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     39589827                       # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::cpu.inst    1857.122291                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.906798                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.906798                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst     39554212                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        39554212                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      39554212                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         39554212                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     39554212                       # number of overall hits
+system.cpu.icache.overall_hits::total        39554212                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        16738                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         16738                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        16738                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          16738                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        16738                       # number of overall misses
+system.cpu.icache.overall_misses::total         16738                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    211077500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    211077500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    211077500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    211077500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    211077500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    211077500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     39570950                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     39570950                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     39570950                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     39570950                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     39570950                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     39570950                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000423                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000423                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000423                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000423                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000423                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000423                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12260.133723                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 12260.133723                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 12260.133723                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 12260.133723                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 12260.133723                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 12260.133723                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12610.676305                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 12610.676305                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 12610.676305                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 12610.676305                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 12610.676305                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 12610.676305                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -394,146 +394,146 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          765                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          765                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          765                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          765                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          765                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          765                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        15986                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        15986                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        15986                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        15986                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        15986                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        15986                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    137471000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    137471000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    137471000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    137471000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    137471000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    137471000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          750                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          750                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          750                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          750                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          750                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          750                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        15988                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        15988                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        15988                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        15988                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        15988                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        15988                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    140340000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    140340000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    140340000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    140340000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    140340000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    140340000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000404                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000404                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000404                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000404                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000404                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000404                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  8599.462029                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  8599.462029                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  8599.462029                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total  8599.462029                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  8599.462029                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total  8599.462029                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  8777.833375                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  8777.833375                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  8777.833375                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total  8777.833375                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  8777.833375                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total  8777.833375                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                   1422                       # number of replacements
-system.cpu.dcache.tagsinuse               3120.754345                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                172231049                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                   4634                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs               37166.821105                       # Average number of references to valid blocks.
+system.cpu.dcache.replacements                   1419                       # number of replacements
+system.cpu.dcache.tagsinuse               3123.008839                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                172229353                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                   4629                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs               37206.600346                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    3120.754345                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.761903                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.761903                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data     90171406                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        90171406                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     82032842                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       82032842                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data        13547                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total        13547                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data        13253                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total        13253                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     172204248                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        172204248                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    172204248                       # number of overall hits
-system.cpu.dcache.overall_hits::total       172204248                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data         3698                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total          3698                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data        19818                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total        19818                       # number of WriteReq misses
+system.cpu.dcache.occ_blocks::cpu.data    3123.008839                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.762453                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.762453                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     90171250                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        90171250                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     82031303                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       82031303                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data        13543                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total        13543                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data        13257                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total        13257                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data     172202553                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        172202553                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    172202553                       # number of overall hits
+system.cpu.dcache.overall_hits::total       172202553                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data         3872                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total          3872                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data        21357                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        21357                       # number of WriteReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            2                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            2                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data        23516                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total          23516                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data        23516                       # number of overall misses
-system.cpu.dcache.overall_misses::total         23516                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data    118442000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total    118442000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    655611500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    655611500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data        25229                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total          25229                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data        25229                       # number of overall misses
+system.cpu.dcache.overall_misses::total         25229                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data    139932500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total    139932500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    828692500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    828692500                       # number of WriteReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        76000                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::total        76000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    774053500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    774053500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    774053500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    774053500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     90175104                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     90175104                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data    968625000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    968625000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    968625000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    968625000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     90175122                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     90175122                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     82052660                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     82052660                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data        13549                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total        13549                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data        13253                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total        13253                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    172227764                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    172227764                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    172227764                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    172227764                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000041                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.000041                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000242                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.000242                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data        13545                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total        13545                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data        13257                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total        13257                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    172227782                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    172227782                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    172227782                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    172227782                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000043                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.000043                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000260                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.000260                       # miss rate for WriteReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000148                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000148                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.000137                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.000137                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.000137                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.000137                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32028.664143                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 32028.664143                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33081.617721                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 33081.617721                       # average WriteReq miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.000146                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.000146                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.000146                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.000146                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36139.591942                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 36139.591942                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38801.915063                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 38801.915063                       # average WriteReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        38000                       # average LoadLockedReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        38000                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 32916.035890                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 32916.035890                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 32916.035890                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 32916.035890                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 38393.317214                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 38393.317214                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 38393.317214                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 38393.317214                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets       307000                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets       334500                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets              11                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets              12                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 27909.090909                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets        27875                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks         1041                       # number of writebacks
-system.cpu.dcache.writebacks::total              1041                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data         1882                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total         1882                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        16999                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        16999                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks         1036                       # number of writebacks
+system.cpu.dcache.writebacks::total              1036                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data         2060                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total         2060                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        18540                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        18540                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            2                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total            2                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data        18881                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total        18881                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data        18881                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total        18881                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data         1816                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total         1816                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data         2819                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total         2819                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data         4635                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total         4635                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data         4635                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total         4635                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     55172500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     55172500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    100155500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    100155500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    155328000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    155328000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    155328000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    155328000                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_hits::cpu.data        20600                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total        20600                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data        20600                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total        20600                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data         1812                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total         1812                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         2817                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         2817                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data         4629                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         4629                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data         4629                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         4629                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     59543000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     59543000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    108480500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    108480500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    168023500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    168023500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    168023500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    168023500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000020                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000020                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000034                       # mshr miss rate for WriteReq accesses
@@ -542,102 +542,98 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000027
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000027                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000027                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000027                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30381.332599                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30381.332599                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35528.733593                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35528.733593                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33511.974110                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 33511.974110                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33511.974110                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 33511.974110                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32860.375276                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32860.375276                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38509.229677                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38509.229677                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36298.012530                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 36298.012530                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36298.012530                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 36298.012530                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse              3993.397220                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                   13323                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                  5445                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  2.446832                       # Average number of references to valid blocks.
+system.cpu.l2cache.tagsinuse              3998.487468                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                   13321                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                  5435                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  2.450966                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks   372.052721                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst   2804.768410                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data    816.576088                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.011354                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst     0.085595                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.024920                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.121869                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst        12916                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data          301                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total          13217                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks         1041                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total         1041                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data            1                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total            1                       # number of UpgradeReq hits
+system.cpu.l2cache.occ_blocks::writebacks   369.804523                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst   2809.273532                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    819.409413                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.011286                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.085732                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.025006                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.122024                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst        12911                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data          300                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total          13211                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks         1036                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total         1036                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data           18                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total           18                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        12916                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data          319                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total           13235                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst        12916                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data          319                       # number of overall hits
-system.cpu.l2cache.overall_hits::total          13235                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         3069                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data         1513                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         4582                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data         2802                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total         2802                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         3069                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data         4315                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total          7384                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         3069                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data         4315                       # number of overall misses
-system.cpu.l2cache.overall_misses::total         7384                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    105043500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     51988500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    157032000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     96644500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total     96644500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    105043500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    148633000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    253676500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    105043500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    148633000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    253676500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst        15985                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data         1814                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.demand_hits::cpu.inst        12911                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data          318                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total           13229                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst        12911                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data          318                       # number of overall hits
+system.cpu.l2cache.overall_hits::total          13229                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         3077                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data         1511                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total         4588                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data         2800                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total         2800                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         3077                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data         4311                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total          7388                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         3077                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data         4311                       # number of overall misses
+system.cpu.l2cache.overall_misses::total         7388                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    108258000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     56236500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    164494500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    104322000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    104322000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    108258000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    160558500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    268816500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    108258000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    160558500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    268816500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst        15988                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data         1811                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total        17799                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks         1041                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total         1041                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data            1                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total            1                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data         2820                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total         2820                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        15985                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data         4634                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total        20619                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        15985                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data         4634                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total        20619                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.191992                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.834068                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.257430                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.993617                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.993617                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.191992                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.931161                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.358116                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.191992                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.931161                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.358116                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34227.272727                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34361.202908                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 34271.497163                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34491.256246                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34491.256246                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34227.272727                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34445.654693                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 34354.888949                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34227.272727                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34445.654693                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 34354.888949                       # average overall miss latency
+system.cpu.l2cache.Writeback_accesses::writebacks         1036                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total         1036                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data         2818                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total         2818                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        15988                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data         4629                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total        20617                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        15988                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data         4629                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total        20617                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.192457                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.834346                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.257767                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.993612                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.993612                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.192457                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.931303                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.358345                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.192457                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.931303                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.358345                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35182.970426                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 37218.067505                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 35853.204010                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 37257.857143                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 37257.857143                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35182.970426                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 37243.910926                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 36385.557661                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35182.970426                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 37243.910926                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 36385.557661                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -646,59 +642,59 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           14                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           37                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total           51                       # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst           14                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data           37                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           51                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst           14                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data           37                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           51                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3055                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data         1476                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         4531                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         2802                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total         2802                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3055                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data         4278                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         7333                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3055                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data         4278                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total         7333                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     94947500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     46180500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    141128000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     87716500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     87716500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     94947500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    133897000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    228844500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     94947500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    133897000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    228844500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.191117                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.813671                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.254565                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.993617                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.993617                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.191117                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.923177                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.355643                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.191117                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.923177                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.355643                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31079.378069                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31287.601626                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31147.208122                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31304.960742                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31304.960742                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31079.378069                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31298.971482                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31207.486704                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31079.378069                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31298.971482                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31207.486704                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           19                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           41                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total           60                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst           19                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data           41                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           60                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst           19                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data           41                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total           60                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3058                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data         1470                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         4528                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         2800                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         2800                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3058                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data         4270                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         7328                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3058                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data         4270                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total         7328                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     98125000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     50350500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    148475500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     95488500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     95488500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     98125000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    145839000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    243964000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     98125000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    145839000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    243964000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.191268                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.811706                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.254396                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.993612                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.993612                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.191268                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.922445                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.355435                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.191268                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.922445                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.355435                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32087.965991                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 34252.040816                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32790.525618                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 34103.035714                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 34103.035714                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32087.965991                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34154.332553                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33292.030568                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32087.965991                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34154.332553                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33292.030568                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini
index 68ac46334..0fa8c3883 100644
--- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini
@@ -166,7 +166,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
@@ -198,7 +198,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout
index ddb90c634..091d7545a 100755
--- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:10:14
-gem5 started Jun 29 2012 00:56:30
+gem5 compiled Jul  2 2012 09:08:16
+gem5 started Jul  2 2012 16:02:17
 gem5 executing on zizzer
 command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
@@ -13,4 +13,4 @@ info: Increasing stack size by one page.
 info: Increasing stack size by one page.
 info: Increasing stack size by one page.
 OO-style eon Time= 0.520000
-Exiting @ tick 525854423000 because target called exit()
+Exiting @ tick 525920061000 because target called exit()
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
index bbdf06ba7..3487a1e4f 100644
--- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.525854                       # Number of seconds simulated
-sim_ticks                                525854423000                       # Number of ticks simulated
-final_tick                               525854423000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.525920                       # Number of seconds simulated
+sim_ticks                                525920061000                       # Number of ticks simulated
+final_tick                               525920061000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1009014                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1289987                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1945426950                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 241152                       # Number of bytes of host memory used
-host_seconds                                   270.30                       # Real time elapsed on the host
+host_inst_rate                                 966127                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1235157                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1862970627                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 241076                       # Number of bytes of host memory used
+host_seconds                                   282.30                       # Real time elapsed on the host
 sim_insts                                   272739283                       # Number of instructions simulated
 sim_ops                                     348687122                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst            166976                       # Number of bytes read from this memory
@@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total          166976                       # Nu
 system.physmem.num_reads::cpu.inst               2609                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data               4223                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                  6832                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst               317533                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data               513967                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                  831500                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          317533                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             317533                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              317533                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data              513967                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                 831500                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               317493                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data               513903                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                  831396                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          317493                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             317493                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              317493                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data              513903                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                 831396                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -70,7 +70,7 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  191                       # Number of system calls
-system.cpu.numCycles                       1051708846                       # number of cpu cycles simulated
+system.cpu.numCycles                       1051840122                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   272739283                       # Number of instructions committed
@@ -89,18 +89,18 @@ system.cpu.num_mem_refs                     177024356                       # nu
 system.cpu.num_load_insts                    94648757                       # Number of load instructions
 system.cpu.num_store_insts                   82375599                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                 1051708846                       # Number of busy cycles
+system.cpu.num_busy_cycles                 1051840122                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                  13796                       # number of replacements
-system.cpu.icache.tagsinuse               1765.984191                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse               1765.965460                       # Cycle average of tags in use
 system.cpu.icache.total_refs                348644747                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                  15603                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               22344.725181                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst    1765.984191                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.862297                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.862297                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst    1765.965460                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.862288                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.862288                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst    348644747                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total       348644747                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst     348644747                       # number of demand (read+write) hits
@@ -113,12 +113,12 @@ system.cpu.icache.demand_misses::cpu.inst        15603                       # n
 system.cpu.icache.demand_misses::total          15603                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst        15603                       # number of overall misses
 system.cpu.icache.overall_misses::total         15603                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    328020000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    328020000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    328020000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    328020000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    328020000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    328020000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    328087000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    328087000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    328087000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    328087000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    328087000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    328087000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst    348660350                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total    348660350                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst    348660350                       # number of demand (read+write) accesses
@@ -131,12 +131,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000045
 system.cpu.icache.demand_miss_rate::total     0.000045                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000045                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000045                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21022.880215                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 21022.880215                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 21022.880215                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 21022.880215                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 21022.880215                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 21022.880215                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21027.174261                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 21027.174261                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 21027.174261                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 21027.174261                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 21027.174261                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 21027.174261                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -151,34 +151,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst        15603
 system.cpu.icache.demand_mshr_misses::total        15603                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst        15603                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total        15603                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    281211000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    281211000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    281211000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    281211000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    281211000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    281211000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    281278000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    281278000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    281278000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    281278000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    281278000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    281278000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000045                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000045                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000045                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000045                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000045                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000045                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18022.880215                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18022.880215                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18022.880215                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 18022.880215                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18022.880215                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 18022.880215                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18027.174261                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18027.174261                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18027.174261                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 18027.174261                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18027.174261                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 18027.174261                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                   1332                       # number of replacements
-system.cpu.dcache.tagsinuse               3078.396294                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               3078.361570                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                176641599                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                   4478                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs               39446.538410                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    3078.396294                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.751562                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.751562                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::cpu.data    3078.361570                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.751553                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.751553                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data     94570004                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        94570004                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     82049805                       # number of WriteReq hits
@@ -199,14 +199,14 @@ system.cpu.dcache.demand_misses::cpu.data         4478                       # n
 system.cpu.dcache.demand_misses::total           4478                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data         4478                       # number of overall misses
 system.cpu.dcache.overall_misses::total          4478                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     79898000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     79898000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    160160000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    160160000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    240058000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    240058000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    240058000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    240058000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     80120000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     80120000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    160192000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    160192000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    240312000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    240312000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    240312000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    240312000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data     94571610                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total     94571610                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     82052677                       # number of WriteReq accesses(hits+misses)
@@ -227,14 +227,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.000025
 system.cpu.dcache.demand_miss_rate::total     0.000025                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.000025                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.000025                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49749.688667                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 49749.688667                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55766.016713                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 55766.016713                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 53608.307280                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 53608.307280                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 53608.307280                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 53608.307280                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49887.920299                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 49887.920299                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55777.158774                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 55777.158774                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 53665.029031                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 53665.029031                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 53665.029031                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 53665.029031                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -253,14 +253,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data         4478
 system.cpu.dcache.demand_mshr_misses::total         4478                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data         4478                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total         4478                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     75080000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     75080000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    151544000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    151544000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    226624000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    226624000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    226624000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    226624000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     75302000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     75302000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    151576000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    151576000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    226878000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    226878000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    226878000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    226878000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000017                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000017                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000035                       # mshr miss rate for WriteReq accesses
@@ -269,28 +269,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000025
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000025                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000025                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000025                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46749.688667                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46749.688667                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52766.016713                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52766.016713                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50608.307280                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 50608.307280                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50608.307280                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 50608.307280                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46887.920299                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46887.920299                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52777.158774                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52777.158774                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50665.029031                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 50665.029031                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50665.029031                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 50665.029031                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse              3487.701804                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse              3487.655618                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                   13310                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                  4882                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  2.726342                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks   341.613277                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst   2408.384377                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data    737.704150                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::writebacks   341.607182                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst   2408.352970                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    737.695465                       # Average occupied blocks per requestor
 system.cpu.l2cache.occ_percent::writebacks     0.010425                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst     0.073498                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.073497                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.data     0.022513                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.106436                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.106435                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst        12994                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data          239                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total          13233                       # number of ReadReq hits
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
index 1dc93d52f..0ba1f17a2 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
@@ -479,7 +479,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
@@ -511,7 +511,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout
index fbf7fa994..b26c5402f 100755
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:05:18
-gem5 started Jun 28 2012 22:12:31
+gem5 compiled Jul  2 2012 08:30:56
+gem5 started Jul  2 2012 09:41:27
 gem5 executing on zizzer
 command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
@@ -1385,4 +1385,4 @@ info: Increasing stack size by one page.
 2000: 760651391
 1000: 4031656975
 0: 2206428413
-Exiting @ tick 639588907000 because target called exit()
+Exiting @ tick 646278131000 because target called exit()
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
index f93e57319..042c81ef0 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,59 +1,59 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.639589                       # Number of seconds simulated
-sim_ticks                                639588907000                       # Number of ticks simulated
-final_tick                               639588907000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.646278                       # Number of seconds simulated
+sim_ticks                                646278131000                       # Number of ticks simulated
+final_tick                               646278131000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 210347                       # Simulator instruction rate (inst/s)
-host_op_rate                                   210347                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               73797228                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 229080                       # Number of bytes of host memory used
-host_seconds                                  8666.84                       # Real time elapsed on the host
+host_inst_rate                                 212773                       # Simulator instruction rate (inst/s)
+host_op_rate                                   212773                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               75429257                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 229040                       # Number of bytes of host memory used
+host_seconds                                  8568.00                       # Real time elapsed on the host
 sim_insts                                  1823043370                       # Number of instructions simulated
 sim_ops                                    1823043370                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst            191360                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          94464192                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             94655552                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       191360                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          191360                       # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu.inst            191680                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          94465088                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             94656768                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       191680                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          191680                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::writebacks      4281472                       # Number of bytes written to this memory
 system.physmem.bytes_written::total           4281472                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               2990                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            1476003                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1478993                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst               2995                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            1476017                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1479012                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks           66898                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                66898                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               299192                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            147695169                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               147994362                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          299192                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             299192                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           6694100                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                6694100                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           6694100                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              299192                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           147695169                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              154688461                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               296591                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            146167855                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               146464445                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          296591                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             296591                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           6624813                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                6624813                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           6624813                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              296591                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           146167855                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              153089259                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    525683715                       # DTB read hits
-system.cpu.dtb.read_misses                     628896                       # DTB read misses
+system.cpu.dtb.read_hits                    528353322                       # DTB read hits
+system.cpu.dtb.read_misses                     626455                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                526312611                       # DTB read accesses
-system.cpu.dtb.write_hits                   287304184                       # DTB write hits
-system.cpu.dtb.write_misses                     53890                       # DTB write misses
+system.cpu.dtb.read_accesses                528979777                       # DTB read accesses
+system.cpu.dtb.write_hits                   292227311                       # DTB write hits
+system.cpu.dtb.write_misses                     54391                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses               287358074                       # DTB write accesses
-system.cpu.dtb.data_hits                    812987899                       # DTB hits
-system.cpu.dtb.data_misses                     682786                       # DTB misses
+system.cpu.dtb.write_accesses               292281702                       # DTB write accesses
+system.cpu.dtb.data_hits                    820580633                       # DTB hits
+system.cpu.dtb.data_misses                     680846                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                813670685                       # DTB accesses
-system.cpu.itb.fetch_hits                   398461552                       # ITB hits
-system.cpu.itb.fetch_misses                      1212                       # ITB misses
+system.cpu.dtb.data_accesses                821261479                       # DTB accesses
+system.cpu.itb.fetch_hits                   401438115                       # ITB hits
+system.cpu.itb.fetch_misses                       852                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses               398462764                       # ITB accesses
+system.cpu.itb.fetch_accesses               401438967                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -67,247 +67,247 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   39                       # Number of system calls
-system.cpu.numCycles                       1279177815                       # number of cpu cycles simulated
+system.cpu.numCycles                       1292556263                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                391601012                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted          255930815                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect           27097905                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups             318432805                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                256621752                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                394747270                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted          256599366                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect           27590844                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups             323468940                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                262010178                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                 59044090                       # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect                7305                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles          417206849                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     3304631660                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   391601012                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          315665842                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     634205086                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles               158948618                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles               96266839                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                  158                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles         11708                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                 398461552                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               8907646                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples         1279053519                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.583654                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.145594                       # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS                 57787448                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect                7273                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles          421195056                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     3322341707                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   394747270                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          319797626                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     638354680                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles               162914777                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               98034183                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                  162                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles          9273                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                 401438115                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               8412038                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples         1292428853                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.570619                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.140035                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                644848433     50.42%     50.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 60073670      4.70%     55.11% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 44904383      3.51%     58.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 71013010      5.55%     64.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                124436565      9.73%     73.90% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 45667903      3.57%     77.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 41114141      3.21%     80.69% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  7023739      0.55%     81.24% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                239971675     18.76%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                654074173     50.61%     50.61% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 60911661      4.71%     55.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 43750931      3.39%     58.71% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 72637907      5.62%     64.33% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                126293368      9.77%     74.10% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 45669959      3.53%     77.63% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 41606825      3.22%     80.85% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  7021986      0.54%     81.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                240462043     18.61%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1279053519                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.306135                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.583403                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                450209575                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              79019815                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 608453320                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              10020119                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles              131350690                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             33655569                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 12307                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             3205531959                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                 46810                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles              131350690                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                478839352                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                32033074                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          25872                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 588505763                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              48298768                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             3118953725                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                   371                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                   8014                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents              42155636                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands          2071308237                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            3619384197                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       3501684594                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups         117699603                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total           1292428853                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.305400                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.570365                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                452871359                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              80658875                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 614115226                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               9960098                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles              134823295                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             34649231                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 12312                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             3231646724                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                 46688                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles              134823295                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                482927881                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                33597057                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          26321                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 592678256                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              48376043                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             3142025534                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                   359                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                  11387                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents              42577596                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands          2088048295                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            3654580538                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       3537192552                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups         117387986                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps            1384969070                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                686339167                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               4232                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            137                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 140575935                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            734762265                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           354500186                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          67932920                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          9138793                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 2625466002                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                 122                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                2176735177                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued          17945547                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       802302909                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    703322223                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             83                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples    1279053519                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.701833                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.797036                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                703079225                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               4247                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            139                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 143016933                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            739120184                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           360450433                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          67842482                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          9359459                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 2647443518                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                 119                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                2196739038                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued          17945817                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       824288888                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    711675230                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             80                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    1292428853                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.699698                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.805222                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           464081398     36.28%     36.28% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           216592353     16.93%     53.22% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           250622762     19.59%     72.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           121884176      9.53%     82.34% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4           104836053      8.20%     90.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            77987896      6.10%     96.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            21570720      1.69%     98.32% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7            17288528      1.35%     99.67% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             4189633      0.33%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           470829214     36.43%     36.43% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           219635474     16.99%     53.42% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           252835920     19.56%     72.99% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           120249082      9.30%     82.29% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4           106312850      8.23%     90.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            78591497      6.08%     96.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            21017975      1.63%     98.22% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7            17286985      1.34%     99.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             5669856      0.44%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      1279053519                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1292428853                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 1140853      3.19%      3.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      3.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      3.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      3.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      3.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      3.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      3.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      3.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      3.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      3.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      3.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      3.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      3.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      3.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      3.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      3.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      3.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      3.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      3.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      3.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      3.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      3.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      3.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      3.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      3.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      3.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      3.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      3.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      3.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               24076891     67.30%     70.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite              10558644     29.51%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 1140834      3.16%      3.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      3.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      3.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      3.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      3.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      3.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      3.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      3.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      3.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      3.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      3.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      3.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      3.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      3.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      3.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      3.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      3.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      3.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      3.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      3.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      3.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      3.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      3.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      3.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      3.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      3.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      3.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      3.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      3.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               24068551     66.72%     69.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite              10866173     30.12%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass              2752      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1247700404     57.32%     57.32% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                16695      0.00%     57.32% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     57.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd            28729941      1.32%     58.64% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp             8254693      0.38%     59.02% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt             7204651      0.33%     59.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  4      0.00%     59.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     59.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     59.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     59.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     59.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     59.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     59.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     59.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     59.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     59.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     59.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     59.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     59.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     59.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     59.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     59.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     59.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     59.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     59.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     59.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     59.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     59.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     59.35% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            586556392     26.95%     86.30% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           298269645     13.70%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1257954368     57.26%     57.26% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                16688      0.00%     57.27% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     57.27% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd            29223285      1.33%     58.60% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp             8254700      0.38%     58.97% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt             7204654      0.33%     59.30% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  4      0.00%     59.30% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     59.30% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     59.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     59.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     59.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     59.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     59.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     59.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     59.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     59.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     59.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     59.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     59.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     59.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     59.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     59.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     59.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     59.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     59.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     59.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     59.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     59.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     59.30% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            590393009     26.88%     86.18% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           303689578     13.82%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             2176735177                       # Type of FU issued
-system.cpu.iq.rate                           1.701667                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    35776388                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.016436                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         5534048167                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        3341408955                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   2010160977                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads           152197641                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes           86432816                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses     74384435                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             2134737053                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                77771760                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         67976479                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             2196739038                       # Type of FU issued
+system.cpu.iq.rate                           1.699531                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    36075558                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.016422                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         5585448848                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        3387972541                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   2024033733                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads           154479456                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes           83833082                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses     75371142                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             2153745376                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                79066468                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         69378492                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    223692239                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        13198                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        75649                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores    143705290                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads    228050158                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses      2255425                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        75959                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores    149655537                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads         4417                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked            29                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads         4423                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked            39                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles              131350690                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 3811054                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                200562                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          2981894857                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts           2707472                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             734762265                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            354500186                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                122                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 131033                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                  4888                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          75649                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect       27118847                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect        31958                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             27150805                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            2088347607                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             526312810                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          88387570                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles              134823295                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 4267154                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                460832                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          3006059050                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           2702145                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             739120184                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            360450433                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                119                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 451591                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                  5232                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          75959                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect       27593158                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect        31610                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             27624768                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            2105923301                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             528979869                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          90815737                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                     356428733                       # number of nop insts executed
-system.cpu.iew.exec_refs                    813671363                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                280895404                       # Number of branches executed
-system.cpu.iew.exec_stores                  287358553                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.632570                       # Inst execution rate
-system.cpu.iew.wb_sent                     2087345359                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    2084545412                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1181911333                       # num instructions producing a value
-system.cpu.iew.wb_consumers                1746825923                       # num instructions consuming a value
+system.cpu.iew.exec_nop                     358615413                       # number of nop insts executed
+system.cpu.iew.exec_refs                    821261997                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                282350798                       # Number of branches executed
+system.cpu.iew.exec_stores                  292282128                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.629270                       # Inst execution rate
+system.cpu.iew.wb_sent                     2102194150                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    2099404875                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1185212781                       # num instructions producing a value
+system.cpu.iew.wb_consumers                1754721969                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.629598                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.676605                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.624227                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.675442                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts     2008987604                       # The number of committed instructions
 system.cpu.commit.commitCommittedOps       2008987604                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts       956239558                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       980398498                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              39                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts          27085717                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples   1147702829                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.750442                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.504523                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts          27578641                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   1157605558                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.735468                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.494432                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    533397723     46.48%     46.48% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    226612269     19.74%     66.22% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2    118218768     10.30%     76.52% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     56744377      4.94%     81.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     50032490      4.36%     85.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     24020067      2.09%     87.92% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     19167450      1.67%     89.59% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     15607807      1.36%     90.95% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8    103901878      9.05%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    541345046     46.76%     46.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    227581474     19.66%     66.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2    119272187     10.30%     76.73% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     56742029      4.90%     81.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     51019589      4.41%     86.04% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     24162951      2.09%     88.12% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     18255182      1.58%     89.70% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     15605334      1.35%     91.05% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8    103621766      8.95%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   1147702829                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total   1157605558                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts           2008987604                       # Number of instructions committed
 system.cpu.commit.committedOps             2008987604                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -318,70 +318,70 @@ system.cpu.commit.branches                  266706457                       # Nu
 system.cpu.commit.fp_insts                   71824891                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                1778941351                       # Number of committed integer instructions.
 system.cpu.commit.function_calls             39955347                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events             103901878                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events             103621766                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   4003391703                       # The number of ROB reads
-system.cpu.rob.rob_writes                  6061807983                       # The number of ROB writes
-system.cpu.timesIdled                            3462                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          124296                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                   4037733484                       # The number of ROB reads
+system.cpu.rob.rob_writes                  6113598013                       # The number of ROB writes
+system.cpu.timesIdled                            3574                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          127410                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                  1823043370                       # Number of Instructions Simulated
 system.cpu.committedOps                    1823043370                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total            1823043370                       # Number of Instructions Simulated
-system.cpu.cpi                               0.701672                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.701672                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.425168                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.425168                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               2657999656                       # number of integer regfile reads
-system.cpu.int_regfile_writes              1510398630                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                  80463471                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                 53540440                       # number of floating regfile writes
+system.cpu.cpi                               0.709010                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.709010                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.410417                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.410417                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               2681938582                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1518871452                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                  81943465                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                 54033824                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                       1                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.icache.replacements                   8417                       # number of replacements
-system.cpu.icache.tagsinuse               1667.677082                       # Cycle average of tags in use
-system.cpu.icache.total_refs                398450176                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                  10137                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs               39306.518299                       # Average number of references to valid blocks.
+system.cpu.icache.replacements                   8410                       # number of replacements
+system.cpu.icache.tagsinuse               1670.523326                       # Cycle average of tags in use
+system.cpu.icache.total_refs                401426768                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                  10133                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               39615.786835                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst    1667.677082                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.814295                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.814295                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst    398450176                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       398450176                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     398450176                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        398450176                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    398450176                       # number of overall hits
-system.cpu.icache.overall_hits::total       398450176                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        11376                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         11376                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        11376                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          11376                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        11376                       # number of overall misses
-system.cpu.icache.overall_misses::total         11376                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    188382000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    188382000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    188382000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    188382000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    188382000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    188382000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    398461552                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    398461552                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    398461552                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    398461552                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    398461552                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    398461552                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000029                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000029                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000029                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000029                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000029                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000029                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16559.599156                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 16559.599156                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 16559.599156                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 16559.599156                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 16559.599156                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 16559.599156                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst    1670.523326                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.815685                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.815685                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst    401426768                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       401426768                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     401426768                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        401426768                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    401426768                       # number of overall hits
+system.cpu.icache.overall_hits::total       401426768                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        11347                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         11347                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        11347                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          11347                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        11347                       # number of overall misses
+system.cpu.icache.overall_misses::total         11347                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    204563500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    204563500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    204563500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    204563500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    204563500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    204563500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    401438115                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    401438115                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    401438115                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    401438115                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    401438115                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    401438115                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000028                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000028                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000028                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000028                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000028                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000028                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18027.980964                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 18027.980964                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 18027.980964                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 18027.980964                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 18027.980964                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 18027.980964                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -390,296 +390,286 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1238                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         1238                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         1238                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         1238                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         1238                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         1238                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        10138                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        10138                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        10138                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        10138                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        10138                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        10138                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    122862500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    122862500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    122862500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    122862500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    122862500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    122862500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1213                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         1213                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         1213                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         1213                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         1213                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         1213                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        10134                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        10134                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        10134                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        10134                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        10134                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        10134                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    139352000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    139352000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    139352000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    139352000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    139352000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    139352000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000025                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000025                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000025                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000025                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000025                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000025                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12119.007694                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12119.007694                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12119.007694                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12119.007694                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12119.007694                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12119.007694                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13750.937438                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13750.937438                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13750.937438                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 13750.937438                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13750.937438                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 13750.937438                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                1527982                       # number of replacements
-system.cpu.dcache.tagsinuse               4095.064488                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                666017344                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                1532078                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                 434.715037                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              264095000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4095.064488                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.999772                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.999772                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data    455774339                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       455774339                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    210242956                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      210242956                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data           49                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total           49                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data     666017295                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        666017295                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    666017295                       # number of overall hits
-system.cpu.dcache.overall_hits::total       666017295                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1928410                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1928410                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       551940                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       551940                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data            1                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total            1                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      2480350                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2480350                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      2480350                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2480350                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  71225328000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  71225328000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  20805642991                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  20805642991                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        20500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total        20500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  92030970991                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  92030970991                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  92030970991                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  92030970991                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    457702749                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    457702749                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.replacements                1528066                       # number of replacements
+system.cpu.dcache.tagsinuse               4095.024861                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                667221349                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                1532162                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 435.477025                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              286461000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4095.024861                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.999762                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.999762                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data    457042035                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       457042035                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    210179266                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      210179266                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data           48                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total           48                       # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits::cpu.data     667221301                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        667221301                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    667221301                       # number of overall hits
+system.cpu.dcache.overall_hits::total       667221301                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1928301                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1928301                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       615630                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       615630                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      2543931                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2543931                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2543931                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2543931                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  76609230000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  76609230000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  30362374985                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  30362374985                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 106971604985                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 106971604985                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 106971604985                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 106971604985                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    458970336                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    458970336                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    210794896                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    210794896                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data           50                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total           50                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    668497645                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    668497645                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    668497645                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    668497645                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.004213                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.004213                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.002618                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.002618                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.020000                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.020000                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.003710                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.003710                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.003710                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.003710                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36934.743130                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 36934.743130                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37695.479565                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 37695.479565                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        20500                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        20500                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 37104.026041                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 37104.026041                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 37104.026041                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 37104.026041                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs        98500                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets        22000                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                16                       # number of cycles access was blocked
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data           48                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total           48                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    669765232                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    669765232                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    669765232                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    669765232                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.004201                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.004201                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.002921                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.002921                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.003798                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.003798                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.003798                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.003798                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39728.875316                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 39728.875316                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 49319.193322                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 49319.193322                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 42049.727365                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 42049.727365                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 42049.727365                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 42049.727365                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       174500                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets        21500                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                19                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               1                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs  6156.250000                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets        22000                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  9184.210526                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets        21500                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       109405                       # number of writebacks
-system.cpu.dcache.writebacks::total            109405                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       467937                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       467937                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       480335                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       480335                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            1                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total            1                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       948272                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       948272                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       948272                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       948272                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1460473                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1460473                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data        71605                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total        71605                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1532078                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1532078                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1532078                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1532078                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  49721165500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  49721165500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2483602000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   2483602000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  52204767500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  52204767500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  52204767500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  52204767500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.003191                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.003191                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.writebacks::writebacks       109390                       # number of writebacks
+system.cpu.dcache.writebacks::total            109390                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       467746                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       467746                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       544023                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       544023                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      1011769                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1011769                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1011769                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1011769                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1460555                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1460555                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data        71607                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total        71607                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1532162                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1532162                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1532162                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1532162                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  50266374000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  50266374000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   3176553000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   3176553000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  53442927000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  53442927000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  53442927000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  53442927000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.003182                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.003182                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000340                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000340                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002292                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.002292                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002292                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.002292                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34044.563302                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34044.563302                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34684.756651                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34684.756651                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34074.484132                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 34074.484132                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34074.484132                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 34074.484132                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002288                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.002288                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002288                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.002288                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34415.940516                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34415.940516                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44360.928401                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44360.928401                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34880.728670                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 34880.728670                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34880.728670                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 34880.728670                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.replacements               1480674                       # number of replacements
-system.cpu.l2cache.tagsinuse             32705.756030                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                   66279                       # Total number of references to valid blocks.
+system.cpu.l2cache.replacements               1480672                       # number of replacements
+system.cpu.l2cache.tagsinuse             32700.801266                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                   66336                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs               1513408                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  0.043795                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.043832                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks  3232.284223                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst     45.882783                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data  29427.589024                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.098641                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst     0.001400                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.898059                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.998100                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst         7148                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data        51323                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total          58471                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       109405                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       109405                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data         4752                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total         4752                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         7148                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data        56075                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total           63223                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         7148                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data        56075                       # number of overall hits
-system.cpu.l2cache.overall_hits::total          63223                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         2990                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data      1409150                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total      1412140                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data        66853                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total        66853                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         2990                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data      1476003                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total       1478993                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         2990                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data      1476003                       # number of overall misses
-system.cpu.l2cache.overall_misses::total      1478993                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    102622500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data  48197202500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total  48299825000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   2339465500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   2339465500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    102622500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  50536668000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  50639290500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    102622500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  50536668000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  50639290500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst        10138                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      1460473                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      1470611                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       109405                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       109405                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data        71605                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total        71605                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        10138                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      1532078                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      1542216                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        10138                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      1532078                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      1542216                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.294930                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.964859                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.960240                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.933636                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.933636                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.294930                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.963399                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.959005                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.294930                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.963399                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.959005                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34321.906355                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34203.031970                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 34203.283669                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34994.173784                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34994.173784                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34321.906355                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34238.865368                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 34239.033248                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34321.906355                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34238.865368                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 34239.033248                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs        40000                       # number of cycles access was blocked
+system.cpu.l2cache.occ_blocks::writebacks  3222.422706                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst     46.121130                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data  29432.257430                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.098341                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.001408                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.898201                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.997949                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst         7139                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data        51386                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total          58525                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       109390                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       109390                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data         4759                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total         4759                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst         7139                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data        56145                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total           63284                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         7139                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data        56145                       # number of overall hits
+system.cpu.l2cache.overall_hits::total          63284                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         2995                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data      1409163                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total      1412158                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data        66854                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total        66854                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         2995                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data      1476017                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total       1479012                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         2995                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data      1476017                       # number of overall misses
+system.cpu.l2cache.overall_misses::total      1479012                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    106968000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data  48399950500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total  48506918500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   2813587500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   2813587500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    106968000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  51213538000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  51320506000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    106968000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  51213538000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  51320506000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst        10134                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      1460549                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      1470683                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       109390                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       109390                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data        71613                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total        71613                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        10134                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      1532162                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      1542296                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        10134                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      1532162                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      1542296                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.295540                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.964817                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.960206                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.933546                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.933546                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.295540                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.963356                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.958968                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.295540                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.963356                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.958968                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35715.525876                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34346.594752                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 34349.498073                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 42085.552099                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 42085.552099                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35715.525876                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34697.119342                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 34699.181616                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35715.525876                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34697.119342                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 34699.181616                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs       107500                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs               11                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs               20                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs  3636.363636                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs         5375                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        66898                       # number of writebacks
 system.cpu.l2cache.writebacks::total            66898                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2990                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data      1409150                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total      1412140                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66853                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total        66853                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         2990                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data      1476003                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total      1478993                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         2990                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data      1476003                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total      1478993                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     92982500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  43684578500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  43777561000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   2138150500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   2138150500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     92982500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  45822729000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  45915711500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     92982500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  45822729000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  45915711500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.294930                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.964859                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.960240                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.933636                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.933636                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.294930                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.963399                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.959005                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.294930                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.963399                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.959005                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31097.826087                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31000.658908                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31000.864645                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31982.865391                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31982.865391                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31097.826087                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31045.146250                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31045.252750                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31097.826087                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31045.146250                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31045.252750                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2995                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data      1409163                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total      1412158                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66854                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        66854                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         2995                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data      1476017                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total      1479012                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         2995                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data      1476017                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total      1479012                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     97365000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  43717529000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  43814894000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   2612258000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   2612258000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     97365000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  46329787000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  46427152000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     97365000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  46329787000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  46427152000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.295540                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.964817                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.960206                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.933546                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.933546                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.295540                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.963356                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.958968                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.295540                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.963356                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.958968                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32509.181970                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31023.755946                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31026.906338                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39074.071858                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39074.071858                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32509.181970                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31388.383061                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31390.652679                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32509.181970                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31388.383061                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31390.652679                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
index acb7a4c77..77bc7da26 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
@@ -148,7 +148,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
@@ -180,7 +180,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout
index 85893d278..af38cd121 100755
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:05:18
-gem5 started Jun 28 2012 22:15:06
+gem5 compiled Jul  2 2012 08:30:56
+gem5 started Jul  2 2012 09:50:30
 gem5 executing on zizzer
 command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
@@ -1385,4 +1385,4 @@ info: Increasing stack size by one page.
 2000: 760651391
 1000: 4031656975
 0: 2206428413
-Exiting @ tick 2813377164000 because target called exit()
+Exiting @ tick 2813572242000 because target called exit()
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
index 9b3a7daff..ed560b063 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.813377                       # Number of seconds simulated
-sim_ticks                                2813377164000                       # Number of ticks simulated
-final_tick                               2813377164000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.813572                       # Number of seconds simulated
+sim_ticks                                2813572242000                       # Number of ticks simulated
+final_tick                               2813572242000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2127881                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2127880                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2979874149                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 227924                       # Number of bytes of host memory used
-host_seconds                                   944.13                       # Real time elapsed on the host
+host_inst_rate                                1893151                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1893151                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2651343461                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 227888                       # Number of bytes of host memory used
+host_seconds                                  1061.19                       # Real time elapsed on the host
 sim_insts                                  2008987605                       # Number of instructions simulated
 sim_ops                                    2008987605                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst            152128                       # Number of bytes read from this memory
@@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data            1475279                       # Nu
 system.physmem.num_reads::total               1477656                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks           66898                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                66898                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                54073                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             33560326                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                33614400                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           54073                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              54073                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1521827                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1521827                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1521827                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               54073                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            33560326                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               35136226                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst                54069                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             33558000                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                33612069                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           54069                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              54069                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1521721                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1521721                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1521721                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               54069                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            33558000                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               35133790                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -67,7 +67,7 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   39                       # Number of system calls
-system.cpu.numCycles                       5626754328                       # number of cpu cycles simulated
+system.cpu.numCycles                       5627144484                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                  2008987605                       # Number of instructions committed
@@ -86,18 +86,18 @@ system.cpu.num_mem_refs                     722298387                       # nu
 system.cpu.num_load_insts                   511488910                       # Number of load instructions
 system.cpu.num_store_insts                  210809477                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                 5626754328                       # Number of busy cycles
+system.cpu.num_busy_cycles                 5627144484                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                   9046                       # number of replacements
-system.cpu.icache.tagsinuse               1478.423352                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse               1478.417406                       # Cycle average of tags in use
 system.cpu.icache.total_refs               2009410475                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                  10596                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               189638.587675                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst    1478.423352                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.721886                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.721886                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst    1478.417406                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.721883                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.721883                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst   2009410475                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total      2009410475                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst    2009410475                       # number of demand (read+write) hits
@@ -110,12 +110,12 @@ system.cpu.icache.demand_misses::cpu.inst        10596                       # n
 system.cpu.icache.demand_misses::total          10596                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst        10596                       # number of overall misses
 system.cpu.icache.overall_misses::total         10596                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    248178000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    248178000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    248178000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    248178000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    248178000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    248178000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    248319000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    248319000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    248319000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    248319000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    248319000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    248319000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst   2009421071                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total   2009421071                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst   2009421071                       # number of demand (read+write) accesses
@@ -128,12 +128,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000005
 system.cpu.icache.demand_miss_rate::total     0.000005                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000005                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000005                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23421.857305                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 23421.857305                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 23421.857305                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 23421.857305                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 23421.857305                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 23421.857305                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23435.164213                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 23435.164213                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 23435.164213                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 23435.164213                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 23435.164213                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 23435.164213                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -148,34 +148,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst        10596
 system.cpu.icache.demand_mshr_misses::total        10596                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst        10596                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total        10596                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    216390000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    216390000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    216390000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    216390000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    216390000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    216390000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    216531000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    216531000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    216531000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    216531000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    216531000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    216531000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000005                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000005                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000005                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000005                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000005                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000005                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20421.857305                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20421.857305                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20421.857305                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 20421.857305                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20421.857305                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 20421.857305                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20435.164213                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20435.164213                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20435.164213                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 20435.164213                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20435.164213                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 20435.164213                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                1526048                       # number of replacements
-system.cpu.dcache.tagsinuse               4095.204600                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               4095.192384                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                720334778                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                1530144                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                 470.762737                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle             1049839000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4095.204600                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.999806                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.999806                       # Average percentage of cache occupancy
+system.cpu.dcache.warmup_cycle             1063975000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4095.192384                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.999803                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.999803                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data    509611834                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total       509611834                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data    210722944                       # number of WriteReq hits
@@ -192,14 +192,14 @@ system.cpu.dcache.demand_misses::cpu.data      1530144                       # n
 system.cpu.dcache.demand_misses::total        1530144                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data      1530144                       # number of overall misses
 system.cpu.dcache.overall_misses::total       1530144                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  79567740000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  79567740000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   3815994000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   3815994000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  83383734000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  83383734000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  83383734000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  83383734000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  79567803000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  79567803000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   3816006000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   3816006000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  83383809000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  83383809000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  83383809000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  83383809000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data    511070026                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total    511070026                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    210794896                       # number of WriteReq accesses(hits+misses)
@@ -216,14 +216,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.002120
 system.cpu.dcache.demand_miss_rate::total     0.002120                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.002120                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.002120                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54566.024227                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 54566.024227                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53035.273516                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 53035.273516                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 54494.043698                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 54494.043698                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 54494.043698                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 54494.043698                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54566.067431                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 54566.067431                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53035.440294                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 53035.440294                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 54494.092713                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 54494.092713                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 54494.092713                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 54494.092713                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -242,14 +242,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data      1530144
 system.cpu.dcache.demand_mshr_misses::total      1530144                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data      1530144                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total      1530144                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  75193164000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  75193164000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   3600138000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   3600138000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  78793302000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  78793302000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  78793302000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  78793302000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  75193227000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  75193227000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   3600150000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   3600150000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  78793377000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  78793377000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  78793377000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  78793377000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002853                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002853                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000341                       # mshr miss rate for WriteReq accesses
@@ -258,28 +258,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002120
 system.cpu.dcache.demand_mshr_miss_rate::total     0.002120                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002120                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.002120                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51566.024227                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51566.024227                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50035.273516                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50035.273516                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51494.043698                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 51494.043698                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51494.043698                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 51494.043698                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51566.067431                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51566.067431                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50035.440294                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50035.440294                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51494.092713                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 51494.092713                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51494.092713                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 51494.092713                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements               1479705                       # number of replacements
-system.cpu.l2cache.tagsinuse             32704.227313                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse             32703.875584                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                   65761                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs               1512436                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.043480                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks  3254.893374                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst     33.487953                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data  29415.845986                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.099331                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::writebacks  3255.326122                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst     33.503711                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data  29415.045751                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.099345                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.inst     0.001022                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.897700                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.998054                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.897676                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.998043                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst         8219                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data        49786                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total          58005                       # number of ReadReq hits
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
index 420e789e0..69901d605 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
@@ -497,7 +497,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
@@ -529,7 +529,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout
index 95a99c94b..bf499b85a 100755
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:10:14
-gem5 started Jun 29 2012 01:01:11
+gem5 compiled Jul  2 2012 09:08:16
+gem5 started Jul  2 2012 16:07:10
 gem5 executing on zizzer
 command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
@@ -1385,4 +1385,4 @@ info: Increasing stack size by one page.
 2000: 760651391
 1000: 4031656975
 0: 2206428413
-Exiting @ tick 734755023500 because target called exit()
+Exiting @ tick 735462942500 because target called exit()
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
index abd280906..7a9f62c0c 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
@@ -1,39 +1,39 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.734755                       # Number of seconds simulated
-sim_ticks                                734755023500                       # Number of ticks simulated
-final_tick                               734755023500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.735463                       # Number of seconds simulated
+sim_ticks                                735462942500                       # Number of ticks simulated
+final_tick                               735462942500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 119232                       # Simulator instruction rate (inst/s)
-host_op_rate                                   162378                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               63282228                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 243808                       # Number of bytes of host memory used
-host_seconds                                 11610.76                       # Real time elapsed on the host
-sim_insts                                  1384372850                       # Number of instructions simulated
-sim_ops                                    1885327602                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst            205760                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          94510912                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             94716672                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       205760                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          205760                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      4230336                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           4230336                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               3215                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            1476733                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1479948                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           66099                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                66099                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               280039                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            128629147                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               128909186                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          280039                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             280039                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           5757478                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                5757478                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           5757478                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              280039                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           128629147                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              134666664                       # Total bandwidth to/from this memory (bytes/s)
+host_inst_rate                                 115593                       # Simulator instruction rate (inst/s)
+host_op_rate                                   157422                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               61409842                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 243732                       # Number of bytes of host memory used
+host_seconds                                 11976.30                       # Real time elapsed on the host
+sim_insts                                  1384378705                       # Number of instructions simulated
+sim_ops                                    1885333457                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst            209152                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          94513152                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             94722304                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       209152                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          209152                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      4230272                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           4230272                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               3268                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            1476768                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1480036                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           66098                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                66098                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               284381                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            128508381                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               128792762                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          284381                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             284381                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           5751849                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                5751849                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           5751849                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              284381                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           128508381                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              134544612                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -77,322 +77,322 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                 1411                       # Number of system calls
-system.cpu.numCycles                       1469510048                       # number of cpu cycles simulated
+system.cpu.numCycles                       1470925886                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                526868038                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted          401113446                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect           36046358                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups             383398262                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                286508671                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                526944807                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted          400998639                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect           36103831                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups             389912593                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                290078755                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                 60655682                       # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect             2811201                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles          448614021                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     2626557864                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   526868038                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          347164353                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     716084096                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles               226374824                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles              100079168                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                 2230                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles         20420                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                 419610687                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes              12785505                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples         1449541071                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.542405                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.156280                       # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS                 59371448                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect             2810327                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles          451184041                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     2630280787                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   526944807                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          349450203                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     714901139                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles               225817309                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles              101657894                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                 2270                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles         20337                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                 420935290                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes              11687737                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples         1451892883                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.541647                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.159630                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                733526710     50.60%     50.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 55834579      3.85%     54.46% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                113825896      7.85%     62.31% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 72745123      5.02%     67.33% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 84690661      5.84%     73.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 54721422      3.78%     76.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 33849353      2.34%     79.28% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 34645380      2.39%     81.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                265701947     18.33%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                737052267     50.76%     50.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 55648987      3.83%     54.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                113021811      7.78%     62.38% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 71058557      4.89%     67.28% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 83474414      5.75%     73.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 55105836      3.80%     76.82% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 35245314      2.43%     79.25% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 35853884      2.47%     81.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                265431813     18.28%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1449541071                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.358533                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.787370                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                497288026                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              79567524                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 676485575                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              11475102                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles              184724844                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             81162192                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 16785                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             3548614330                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                 38542                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles              184724844                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                535414239                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                30600962                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         541148                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 648147088                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              50112790                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             3434293747                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                   117                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                4398993                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents              40741019                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents             1775                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands          3359442434                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups           16257634697                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups      15596931258                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups         660703439                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps            1993143706                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps               1366298728                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts              50062                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts          45371                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 137456980                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads           1058714008                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           577829073                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          31866160                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         36849262                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 3203795171                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded               52627                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                2727879490                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued          26513766                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined      1318072615                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined   3048733772                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved          30791                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples    1449541071                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.881892                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.914534                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total           1451892883                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.358240                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.788180                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                498609504                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              80967892                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 677644967                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              10558484                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles              184112036                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             82169847                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 15539                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             3562988403                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                 34450                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles              184112036                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                537763866                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                32181538                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         530906                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 647549947                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              49754590                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             3439334544                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                   240                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                4507727                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents              40704108                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents             1637                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands          3357877059                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups           16273276362                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups      15612337004                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups         660939358                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps            1993153074                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps               1364723985                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts              50374                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts          45755                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 138448530                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads           1057693537                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           579697033                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          32301976                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         40224751                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 3204253855                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               55204                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                2728539607                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued          26296633                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined      1318520975                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined   3049786617                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved          32197                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    1451892883                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.879298                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.913242                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           528205619     36.44%     36.44% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           200385301     13.82%     50.26% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           218048243     15.04%     65.31% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           179845166     12.41%     77.71% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4           155269867     10.71%     88.42% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5           101678601      7.01%     95.44% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            47766137      3.30%     98.73% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7            10944186      0.76%     99.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             7397951      0.51%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           529391229     36.46%     36.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           201881649     13.90%     50.37% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           217086646     14.95%     65.32% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           180698536     12.45%     77.76% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4           155303824     10.70%     88.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5           101627119      7.00%     95.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            47687061      3.28%     98.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7            10818751      0.75%     99.49% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             7398068      0.51%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      1449541071                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1451892883                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 1786371      1.87%      1.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                  23899      0.03%      1.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      1.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      1.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      1.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      1.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      1.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      1.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      1.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      1.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      1.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      1.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      1.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      1.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      1.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      1.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      1.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      1.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      1.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      1.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      1.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      1.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      1.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      1.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      1.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      1.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      1.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      1.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      1.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               56927453     59.70%     61.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite              36612005     38.40%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 1769730      1.85%      1.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                  23897      0.03%      1.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      1.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      1.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      1.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      1.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      1.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      1.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      1.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      1.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      1.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      1.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      1.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      1.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      1.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      1.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      1.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      1.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      1.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      1.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      1.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      1.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      1.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      1.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      1.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      1.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      1.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      1.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      1.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               57017691     59.74%     61.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite              36624161     38.38%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1265692730     46.40%     46.40% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult             11246210      0.41%     46.81% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     46.81% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   1      0.00%     46.81% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     46.81% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     46.81% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     46.81% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     46.81% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     46.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     46.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     46.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     46.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     46.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     46.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     46.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     46.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     46.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     46.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     46.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     46.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd         1375289      0.05%     46.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     46.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp         6876504      0.25%     47.11% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt         5503517      0.20%     47.31% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv              65      0.00%     47.31% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc       23431459      0.86%     48.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     48.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     48.17% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     48.17% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            901624360     33.05%     81.23% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           512129355     18.77%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1267852875     46.47%     46.47% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult             11249841      0.41%     46.88% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     46.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   1      0.00%     46.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     46.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     46.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     46.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     46.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     46.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     46.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     46.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     46.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     46.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     46.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     46.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     46.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     46.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     46.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     46.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     46.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd         1375289      0.05%     46.93% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     46.93% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp         6876502      0.25%     47.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt         5509242      0.20%     47.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv              10      0.00%     47.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc       23422716      0.86%     48.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     48.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     48.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     48.24% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            900241539     32.99%     81.23% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           512011592     18.77%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             2727879490                       # Type of FU issued
-system.cpu.iq.rate                           1.856319                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    95349728                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.034954                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         6892702222                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        4416661768                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   2501406306                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads           134461323                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes          105324073                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses     59997583                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             2754068673                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                69160545                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         71273395                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             2728539607                       # Type of FU issued
+system.cpu.iq.rate                           1.854981                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    95435479                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.034977                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         6896111029                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        4417455828                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   2500265065                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads           134593180                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes          105438972                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses     60061785                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             2754719800                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                69255286                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         70868561                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    427326375                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses       261567                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation      1134338                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores    300833324                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads    426304733                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       264948                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation      1116073                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores    302700113                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            2                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked            15                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked            13                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles              184724844                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                16014821                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               1979639                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          3203920541                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts           4008843                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts            1058714008                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            577829073                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts              42582                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                1976809                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                   591                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents        1134338                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect       37198169                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      9007131                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             46205300                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            2628771663                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             847609803                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          99107827                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles              184112036                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                17217570                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               2222077                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          3204383976                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           3801477                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts            1057693537                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            579697033                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts              44065                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                2220604                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                   655                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents        1116073                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect       37419443                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      9018722                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             46438165                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            2627591050                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             846492275                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts         100948557                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                         72743                       # number of nop insts executed
-system.cpu.iew.exec_refs                   1330077082                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                361648549                       # Number of branches executed
-system.cpu.iew.exec_stores                  482467279                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.788876                       # Inst execution rate
-system.cpu.iew.wb_sent                     2589616129                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    2561403889                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1477403496                       # num instructions producing a value
-system.cpu.iew.wb_consumers                2764851406                       # num instructions consuming a value
+system.cpu.iew.exec_nop                         74917                       # number of nop insts executed
+system.cpu.iew.exec_refs                   1329282286                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                361424797                       # Number of branches executed
+system.cpu.iew.exec_stores                  482790011                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.786352                       # Inst execution rate
+system.cpu.iew.wb_sent                     2588656133                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    2560326850                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1477151291                       # num instructions producing a value
+system.cpu.iew.wb_consumers                2761912490                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.743033                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.534352                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.740623                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.534829                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts     1384383866                       # The number of committed instructions
-system.cpu.commit.commitCommittedOps       1885338618                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts      1318582287                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls           21836                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts          41567877                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples   1264816229                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.490603                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.207767                       # Number of insts commited each cycle
+system.cpu.commit.commitCommittedInsts     1384389721                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps       1885344473                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts      1319039983                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls           23007                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts          41626374                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   1267780849                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.487122                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.205349                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    584481462     46.21%     46.21% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    317753060     25.12%     71.33% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2    101743247      8.04%     79.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     79200545      6.26%     85.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     52876697      4.18%     89.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     23864362      1.89%     91.71% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     17162643      1.36%     93.06% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      9180731      0.73%     93.79% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     78553482      6.21%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    586908423     46.29%     46.29% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    318188211     25.10%     71.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2    101915381      8.04%     79.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     79184752      6.25%     85.68% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     52930899      4.18%     89.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     24002778      1.89%     91.75% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     17056118      1.35%     93.09% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      9057246      0.71%     93.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     78537041      6.19%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   1264816229                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts           1384383866                       # Number of instructions committed
-system.cpu.commit.committedOps             1885338618                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total   1267780849                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts           1384389721                       # Number of instructions committed
+system.cpu.commit.committedOps             1885344473                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                      908383382                       # Number of memory references committed
-system.cpu.commit.loads                     631387633                       # Number of loads committed
+system.cpu.commit.refs                      908385724                       # Number of memory references committed
+system.cpu.commit.loads                     631388804                       # Number of loads committed
 system.cpu.commit.membars                        9986                       # Number of memory barriers committed
-system.cpu.commit.branches                  291348996                       # Number of branches committed
+system.cpu.commit.branches                  291350167                       # Number of branches committed
 system.cpu.commit.fp_insts                   52289415                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                1653700675                       # Number of committed integer instructions.
+system.cpu.commit.int_insts                1653705359                       # Number of committed integer instructions.
 system.cpu.commit.function_calls             41577833                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events              78553482                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events              78537041                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   4390165307                       # The number of ROB reads
-system.cpu.rob.rob_writes                  6592584661                       # The number of ROB writes
-system.cpu.timesIdled                         1305443                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        19968977                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                  1384372850                       # Number of Instructions Simulated
-system.cpu.committedOps                    1885327602                       # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total            1384372850                       # Number of Instructions Simulated
-system.cpu.cpi                               1.061499                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.061499                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.942064                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.942064                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads              12961850201                       # number of integer regfile reads
-system.cpu.int_regfile_writes              2434855102                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                  71417921                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                 51448336                       # number of floating regfile writes
-system.cpu.misc_regfile_reads              4106986212                       # number of misc regfile reads
-system.cpu.misc_regfile_writes               13773806                       # number of misc regfile writes
-system.cpu.icache.replacements                  25589                       # number of replacements
-system.cpu.icache.tagsinuse               1654.450414                       # Cycle average of tags in use
-system.cpu.icache.total_refs                419572856                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                  27281                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs               15379.672886                       # Average number of references to valid blocks.
+system.cpu.rob.rob_reads                   4393609919                       # The number of ROB reads
+system.cpu.rob.rob_writes                  6592898385                       # The number of ROB writes
+system.cpu.timesIdled                         1319009                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        19033003                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                  1384378705                       # Number of Instructions Simulated
+system.cpu.committedOps                    1885333457                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total            1384378705                       # Number of Instructions Simulated
+system.cpu.cpi                               1.062517                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.062517                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.941161                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.941161                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads              12954963873                       # number of integer regfile reads
+system.cpu.int_regfile_writes              2433899431                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                  71453474                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                 51512029                       # number of floating regfile writes
+system.cpu.misc_regfile_reads              4110345957                       # number of misc regfile reads
+system.cpu.misc_regfile_writes               13776148                       # number of misc regfile writes
+system.cpu.icache.replacements                  27727                       # number of replacements
+system.cpu.icache.tagsinuse               1657.357291                       # Cycle average of tags in use
+system.cpu.icache.total_refs                420895339                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                  29422                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               14305.463225                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst    1654.450414                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.807837                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.807837                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst    419577538                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       419577538                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     419577538                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        419577538                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    419577538                       # number of overall hits
-system.cpu.icache.overall_hits::total       419577538                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        33149                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         33149                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        33149                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          33149                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        33149                       # number of overall misses
-system.cpu.icache.overall_misses::total         33149                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    298308500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    298308500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    298308500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    298308500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    298308500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    298308500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    419610687                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    419610687                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    419610687                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    419610687                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    419610687                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    419610687                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000079                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000079                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000079                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000079                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000079                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000079                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  8999.019578                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total  8999.019578                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst  8999.019578                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total  8999.019578                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst  8999.019578                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total  8999.019578                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst    1657.357291                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.809256                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.809256                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst    420900012                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       420900012                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     420900012                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        420900012                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    420900012                       # number of overall hits
+system.cpu.icache.overall_hits::total       420900012                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        35278                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         35278                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        35278                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          35278                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        35278                       # number of overall misses
+system.cpu.icache.overall_misses::total         35278                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    347510000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    347510000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    347510000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    347510000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    347510000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    347510000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    420935290                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    420935290                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    420935290                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    420935290                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    420935290                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    420935290                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000084                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000084                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000084                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000084                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000084                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000084                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  9850.615114                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total  9850.615114                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst  9850.615114                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total  9850.615114                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst  9850.615114                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total  9850.615114                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -401,254 +401,254 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          781                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          781                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          781                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          781                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          781                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          781                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        32368                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        32368                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        32368                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        32368                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        32368                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        32368                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    180567000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    180567000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    180567000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    180567000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    180567000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    180567000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000077                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000077                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000077                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000077                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000077                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000077                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  5578.565250                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  5578.565250                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  5578.565250                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total  5578.565250                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  5578.565250                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total  5578.565250                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          933                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          933                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          933                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          933                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          933                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          933                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        34345                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        34345                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        34345                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        34345                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        34345                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        34345                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    217293500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    217293500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    217293500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    217293500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    217293500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    217293500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000082                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000082                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000082                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000082                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000082                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000082                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  6326.787014                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  6326.787014                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  6326.787014                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total  6326.787014                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  6326.787014                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total  6326.787014                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                1532821                       # number of replacements
-system.cpu.dcache.tagsinuse               4094.970368                       # Cycle average of tags in use
-system.cpu.dcache.total_refs               1034449788                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                1536917                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                 673.068089                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              277219000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4094.970368                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.999749                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.999749                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data    758296274                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       758296274                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    276114755                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      276114755                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data        10674                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total        10674                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data        10437                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total        10437                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data    1034411029                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total       1034411029                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data   1034411029                       # number of overall hits
-system.cpu.dcache.overall_hits::total      1034411029                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      2832781                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       2832781                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       820923                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       820923                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data            3                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total            3                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      3653704                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3653704                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      3653704                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3653704                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  91513466000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  91513466000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  28577501500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  28577501500                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       115500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total       115500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 120090967500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 120090967500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 120090967500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 120090967500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    761129055                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    761129055                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.replacements                1532802                       # number of replacements
+system.cpu.dcache.tagsinuse               4094.906416                       # Cycle average of tags in use
+system.cpu.dcache.total_refs               1033702432                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                1536898                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 672.590134                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              306710000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4094.906416                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.999733                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.999733                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data    757546654                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       757546654                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    276115180                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      276115180                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data        11970                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total        11970                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data        11608                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total        11608                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data    1033661834                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total       1033661834                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data   1033661834                       # number of overall hits
+system.cpu.dcache.overall_hits::total      1033661834                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      2867388                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       2867388                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       820498                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       820498                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data            6                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total            6                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data      3687886                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3687886                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      3687886                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3687886                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  99520769500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  99520769500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  33963338500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  33963338500                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       216500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total       216500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 133484108000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 133484108000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 133484108000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 133484108000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    760414042                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    760414042                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    276935678                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    276935678                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data        10677                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total        10677                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data        10437                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total        10437                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data   1038064733                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total   1038064733                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data   1038064733                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total   1038064733                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.003722                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.003722                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.002964                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.002964                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000281                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000281                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.003520                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.003520                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.003520                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.003520                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32305.167960                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 32305.167960                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34811.427503                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 34811.427503                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        38500                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        38500                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 32868.280381                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 32868.280381                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 32868.280381                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 32868.280381                       # average overall miss latency
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data        11976                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total        11976                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data        11608                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total        11608                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data   1037349720                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total   1037349720                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data   1037349720                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total   1037349720                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.003771                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.003771                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.002963                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.002963                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000501                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000501                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.003555                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.003555                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.003555                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.003555                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34707.814045                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 34707.814045                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41393.566468                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 41393.566468                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 36083.333333                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 36083.333333                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 36195.291286                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 36195.291286                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 36195.291286                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 36195.291286                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets        62000                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets        58500                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               4                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               3                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets        15500                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets        19500                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       108625                       # number of writebacks
-system.cpu.dcache.writebacks::total            108625                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      1368436                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      1368436                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       743264                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       743264                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            3                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total            3                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      2111700                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      2111700                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      2111700                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      2111700                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1464345                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1464345                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data        77659                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total        77659                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1542004                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1542004                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1542004                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1542004                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  49970798500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  49970798500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2507122500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   2507122500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  52477921000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  52477921000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  52477921000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  52477921000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.001924                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.001924                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.writebacks::writebacks       108638                       # number of writebacks
+system.cpu.dcache.writebacks::total            108638                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      1403027                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      1403027                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       743038                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       743038                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            6                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total            6                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      2146065                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      2146065                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      2146065                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      2146065                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1464361                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1464361                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data        77460                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total        77460                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1541821                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1541821                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1541821                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1541821                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  50337065001                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  50337065001                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2525124500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   2525124500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  52862189501                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  52862189501                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  52862189501                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  52862189501                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.001926                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.001926                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000280                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000280                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.001485                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.001485                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.001485                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.001485                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34125.017329                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34125.017329                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32283.734017                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32283.734017                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34032.285908                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 34032.285908                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34032.285908                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 34032.285908                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.001486                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.001486                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.001486                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.001486                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34374.764830                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34374.764830                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32599.076943                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32599.076943                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34285.555522                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 34285.555522                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34285.555522                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 34285.555522                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.replacements               1480163                       # number of replacements
-system.cpu.l2cache.tagsinuse             32703.911790                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                   86402                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs               1512907                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  0.057110                       # Average number of references to valid blocks.
+system.cpu.l2cache.replacements               1480261                       # number of replacements
+system.cpu.l2cache.tagsinuse             32698.232813                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                   88469                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs               1513005                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.058472                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks  3110.119974                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst     59.486457                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data  29534.305360                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.094913                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst     0.001815                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.901315                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.998044                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst        24063                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data        53671                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total          77734                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       108625                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       108625                       # number of Writeback hits
+system.cpu.l2cache.occ_blocks::writebacks  3127.449947                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst     61.048059                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data  29509.734807                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.095442                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.001863                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.900566                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.997871                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst        26144                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data        53654                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total          79798                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       108638                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       108638                       # number of Writeback hits
 system.cpu.l2cache.UpgradeReq_hits::cpu.data            3                       # number of UpgradeReq hits
 system.cpu.l2cache.UpgradeReq_hits::total            3                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data         6493                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total         6493                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        24063                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data        60164                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total           84227                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst        24063                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data        60164                       # number of overall hits
-system.cpu.l2cache.overall_hits::total          84227                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         3219                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data      1410673                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total      1413892                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data         5084                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total         5084                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data        66080                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total        66080                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         3219                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data      1476753                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total       1479972                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         3219                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data      1476753                       # number of overall misses
-system.cpu.l2cache.overall_misses::total      1479972                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    110372500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data  48394540000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total  48504912500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   2252380000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   2252380000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    110372500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  50646920000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  50757292500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    110372500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  50646920000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  50757292500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst        27282                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      1464344                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      1491626                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       108625                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       108625                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data         5087                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total         5087                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data        72573                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total        72573                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        27282                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      1536917                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      1564199                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        27282                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      1536917                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      1564199                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.117990                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.963348                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.947886                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.999410                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.999410                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.910531                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.910531                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.117990                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.960854                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.946153                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.117990                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.960854                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.946153                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34287.822305                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34305.994373                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 34305.953001                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34085.653753                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34085.653753                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34287.822305                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34296.134831                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 34296.116751                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34287.822305                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34296.134831                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 34296.116751                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_hits::cpu.data         6457                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total         6457                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst        26144                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data        60111                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total           86255                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst        26144                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data        60111                       # number of overall hits
+system.cpu.l2cache.overall_hits::total          86255                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         3279                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data      1410706                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total      1413985                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data         4920                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total         4920                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data        66081                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total        66081                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         3279                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data      1476787                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total       1480066                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         3279                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data      1476787                       # number of overall misses
+system.cpu.l2cache.overall_misses::total      1480066                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    116051500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data  48793887000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total  48909938500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   2274851500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   2274851500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    116051500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  51068738500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  51184790000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    116051500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  51068738500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  51184790000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst        29423                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      1464360                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      1493783                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       108638                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       108638                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data         4923                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total         4923                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data        72538                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total        72538                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        29423                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      1536898                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      1566321                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        29423                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      1536898                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      1566321                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.111443                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.963360                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.946580                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.999391                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.999391                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.910985                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.910985                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.111443                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.960888                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.944931                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.111443                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.960888                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.944931                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35392.345227                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34588.274949                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 34590.139570                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34425.197863                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34425.197863                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35392.345227                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34580.977826                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 34582.775363                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35392.345227                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34580.977826                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 34582.775363                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -657,69 +657,69 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        66099                       # number of writebacks
-system.cpu.l2cache.writebacks::total            66099                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            4                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           20                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total           24                       # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst            4                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data           20                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           24                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst            4                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data           20                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           24                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3215                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data      1410653                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total      1413868                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         5084                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total         5084                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66080                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total        66080                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3215                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data      1476733                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total      1479948                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3215                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data      1476733                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total      1479948                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     99910500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  43827558000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  43927468500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    157604000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    157604000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   2048533500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   2048533500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     99910500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  45876091500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  45976002000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     99910500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  45876091500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  45976002000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.117843                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.963334                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.947870                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.999410                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.999410                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.910531                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.910531                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.117843                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.960841                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.946138                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.117843                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.960841                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.946138                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31076.360809                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31068.985782                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31069.002552                       # average ReadReq mshr miss latency
+system.cpu.l2cache.writebacks::writebacks        66098                       # number of writebacks
+system.cpu.l2cache.writebacks::total            66098                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           11                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           19                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total           30                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst           11                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data           19                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           30                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst           11                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data           19                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total           30                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3268                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data      1410687                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total      1413955                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         4920                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total         4920                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66081                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        66081                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3268                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data      1476768                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total      1480036                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3268                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data      1476768                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total      1480036                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    105473000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  44226810500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  44332283500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    152520000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    152520000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   2049208000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   2049208000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    105473000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  46276018500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  46381491500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    105473000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  46276018500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  46381491500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.111070                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.963347                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.946560                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.999391                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.999391                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.910985                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.910985                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.111070                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.960876                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.944912                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.111070                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.960876                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.944912                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32274.479804                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31351.256870                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31353.390667                       # average ReadReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        31000                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        31000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.809625                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31000.809625                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31076.360809                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31065.935074                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31065.957723                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31076.360809                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31065.935074                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31065.957723                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31010.547661                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31010.547661                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32274.479804                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31336.011141                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31338.083330                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32274.479804                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31336.011141                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31338.083330                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini
index a14c026cf..350b3e880 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini
@@ -166,7 +166,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
@@ -198,7 +198,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout
index e82eb191d..2b2490099 100755
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:10:14
-gem5 started Jun 29 2012 01:12:18
+gem5 compiled Jul  2 2012 09:08:16
+gem5 started Jul  2 2012 16:24:15
 gem5 executing on zizzer
 command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
@@ -1385,4 +1385,4 @@ info: Increasing stack size by one page.
 2000: 760651391
 1000: 4031656975
 0: 2206428413
-Exiting @ tick 2369826854000 because target called exit()
+Exiting @ tick 2369931974000 because target called exit()
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
index a105f9616..8787dc4d5 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.369827                       # Number of seconds simulated
-sim_ticks                                2369826854000                       # Number of ticks simulated
-final_tick                               2369826854000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.369932                       # Number of seconds simulated
+sim_ticks                                2369931974000                       # Number of ticks simulated
+final_tick                               2369931974000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1185646                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1608413                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2033704433                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 241756                       # Number of bytes of host memory used
-host_seconds                                  1165.28                       # Real time elapsed on the host
+host_inst_rate                                1141587                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1548644                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1958218374                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 241676                       # Number of bytes of host memory used
+host_seconds                                  1210.25                       # Real time elapsed on the host
 sim_insts                                  1381604339                       # Number of instructions simulated
 sim_ops                                    1874244941                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst            144448                       # Number of bytes read from this memory
@@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data            1475585                       # Nu
 system.physmem.num_reads::total               1477842                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks           66099                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                66099                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                60953                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             39849932                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                39910885                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           60953                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              60953                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1785082                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1785082                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1785082                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               60953                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            39849932                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               41695968                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst                60950                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             39848165                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                39909115                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           60950                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              60950                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1785003                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1785003                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1785003                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               60950                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            39848165                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               41694118                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -77,7 +77,7 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                 1411                       # Number of system calls
-system.cpu.numCycles                       4739653708                       # number of cpu cycles simulated
+system.cpu.numCycles                       4739863948                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                  1381604339                       # Number of instructions committed
@@ -96,18 +96,18 @@ system.cpu.num_mem_refs                     908382479                       # nu
 system.cpu.num_load_insts                   631387181                       # Number of load instructions
 system.cpu.num_store_insts                  276995298                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                 4739653708                       # Number of busy cycles
+system.cpu.num_busy_cycles                 4739863948                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                  18364                       # number of replacements
-system.cpu.icache.tagsinuse               1392.324421                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse               1392.322496                       # Cycle average of tags in use
 system.cpu.icache.total_refs               1390251699                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                  19803                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               70204.095289                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst    1392.324421                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.679846                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.679846                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst    1392.322496                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.679845                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.679845                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst   1390251699                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total      1390251699                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst    1390251699                       # number of demand (read+write) hits
@@ -120,12 +120,12 @@ system.cpu.icache.demand_misses::cpu.inst        19803                       # n
 system.cpu.icache.demand_misses::total          19803                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst        19803                       # number of overall misses
 system.cpu.icache.overall_misses::total         19803                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    372036000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    372036000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    372036000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    372036000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    372036000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    372036000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    372133000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    372133000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    372133000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    372133000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    372133000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    372133000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst   1390271502                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total   1390271502                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst   1390271502                       # number of demand (read+write) accesses
@@ -138,12 +138,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000014
 system.cpu.icache.demand_miss_rate::total     0.000014                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000014                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000014                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18786.850477                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 18786.850477                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 18786.850477                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 18786.850477                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 18786.850477                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 18786.850477                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18791.748725                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 18791.748725                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 18791.748725                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 18791.748725                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 18791.748725                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 18791.748725                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -158,34 +158,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst        19803
 system.cpu.icache.demand_mshr_misses::total        19803                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst        19803                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total        19803                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    312627000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    312627000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    312627000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    312627000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    312627000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    312627000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    312724000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    312724000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    312724000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    312724000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    312724000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    312724000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000014                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000014                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000014                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000014                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000014                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000014                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15786.850477                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15786.850477                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15786.850477                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 15786.850477                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15786.850477                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 15786.850477                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15791.748725                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15791.748725                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15791.748725                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 15791.748725                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15791.748725                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 15791.748725                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                1529557                       # number of replacements
-system.cpu.dcache.tagsinuse               4094.960317                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               4094.950469                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                895757408                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                1533653                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                 584.067848                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              997872000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4094.960317                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.999746                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.999746                       # Average percentage of cache occupancy
+system.cpu.dcache.warmup_cycle             1004561000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4094.950469                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.999744                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.999744                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data    618874540                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total       618874540                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data    276862898                       # number of WriteReq hits
@@ -206,14 +206,14 @@ system.cpu.dcache.demand_misses::cpu.data      1533653                       # n
 system.cpu.dcache.demand_misses::total        1533653                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data      1533653                       # number of overall misses
 system.cpu.dcache.overall_misses::total       1533653                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  79650886000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  79650886000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   3794826000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   3794826000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  83445712000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  83445712000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  83445712000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  83445712000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  79650958000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  79650958000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   3794840000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   3794840000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  83445798000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  83445798000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  83445798000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  83445798000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data    620335413                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total    620335413                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    276935678                       # number of WriteReq accesses(hits+misses)
@@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.001709
 system.cpu.dcache.demand_miss_rate::total     0.001709                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.001709                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.001709                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54522.799723                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 54522.799723                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52141.055235                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 52141.055235                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 54409.773267                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 54409.773267                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 54409.773267                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 54409.773267                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54522.849009                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 54522.849009                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52141.247595                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 52141.247595                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 54409.829342                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 54409.829342                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 54409.829342                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 54409.829342                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data      1533653
 system.cpu.dcache.demand_mshr_misses::total      1533653                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data      1533653                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total      1533653                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  75268267000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  75268267000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   3576486000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   3576486000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  78844753000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  78844753000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  78844753000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  78844753000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  75268339000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  75268339000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   3576500000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   3576500000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  78844839000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  78844839000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  78844839000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  78844839000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002355                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002355                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000263                       # mshr miss rate for WriteReq accesses
@@ -276,28 +276,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.001709
 system.cpu.dcache.demand_mshr_miss_rate::total     0.001709                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.001709                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.001709                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51522.799723                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51522.799723                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49141.055235                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49141.055235                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51409.773267                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 51409.773267                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51409.773267                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 51409.773267                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51522.849009                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51522.849009                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49141.247595                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49141.247595                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51409.829342                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 51409.829342                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51409.829342                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 51409.829342                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements               1478696                       # number of replacements
-system.cpu.l2cache.tagsinuse             32689.777876                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse             32689.689328                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                   77413                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs               1511439                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.051218                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks  3194.588699                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst     32.929350                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data  29462.259827                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::writebacks  3194.581985                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst     32.931287                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data  29462.176056                       # Average occupied blocks per requestor
 system.cpu.l2cache.occ_percent::writebacks     0.097491                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.inst     0.001005                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.899117                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.997613                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.899114                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.997610                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst        17546                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data        51381                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total          68927                       # number of ReadReq hits
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
index ef879d8e7..fc9577d62 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
@@ -181,7 +181,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
@@ -213,7 +213,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout
index 23e06e448..e501186a7 100755
--- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout
@@ -1,11 +1,11 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:05:18
-gem5 started Jun 28 2012 22:15:35
+gem5 compiled Jul  2 2012 08:30:56
+gem5 started Jul  2 2012 09:54:39
 gem5 executing on zizzer
 command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
-Exiting @ tick 47017029500 because target called exit()
+Exiting @ tick 47910283500 because target called exit()
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
index 0041bdcc8..52b1e9eb7 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
@@ -1,59 +1,59 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.047017                       # Number of seconds simulated
-sim_ticks                                 47017029500                       # Number of ticks simulated
-final_tick                                47017029500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.047910                       # Number of seconds simulated
+sim_ticks                                 47910283500                       # Number of ticks simulated
+final_tick                                47910283500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 156470                       # Simulator instruction rate (inst/s)
-host_op_rate                                   156470                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               83276889                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 227180                       # Number of bytes of host memory used
-host_seconds                                   564.59                       # Real time elapsed on the host
+host_inst_rate                                 137428                       # Simulator instruction rate (inst/s)
+host_op_rate                                   137428                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               74532010                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 227148                       # Number of bytes of host memory used
+host_seconds                                   642.82                       # Real time elapsed on the host
 sim_insts                                    88340673                       # Number of instructions simulated
 sim_ops                                      88340673                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst            515072                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          10272768                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             10787840                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       515072                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          515072                       # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu.inst            515328                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          10272960                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             10788288                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       515328                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          515328                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::writebacks      7422400                       # Number of bytes written to this memory
 system.physmem.bytes_written::total           7422400                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               8048                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             160512                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                168560                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst               8052                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             160515                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                168567                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks          115975                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total               115975                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst             10955009                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            218490366                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               229445376                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst        10955009                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total           10955009                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks         157866205                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              157866205                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks         157866205                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst            10955009                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           218490366                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              387311580                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst             10756104                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            214420773                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               225176877                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst        10756104                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total           10756104                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks         154922899                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              154922899                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks         154922899                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst            10756104                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           214420773                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              380099775                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     20277221                       # DTB read hits
+system.cpu.dtb.read_hits                     20277225                       # DTB read hits
 system.cpu.dtb.read_misses                      90148                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                 20367369                       # DTB read accesses
-system.cpu.dtb.write_hits                    14736814                       # DTB write hits
+system.cpu.dtb.read_accesses                 20367373                       # DTB read accesses
+system.cpu.dtb.write_hits                    14736863                       # DTB write hits
 system.cpu.dtb.write_misses                      7252                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                14744066                       # DTB write accesses
-system.cpu.dtb.data_hits                     35014035                       # DTB hits
+system.cpu.dtb.write_accesses                14744115                       # DTB write accesses
+system.cpu.dtb.data_hits                     35014088                       # DTB hits
 system.cpu.dtb.data_misses                      97400                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                 35111435                       # DTB accesses
-system.cpu.itb.fetch_hits                    12478267                       # ITB hits
-system.cpu.itb.fetch_misses                     13087                       # ITB misses
+system.cpu.dtb.data_accesses                 35111488                       # DTB accesses
+system.cpu.itb.fetch_hits                    12475946                       # ITB hits
+system.cpu.itb.fetch_misses                     12952                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                12491354                       # ITB accesses
+system.cpu.itb.fetch_accesses                12488898                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -67,42 +67,42 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                 4583                       # Number of system calls
-system.cpu.numCycles                         94034060                       # number of cpu cycles simulated
+system.cpu.numCycles                         95820568                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.branch_predictor.lookups          18830633                       # Number of BP lookups
-system.cpu.branch_predictor.condPredicted     12442208                       # Number of conditional branches predicted
-system.cpu.branch_predictor.condIncorrect      5026177                       # Number of conditional branches incorrect
-system.cpu.branch_predictor.BTBLookups       16228748                       # Number of BTB lookups
-system.cpu.branch_predictor.BTBHits           5052031                       # Number of BTB hits
-system.cpu.branch_predictor.usedRAS           1660951                       # Number of times the RAS was used to get a target.
+system.cpu.branch_predictor.lookups          18829757                       # Number of BP lookups
+system.cpu.branch_predictor.condPredicted     12442338                       # Number of conditional branches predicted
+system.cpu.branch_predictor.condIncorrect      5025331                       # Number of conditional branches incorrect
+system.cpu.branch_predictor.BTBLookups       16200752                       # Number of BTB lookups
+system.cpu.branch_predictor.BTBHits           5042995                       # Number of BTB hits
+system.cpu.branch_predictor.usedRAS           1660949                       # Number of times the RAS was used to get a target.
 system.cpu.branch_predictor.RASInCorrect         1029                       # Number of incorrect RAS predictions.
-system.cpu.branch_predictor.BTBHitPct       31.130134                       # BTB Hit Percentage
-system.cpu.branch_predictor.predictedTaken      8480322                       # Number of Branches Predicted As Taken (True).
-system.cpu.branch_predictor.predictedNotTaken     10350311                       # Number of Branches Predicted As Not Taken (False).
-system.cpu.regfile_manager.intRegFileReads     74324480                       # Number of Reads from Int. Register File
+system.cpu.branch_predictor.BTBHitPct       31.128154                       # BTB Hit Percentage
+system.cpu.branch_predictor.predictedTaken      8471214                       # Number of Branches Predicted As Taken (True).
+system.cpu.branch_predictor.predictedNotTaken     10358543                       # Number of Branches Predicted As Not Taken (False).
+system.cpu.regfile_manager.intRegFileReads     74332888                       # Number of Reads from Int. Register File
 system.cpu.regfile_manager.intRegFileWrites     52319250                       # Number of Writes to Int. Register File
-system.cpu.regfile_manager.intRegFileAccesses    126643730                       # Total Accesses (Read+Write) to the Int. Register File
-system.cpu.regfile_manager.floatRegFileReads        65335                       # Number of Reads from FP Register File
+system.cpu.regfile_manager.intRegFileAccesses    126652138                       # Total Accesses (Read+Write) to the Int. Register File
+system.cpu.regfile_manager.floatRegFileReads        65238                       # Number of Reads from FP Register File
 system.cpu.regfile_manager.floatRegFileWrites       227630                       # Number of Writes to FP Register File
-system.cpu.regfile_manager.floatRegFileAccesses       292965                       # Total Accesses (Read+Write) to the FP Register File
-system.cpu.regfile_manager.regForwards       14127744                       # Number of Registers Read Through Forwarding Logic
-system.cpu.agen_unit.agens                   35064158                       # Number of Address Generations
-system.cpu.execution_unit.predictedTakenIncorrect      4682153                       # Number of Branches Incorrectly Predicted As Taken.
-system.cpu.execution_unit.predictedNotTakenIncorrect       233524                       # Number of Branches Incorrectly Predicted As Not Taken).
-system.cpu.execution_unit.mispredicted        4915677                       # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.predicted           8856497                       # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.mispredictPct     35.692818                       # Percentage of Incorrect Branches Predicts
-system.cpu.execution_unit.executions         44775466                       # Number of Instructions Executed.
+system.cpu.regfile_manager.floatRegFileAccesses       292868                       # Total Accesses (Read+Write) to the FP Register File
+system.cpu.regfile_manager.regForwards       14120784                       # Number of Registers Read Through Forwarding Logic
+system.cpu.agen_unit.agens                   35064786                       # Number of Address Generations
+system.cpu.execution_unit.predictedTakenIncorrect      4680831                       # Number of Branches Incorrectly Predicted As Taken.
+system.cpu.execution_unit.predictedNotTakenIncorrect       234000                       # Number of Branches Incorrectly Predicted As Not Taken).
+system.cpu.execution_unit.mispredicted        4914831                       # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.predicted           8857404                       # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.mispredictPct     35.686517                       # Percentage of Incorrect Branches Predicts
+system.cpu.execution_unit.executions         44775821                       # Number of Instructions Executed.
 system.cpu.mult_div_unit.multiplies             41107                       # Number of Multipy Operations Executed
 system.cpu.mult_div_unit.divides                    0                       # Number of Divide Operations Executed
 system.cpu.contextSwitches                          1                       # Number of context switches
-system.cpu.threadCycles                      78068863                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles                      78582823                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
 system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled                          305152                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        23747130                       # Number of cycles cpu's stages were not processed
-system.cpu.runCycles                         70286930                       # Number of cycles cpu stages are processed.
-system.cpu.activity                         74.746246                       # Percentage of cycles cpu is active
+system.cpu.timesIdled                          467369                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        25529650                       # Number of cycles cpu's stages were not processed
+system.cpu.runCycles                         70290918                       # Number of cycles cpu stages are processed.
+system.cpu.activity                         73.356816                       # Percentage of cycles cpu is active
 system.cpu.comLoads                          20276638                       # Number of Load instructions committed
 system.cpu.comStores                         14613377                       # Number of Store instructions committed
 system.cpu.comBranches                       13754477                       # Number of Branches instructions committed
@@ -114,144 +114,144 @@ system.cpu.committedInsts                    88340673                       # Nu
 system.cpu.committedOps                      88340673                       # Number of Ops committed (Per-Thread)
 system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
 system.cpu.committedInsts_total              88340673                       # Number of Instructions committed (Total)
-system.cpu.cpi                               1.064448                       # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi                               1.084671                       # CPI: Cycles Per Instruction (Per-Thread)
 system.cpu.smt_cpi                                nan                       # CPI: Total SMT-CPI
-system.cpu.cpi_total                         1.064448                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.939454                       # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.cpi_total                         1.084671                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.921939                       # IPC: Instructions Per Cycle (Per-Thread)
 system.cpu.smt_ipc                                nan                       # IPC: Total SMT-IPC
-system.cpu.ipc_total                         0.939454                       # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles                 40602486                       # Number of cycles 0 instructions are processed.
-system.cpu.stage0.runCycles                  53431574                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization               56.821511                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles                 51377982                       # Number of cycles 0 instructions are processed.
-system.cpu.stage1.runCycles                  42656078                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization               45.362370                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles                 50907944                       # Number of cycles 0 instructions are processed.
-system.cpu.stage2.runCycles                  43126116                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization               45.862229                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles                 71905105                       # Number of cycles 0 instructions are processed.
-system.cpu.stage3.runCycles                  22128955                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization               23.532915                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles                 47936936                       # Number of cycles 0 instructions are processed.
-system.cpu.stage4.runCycles                  46097124                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization               49.021731                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.icache.replacements                  85298                       # number of replacements
-system.cpu.icache.tagsinuse               1887.307132                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 12360070                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                  87344                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                 141.510235                       # Average number of references to valid blocks.
+system.cpu.ipc_total                         0.921939                       # IPC: Total IPC of All Threads
+system.cpu.stage0.idleCycles                 42393437                       # Number of cycles 0 instructions are processed.
+system.cpu.stage0.runCycles                  53427131                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.utilization               55.757477                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles                 53162471                       # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles                  42658097                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization               44.518727                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles                 52693934                       # Number of cycles 0 instructions are processed.
+system.cpu.stage2.runCycles                  43126634                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage2.utilization               45.007700                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles                 73699390                       # Number of cycles 0 instructions are processed.
+system.cpu.stage3.runCycles                  22121178                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage3.utilization               23.086043                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles                 49718373                       # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles                  46102195                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization               48.113047                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.icache.replacements                  85335                       # number of replacements
+system.cpu.icache.tagsinuse               1885.674809                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 12357256                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                  87381                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                 141.418111                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst    1887.307132                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.921537                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.921537                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst     12360070                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        12360070                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      12360070                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         12360070                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     12360070                       # number of overall hits
-system.cpu.icache.overall_hits::total        12360070                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       118149                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        118149                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       118149                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         118149                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       118149                       # number of overall misses
-system.cpu.icache.overall_misses::total        118149                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   2012242500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   2012242500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   2012242500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   2012242500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   2012242500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   2012242500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     12478219                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     12478219                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     12478219                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     12478219                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     12478219                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     12478219                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.009468                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.009468                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.009468                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.009468                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.009468                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.009468                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17031.396796                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 17031.396796                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 17031.396796                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 17031.396796                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 17031.396796                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 17031.396796                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst    1885.674809                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.920740                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.920740                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst     12357256                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        12357256                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      12357256                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         12357256                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     12357256                       # number of overall hits
+system.cpu.icache.overall_hits::total        12357256                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       118639                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        118639                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       118639                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         118639                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       118639                       # number of overall misses
+system.cpu.icache.overall_misses::total        118639                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   2081821000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   2081821000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   2081821000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   2081821000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   2081821000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   2081821000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     12475895                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     12475895                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     12475895                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     12475895                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     12475895                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     12475895                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.009509                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.009509                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.009509                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.009509                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.009509                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.009509                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17547.526530                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 17547.526530                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 17547.526530                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 17547.526530                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 17547.526530                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 17547.526530                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets      1223500                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets      1176500                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets             109                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets             105                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets 11224.770642                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets 11204.761905                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        30805                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        30805                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        30805                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        30805                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        30805                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        30805                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        87344                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        87344                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        87344                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        87344                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        87344                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        87344                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   1308493500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total   1308493500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst   1308493500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total   1308493500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst   1308493500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total   1308493500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.007000                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.007000                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.007000                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.007000                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.007000                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.007000                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14980.920269                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14980.920269                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14980.920269                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 14980.920269                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14980.920269                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 14980.920269                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        31258                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        31258                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        31258                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        31258                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        31258                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        31258                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        87381                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        87381                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        87381                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        87381                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        87381                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        87381                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   1364843500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total   1364843500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   1364843500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   1364843500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst   1364843500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total   1364843500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.007004                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.007004                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.007004                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.007004                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.007004                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.007004                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15619.453886                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15619.453886                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15619.453886                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 15619.453886                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15619.453886                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 15619.453886                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                 200251                       # number of replacements
-system.cpu.dcache.tagsinuse               4073.021699                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 34126085                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse               4073.238674                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 34125947                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                 204347                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                 167.000666                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              487962000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4073.021699                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.994390                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.994390                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data     20180546                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        20180546                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     13945539                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       13945539                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      34126085                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         34126085                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     34126085                       # number of overall hits
-system.cpu.dcache.overall_hits::total        34126085                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data        96092                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total         96092                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       667838                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       667838                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data       763930                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         763930                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       763930                       # number of overall misses
-system.cpu.dcache.overall_misses::total        763930                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   3967104000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   3967104000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  35310638000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  35310638000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  39277742000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  39277742000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  39277742000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  39277742000                       # number of overall miss cycles
+system.cpu.dcache.avg_refs                 166.999990                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              499859000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4073.238674                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.994443                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.994443                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     20180530                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        20180530                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     13945417                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       13945417                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      34125947                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         34125947                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     34125947                       # number of overall hits
+system.cpu.dcache.overall_hits::total        34125947                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data        96108                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total         96108                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       667960                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       667960                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data       764068                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         764068                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       764068                       # number of overall misses
+system.cpu.dcache.overall_misses::total        764068                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   4228645500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   4228645500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  42086848500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  42086848500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  46315494000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  46315494000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  46315494000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  46315494000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data     20276638                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total     20276638                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     14613377                       # number of WriteReq accesses(hits+misses)
@@ -260,40 +260,40 @@ system.cpu.dcache.demand_accesses::cpu.data     34890015                       #
 system.cpu.dcache.demand_accesses::total     34890015                       # number of demand (read+write) accesses
 system.cpu.dcache.overall_accesses::cpu.data     34890015                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total     34890015                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.004739                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.004739                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.045700                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.045700                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.021895                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.021895                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.021895                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.021895                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41284.435749                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 41284.435749                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52873.059035                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 52873.059035                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 51415.367900                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 51415.367900                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 51415.367900                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 51415.367900                       # average overall miss latency
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.004740                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.004740                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.045709                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.045709                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.021899                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.021899                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.021899                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.021899                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 43998.891872                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 43998.891872                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63008.037158                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 63008.037158                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 60616.979117                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 60616.979117                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 60616.979117                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 60616.979117                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets   6330819000                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets   6945858000                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets          124116                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets          124169                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 51007.275452                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 55938.744775                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       165812                       # number of writebacks
-system.cpu.dcache.writebacks::total            165812                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data        35325                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        35325                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       524258                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       524258                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       559583                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       559583                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       559583                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       559583                       # number of overall MSHR hits
+system.cpu.dcache.writebacks::writebacks       165805                       # number of writebacks
+system.cpu.dcache.writebacks::total            165805                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        35341                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        35341                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       524380                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       524380                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       559721                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       559721                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       559721                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       559721                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data        60767                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total        60767                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data       143580                       # number of WriteReq MSHR misses
@@ -302,14 +302,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data       204347
 system.cpu.dcache.demand_mshr_misses::total       204347                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data       204347                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total       204347                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   1914810500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   1914810500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   7237342000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   7237342000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data   9152152500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total   9152152500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data   9152152500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total   9152152500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   1936845000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   1936845000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   7868977000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   7868977000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   9805822000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   9805822000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data   9805822000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   9805822000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002997                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002997                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009825                       # mshr miss rate for WriteReq accesses
@@ -318,98 +318,98 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.005857
 system.cpu.dcache.demand_mshr_miss_rate::total     0.005857                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.005857                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.005857                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31510.696595                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31510.696595                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50406.337930                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50406.337930                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44787.310310                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 44787.310310                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44787.310310                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 44787.310310                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31873.302944                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31873.302944                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54805.523053                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54805.523053                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 47986.131433                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 47986.131433                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 47986.131433                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 47986.131433                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.replacements                136133                       # number of replacements
-system.cpu.l2cache.tagsinuse             28807.621629                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                  146477                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                166996                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  0.877129                       # Average number of references to valid blocks.
+system.cpu.l2cache.replacements                136141                       # number of replacements
+system.cpu.l2cache.tagsinuse             28773.047265                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                  146499                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                167004                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.877219                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 25341.359652                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst   1731.515405                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data   1734.746571                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.773357                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst     0.052842                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.052940                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.879139                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst        79296                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data        31113                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total         110409                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       165812                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       165812                       # number of Writeback hits
+system.cpu.l2cache.occ_blocks::writebacks 25287.688081                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst   1723.908362                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data   1761.450821                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.771719                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.052610                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.053755                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.878084                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst        79329                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data        31110                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         110439                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       165805                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       165805                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data        12722                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total        12722                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        79296                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data        43835                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          123131                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst        79296                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data        43835                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         123131                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         8048                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data        29464                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        37512                       # number of ReadReq misses
+system.cpu.l2cache.demand_hits::cpu.inst        79329                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data        43832                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          123161                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst        79329                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data        43832                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         123161                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         8052                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data        29467                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        37519                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data       131048                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total       131048                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         8048                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       160512                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        168560                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         8048                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       160512                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       168560                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    420766000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1537793000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total   1958559000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   6828933500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   6828933500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    420766000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data   8366726500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total   8787492500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    420766000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data   8366726500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total   8787492500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst        87344                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.demand_misses::cpu.inst         8052                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       160515                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        168567                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         8052                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       160515                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       168567                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    427362500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1541002500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   1968365000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   6838998500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   6838998500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    427362500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   8380001000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   8807363500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    427362500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   8380001000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   8807363500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst        87381                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data        60577                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total       147921                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       165812                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       165812                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       147958                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       165805                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       165805                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data       143770                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total       143770                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        87344                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst        87381                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data       204347                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       291691                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        87344                       # number of overall (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       291728                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        87381                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data       204347                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       291691                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.092141                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.486389                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.253595                       # miss rate for ReadReq accesses
+system.cpu.l2cache.overall_accesses::total       291728                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.092148                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.486439                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.253579                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.911511                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.911511                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.092141                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.785487                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.577872                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.092141                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.785487                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.577872                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52282.057654                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52192.268531                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 52211.532310                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52110.169556                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52110.169556                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52282.057654                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52125.239857                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52132.727219                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52282.057654                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52125.239857                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52132.727219                       # average overall miss latency
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.092148                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.785502                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.577822                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.092148                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.785502                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.577822                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53075.322901                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52295.873350                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 52463.152003                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52186.973475                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52186.973475                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53075.322901                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52206.965081                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 52248.444239                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53075.322901                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52206.965081                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 52248.444239                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -420,50 +420,50 @@ system.cpu.l2cache.fast_writes                      0                       # nu
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks       115975                       # number of writebacks
 system.cpu.l2cache.writebacks::total           115975                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         8048                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        29464                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        37512                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         8052                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        29467                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        37519                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       131048                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total       131048                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         8048                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       160512                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       168560                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         8048                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       160512                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       168560                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    322504500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1178813500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1501318000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   5243991500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   5243991500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    322504500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   6422805000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   6745309500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    322504500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   6422805000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   6745309500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.092141                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.486389                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.253595                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         8052                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       160515                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       168567                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         8052                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       160515                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       168567                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    329154000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1181438500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1510592500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   5254733000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   5254733000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    329154000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   6436171500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   6765325500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    329154000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   6436171500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   6765325500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.092148                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.486439                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.253579                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.911511                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.911511                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.092141                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.785487                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.577872                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.092141                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.785487                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.577872                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40072.626740                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40008.603720                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40022.339518                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40015.807185                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40015.807185                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40072.626740                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40014.484898                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40017.260916                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40072.626740                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40014.484898                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40017.260916                       # average overall mshr miss latency
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.092148                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.785502                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.577822                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.092148                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.785502                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.577822                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40878.539493                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40093.613194                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40262.067219                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40097.773335                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40097.773335                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40878.539493                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40097.009625                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40134.341241                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40878.539493                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40097.009625                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40134.341241                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini
index 6543d2325..0698ab8df 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini
@@ -479,7 +479,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
@@ -511,7 +511,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout
index 109541527..3d5324180 100755
--- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout
@@ -1,11 +1,11 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:05:18
-gem5 started Jun 28 2012 22:20:14
+gem5 compiled Jul  2 2012 08:30:56
+gem5 started Jul  2 2012 10:05:33
 gem5 executing on zizzer
 command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
-Exiting @ tick 21029927000 because target called exit()
+Exiting @ tick 21619648000 because target called exit()
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
index 3719775b2..6999de96c 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,59 +1,59 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.021030                       # Number of seconds simulated
-sim_ticks                                 21029927000                       # Number of ticks simulated
-final_tick                                21029927000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.021620                       # Number of seconds simulated
+sim_ticks                                 21619648000                       # Number of ticks simulated
+final_tick                                21619648000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 262496                       # Simulator instruction rate (inst/s)
-host_op_rate                                   262496                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               69357396                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 228212                       # Number of bytes of host memory used
-host_seconds                                   303.21                       # Real time elapsed on the host
+host_inst_rate                                 236725                       # Simulator instruction rate (inst/s)
+host_op_rate                                   236725                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               64301983                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 228176                       # Number of bytes of host memory used
+host_seconds                                   336.22                       # Real time elapsed on the host
 sim_insts                                    79591756                       # Number of instructions simulated
 sim_ops                                      79591756                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst            558848                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          10293248                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             10852096                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       558848                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          558848                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7426112                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7426112                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               8732                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             160832                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                169564                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          116033                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               116033                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst             26573939                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            489457144                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               516031083                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst        26573939                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total           26573939                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks         353121150                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              353121150                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks         353121150                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst            26573939                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           489457144                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              869152232                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst            559360                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          10295744                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             10855104                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       559360                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          559360                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7426560                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7426560                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               8740                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             160871                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                169611                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          116040                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               116040                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst             25872762                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            476221630                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               502094391                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst        25872762                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total           25872762                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks         343509756                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              343509756                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks         343509756                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst            25872762                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           476221630                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              845604147                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     22489459                       # DTB read hits
-system.cpu.dtb.read_misses                     217588                       # DTB read misses
-system.cpu.dtb.read_acv                            44                       # DTB read access violations
-system.cpu.dtb.read_accesses                 22707047                       # DTB read accesses
-system.cpu.dtb.write_hits                    15786869                       # DTB write hits
-system.cpu.dtb.write_misses                     41269                       # DTB write misses
+system.cpu.dtb.read_hits                     22479620                       # DTB read hits
+system.cpu.dtb.read_misses                     218266                       # DTB read misses
+system.cpu.dtb.read_acv                            51                       # DTB read access violations
+system.cpu.dtb.read_accesses                 22697886                       # DTB read accesses
+system.cpu.dtb.write_hits                    15794697                       # DTB write hits
+system.cpu.dtb.write_misses                     42457                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                15828138                       # DTB write accesses
-system.cpu.dtb.data_hits                     38276328                       # DTB hits
-system.cpu.dtb.data_misses                     258857                       # DTB misses
-system.cpu.dtb.data_acv                            44                       # DTB access violations
-system.cpu.dtb.data_accesses                 38535185                       # DTB accesses
-system.cpu.itb.fetch_hits                    14133999                       # ITB hits
-system.cpu.itb.fetch_misses                     38583                       # ITB misses
+system.cpu.dtb.write_accesses                15837154                       # DTB write accesses
+system.cpu.dtb.data_hits                     38274317                       # DTB hits
+system.cpu.dtb.data_misses                     260723                       # DTB misses
+system.cpu.dtb.data_acv                            51                       # DTB access violations
+system.cpu.dtb.data_accesses                 38535040                       # DTB accesses
+system.cpu.itb.fetch_hits                    14126097                       # ITB hits
+system.cpu.itb.fetch_misses                     39352                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                14172582                       # ITB accesses
+system.cpu.itb.fetch_accesses                14165449                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -67,105 +67,105 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                 4583                       # Number of system calls
-system.cpu.numCycles                         42059856                       # number of cpu cycles simulated
+system.cpu.numCycles                         43239299                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                 16727417                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted           10795081                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect             475795                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups              12310974                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                  7475407                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                 16709943                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           10781072                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect             476192                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              12038225                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                  7471491                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                  1997632                       # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect               44950                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles           15195386                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      106731428                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    16727417                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            9473039                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      19807941                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 2142694                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles                4831440                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                 7974                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        318425                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                  14133999                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                219929                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples           41712717                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.558726                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.170110                       # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS                  1995310                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect               44665                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles           15444845                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      106679218                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    16709943                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            9466801                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      19799027                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 2146422                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles                5702055                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                 8316                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        320776                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                  14126097                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                222277                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples           42829816                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.490770                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.154588                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 21904776     52.51%     52.51% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  1546832      3.71%     56.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  1409518      3.38%     59.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  1517307      3.64%     63.24% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  4200862     10.07%     73.31% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  1863663      4.47%     77.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                   687442      1.65%     79.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1091312      2.62%     82.04% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                  7491005     17.96%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 23030789     53.77%     53.77% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  1545838      3.61%     57.38% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  1407824      3.29%     60.67% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  1518177      3.54%     64.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  4200095      9.81%     74.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  1866083      4.36%     78.38% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                   683567      1.60%     79.97% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1088540      2.54%     82.51% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                  7488903     17.49%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total             41712717                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.397705                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.537608                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 16282600                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles               4400388                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  18871589                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                713555                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                1444585                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              3801857                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                109351                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              104838793                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                305565                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                1444585                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 16762775                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 2290284                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          81927                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  19061483                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               2071663                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              103408033                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                   177                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                   1890                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               1956072                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands            62335498                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             124694291                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        124234000                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups            460291                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total             42829816                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.386453                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.467182                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 16586159                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles               5216387                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  18831807                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                747368                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                1448095                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              3802176                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                109343                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              104798684                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                306113                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                1448095                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 17060162                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 2943499                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          82970                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  19071081                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               2224009                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              103374463                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                   294                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                  47714                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               2072135                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands            62309566                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             124647358                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        124190382                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups            456976                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps              52546881                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                  9788617                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               5545                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts           5542                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                   4401091                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             23371275                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            16383320                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1113297                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores           382577                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                   91444399                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                5409                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                  89052036                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            123621                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        11266129                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined      4895344                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            826                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples      41712717                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.134889                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.120974                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                  9762685                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               5585                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           5583                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                   4545963                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             23367723                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            16390642                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1133008                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores           393146                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                   91432081                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                5446                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                  89033358                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            121532                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        11257440                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined      4905922                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            863                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples      42829816                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.078770                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.113525                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            13445094     32.23%     32.23% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1             6815105     16.34%     48.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             5522712     13.24%     61.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             4804260     11.52%     73.33% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             4760133     11.41%     84.74% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             2656664      6.37%     91.11% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             1952953      4.68%     95.79% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             1309211      3.14%     98.93% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              446585      1.07%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            14329925     33.46%     33.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1             7119620     16.62%     50.08% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             5526453     12.90%     62.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             4793299     11.19%     74.18% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             4689695     10.95%     85.13% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             2671983      6.24%     91.36% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             1950910      4.56%     95.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             1326668      3.10%     99.02% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              421263      0.98%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total        41712717                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        42829816                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  129648      6.83%      6.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  128939      6.83%      6.83% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                      0      0.00%      6.83% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%      6.83% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatAdd                     0      0.00%      6.83% # attempts to use FU when none available
@@ -194,120 +194,120 @@ system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      6.83% # at
 system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      6.83% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      6.83% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      6.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                 800646     42.16%     48.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                968600     51.01%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 795203     42.12%     48.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                964007     51.06%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              49748943     55.87%     55.87% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                43836      0.05%     55.91% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     55.91% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd              121395      0.14%     56.05% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                  89      0.00%     56.05% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt              122222      0.14%     56.19% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                 56      0.00%     56.19% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv               38945      0.04%     56.23% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     56.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     56.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     56.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     56.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     56.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     56.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     56.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     56.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     56.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     56.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     56.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     56.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     56.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     56.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     56.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     56.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     56.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     56.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     56.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     56.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     56.23% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             22978145     25.80%     82.03% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            15998405     17.97%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              49729867     55.86%     55.86% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                43817      0.05%     55.90% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     55.90% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd              121200      0.14%     56.04% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                  87      0.00%     56.04% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt              122187      0.14%     56.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                 56      0.00%     56.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv               38946      0.04%     56.22% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     56.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     56.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     56.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     56.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     56.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     56.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     56.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     56.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     56.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     56.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     56.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     56.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     56.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     56.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     56.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     56.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     56.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     56.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     56.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     56.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     56.22% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             22972171     25.80%     82.02% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            16005027     17.98%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total               89052036                       # Type of FU issued
-system.cpu.iq.rate                           2.117269                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     1898894                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.021323                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          221228638                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         102311745                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     87003241                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads              610666                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes             420329                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses       297405                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses               90645490                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                  305440                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          1454782                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total               89033358                       # Type of FU issued
+system.cpu.iq.rate                           2.059084                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     1888149                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.021207                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          222297193                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         102291434                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     86992301                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads              609020                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes             419648                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses       296730                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses               90616918                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                  304589                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1450786                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      3094637                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         5405                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        17198                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      1769943                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      3091085                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         5211                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        17173                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      1777265                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads         2465                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked            56                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads         2461                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked            40                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                1444585                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 1378750                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                 59667                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           100988081                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            245674                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              23371275                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             16383320                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               5409                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  41936                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                   387                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          17198                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         251719                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       174529                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               426248                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts              88078074                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              22710515                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            973962                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                1448095                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 1762662                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                 92194                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           100976081                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            242299                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              23367723                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             16390642                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               5446                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  53221                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                   430                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          17173                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         250537                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       173902                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               424439                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts              88065648                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              22701440                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            967710                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                       9538273                       # number of nop insts executed
-system.cpu.iew.exec_refs                     38539046                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 15143390                       # Number of branches executed
-system.cpu.iew.exec_stores                   15828531                       # Number of stores executed
-system.cpu.iew.exec_rate                     2.094113                       # Inst execution rate
-system.cpu.iew.wb_sent                       87713914                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      87300646                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  33458604                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  43597958                       # num instructions consuming a value
+system.cpu.iew.exec_nop                       9538554                       # number of nop insts executed
+system.cpu.iew.exec_refs                     38538948                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 15139399                       # Number of branches executed
+system.cpu.iew.exec_stores                   15837508                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.036704                       # Inst execution rate
+system.cpu.iew.wb_sent                       87702246                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      87289031                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  33442850                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  43872911                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       2.075629                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.767435                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       2.018743                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.762266                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts       88340672                       # The number of committed instructions
 system.cpu.commit.commitCommittedOps         88340672                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts         9531604                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts         9533571                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls            4583                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            368829                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples     40268132                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.193811                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.828127                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts            369490                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples     41381721                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.134775                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.804212                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     17348502     43.08%     43.08% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1      7047839     17.50%     60.58% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      3405424      8.46%     69.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      2108778      5.24%     74.28% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      2046687      5.08%     79.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1183274      2.94%     82.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      1130602      2.81%     85.11% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       707287      1.76%     86.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      5289739     13.14%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     18296264     44.21%     44.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1      7146737     17.27%     61.48% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      3523583      8.51%     70.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      2099457      5.07%     75.07% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      2039541      4.93%     80.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1177840      2.85%     82.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      1135730      2.74%     85.59% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       713898      1.73%     87.32% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      5248671     12.68%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total     40268132                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total     41381721                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts             88340672                       # Number of instructions committed
 system.cpu.commit.committedOps               88340672                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -318,70 +318,70 @@ system.cpu.commit.branches                   13754477                       # Nu
 system.cpu.commit.fp_insts                     267754                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                  77942044                       # Number of committed integer instructions.
 system.cpu.commit.function_calls              1661057                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events               5289739                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events               5248671                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    131533327                       # The number of ROB reads
-system.cpu.rob.rob_writes                   197192647                       # The number of ROB writes
-system.cpu.timesIdled                           15699                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          347139                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                    132689951                       # The number of ROB reads
+system.cpu.rob.rob_writes                   197200056                       # The number of ROB writes
+system.cpu.timesIdled                           24548                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          409483                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                    79591756                       # Number of Instructions Simulated
 system.cpu.committedOps                      79591756                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total              79591756                       # Number of Instructions Simulated
-system.cpu.cpi                               0.528445                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.528445                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.892345                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.892345                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                116616744                       # number of integer regfile reads
-system.cpu.int_regfile_writes                57879304                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                    252339                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                   241658                       # number of floating regfile writes
-system.cpu.misc_regfile_reads                   38301                       # number of misc regfile reads
+system.cpu.cpi                               0.543264                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.543264                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.840727                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.840727                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                116607964                       # number of integer regfile reads
+system.cpu.int_regfile_writes                57862089                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                    251339                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                   241385                       # number of floating regfile writes
+system.cpu.misc_regfile_reads                   38087                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.icache.replacements                  93371                       # number of replacements
-system.cpu.icache.tagsinuse               1930.973067                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 14034495                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                  95419                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                 147.082814                       # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle            17612659000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst    1930.973067                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.942858                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.942858                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst     14034495                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        14034495                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      14034495                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         14034495                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     14034495                       # number of overall hits
-system.cpu.icache.overall_hits::total        14034495                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        99504                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         99504                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        99504                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          99504                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        99504                       # number of overall misses
-system.cpu.icache.overall_misses::total         99504                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    887461000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    887461000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    887461000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    887461000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    887461000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    887461000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     14133999                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     14133999                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     14133999                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     14133999                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     14133999                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     14133999                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.007040                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.007040                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.007040                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.007040                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.007040                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.007040                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  8918.847484                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total  8918.847484                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst  8918.847484                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total  8918.847484                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst  8918.847484                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total  8918.847484                       # average overall miss latency
+system.cpu.icache.replacements                  92930                       # number of replacements
+system.cpu.icache.tagsinuse               1930.212243                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 14026666                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                  94978                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                 147.683316                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle            18067713000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::cpu.inst    1930.212243                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.942486                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.942486                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst     14026666                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        14026666                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      14026666                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         14026666                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     14026666                       # number of overall hits
+system.cpu.icache.overall_hits::total        14026666                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        99431                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         99431                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        99431                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          99431                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        99431                       # number of overall misses
+system.cpu.icache.overall_misses::total         99431                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   1030437000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   1030437000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   1030437000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   1030437000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   1030437000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   1030437000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     14126097                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     14126097                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     14126097                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     14126097                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     14126097                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     14126097                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.007039                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.007039                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.007039                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.007039                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.007039                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.007039                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10363.337390                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 10363.337390                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 10363.337390                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 10363.337390                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 10363.337390                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 10363.337390                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -390,286 +390,286 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         4084                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         4084                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         4084                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         4084                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         4084                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         4084                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        95420                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        95420                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        95420                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        95420                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        95420                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        95420                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    511334500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    511334500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    511334500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    511334500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    511334500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    511334500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.006751                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.006751                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.006751                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.006751                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.006751                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.006751                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  5358.776986                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  5358.776986                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  5358.776986                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total  5358.776986                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  5358.776986                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total  5358.776986                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         4452                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         4452                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         4452                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         4452                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         4452                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         4452                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        94979                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        94979                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        94979                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        94979                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        94979                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        94979                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    637690000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    637690000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    637690000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    637690000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    637690000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    637690000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.006724                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.006724                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.006724                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.006724                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.006724                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.006724                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  6714.010465                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  6714.010465                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  6714.010465                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total  6714.010465                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  6714.010465                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total  6714.010465                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                 201494                       # number of replacements
-system.cpu.dcache.tagsinuse               4076.242085                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 34356241                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                 205590                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                 167.110467                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              156434000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4076.242085                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.995176                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.995176                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data     20778024                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        20778024                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     13578147                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       13578147                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data           70                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total           70                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data      34356171                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         34356171                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     34356171                       # number of overall hits
-system.cpu.dcache.overall_hits::total        34356171                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       254081                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        254081                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1035230                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1035230                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      1289311                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1289311                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1289311                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1289311                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   7948579000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   7948579000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  34030906498                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  34030906498                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  41979485498                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  41979485498                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  41979485498                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  41979485498                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     21032105                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     21032105                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.replacements                 201568                       # number of replacements
+system.cpu.dcache.tagsinuse               4075.950137                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 34352337                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 205664                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 167.031357                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              168155000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4075.950137                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.995105                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.995105                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     20774825                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        20774825                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     13577434                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       13577434                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data           78                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total           78                       # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits::cpu.data      34352259                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         34352259                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     34352259                       # number of overall hits
+system.cpu.dcache.overall_hits::total        34352259                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       251443                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        251443                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1035943                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1035943                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      1287386                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1287386                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1287386                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1287386                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   8531732000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   8531732000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  45960422000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  45960422000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  54492154000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  54492154000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  54492154000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  54492154000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     21026268                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     21026268                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     14613377                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     14613377                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data           70                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total           70                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     35645482                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     35645482                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     35645482                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     35645482                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.012081                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.012081                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.070841                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.070841                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.036170                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.036170                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.036170                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.036170                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31283.641831                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 31283.641831                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 32872.797830                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 32872.797830                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 32559.627195                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 32559.627195                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 32559.627195                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 32559.627195                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs       100500                       # number of cycles access was blocked
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data           78                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total           78                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     35639645                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     35639645                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     35639645                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     35639645                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.011959                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.011959                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.070890                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.070890                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.036122                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.036122                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.036122                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.036122                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33931.077819                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 33931.077819                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44365.782673                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 44365.782673                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 42327.750962                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 42327.750962                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 42327.750962                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 42327.750962                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       103000                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                17                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs  5911.764706                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  6058.823529                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       166286                       # number of writebacks
-system.cpu.dcache.writebacks::total            166286                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       191915                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       191915                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       891806                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       891806                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1083721                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1083721                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1083721                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1083721                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data        62166                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total        62166                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       143424                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       143424                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       205590                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       205590                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       205590                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       205590                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   1142650000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   1142650000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   4721135000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   4721135000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data   5863785000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total   5863785000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data   5863785000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total   5863785000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002956                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002956                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009815                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009815                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.005768                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.005768                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.005768                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.005768                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18380.626066                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18380.626066                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32917.329038                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32917.329038                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28521.742303                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 28521.742303                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28521.742303                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 28521.742303                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks       166337                       # number of writebacks
+system.cpu.dcache.writebacks::total            166337                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       189183                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       189183                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       892539                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       892539                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      1081722                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1081722                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1081722                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1081722                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data        62260                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total        62260                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       143404                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       143404                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       205664                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       205664                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       205664                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       205664                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   1244458000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   1244458000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5521780000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   5521780000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   6766238000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   6766238000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data   6766238000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   6766238000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002961                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002961                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009813                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009813                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.005771                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.005771                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.005771                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.005771                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19988.082236                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19988.082236                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38505.062620                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38505.062620                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32899.476817                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 32899.476817                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32899.476817                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 32899.476817                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.replacements                137157                       # number of replacements
-system.cpu.l2cache.tagsinuse             29150.308284                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                  155579                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                168030                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  0.925900                       # Average number of references to valid blocks.
+system.cpu.l2cache.replacements                137209                       # number of replacements
+system.cpu.l2cache.tagsinuse             29108.919988                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                  155222                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                168087                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.923462                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 25379.974502                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst   1916.859149                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data   1853.474632                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.774535                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst     0.058498                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.056564                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.889597                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst        86688                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data        32293                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total         118981                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       166286                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       166286                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data        12465                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total        12465                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        86688                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data        44758                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          131446                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst        86688                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data        44758                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         131446                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         8732                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data        29871                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        38603                       # number of ReadReq misses
+system.cpu.l2cache.occ_blocks::writebacks 25319.531401                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst   1909.557763                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data   1879.830824                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.772691                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.058275                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.057368                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.888334                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst        86239                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data        32344                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         118583                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       166337                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       166337                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data        12449                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total        12449                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst        86239                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data        44793                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          131032                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst        86239                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data        44793                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         131032                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         8740                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data        29910                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        38650                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data       130961                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total       130961                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         8732                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       160832                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        169564                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         8732                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       160832                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       169564                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    299903500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1029755500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total   1329659000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   4515967000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   4515967000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    299903500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data   5545722500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total   5845626000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    299903500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data   5545722500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total   5845626000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst        95420                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data        62164                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total       157584                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       166286                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       166286                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       143426                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       143426                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        95420                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       205590                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       301010                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        95420                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       205590                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       301010                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.091511                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.480519                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.244968                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.913091                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.913091                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.091511                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.782295                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.563317                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.091511                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.782295                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.563317                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34345.338983                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34473.419035                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 34444.447323                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34483.296554                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34483.296554                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34345.338983                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34481.462022                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 34474.452124                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34345.338983                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34481.462022                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 34474.452124                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs        28000                       # number of cycles access was blocked
+system.cpu.l2cache.demand_misses::cpu.inst         8740                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       160871                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        169611                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         8740                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       160871                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       169611                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    308686000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1033182500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   1341868500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   5027402000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   5027402000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    308686000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   6060584500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   6369270500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    308686000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   6060584500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   6369270500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst        94979                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data        62254                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       157233                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       166337                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       166337                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       143410                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       143410                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        94979                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       205664                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       300643                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        94979                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       205664                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       300643                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.092020                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.480451                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.245814                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.913193                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.913193                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.092020                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.782203                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.564161                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.092020                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.782203                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.564161                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35318.764302                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34543.045804                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 34718.460543                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 38388.543154                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 38388.543154                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35318.764302                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 37673.567641                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 37552.225386                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35318.764302                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 37673.567641                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 37552.225386                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs        34000                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs               11                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs               12                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs  2545.454545                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs  2833.333333                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       116033                       # number of writebacks
-system.cpu.l2cache.writebacks::total           116033                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         8732                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        29871                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        38603                       # number of ReadReq MSHR misses
+system.cpu.l2cache.writebacks::writebacks       116040                       # number of writebacks
+system.cpu.l2cache.writebacks::total           116040                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         8740                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        29910                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        38650                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       130961                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total       130961                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         8732                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       160832                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       169564                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         8732                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       160832                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       169564                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    271655000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    927105000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1198760000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4112324500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4112324500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    271655000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   5039429500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   5311084500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    271655000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   5039429500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   5311084500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.091511                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.480519                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.244968                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.913091                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.913091                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.091511                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.782295                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.563317                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.091511                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.782295                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.563317                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31110.284013                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31036.958923                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31053.545061                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31401.138507                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31401.138507                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31110.284013                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31333.500174                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31322.005261                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31110.284013                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31333.500174                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31322.005261                       # average overall mshr miss latency
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         8740                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       160871                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       169611                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         8740                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       160871                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       169611                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    281019000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    942134500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1223153500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4629566000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4629566000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    281019000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   5571700500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   5852719500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    281019000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   5571700500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   5852719500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.092020                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.480451                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.245814                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.913193                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.913193                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.092020                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.782203                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.564161                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.092020                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.782203                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.564161                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32153.203661                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31498.980274                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31646.921087                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35350.722734                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35350.722734                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32153.203661                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34634.586097                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34506.721262                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32153.203661                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34634.586097                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34506.721262                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini
index db5db2a63..e15c6aa9f 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini
@@ -148,7 +148,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
@@ -180,7 +180,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout
index 1808f3b15..d2ae983de 100755
--- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout
@@ -1,11 +1,11 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:05:18
-gem5 started Jun 28 2012 22:25:28
+gem5 compiled Jul  2 2012 08:30:56
+gem5 started Jul  2 2012 10:09:02
 gem5 executing on zizzer
 command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
-Exiting @ tick 134036748000 because target called exit()
+Exiting @ tick 134581343000 because target called exit()
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
index 9facba206..5c01fa696 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.134037                       # Number of seconds simulated
-sim_ticks                                134036748000                       # Number of ticks simulated
-final_tick                               134036748000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.134581                       # Number of seconds simulated
+sim_ticks                                134581343000                       # Number of ticks simulated
+final_tick                               134581343000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2004374                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2004373                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             3041175629                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 226164                       # Number of bytes of host memory used
-host_seconds                                    44.07                       # Real time elapsed on the host
+host_inst_rate                                1566292                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1566291                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2386143258                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 226128                       # Number of bytes of host memory used
+host_seconds                                    56.40                       # Real time elapsed on the host
 sim_insts                                    88340673                       # Number of instructions simulated
 sim_ops                                      88340673                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst            485312                       # Number of bytes read from this memory
@@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data             160477                       # Nu
 system.physmem.num_reads::total                168060                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks          115955                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total               115955                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst              3620738                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             76624718                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                80245456                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         3620738                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            3620738                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          55366309                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               55366309                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          55366309                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             3620738                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            76624718                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              135611765                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst              3606087                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             76314649                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                79920736                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         3606087                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            3606087                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          55142264                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               55142264                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          55142264                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             3606087                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            76314649                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              135063001                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -67,7 +67,7 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                 4583                       # Number of system calls
-system.cpu.numCycles                        268073496                       # number of cpu cycles simulated
+system.cpu.numCycles                        269162686                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                    88340673                       # Number of instructions committed
@@ -86,18 +86,18 @@ system.cpu.num_mem_refs                      34987415                       # nu
 system.cpu.num_load_insts                    20366786                       # Number of load instructions
 system.cpu.num_store_insts                   14620629                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  268073496                       # Number of busy cycles
+system.cpu.num_busy_cycles                  269162686                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                  74391                       # number of replacements
-system.cpu.icache.tagsinuse               1871.539157                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse               1871.699205                       # Cycle average of tags in use
 system.cpu.icache.total_refs                 88361638                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                  76436                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                1156.021220                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst    1871.539157                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.913837                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.913837                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst    1871.699205                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.913916                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.913916                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst     88361638                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total        88361638                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst      88361638                       # number of demand (read+write) hits
@@ -110,12 +110,12 @@ system.cpu.icache.demand_misses::cpu.inst        76436                       # n
 system.cpu.icache.demand_misses::total          76436                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst        76436                       # number of overall misses
 system.cpu.icache.overall_misses::total         76436                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   1388590000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   1388590000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   1388590000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   1388590000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   1388590000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   1388590000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   1390813000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   1390813000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   1390813000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   1390813000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   1390813000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   1390813000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst     88438074                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total     88438074                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst     88438074                       # number of demand (read+write) accesses
@@ -128,12 +128,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000864
 system.cpu.icache.demand_miss_rate::total     0.000864                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000864                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000864                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18166.701554                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 18166.701554                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 18166.701554                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 18166.701554                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 18166.701554                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 18166.701554                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18195.784709                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 18195.784709                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 18195.784709                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 18195.784709                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 18195.784709                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 18195.784709                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -148,34 +148,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst        76436
 system.cpu.icache.demand_mshr_misses::total        76436                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst        76436                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total        76436                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   1159282000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total   1159282000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst   1159282000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total   1159282000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst   1159282000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total   1159282000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   1161505000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total   1161505000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   1161505000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   1161505000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst   1161505000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total   1161505000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000864                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000864                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000864                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000864                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000864                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000864                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15166.701554                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15166.701554                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15166.701554                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 15166.701554                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15166.701554                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 15166.701554                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15195.784709                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15195.784709                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15195.784709                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 15195.784709                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15195.784709                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 15195.784709                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                 200248                       # number of replacements
-system.cpu.dcache.tagsinuse               4078.827650                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               4078.801621                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                 34685671                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                 204344                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                 169.741568                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              943232000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4078.827650                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.995808                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.995808                       # Average percentage of cache occupancy
+system.cpu.dcache.warmup_cycle              947396000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4078.801621                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.995801                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.995801                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data     20215872                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        20215872                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     14469799                       # number of WriteReq hits
@@ -192,14 +192,14 @@ system.cpu.dcache.demand_misses::cpu.data       204344                       # n
 system.cpu.dcache.demand_misses::total         204344                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data       204344                       # number of overall misses
 system.cpu.dcache.overall_misses::total        204344                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   2087582000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   2087582000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   7513268000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   7513268000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data   9600850000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total   9600850000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data   9600850000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total   9600850000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   2092728000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   2092728000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   7513894000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   7513894000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data   9606622000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total   9606622000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data   9606622000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total   9606622000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data     20276638                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total     20276638                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     14613377                       # number of WriteReq accesses(hits+misses)
@@ -216,14 +216,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.005857
 system.cpu.dcache.demand_miss_rate::total     0.005857                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.005857                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.005857                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34354.441629                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 34354.441629                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52328.824750                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 52328.824750                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 46983.762675                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 46983.762675                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 46983.762675                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 46983.762675                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34439.127143                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 34439.127143                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52333.184750                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 52333.184750                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 47012.009161                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 47012.009161                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 47012.009161                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 47012.009161                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -242,14 +242,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data       204344
 system.cpu.dcache.demand_mshr_misses::total       204344                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data       204344                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total       204344                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   1905284000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   1905284000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   7082534000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   7082534000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data   8987818000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total   8987818000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data   8987818000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total   8987818000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   1910430000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   1910430000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   7083160000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   7083160000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   8993590000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   8993590000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data   8993590000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   8993590000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002997                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002997                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009825                       # mshr miss rate for WriteReq accesses
@@ -258,28 +258,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.005857
 system.cpu.dcache.demand_mshr_miss_rate::total     0.005857                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.005857                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.005857                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31354.441629                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31354.441629                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49328.824750                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49328.824750                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43983.762675                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 43983.762675                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43983.762675                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 43983.762675                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31439.127143                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31439.127143                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49333.184750                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49333.184750                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44012.009161                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 44012.009161                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44012.009161                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 44012.009161                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                135625                       # number of replacements
-system.cpu.l2cache.tagsinuse             29002.202656                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse             29002.571879                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                  136279                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                166491                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.818537                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 25777.846112                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst   1647.476120                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data   1576.880424                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.786677                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst     0.050277                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.048123                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.885077                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::writebacks 25772.303239                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst   1646.708734                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data   1583.559905                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.786508                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.050254                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.048326                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.885088                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst        68853                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data        31317                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total         100170                       # number of ReadReq hits
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
index 33fd8bc7c..0878a1dc0 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
@@ -497,7 +497,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
@@ -529,7 +529,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout
index 462a53b1f..c4aefb2c9 100755
--- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout
@@ -1,11 +1,11 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:10:14
-gem5 started Jun 29 2012 01:13:16
+gem5 compiled Jul  2 2012 09:08:16
+gem5 started Jul  2 2012 16:29:16
 gem5 executing on zizzer
 command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/50.vortex/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
-Exiting @ tick 23981004500 because target called exit()
+Exiting @ tick 24460150500 because target called exit()
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
index 8d4101747..f26f3a389 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
@@ -1,39 +1,39 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.023981                       # Number of seconds simulated
-sim_ticks                                 23981004500                       # Number of ticks simulated
-final_tick                                23981004500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.024460                       # Number of seconds simulated
+sim_ticks                                 24460150500                       # Number of ticks simulated
+final_tick                                24460150500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 169152                       # Simulator instruction rate (inst/s)
-host_op_rate                                   240031                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               57193739                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 242580                       # Number of bytes of host memory used
-host_seconds                                   419.29                       # Real time elapsed on the host
-sim_insts                                    70924419                       # Number of instructions simulated
-sim_ops                                     100643666                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 167024                       # Simulator instruction rate (inst/s)
+host_op_rate                                   237012                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               57603012                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 242500                       # Number of bytes of host memory used
+host_seconds                                   424.63                       # Real time elapsed on the host
+sim_insts                                    70923824                       # Number of instructions simulated
+sim_ops                                     100643071                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst            326976                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           8029184                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              8356160                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           8028736                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              8355712                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read::cpu.inst       326976                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total          326976                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      5417856                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           5417856                       # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks      5417152                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           5417152                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.inst               5109                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             125456                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                130565                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           84654                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                84654                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst             13634792                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            334814332                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               348449124                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst        13634792                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total           13634792                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks         225922813                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              225922813                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks         225922813                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst            13634792                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           334814332                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              574371937                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_reads::cpu.data             125449                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                130558                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           84643                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                84643                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst             13367702                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            328237392                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               341605094                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst        13367702                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total           13367702                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks         221468466                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              221468466                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks         221468466                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst            13367702                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           328237392                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              563073559                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -77,143 +77,143 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                 1946                       # Number of system calls
-system.cpu.numCycles                         47962010                       # number of cpu cycles simulated
+system.cpu.numCycles                         48920302                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                 16947214                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted           12982117                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect             655322                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups              11804628                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                  7961599                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                 16960531                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           12985874                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect             661473                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              11570513                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                  7976664                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                  1880669                       # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect              114490                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles           12764738                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                       87540471                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    16947214                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            9842268                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      21772804                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 2768546                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles               10027678                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                   28                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles           361                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                  12061426                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                218802                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples           46590944                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.639937                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.350838                       # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS                  1883015                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect              115088                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles           12843999                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                       87580035                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    16960531                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            9859679                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      21787094                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 2782746                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               10982319                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                   56                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles           606                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                  12079139                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                221673                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples           47647021                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.582724                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.336366                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 24839551     53.31%     53.31% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  2175787      4.67%     57.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  1999394      4.29%     62.28% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  2026993      4.35%     66.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  1551688      3.33%     69.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  1408138      3.02%     72.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                   990048      2.12%     75.10% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1240896      2.66%     77.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 10358449     22.23%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 25881368     54.32%     54.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  2178299      4.57%     58.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  2007274      4.21%     63.10% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  2021463      4.24%     67.35% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  1548956      3.25%     70.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  1412983      2.97%     73.56% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                   995678      2.09%     75.65% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1240946      2.60%     78.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 10360054     21.74%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total             46590944                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.353347                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.825204                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 14883106                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles               8408681                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  19993372                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               1386692                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                1919093                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              3458129                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                108409                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              120163882                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                373498                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                1919093                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 16645469                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 2316120                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         802815                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  19569476                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               5337971                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              117636894                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                    44                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                   9686                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               4512387                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents              221                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           117778889                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             541771281                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        541766916                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups              4365                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps              99159536                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 18619353                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts              37368                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts          37363                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  12895568                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             30067923                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            22776958                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           3590168                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          4248242                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  113315749                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded               51911                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 108455143                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            350648                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        12554662                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     29999283                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved          14767                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples      46590944                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.327816                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.997244                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total             47647021                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.346697                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.790259                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 15031484                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles               9298191                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  19969978                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               1421734                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                1925634                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              3462876                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                109476                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              120212842                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                378015                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                1925634                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 16795731                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 2963104                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         805180                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  19544890                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               5612482                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              117675747                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                    86                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                  12709                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               4780104                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents              263                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           117787272                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             541948309                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        541940540                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups              7769                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps              99158584                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 18628688                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts              37002                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts          36987                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  13169886                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             30082364                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            22781735                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           3607820                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          4315548                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  113341575                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               51734                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 108469975                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            351751                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        12575588                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     30093615                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved          14709                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples      47647021                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.276532                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.995144                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            11127507     23.88%     23.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1             8067707     17.32%     41.20% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             7375197     15.83%     57.03% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             7162683     15.37%     72.40% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             5557871     11.93%     84.33% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             3930157      8.44%     92.77% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             1905355      4.09%     96.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              881142      1.89%     98.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              583325      1.25%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            11903537     24.98%     24.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1             8354851     17.53%     42.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             7454693     15.65%     58.16% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             7158692     15.02%     73.19% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             5519097     11.58%     84.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             3907609      8.20%     92.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             1895733      3.98%     96.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              881641      1.85%     98.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              571168      1.20%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total        46590944                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        47647021                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  112830      4.40%      4.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      4.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      4.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      4.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      4.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      4.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      4.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      4.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      4.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      4.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      4.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      4.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      4.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      4.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      4.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      4.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      4.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      4.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      4.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      4.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      4.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      4.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      4.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      4.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      4.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      4.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      4.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      4.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      4.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                1425910     55.61%     60.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               1025351     39.99%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  112989      4.45%      4.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      4.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      4.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     2      0.00%      4.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      4.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      4.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      4.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      4.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      4.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      4.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      4.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      4.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      4.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      4.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      4.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      4.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      4.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      4.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      4.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      4.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      4.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      4.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      4.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      4.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      4.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      4.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      4.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      4.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      4.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                1419251     55.85%     60.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               1008989     39.70%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              57362458     52.89%     52.89% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                91498      0.08%     52.97% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              57363382     52.88%     52.88% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                91507      0.08%     52.97% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     52.97% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                 129      0.00%     52.97% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                 228      0.00%     52.97% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     52.97% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     52.97% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     52.97% # Type of FU issued
@@ -239,160 +239,160 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              7      0.00%     52.97% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     52.97% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     52.97% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     52.97% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             29209051     26.93%     79.91% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            21792000     20.09%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             29217041     26.94%     79.90% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            21797810     20.10%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              108455143                       # Type of FU issued
-system.cpu.iq.rate                           2.261272                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     2564091                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.023642                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          266415556                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         125949072                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    106420629                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 413                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                622                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses          133                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              111019028                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     206                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          2223683                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              108469975                       # Type of FU issued
+system.cpu.iq.rate                           2.217279                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2541231                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.023428                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          267479180                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         125995514                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    106424512                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 773                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes               1272                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses          187                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              111010818                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     388                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          2214998                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      2757457                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         7931                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        28755                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      2217862                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      2772017                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         7458                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        29087                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      2222758                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads           49                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked            70                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads           51                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked            49                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                1919093                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                  944512                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                 30820                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           113447794                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            342667                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              30067923                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             22776958                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts              35363                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                   1047                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                  2166                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          28755                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         424789                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       263529                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               688318                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             107242187                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              28840669                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           1212956                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                1925634                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                  929341                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                 37355                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           113473181                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            343640                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              30082364                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             22781735                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts              35157                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                   2560                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                  3541                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          29087                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         428613                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       264355                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               692968                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             107247329                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              28841677                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1222646                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                         80134                       # number of nop insts executed
-system.cpu.iew.exec_refs                     50312690                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 14662886                       # Number of branches executed
-system.cpu.iew.exec_stores                   21472021                       # Number of stores executed
-system.cpu.iew.exec_rate                     2.235982                       # Inst execution rate
-system.cpu.iew.wb_sent                      106754958                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     106420762                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  53610539                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 104702454                       # num instructions consuming a value
+system.cpu.iew.exec_nop                         79872                       # number of nop insts executed
+system.cpu.iew.exec_refs                     50315882                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 14663606                       # Number of branches executed
+system.cpu.iew.exec_stores                   21474205                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.192287                       # Inst execution rate
+system.cpu.iew.wb_sent                      106761196                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     106424699                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  53424049                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 103788661                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       2.218855                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.512028                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       2.175471                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.514739                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts       70929971                       # The number of committed instructions
-system.cpu.commit.commitCommittedOps        100649218                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts        12799085                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls           37144                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            611847                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples     44671852                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.253079                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.750865                       # Number of insts commited each cycle
+system.cpu.commit.commitCommittedInsts       70929376                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps        100648623                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts        12825262                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls           37025                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            616891                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples     45721388                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.201347                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.733819                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     15424353     34.53%     34.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     11724908     26.25%     60.77% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      3540913      7.93%     68.70% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      2916552      6.53%     75.23% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1906207      4.27%     79.50% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1948042      4.36%     83.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       684228      1.53%     85.39% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       590770      1.32%     86.71% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      5935879     13.29%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     16264410     35.57%     35.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     11914734     26.06%     61.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      3626051      7.93%     69.56% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      2926022      6.40%     75.96% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1880797      4.11%     80.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1911030      4.18%     84.26% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       689200      1.51%     85.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       582969      1.28%     87.04% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      5926175     12.96%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total     44671852                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts             70929971                       # Number of instructions committed
-system.cpu.commit.committedOps              100649218                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total     45721388                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts             70929376                       # Number of instructions committed
+system.cpu.commit.committedOps              100648623                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       47869562                       # Number of memory references committed
-system.cpu.commit.loads                      27310466                       # Number of loads committed
+system.cpu.commit.refs                       47869324                       # Number of memory references committed
+system.cpu.commit.loads                      27310347                       # Number of loads committed
 system.cpu.commit.membars                       15920                       # Number of memory barriers committed
-system.cpu.commit.branches                   13671985                       # Number of branches committed
+system.cpu.commit.branches                   13671866                       # Number of branches committed
 system.cpu.commit.fp_insts                         56                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                  91486211                       # Number of committed integer instructions.
+system.cpu.commit.int_insts                  91485735                       # Number of committed integer instructions.
 system.cpu.commit.function_calls              1679850                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events               5935879                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events               5926175                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    152158977                       # The number of ROB reads
-system.cpu.rob.rob_writes                   228826081                       # The number of ROB writes
-system.cpu.timesIdled                           61655                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         1371066                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                    70924419                       # Number of Instructions Simulated
-system.cpu.committedOps                     100643666                       # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total              70924419                       # Number of Instructions Simulated
-system.cpu.cpi                               0.676241                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.676241                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.478762                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.478762                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                516206868                       # number of integer regfile reads
-system.cpu.int_regfile_writes               104370444                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                       520                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                      444                       # number of floating regfile writes
-system.cpu.misc_regfile_reads               146052754                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                  38556                       # number of misc regfile writes
-system.cpu.icache.replacements                  29824                       # number of replacements
-system.cpu.icache.tagsinuse               1820.810833                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 12028408                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                  31867                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                 377.456554                       # Average number of references to valid blocks.
+system.cpu.rob.rob_reads                    153243799                       # The number of ROB reads
+system.cpu.rob.rob_writes                   228884039                       # The number of ROB writes
+system.cpu.timesIdled                           52429                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         1273281                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                    70923824                       # Number of Instructions Simulated
+system.cpu.committedOps                     100643071                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total              70923824                       # Number of Instructions Simulated
+system.cpu.cpi                               0.689758                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.689758                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.449783                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.449783                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                516242048                       # number of integer regfile reads
+system.cpu.int_regfile_writes               104369908                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                       886                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                      750                       # number of floating regfile writes
+system.cpu.misc_regfile_reads               146091713                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                  38318                       # number of misc regfile writes
+system.cpu.icache.replacements                  30244                       # number of replacements
+system.cpu.icache.tagsinuse               1815.033473                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 12045499                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                  32282                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                 373.133604                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst    1820.810833                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.889068                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.889068                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst     12028408                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        12028408                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      12028408                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         12028408                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     12028408                       # number of overall hits
-system.cpu.icache.overall_hits::total        12028408                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        33018                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         33018                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        33018                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          33018                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        33018                       # number of overall misses
-system.cpu.icache.overall_misses::total         33018                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    367424500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    367424500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    367424500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    367424500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    367424500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    367424500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     12061426                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     12061426                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     12061426                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     12061426                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     12061426                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     12061426                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.002737                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.002737                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.002737                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.002737                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.002737                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.002737                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11128.005936                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 11128.005936                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 11128.005936                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 11128.005936                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 11128.005936                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 11128.005936                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst    1815.033473                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.886247                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.886247                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst     12045501                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        12045501                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      12045501                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         12045501                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     12045501                       # number of overall hits
+system.cpu.icache.overall_hits::total        12045501                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        33638                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         33638                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        33638                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          33638                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        33638                       # number of overall misses
+system.cpu.icache.overall_misses::total         33638                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    406685000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    406685000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    406685000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    406685000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    406685000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    406685000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     12079139                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     12079139                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     12079139                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     12079139                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     12079139                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     12079139                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.002785                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.002785                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.002785                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.002785                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.002785                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.002785                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12090.046971                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 12090.046971                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 12090.046971                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 12090.046971                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 12090.046971                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 12090.046971                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -401,254 +401,254 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1111                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         1111                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         1111                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         1111                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         1111                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         1111                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        31907                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        31907                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        31907                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        31907                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        31907                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        31907                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    244055000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    244055000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    244055000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    244055000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    244055000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    244055000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.002645                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.002645                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.002645                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.002645                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.002645                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.002645                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  7648.948507                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  7648.948507                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  7648.948507                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total  7648.948507                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  7648.948507                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total  7648.948507                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1313                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         1313                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         1313                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         1313                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         1313                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         1313                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        32325                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        32325                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        32325                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        32325                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        32325                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        32325                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    274223500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    274223500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    274223500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    274223500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    274223500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    274223500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.002676                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.002676                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.002676                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.002676                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.002676                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.002676                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  8483.325599                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  8483.325599                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  8483.325599                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total  8483.325599                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  8483.325599                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total  8483.325599                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                 158597                       # number of replacements
-system.cpu.dcache.tagsinuse               4071.944277                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 44611539                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                 162693                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                 274.206874                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              262057000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4071.944277                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.994127                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.994127                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data     26269994                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        26269994                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     18301608                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       18301608                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data        20534                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total        20534                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data        19277                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total        19277                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      44571602                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         44571602                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     44571602                       # number of overall hits
-system.cpu.dcache.overall_hits::total        44571602                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       105369                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        105369                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1548293                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1548293                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data           39                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total           39                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      1653662                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1653662                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1653662                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1653662                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   2114831500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   2114831500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  52578719498                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  52578719498                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       447000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total       447000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  54693550998                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  54693550998                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  54693550998                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  54693550998                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     26375363                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     26375363                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.replacements                 158501                       # number of replacements
+system.cpu.dcache.tagsinuse               4071.855185                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 44605412                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 162597                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 274.331089                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              272454000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4071.855185                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.994105                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.994105                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     26278291                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        26278291                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     18287500                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       18287500                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data        20317                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total        20317                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data        19158                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total        19158                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      44565791                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         44565791                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     44565791                       # number of overall hits
+system.cpu.dcache.overall_hits::total        44565791                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       106674                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        106674                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1562401                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1562401                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data           43                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total           43                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data      1669075                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1669075                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1669075                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1669075                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   2574319000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   2574319000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  63349260500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  63349260500                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       629500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total       629500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  65923579500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  65923579500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  65923579500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  65923579500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     26384965                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     26384965                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     19849901                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     19849901                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data        20573                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total        20573                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data        19277                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total        19277                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     46225264                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     46225264                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     46225264                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     46225264                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.003995                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.003995                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.078000                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.078000                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.001896                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.001896                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.035774                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.035774                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.035774                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.035774                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20070.718143                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 20070.718143                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33959.153402                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 33959.153402                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 11461.538462                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 11461.538462                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 33074.201982                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 33074.201982                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 33074.201982                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 33074.201982                       # average overall miss latency
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data        20360                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total        20360                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data        19158                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total        19158                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     46234866                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     46234866                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     46234866                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     46234866                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.004043                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.004043                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.078711                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.078711                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.002112                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.002112                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.036100                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.036100                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.036100                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.036100                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24132.581510                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 24132.581510                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40546.095721                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 40546.095721                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14639.534884                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14639.534884                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 39497.074427                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 39497.074427                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 39497.074427                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 39497.074427                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets       196000                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets       202500                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets              10                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets              11                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets        19600                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 18409.090909                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       128124                       # number of writebacks
-system.cpu.dcache.writebacks::total            128124                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data        49671                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        49671                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1441258                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      1441258                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           39                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total           39                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1490929                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1490929                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1490929                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1490929                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data        55698                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total        55698                       # number of ReadReq MSHR misses
+system.cpu.dcache.writebacks::writebacks       128059                       # number of writebacks
+system.cpu.dcache.writebacks::total            128059                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        51068                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        51068                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1455366                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      1455366                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           43                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total           43                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      1506434                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1506434                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1506434                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1506434                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data        55606                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total        55606                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data       107035                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total       107035                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       162733                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       162733                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       162733                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       162733                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    907626500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total    907626500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   3661924998                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   3661924998                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data   4569551498                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total   4569551498                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data   4569551498                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total   4569551498                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002112                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002112                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_misses::cpu.data       162641                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       162641                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       162641                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       162641                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    982100000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total    982100000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   3836030000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   3836030000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   4818130000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   4818130000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data   4818130000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   4818130000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002107                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002107                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005392                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.005392                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.003520                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.003520                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.003520                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.003520                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16295.495350                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16295.495350                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34212.407138                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34212.407138                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28080.054433                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 28080.054433                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28080.054433                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 28080.054433                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.003518                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.003518                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.003518                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.003518                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17661.763119                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17661.763119                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35839.024618                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35839.024618                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29624.325969                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 29624.325969                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29624.325969                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 29624.325969                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.replacements                 97993                       # number of replacements
-system.cpu.l2cache.tagsinuse             28658.689941                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                   86749                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                128784                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  0.673601                       # Average number of references to valid blocks.
+system.cpu.l2cache.replacements                 97988                       # number of replacements
+system.cpu.l2cache.tagsinuse             28616.670846                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                   87010                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                128775                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.675675                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 25863.719355                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst   1158.363470                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data   1636.607116                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.789298                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst     0.035350                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.049945                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.874594                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst        26734                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data        32452                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total          59186                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       128124                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       128124                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data            3                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total            3                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data         4717                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total         4717                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        26734                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data        37169                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total           63903                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst        26734                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data        37169                       # number of overall hits
-system.cpu.l2cache.overall_hits::total          63903                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         5128                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data        23210                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        28338                       # number of ReadReq misses
+system.cpu.l2cache.occ_blocks::writebacks 25808.135877                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst   1157.314936                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data   1651.220033                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.787602                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.035318                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.050391                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.873311                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst        27137                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data        32372                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total          59509                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       128059                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       128059                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data            7                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total            7                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data         4712                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total         4712                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst        27137                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data        37084                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total           64221                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst        27137                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data        37084                       # number of overall hits
+system.cpu.l2cache.overall_hits::total          64221                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         5137                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data        23202                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        28339                       # number of ReadReq misses
 system.cpu.l2cache.UpgradeReq_misses::cpu.data           37                       # number of UpgradeReq misses
 system.cpu.l2cache.UpgradeReq_misses::total           37                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       102314                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       102314                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         5128                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       125524                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        130652                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         5128                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       125524                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       130652                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    175705500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data    794795000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    970500500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   3514306000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   3514306000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    175705500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data   4309101000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total   4484806500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    175705500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data   4309101000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total   4484806500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst        31862                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data        55662                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total        87524                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       128124                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       128124                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data           40                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total           40                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       107031                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       107031                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        31862                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       162693                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       194555                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        31862                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       162693                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       194555                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.160944                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.416981                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.323774                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.925000                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.925000                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.955929                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.955929                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.160944                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.771539                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.671543                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.160944                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.771539                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.671543                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34263.943058                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34243.644981                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 34247.318089                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34348.241687                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34348.241687                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34263.943058                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34328.901246                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 34326.351682                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34263.943058                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34328.901246                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 34326.351682                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_misses::cpu.data       102311                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       102311                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         5137                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       125513                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        130650                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         5137                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       125513                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       130650                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    180597500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data    827692000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   1008289500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   3557345000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   3557345000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    180597500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   4385037000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   4565634500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    180597500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   4385037000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   4565634500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst        32274                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data        55574                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total        87848                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       128059                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       128059                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data           44                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total           44                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       107023                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       107023                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        32274                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       162597                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       194871                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        32274                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       162597                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       194871                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.159168                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.417497                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.322591                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.840909                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.840909                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.955972                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.955972                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.159168                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.771927                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.670444                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.159168                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.771927                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.670444                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35156.219583                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 35673.304026                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 35579.572321                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34769.917213                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34769.917213                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35156.219583                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34936.914901                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 34945.537696                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35156.219583                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34936.914901                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 34945.537696                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -657,69 +657,69 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        84654                       # number of writebacks
-system.cpu.l2cache.writebacks::total            84654                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           19                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           68                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total           87                       # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst           19                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data           68                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           87                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst           19                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data           68                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           87                       # number of overall MSHR hits
+system.cpu.l2cache.writebacks::writebacks        84643                       # number of writebacks
+system.cpu.l2cache.writebacks::total            84643                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           28                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           64                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total           92                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst           28                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data           64                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           92                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst           28                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data           64                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total           92                       # number of overall MSHR hits
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         5109                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        23142                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        28251                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        23138                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        28247                       # number of ReadReq MSHR misses
 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           37                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.UpgradeReq_mshr_misses::total           37                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       102314                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       102314                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       102311                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       102311                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.inst         5109                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       125456                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       130565                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       125449                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       130558                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         5109                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       125456                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       130565                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    158798500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    719908500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    878707000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      1150000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      1150000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   3191239500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   3191239500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    158798500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   3911148000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   4069946500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    158798500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   3911148000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   4069946500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.160348                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.415759                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.322780                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.925000                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.925000                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.955929                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.955929                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.160348                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.771121                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.671096                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.160348                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.771121                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.671096                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31082.110002                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31108.309567                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31103.571555                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31081.081081                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31081.081081                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31190.643509                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31190.643509                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31082.110002                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31175.455937                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31171.803316                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31082.110002                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31175.455937                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31171.803316                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_misses::cpu.data       125449                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       130558                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    163941000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    752838000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    916779000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      1147000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      1147000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   3241185000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   3241185000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    163941000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   3994023000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   4157964000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    163941000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   3994023000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   4157964000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.158301                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.416346                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.321544                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.840909                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.840909                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.955972                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.955972                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.158301                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.771533                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.669971                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.158301                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.771533                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.669971                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32088.667058                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32536.865762                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32455.800616                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        31000                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        31000                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31679.731407                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31679.731407                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32088.667058                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31837.822541                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31847.638597                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32088.667058                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31837.822541                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31847.638597                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini
index c08fcfcdd..4c2746778 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini
@@ -166,7 +166,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
@@ -198,7 +198,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout
index b1460f18e..564b30c1c 100755
--- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout
@@ -1,11 +1,11 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:10:14
-gem5 started Jun 29 2012 01:20:08
+gem5 compiled Jul  2 2012 09:08:16
+gem5 started Jul  2 2012 16:37:12
 gem5 executing on zizzer
 command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
-Exiting @ tick 132924820000 because target called exit()
+Exiting @ tick 133513136000 because target called exit()
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
index b1eb24a6a..250f6daa7 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.132925                       # Number of seconds simulated
-sim_ticks                                132924820000                       # Number of ticks simulated
-final_tick                               132924820000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.133513                       # Number of seconds simulated
+sim_ticks                                133513136000                       # Number of ticks simulated
+final_tick                               133513136000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1112405                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1577419                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2101158995                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 240528                       # Number of bytes of host memory used
-host_seconds                                    63.26                       # Real time elapsed on the host
+host_inst_rate                                1170283                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1659492                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2220265254                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 240448                       # Number of bytes of host memory used
+host_seconds                                    60.13                       # Real time elapsed on the host
 sim_insts                                    70373628                       # Number of instructions simulated
 sim_ops                                      99791654                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst            273728                       # Number of bytes read from this memory
@@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data             125054                       # Nu
 system.physmem.num_reads::total                129331                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks           84428                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                84428                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst              2059269                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             60210396                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                62269665                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         2059269                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            2059269                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          40649985                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               40649985                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          40649985                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             2059269                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            60210396                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              102919650                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst              2050195                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             59945083                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                61995278                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         2050195                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            2050195                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          40470864                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               40470864                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          40470864                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             2050195                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            59945083                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              102466142                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -77,7 +77,7 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                 1946                       # Number of system calls
-system.cpu.numCycles                        265849640                       # number of cpu cycles simulated
+system.cpu.numCycles                        267026272                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                    70373628                       # Number of instructions committed
@@ -96,18 +96,18 @@ system.cpu.num_mem_refs                      47862847                       # nu
 system.cpu.num_load_insts                    27307108                       # Number of load instructions
 system.cpu.num_store_insts                   20555739                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  265849640                       # Number of busy cycles
+system.cpu.num_busy_cycles                  267026272                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                  16890                       # number of replacements
-system.cpu.icache.tagsinuse               1736.286948                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse               1735.470121                       # Cycle average of tags in use
 system.cpu.icache.total_refs                 78126161                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                  18908                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                4131.910355                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst    1736.286948                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.847796                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.847796                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst    1735.470121                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.847398                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.847398                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst     78126161                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total        78126161                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst      78126161                       # number of demand (read+write) hits
@@ -120,12 +120,12 @@ system.cpu.icache.demand_misses::cpu.inst        18908                       # n
 system.cpu.icache.demand_misses::total          18908                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst        18908                       # number of overall misses
 system.cpu.icache.overall_misses::total         18908                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    444346000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    444346000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    444346000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    444346000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    444346000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    444346000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    445311000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    445311000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    445311000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    445311000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    445311000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    445311000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst     78145069                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total     78145069                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst     78145069                       # number of demand (read+write) accesses
@@ -138,12 +138,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000242
 system.cpu.icache.demand_miss_rate::total     0.000242                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000242                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000242                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23500.423101                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 23500.423101                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 23500.423101                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 23500.423101                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 23500.423101                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 23500.423101                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23551.459700                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 23551.459700                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 23551.459700                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 23551.459700                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 23551.459700                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 23551.459700                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -158,34 +158,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst        18908
 system.cpu.icache.demand_mshr_misses::total        18908                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst        18908                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total        18908                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    387622000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    387622000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    387622000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    387622000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    387622000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    387622000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    388587000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    388587000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    388587000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    388587000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    388587000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    388587000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000242                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000242                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000242                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000242                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000242                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000242                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20500.423101                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20500.423101                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20500.423101                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 20500.423101                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20500.423101                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 20500.423101                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20551.459700                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20551.459700                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20551.459700                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 20551.459700                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20551.459700                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 20551.459700                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                 155902                       # number of replacements
-system.cpu.dcache.tagsinuse               4076.906689                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               4076.664624                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                 46862074                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                 159998                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                 292.891624                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle             1079631000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4076.906689                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.995339                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.995339                       # Average percentage of cache occupancy
+system.cpu.dcache.warmup_cycle             1111220000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4076.664624                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.995279                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.995279                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data     27087367                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        27087367                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     19742869                       # number of WriteReq hits
@@ -206,14 +206,14 @@ system.cpu.dcache.demand_misses::cpu.data       159998                       # n
 system.cpu.dcache.demand_misses::total         159998                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data       159998                       # number of overall misses
 system.cpu.dcache.overall_misses::total        159998                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   1695470000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   1695470000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   5796770000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   5796770000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data   7492240000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total   7492240000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data   7492240000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total   7492240000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   1699159000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   1699159000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   5797120000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   5797120000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data   7496279000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total   7496279000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data   7496279000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total   7496279000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data     27140333                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total     27140333                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     19849901                       # number of WriteReq accesses(hits+misses)
@@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.003405
 system.cpu.dcache.demand_miss_rate::total     0.003405                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.003405                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.003405                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32010.535060                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 32010.535060                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54159.223410                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 54159.223410                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 46827.085339                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 46827.085339                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 46827.085339                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 46827.085339                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32080.183514                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 32080.183514                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54162.493460                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 54162.493460                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 46852.329404                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 46852.329404                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 46852.329404                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 46852.329404                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data       159998
 system.cpu.dcache.demand_mshr_misses::total       159998                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data       159998                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total       159998                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   1536572000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   1536572000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5475674000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   5475674000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data   7012246000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total   7012246000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data   7012246000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total   7012246000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   1540261000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   1540261000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5476024000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   5476024000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   7016285000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   7016285000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data   7016285000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   7016285000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.001952                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.001952                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005392                       # mshr miss rate for WriteReq accesses
@@ -276,28 +276,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.003405
 system.cpu.dcache.demand_mshr_miss_rate::total     0.003405                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.003405                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.003405                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29010.535060                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29010.535060                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51159.223410                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51159.223410                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43827.085339                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 43827.085339                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43827.085339                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 43827.085339                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29080.183514                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29080.183514                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51162.493460                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51162.493460                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43852.329404                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 43852.329404                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43852.329404                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 43852.329404                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                 96735                       # number of replacements
-system.cpu.l2cache.tagsinuse             28872.647154                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse             28857.116422                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                   71387                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                127516                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.559828                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 26446.371833                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst    949.934371                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data   1476.340950                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.807079                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst     0.028990                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.045054                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.881123                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::writebacks 26427.849240                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst    949.438432                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data   1479.828749                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.806514                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.028975                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.045161                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.880649                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst        14631                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data        30253                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total          44884                       # number of ReadReq hits
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini
index 480848980..221d86591 100644
--- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini
@@ -148,7 +148,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
@@ -180,7 +180,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout
index 2acf8263c..98fb0b2cd 100755
--- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout
@@ -1,11 +1,11 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:06:58
-gem5 started Jun 28 2012 22:58:54
+gem5 compiled Jul  2 2012 08:54:18
+gem5 started Jul  2 2012 12:32:55
 gem5 executing on zizzer
 command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
-Exiting @ tick 202680458000 because target called exit()
+Exiting @ tick 204097192000 because target called exit()
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
index b1d40b1a6..a6ef18324 100644
--- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.202680                       # Number of seconds simulated
-sim_ticks                                202680458000                       # Number of ticks simulated
-final_tick                               202680458000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.204097                       # Number of seconds simulated
+sim_ticks                                204097192000                       # Number of ticks simulated
+final_tick                               204097192000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1918134                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1942970                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2892641209                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 229316                       # Number of bytes of host memory used
-host_seconds                                    70.07                       # Real time elapsed on the host
+host_inst_rate                                1236624                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1252636                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1877926206                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 229284                       # Number of bytes of host memory used
+host_seconds                                   108.68                       # Real time elapsed on the host
 sim_insts                                   134398975                       # Number of instructions simulated
 sim_ops                                     136139203                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst            665664                       # Number of bytes read from this memory
@@ -23,19 +23,19 @@ system.physmem.num_reads::cpu.data             123533                       # Nu
 system.physmem.num_reads::total                133934                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks           82834                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                82834                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst              3284303                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             39007767                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                42292069                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         3284303                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            3284303                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          26156325                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               26156325                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          26156325                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             3284303                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            39007767                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               68448395                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst              3261505                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             38736995                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                41998500                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         3261505                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            3261505                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          25974762                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               25974762                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          25974762                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             3261505                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            38736995                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               67973262                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                 1946                       # Number of system calls
-system.cpu.numCycles                        405360916                       # number of cpu cycles simulated
+system.cpu.numCycles                        408194384                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   134398975                       # Number of instructions committed
@@ -54,18 +54,18 @@ system.cpu.num_mem_refs                      58160249                       # nu
 system.cpu.num_load_insts                    37275868                       # Number of load instructions
 system.cpu.num_store_insts                   20884381                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  405360916                       # Number of busy cycles
+system.cpu.num_busy_cycles                  408194384                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                 184976                       # number of replacements
-system.cpu.icache.tagsinuse               2004.741762                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse               2004.409813                       # Cycle average of tags in use
 system.cpu.icache.total_refs                134366560                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                 187024                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                 718.445547                       # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle           144318639000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst    2004.741762                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.978878                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.978878                       # Average percentage of cache occupancy
+system.cpu.icache.warmup_cycle           145330300000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::cpu.inst    2004.409813                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.978716                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.978716                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst    134366560                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total       134366560                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst     134366560                       # number of demand (read+write) hits
@@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst       187024                       # n
 system.cpu.icache.demand_misses::total         187024                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst       187024                       # number of overall misses
 system.cpu.icache.overall_misses::total        187024                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   3055178000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   3055178000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   3055178000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   3055178000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   3055178000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   3055178000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   3060544000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   3060544000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   3060544000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   3060544000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   3060544000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   3060544000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst    134553584                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total    134553584                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst    134553584                       # number of demand (read+write) accesses
@@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.001390
 system.cpu.icache.demand_miss_rate::total     0.001390                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.001390                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.001390                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16335.753700                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 16335.753700                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 16335.753700                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 16335.753700                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 16335.753700                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 16335.753700                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16364.445205                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 16364.445205                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 16364.445205                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 16364.445205                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 16364.445205                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 16364.445205                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -116,34 +116,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst       187024
 system.cpu.icache.demand_mshr_misses::total       187024                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst       187024                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total       187024                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   2494106000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total   2494106000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst   2494106000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total   2494106000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst   2494106000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total   2494106000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   2499472000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total   2499472000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   2499472000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   2499472000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst   2499472000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total   2499472000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.001390                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.001390                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.001390                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.001390                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.001390                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.001390                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13335.753700                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13335.753700                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13335.753700                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 13335.753700                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13335.753700                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 13335.753700                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13364.445205                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13364.445205                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13364.445205                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 13364.445205                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13364.445205                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 13364.445205                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                 146582                       # number of replacements
-system.cpu.dcache.tagsinuse               4087.606333                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               4087.412837                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                 57960843                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                 150678                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                 384.666925                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              776708000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4087.606333                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.997951                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.997951                       # Average percentage of cache occupancy
+system.cpu.dcache.warmup_cycle              812044000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4087.412837                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.997904                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.997904                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data     37185802                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        37185802                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     20759140                       # number of WriteReq hits
@@ -164,16 +164,16 @@ system.cpu.dcache.demand_misses::cpu.data       150663                       # n
 system.cpu.dcache.demand_misses::total         150663                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data       150663                       # number of overall misses
 system.cpu.dcache.overall_misses::total        150663                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   1569302000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   1569302000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   5728156000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   5728156000                       # number of WriteReq miss cycles
-system.cpu.dcache.SwapReq_miss_latency::cpu.data       420000                       # number of SwapReq miss cycles
-system.cpu.dcache.SwapReq_miss_latency::total       420000                       # number of SwapReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data   7297458000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total   7297458000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data   7297458000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total   7297458000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   1571682000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   1571682000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   5728295000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   5728295000                       # number of WriteReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency::cpu.data       430000                       # number of SwapReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency::total       430000                       # number of SwapReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data   7299977000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total   7299977000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data   7299977000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total   7299977000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data     37231301                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total     37231301                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     20864304                       # number of WriteReq accesses(hits+misses)
@@ -194,16 +194,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.002593
 system.cpu.dcache.demand_miss_rate::total     0.002593                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.002593                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.002593                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34490.911888                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 34490.911888                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54468.791602                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 54468.791602                       # average WriteReq miss latency
-system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data        28000                       # average SwapReq miss latency
-system.cpu.dcache.SwapReq_avg_miss_latency::total        28000                       # average SwapReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 48435.634496                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 48435.634496                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 48435.634496                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 48435.634496                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34543.220730                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 34543.220730                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54470.113347                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 54470.113347                       # average WriteReq miss latency
+system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 28666.666667                       # average SwapReq miss latency
+system.cpu.dcache.SwapReq_avg_miss_latency::total 28666.666667                       # average SwapReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 48452.353929                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 48452.353929                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 48452.353929                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 48452.353929                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -224,16 +224,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data       150663
 system.cpu.dcache.demand_mshr_misses::total       150663                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data       150663                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total       150663                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   1432805000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   1432805000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5412664000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   5412664000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data       375000                       # number of SwapReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_latency::total       375000                       # number of SwapReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data   6845469000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total   6845469000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data   6845469000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total   6845469000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   1435185000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   1435185000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5412803000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   5412803000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data       385000                       # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency::total       385000                       # number of SwapReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   6847988000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   6847988000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data   6847988000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   6847988000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.001222                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.001222                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005040                       # mshr miss rate for WriteReq accesses
@@ -244,30 +244,30 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002593
 system.cpu.dcache.demand_mshr_miss_rate::total     0.002593                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002593                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.002593                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31490.911888                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31490.911888                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51468.791602                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51468.791602                       # average WriteReq mshr miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data        25000                       # average SwapReq mshr miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total        25000                       # average SwapReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45435.634496                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 45435.634496                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45435.634496                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 45435.634496                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31543.220730                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31543.220730                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51470.113347                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51470.113347                       # average WriteReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 25666.666667                       # average SwapReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 25666.666667                       # average SwapReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45452.353929                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 45452.353929                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45452.353929                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 45452.353929                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                101560                       # number of replacements
-system.cpu.l2cache.tagsinuse             29288.840921                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse             29278.940429                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                  222505                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                132357                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  1.681097                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 24773.097821                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst   3265.951230                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data   1249.791870                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.756015                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst     0.099669                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.038141                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.893824                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::writebacks 24760.226438                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst   3263.271337                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data   1255.442654                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.755622                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.099587                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.038313                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.893522                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst       176623                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data        23301                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total         199924                       # number of ReadReq hits
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini
index 4a4e79f41..38e3365ee 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini
@@ -181,7 +181,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
@@ -213,7 +213,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout
index 74ab835bf..1e72565e9 100755
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:05:18
-gem5 started Jun 28 2012 22:25:40
+gem5 compiled Jul  2 2012 08:30:56
+gem5 started Jul  2 2012 10:10:01
 gem5 executing on zizzer
 command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/inorder-timing
 Global frequency set at 1000000000000 ticks per second
@@ -23,4 +23,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 991340143500 because target called exit()
+Exiting @ tick 996061088500 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
index 35d38838f..def42a9fe 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
@@ -1,59 +1,59 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.991340                       # Number of seconds simulated
-sim_ticks                                991340143500                       # Number of ticks simulated
-final_tick                               991340143500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.996061                       # Number of seconds simulated
+sim_ticks                                996061088500                       # Number of ticks simulated
+final_tick                               996061088500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 147354                       # Simulator instruction rate (inst/s)
-host_op_rate                                   147354                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               80272080                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 218972                       # Number of bytes of host memory used
-host_seconds                                 12349.75                       # Real time elapsed on the host
+host_inst_rate                                 139633                       # Simulator instruction rate (inst/s)
+host_op_rate                                   139633                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               76428343                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 218940                       # Number of bytes of host memory used
+host_seconds                                 13032.61                       # Real time elapsed on the host
 sim_insts                                  1819780127                       # Number of instructions simulated
 sim_ops                                    1819780127                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             54976                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         137579712                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            137634688                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         137579648                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            137634624                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read::cpu.inst        54976                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total           54976                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     67105088                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          67105088                       # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks     67105024                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          67105024                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.inst                859                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            2149683                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               2150542                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1048517                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1048517                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                55456                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            138781540                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               138836996                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           55456                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              55456                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          67691285                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               67691285                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          67691285                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               55456                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           138781540                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              206528281                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_reads::cpu.data            2149682                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               2150541                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1048516                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1048516                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst                55193                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            138123705                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               138178898                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           55193                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              55193                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          67370390                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               67370390                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          67370390                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               55193                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           138123705                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              205549288                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    444614343                       # DTB read hits
+system.cpu.dtb.read_hits                    444620723                       # DTB read hits
 system.cpu.dtb.read_misses                    4897078                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                449511421                       # DTB read accesses
-system.cpu.dtb.write_hits                   160920087                       # DTB write hits
+system.cpu.dtb.read_accesses                449517801                       # DTB read accesses
+system.cpu.dtb.write_hits                   160920434                       # DTB write hits
 system.cpu.dtb.write_misses                   1701304                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses               162621391                       # DTB write accesses
-system.cpu.dtb.data_hits                    605534430                       # DTB hits
+system.cpu.dtb.write_accesses               162621738                       # DTB write accesses
+system.cpu.dtb.data_hits                    605541157                       # DTB hits
 system.cpu.dtb.data_misses                    6598382                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                612132812                       # DTB accesses
-system.cpu.itb.fetch_hits                   232194533                       # ITB hits
+system.cpu.dtb.data_accesses                612139539                       # DTB accesses
+system.cpu.itb.fetch_hits                   232151959                       # ITB hits
 system.cpu.itb.fetch_misses                        22                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses               232194555                       # ITB accesses
+system.cpu.itb.fetch_accesses               232151981                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -67,42 +67,42 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   29                       # Number of system calls
-system.cpu.numCycles                       1982680288                       # number of cpu cycles simulated
+system.cpu.numCycles                       1992122178                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.branch_predictor.lookups         328915928                       # Number of BP lookups
-system.cpu.branch_predictor.condPredicted    253819011                       # Number of conditional branches predicted
-system.cpu.branch_predictor.condIncorrect    140072488                       # Number of conditional branches incorrect
-system.cpu.branch_predictor.BTBLookups      231593889                       # Number of BTB lookups
-system.cpu.branch_predictor.BTBHits         138169193                       # Number of BTB hits
+system.cpu.branch_predictor.lookups         328832264                       # Number of BP lookups
+system.cpu.branch_predictor.condPredicted    253784019                       # Number of conditional branches predicted
+system.cpu.branch_predictor.condIncorrect    139998376                       # Number of conditional branches incorrect
+system.cpu.branch_predictor.BTBLookups      232594122                       # Number of BTB lookups
+system.cpu.branch_predictor.BTBHits         138120343                       # Number of BTB hits
 system.cpu.branch_predictor.usedRAS          16767439                       # Number of times the RAS was used to get a target.
 system.cpu.branch_predictor.RASInCorrect            6                       # Number of incorrect RAS predictions.
-system.cpu.branch_predictor.BTBHitPct       59.660120                       # BTB Hit Percentage
-system.cpu.branch_predictor.predictedTaken    175201939                       # Number of Branches Predicted As Taken (True).
-system.cpu.branch_predictor.predictedNotTaken    153713989                       # Number of Branches Predicted As Not Taken (False).
-system.cpu.regfile_manager.intRegFileReads   1669764044                       # Number of Reads from Int. Register File
+system.cpu.branch_predictor.BTBHitPct       59.382560                       # BTB Hit Percentage
+system.cpu.branch_predictor.predictedTaken    175107833                       # Number of Branches Predicted As Taken (True).
+system.cpu.branch_predictor.predictedNotTaken    153724431                       # Number of Branches Predicted As Not Taken (False).
+system.cpu.regfile_manager.intRegFileReads   1669698374                       # Number of Reads from Int. Register File
 system.cpu.regfile_manager.intRegFileWrites   1376202617                       # Number of Writes to Int. Register File
-system.cpu.regfile_manager.intRegFileAccesses   3045966661                       # Total Accesses (Read+Write) to the Int. Register File
-system.cpu.regfile_manager.floatRegFileReads          236                       # Number of Reads from FP Register File
+system.cpu.regfile_manager.intRegFileAccesses   3045900991                       # Total Accesses (Read+Write) to the Int. Register File
+system.cpu.regfile_manager.floatRegFileReads          237                       # Number of Reads from FP Register File
 system.cpu.regfile_manager.floatRegFileWrites          345                       # Number of Writes to FP Register File
-system.cpu.regfile_manager.floatRegFileAccesses          581                       # Total Accesses (Read+Write) to the FP Register File
-system.cpu.regfile_manager.regForwards      651015392                       # Number of Registers Read Through Forwarding Logic
-system.cpu.agen_unit.agens                  617989806                       # Number of Address Generations
-system.cpu.execution_unit.predictedTakenIncorrect    121318277                       # Number of Branches Incorrectly Predicted As Taken.
-system.cpu.execution_unit.predictedNotTakenIncorrect     12155753                       # Number of Branches Incorrectly Predicted As Not Taken).
-system.cpu.execution_unit.mispredicted      133474030                       # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.predicted          81726039                       # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.mispredictPct     62.023228                       # Percentage of Incorrect Branches Predicts
-system.cpu.execution_unit.executions       1139614733                       # Number of Instructions Executed.
+system.cpu.regfile_manager.floatRegFileAccesses          582                       # Total Accesses (Read+Write) to the FP Register File
+system.cpu.regfile_manager.regForwards      651085046                       # Number of Registers Read Through Forwarding Logic
+system.cpu.agen_unit.agens                  617993265                       # Number of Address Generations
+system.cpu.execution_unit.predictedTakenIncorrect    121277812                       # Number of Branches Incorrectly Predicted As Taken.
+system.cpu.execution_unit.predictedNotTakenIncorrect     12122106                       # Number of Branches Incorrectly Predicted As Not Taken).
+system.cpu.execution_unit.mispredicted      133399918                       # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.predicted          81800180                       # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.mispredictPct     61.988781                       # Percentage of Incorrect Branches Predicts
+system.cpu.execution_unit.executions       1139625101                       # Number of Instructions Executed.
 system.cpu.mult_div_unit.multiplies                75                       # Number of Multipy Operations Executed
 system.cpu.mult_div_unit.divides                    0                       # Number of Divide Operations Executed
 system.cpu.contextSwitches                          1                       # Number of context switches
-system.cpu.threadCycles                    1746574278                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles                    1749883167                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
 system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled                         7486032                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                       405569141                       # Number of cycles cpu's stages were not processed
-system.cpu.runCycles                       1577111147                       # Number of cycles cpu stages are processed.
-system.cpu.activity                         79.544400                       # Percentage of cycles cpu is active
+system.cpu.timesIdled                         7972682                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                       415150633                       # Number of cycles cpu's stages were not processed
+system.cpu.runCycles                       1576971545                       # Number of cycles cpu stages are processed.
+system.cpu.activity                         79.160383                       # Percentage of cycles cpu is active
 system.cpu.comLoads                         444595663                       # Number of Load instructions committed
 system.cpu.comStores                        160728502                       # Number of Store instructions committed
 system.cpu.comBranches                      214632552                       # Number of Branches instructions committed
@@ -114,144 +114,144 @@ system.cpu.committedInsts                  1819780127                       # Nu
 system.cpu.committedOps                    1819780127                       # Number of Ops committed (Per-Thread)
 system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
 system.cpu.committedInsts_total            1819780127                       # Number of Instructions committed (Total)
-system.cpu.cpi                               1.089516                       # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi                               1.094705                       # CPI: Cycles Per Instruction (Per-Thread)
 system.cpu.smt_cpi                                nan                       # CPI: Total SMT-CPI
-system.cpu.cpi_total                         1.089516                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.917838                       # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.cpi_total                         1.094705                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.913488                       # IPC: Instructions Per Cycle (Per-Thread)
 system.cpu.smt_ipc                                nan                       # IPC: Total SMT-IPC
-system.cpu.ipc_total                         0.917838                       # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles                791779407                       # Number of cycles 0 instructions are processed.
-system.cpu.stage0.runCycles                1190900881                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization               60.065200                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles               1050371352                       # Number of cycles 0 instructions are processed.
-system.cpu.stage1.runCycles                 932308936                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization               47.022656                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles               1008674680                       # Number of cycles 0 instructions are processed.
-system.cpu.stage2.runCycles                 974005608                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization               49.125702                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles               1572973951                       # Number of cycles 0 instructions are processed.
-system.cpu.stage3.runCycles                 409706337                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization               20.664266                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles                959730175                       # Number of cycles 0 instructions are processed.
-system.cpu.stage4.runCycles                1022950113                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization               51.594305                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.ipc_total                         0.913488                       # IPC: Total IPC of All Threads
+system.cpu.stage0.idleCycles                801357098                       # Number of cycles 0 instructions are processed.
+system.cpu.stage0.runCycles                1190765080                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.utilization               59.773697                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles               1059714238                       # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles                 932407940                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization               46.804757                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles               1018188148                       # Number of cycles 0 instructions are processed.
+system.cpu.stage2.runCycles                 973934030                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage2.utilization               48.889272                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles               1582467246                       # Number of cycles 0 instructions are processed.
+system.cpu.stage3.runCycles                 409654932                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage3.utilization               20.563745                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles                969329070                       # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles                1022793108                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization               51.341887                       # Percentage of cycles stage was utilized (processing insts).
 system.cpu.icache.replacements                      1                       # number of replacements
-system.cpu.icache.tagsinuse                666.725255                       # Cycle average of tags in use
-system.cpu.icache.total_refs                232193463                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                666.783228                       # Cycle average of tags in use
+system.cpu.icache.total_refs                232150871                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    859                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs               270306.708964                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs               270257.125728                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     666.725255                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.325549                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.325549                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst    232193463                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       232193463                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     232193463                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        232193463                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    232193463                       # number of overall hits
-system.cpu.icache.overall_hits::total       232193463                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         1067                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          1067                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         1067                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           1067                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         1067                       # number of overall misses
-system.cpu.icache.overall_misses::total          1067                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     58495000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     58495000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     58495000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     58495000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     58495000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     58495000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    232194530                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    232194530                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    232194530                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    232194530                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    232194530                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    232194530                       # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::cpu.inst     666.783228                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.325578                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.325578                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst    232150871                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       232150871                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     232150871                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        232150871                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    232150871                       # number of overall hits
+system.cpu.icache.overall_hits::total       232150871                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1085                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1085                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1085                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1085                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1085                       # number of overall misses
+system.cpu.icache.overall_misses::total          1085                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     60468000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     60468000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     60468000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     60468000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     60468000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     60468000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    232151956                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    232151956                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    232151956                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    232151956                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    232151956                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    232151956                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000005                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000005                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000005                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000005                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000005                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000005                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54821.930647                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 54821.930647                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 54821.930647                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 54821.930647                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 54821.930647                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 54821.930647                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55730.875576                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 55730.875576                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 55730.875576                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 55730.875576                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 55730.875576                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 55730.875576                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets        85000                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets       114500                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               3                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               5                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets 28333.333333                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets        22900                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          208                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          208                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          208                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          208                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          208                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          208                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          226                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          226                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          226                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          226                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          226                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          226                       # number of overall MSHR hits
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          859                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total          859                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst          859                       # number of demand (read+write) MSHR misses
 system.cpu.icache.demand_mshr_misses::total          859                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          859                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          859                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     45935000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     45935000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     45935000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     45935000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     45935000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     45935000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     47379000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     47379000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     47379000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     47379000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     47379000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     47379000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000004                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000004                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000004                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000004                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000004                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000004                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53474.970896                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53474.970896                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53474.970896                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 53474.970896                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53474.970896                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 53474.970896                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55155.995343                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55155.995343                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55155.995343                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 55155.995343                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55155.995343                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 55155.995343                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                9107366                       # number of replacements
-system.cpu.dcache.tagsinuse               4082.290547                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                595076211                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                9111462                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  65.310727                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle            12667784000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4082.290547                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.996653                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.996653                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data    437271439                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       437271439                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    157804772                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      157804772                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data     595076211                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        595076211                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    595076211                       # number of overall hits
-system.cpu.dcache.overall_hits::total       595076211                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      7324224                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       7324224                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      2923730                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      2923730                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data     10247954                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total       10247954                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data     10247954                       # number of overall misses
-system.cpu.dcache.overall_misses::total      10247954                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 162150578000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 162150578000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 105068682500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 105068682500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 267219260500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 267219260500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 267219260500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 267219260500                       # number of overall miss cycles
+system.cpu.dcache.replacements                9107309                       # number of replacements
+system.cpu.dcache.tagsinuse               4082.354199                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                595073835                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                9111405                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  65.310875                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle            12655884000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4082.354199                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.996669                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.996669                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data    437271435                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       437271435                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    157802400                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      157802400                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     595073835                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        595073835                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    595073835                       # number of overall hits
+system.cpu.dcache.overall_hits::total       595073835                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      7324228                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       7324228                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      2926102                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      2926102                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data     10250330                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total       10250330                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data     10250330                       # number of overall misses
+system.cpu.dcache.overall_misses::total      10250330                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 166496556500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 166496556500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 130053734500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 130053734500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 296550291000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 296550291000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 296550291000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 296550291000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data    444595663                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total    444595663                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    160728502                       # number of WriteReq accesses(hits+misses)
@@ -262,54 +262,54 @@ system.cpu.dcache.overall_accesses::cpu.data    605324165
 system.cpu.dcache.overall_accesses::total    605324165                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.016474                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.016474                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.018190                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.018190                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.016930                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.016930                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.016930                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.016930                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22138.943047                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 22138.943047                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35936.520301                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 35936.520301                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 26075.376656                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 26075.376656                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 26075.376656                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 26075.376656                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs     10790500                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets   7928721000                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs              2625                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets          208163                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs  4110.666667                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 38089.002368                       # average number of cycles each access was blocked
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.018205                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.018205                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.016934                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.016934                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.016934                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.016934                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22732.301138                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 22732.301138                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44446.070062                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 44446.070062                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 28930.804277                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 28930.804277                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 28930.804277                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 28930.804277                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs     76478500                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets   8150814500                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs             14619                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets          208452                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  5231.445379                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 39101.637307                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      3389687                       # number of writebacks
-system.cpu.dcache.writebacks::total           3389687                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       101944                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       101944                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1034548                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      1034548                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1136492                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1136492                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1136492                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1136492                       # number of overall MSHR hits
+system.cpu.dcache.writebacks::writebacks      3389633                       # number of writebacks
+system.cpu.dcache.writebacks::total           3389633                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       101948                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       101948                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1036977                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      1036977                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      1138925                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1138925                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1138925                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1138925                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7222280                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total      7222280                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1889182                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      1889182                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      9111462                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      9111462                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      9111462                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      9111462                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 137265020500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 137265020500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  54890953000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  54890953000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 192155973500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 192155973500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 192155973500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 192155973500                       # number of overall MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1889125                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      1889125                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      9111405                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      9111405                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      9111405                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      9111405                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 140938235500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 140938235500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  71711487500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  71711487500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 212649723000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 212649723000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 212649723000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 212649723000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.016245                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.016245                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.011754                       # mshr miss rate for WriteReq accesses
@@ -318,149 +318,149 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.015052
 system.cpu.dcache.demand_mshr_miss_rate::total     0.015052                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.015052                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.015052                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19005.773869                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19005.773869                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29055.407579                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29055.407579                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21089.477572                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 21089.477572                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21089.477572                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 21089.477572                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19514.368800                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19514.368800                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37960.160127                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37960.160127                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23338.850924                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 23338.850924                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23338.850924                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 23338.850924                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.replacements               2133759                       # number of replacements
-system.cpu.l2cache.tagsinuse             30545.371941                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 8448402                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs               2163450                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  3.905060                       # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle          183782202000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 14422.538140                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst     34.487886                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data  16088.345915                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.440141                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst     0.001052                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.490977                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.932171                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.data      5860988                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        5860988                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      3389687                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      3389687                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1100791                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1100791                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.data      6961779                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         6961779                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.data      6961779                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        6961779                       # number of overall hits
+system.cpu.l2cache.replacements               2133758                       # number of replacements
+system.cpu.l2cache.tagsinuse             30551.127244                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 8448350                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs               2163449                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  3.905038                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle          184402684000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::writebacks 14423.839124                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst     34.322166                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data  16092.965953                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.440181                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.001047                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.491118                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.932346                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.data      5860987                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        5860987                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      3389633                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      3389633                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data      1100736                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total      1100736                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.data      6961723                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         6961723                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.data      6961723                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        6961723                       # number of overall hits
 system.cpu.l2cache.ReadReq_misses::cpu.inst          859                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data      1360850                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total      1361709                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       788833                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       788833                       # number of ReadExReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data      1360852                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total      1361711                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       788830                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       788830                       # number of ReadExReq misses
 system.cpu.l2cache.demand_misses::cpu.inst          859                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data      2149683                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total       2150542                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data      2149682                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total       2150541                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst          859                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data      2149683                       # number of overall misses
-system.cpu.l2cache.overall_misses::total      2150542                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     44957500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data  71113174500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total  71158132000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  41236980000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  41236980000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     44957500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 112350154500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 112395112000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     44957500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 112350154500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 112395112000                       # number of overall miss cycles
+system.cpu.l2cache.overall_misses::cpu.data      2149682                       # number of overall misses
+system.cpu.l2cache.overall_misses::total      2150541                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     46160000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data  71425674500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total  71471834500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  41981087000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  41981087000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     46160000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 113406761500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 113452921500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     46160000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 113406761500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 113452921500                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst          859                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      7221838                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      7222697                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      3389687                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      3389687                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data      1889624                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total      1889624                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      7221839                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      7222698                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      3389633                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      3389633                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data      1889566                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total      1889566                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.inst          859                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      9111462                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      9112321                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      9111405                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      9112264                       # number of demand (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.inst          859                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      9111462                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      9112321                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      9111405                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      9112264                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst            1                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.188435                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.188436                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::total     0.188532                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.417455                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.417455                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.417466                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.417466                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.235932                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.236004                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.235933                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.236005                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.235932                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.236004                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52337.019790                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52256.438623                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 52256.489456                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52275.931661                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52275.931661                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52337.019790                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52263.591655                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52263.620985                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52337.019790                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52263.591655                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52263.620985                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs       580500                       # number of cycles access was blocked
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.235933                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.236005                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53736.903376                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52485.997375                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 52486.786477                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53219.435113                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53219.435113                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53736.903376                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52755.133783                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 52755.525935                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53736.903376                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52755.133783                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 52755.525935                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs      3381000                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs               70                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs              111                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs  8292.857143                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs 30459.459459                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks      1048517                       # number of writebacks
-system.cpu.l2cache.writebacks::total          1048517                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks      1048516                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1048516                       # number of writebacks
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          859                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data      1360850                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total      1361709                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       788833                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       788833                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data      1360852                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total      1361711                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       788830                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       788830                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.inst          859                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data      2149683                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total      2150542                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data      2149682                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total      2150541                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          859                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data      2149683                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total      2150542                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     34481000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  54466888500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  54501369500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  31621283000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  31621283000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     34481000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  86088171500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  86122652500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     34481000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  86088171500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  86122652500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_misses::cpu.data      2149682                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total      2150541                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     35698000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  54780311000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  54816009000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  32410594000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  32410594000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     35698000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  87190905000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  87226603000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     35698000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  87190905000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  87226603000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.188435                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.188436                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.188532                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.417455                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.417455                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.417466                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.417466                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.235932                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.236004                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.235933                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.236005                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.235932                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.236004                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40140.861467                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40024.167616                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40024.241229                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40086.156385                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40086.156385                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40140.861467                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40046.914592                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40046.952117                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40140.861467                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40046.914592                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40046.952117                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.235933                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.236005                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41557.625146                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40254.422230                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40255.244321                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41086.918601                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41086.918601                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41557.625146                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40559.908396                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40560.306918                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41557.625146                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40559.908396                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40560.306918                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
index b3f63cedd..2f4837fe9 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
@@ -479,7 +479,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
@@ -511,7 +511,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout
index 41442f622..3e5b31249 100755
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:05:18
-gem5 started Jun 28 2012 22:26:23
+gem5 compiled Jul  2 2012 08:30:56
+gem5 started Jul  2 2012 10:10:10
 gem5 executing on zizzer
 command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
@@ -23,4 +23,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 607216877500 because target called exit()
+Exiting @ tick 621254733000 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
index 66e8bd283..3ccb6ec23 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,59 +1,59 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.607217                       # Number of seconds simulated
-sim_ticks                                607216877500                       # Number of ticks simulated
-final_tick                               607216877500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.621255                       # Number of seconds simulated
+sim_ticks                                621254733000                       # Number of ticks simulated
+final_tick                               621254733000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 209626                       # Simulator instruction rate (inst/s)
-host_op_rate                                   209626                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               73321119                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 219996                       # Number of bytes of host memory used
-host_seconds                                  8281.61                       # Real time elapsed on the host
+host_inst_rate                                 206958                       # Simulator instruction rate (inst/s)
+host_op_rate                                   206958                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               74061263                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 219968                       # Number of bytes of host memory used
+host_seconds                                  8388.39                       # Real time elapsed on the host
 sim_insts                                  1736043781                       # Number of instructions simulated
 sim_ops                                    1736043781                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst             61952                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         138164352                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            138226304                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        61952                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           61952                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     67205952                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          67205952                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst                968                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            2158818                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               2159786                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1050093                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1050093                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               102026                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            227537075                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               227639101                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          102026                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             102026                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks         110678663                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              110678663                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks         110678663                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              102026                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           227537075                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              338317764                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst             61888                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         138177216                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            138239104                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        61888                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           61888                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     67208512                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          67208512                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst                967                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            2159019                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               2159986                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1050133                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1050133                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst                99618                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            222416359                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               222515977                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           99618                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              99618                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks         108181891                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              108181891                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks         108181891                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               99618                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           222416359                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              330697869                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    612238035                       # DTB read hits
-system.cpu.dtb.read_misses                   10898868                       # DTB read misses
+system.cpu.dtb.read_hits                    614267388                       # DTB read hits
+system.cpu.dtb.read_misses                   10994218                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                623136903                       # DTB read accesses
-system.cpu.dtb.write_hits                   208056215                       # DTB write hits
-system.cpu.dtb.write_misses                   6766994                       # DTB write misses
+system.cpu.dtb.read_accesses                625261606                       # DTB read accesses
+system.cpu.dtb.write_hits                   208720588                       # DTB write hits
+system.cpu.dtb.write_misses                   6852950                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses               214823209                       # DTB write accesses
-system.cpu.dtb.data_hits                    820294250                       # DTB hits
-system.cpu.dtb.data_misses                   17665862                       # DTB misses
+system.cpu.dtb.write_accesses               215573538                       # DTB write accesses
+system.cpu.dtb.data_hits                    822987976                       # DTB hits
+system.cpu.dtb.data_misses                   17847168                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                837960112                       # DTB accesses
-system.cpu.itb.fetch_hits                   401011528                       # ITB hits
-system.cpu.itb.fetch_misses                        57                       # ITB misses
+system.cpu.dtb.data_accesses                840835144                       # DTB accesses
+system.cpu.itb.fetch_hits                   402675877                       # ITB hits
+system.cpu.itb.fetch_misses                        58                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses               401011585                       # ITB accesses
+system.cpu.itb.fetch_accesses               402675935                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -67,247 +67,247 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   29                       # Number of system calls
-system.cpu.numCycles                       1214433756                       # number of cpu cycles simulated
+system.cpu.numCycles                       1242509467                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                380951023                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted          293099658                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect           18933784                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups             266477220                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                262392566                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                383372990                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted          295235565                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect           19006052                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups             268408458                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                264104025                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                 25151704                       # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect                6168                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles          412376649                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     3157323952                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   380951023                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          287544270                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     576306152                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles               134891835                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles              111419989                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                   29                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          1063                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                 401011528                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes              10506825                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples         1209281794                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.610908                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.168401                       # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS                 25197943                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect                6076                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles          414160425                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     3172269212                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   383372990                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          289301968                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     579083206                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles               137694854                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles              132940581                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                   31                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles          1360                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                 402675877                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes              10477889                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples         1238022002                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.562369                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.158541                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                632975642     52.34%     52.34% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 43351030      3.58%     55.93% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 22268396      1.84%     57.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 40872577      3.38%     61.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                127179039     10.52%     71.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 63789232      5.27%     76.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 40665333      3.36%     80.30% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 30280275      2.50%     82.81% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                207900270     17.19%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                658938796     53.23%     53.23% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 43587849      3.52%     56.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 22400320      1.81%     58.56% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 41027424      3.31%     61.87% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                127967453     10.34%     72.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 63937343      5.16%     77.37% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 40820174      3.30%     80.67% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 30420264      2.46%     83.12% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                208922379     16.88%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1209281794                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.313686                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.599832                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                441212287                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              97730865                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 545630156                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              15531465                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles              109177021                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             60290905                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                  1025                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             3078047382                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                  2151                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles              109177021                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                462067522                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                51929068                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           5163                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 539154184                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              46948836                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             2995870549                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                446955                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                1708785                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents              42808765                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands          2241183009                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            3870137990                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       3868740839                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups           1397151                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total           1238022002                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.308547                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.553115                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                444879640                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             117490931                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 546452553                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              17363359                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles              111835519                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             60534072                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                   962                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             3092225969                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                  2145                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles              111835519                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                466447238                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                65379308                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           5467                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 540801711                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              53552759                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             3009893694                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                588891                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                2795172                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents              47908313                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands          2251120190                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            3888621958                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       3887220740                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups           1401218                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps            1376202963                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                864980046                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                207                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            206                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 100505126                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            676579077                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           251278116                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          61563067                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         34698773                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 2690247704                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.rename.UndoneMaps                874917227                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                215                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            214                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 112891088                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            679356489                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           252372715                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          62271668                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         36485662                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 2703868851                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqNonSpecInstsAdded                 183                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                2489728191                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           3267337                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       942739143                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    400071480                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued                2499086402                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           3468008                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       959949757                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    407382923                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved            154                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples    1209281794                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.058849                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.971213                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples    1238022002                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.018612                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.960549                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           378679312     31.31%     31.31% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           195809975     16.19%     47.51% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           182681515     15.11%     62.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           152412696     12.60%     75.22% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4           135959135     11.24%     86.46% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            80206603      6.63%     93.09% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            63601344      5.26%     98.35% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7            14610233      1.21%     99.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             5320981      0.44%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           396920026     32.06%     32.06% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           203237579     16.42%     48.48% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           185771607     15.01%     63.48% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           153281748     12.38%     75.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4           136530779     11.03%     86.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            79975547      6.46%     93.35% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            62882805      5.08%     98.43% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7            14212604      1.15%     99.58% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             5209307      0.42%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      1209281794                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1238022002                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 1977743     10.56%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               12229984     65.27%     75.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               4528924     24.17%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 1901972     10.18%     10.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     10.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     10.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     10.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     10.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     10.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     10.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     10.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     10.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     10.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     10.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     10.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     10.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     10.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     10.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     10.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     10.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     10.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     10.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     10.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     10.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     10.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     10.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     10.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     10.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     10.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     10.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     10.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     10.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               12247269     65.56%     75.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               4530432     24.25%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1627060855     65.35%     65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                  100      0.00%     65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                 286      0.00%     65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                  14      0.00%     65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                 171      0.00%     65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                 30      0.00%     65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                  25      0.00%     65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     65.35% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            640749326     25.74%     91.09% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           221917384      8.91%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1633606519     65.37%     65.37% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                   96      0.00%     65.37% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     65.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                 295      0.00%     65.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                  17      0.00%     65.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                 168      0.00%     65.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                 36      0.00%     65.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                  25      0.00%     65.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     65.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     65.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     65.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     65.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     65.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     65.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     65.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     65.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     65.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     65.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     65.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     65.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     65.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     65.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     65.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     65.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     65.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     65.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     65.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     65.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     65.37% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            642839630     25.72%     91.09% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           222639616      8.91%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             2489728191                       # Type of FU issued
-system.cpu.iq.rate                           2.050114                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    18736651                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.007526                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         6208757898                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        3631737993                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   2386612184                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads             1984266                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes            1351861                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses       870224                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             2507489711                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                  975131                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         57077193                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             2499086402                       # Type of FU issued
+system.cpu.iq.rate                           2.011322                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    18679673                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.007475                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         6256352202                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        3662566047                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   2395383662                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             1990285                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes            1357397                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses       872084                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             2516787863                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                  978212                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         57513083                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    231983414                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses       247523                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       104727                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     90549614                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads    234760826                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       254713                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       106352                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     91644213                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads          172                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        177103                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads          271                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        267185                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles              109177021                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                19521566                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                973961                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          2832586299                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts          17875212                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             676579077                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            251278116                       # Number of dispatched store instructions
+system.cpu.iew.iewSquashCycles              111835519                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                23640124                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               1166146                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          2847163562                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts          17865598                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             679356489                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            252372715                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts                183                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 178484                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 13307                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         104727                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect       13292243                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      8865054                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             22157297                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            2437364251                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             623138442                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          52363940                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewIQFullEvents                 265739                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 14899                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         106352                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect       13291147                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      8879247                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             22170394                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            2446896238                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             625263073                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          52190164                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                     142338412                       # number of nop insts executed
-system.cpu.iew.exec_refs                    837961692                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                298501873                       # Number of branches executed
-system.cpu.iew.exec_stores                  214823250                       # Number of stores executed
-system.cpu.iew.exec_rate                     2.006996                       # Inst execution rate
-system.cpu.iew.wb_sent                     2416135407                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    2387482408                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1367770503                       # num instructions producing a value
-system.cpu.iew.wb_consumers                1732591741                       # num instructions consuming a value
+system.cpu.iew.exec_nop                     143294528                       # number of nop insts executed
+system.cpu.iew.exec_refs                    840836661                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                299907540                       # Number of branches executed
+system.cpu.iew.exec_stores                  215573588                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.969318                       # Inst execution rate
+system.cpu.iew.wb_sent                     2424978134                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    2396255746                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1371174091                       # num instructions producing a value
+system.cpu.iew.wb_consumers                1736703047                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.965922                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.789436                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.928561                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.789527                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts     1819780126                       # The number of committed instructions
 system.cpu.commit.commitCommittedOps       1819780126                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts       773736355                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       793041487                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              29                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts          18932893                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples   1100104773                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.654188                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.513944                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts          19005172                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   1126186483                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.615878                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.496171                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    575678608     52.33%     52.33% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    180745216     16.43%     68.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     90628498      8.24%     77.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     53598095      4.87%     81.87% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     36474012      3.32%     85.19% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     28175112      2.56%     87.75% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     22568883      2.05%     89.80% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     23092069      2.10%     91.90% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     89144280      8.10%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    601057240     53.37%     53.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    181431262     16.11%     69.48% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     90818871      8.06%     77.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     53582935      4.76%     82.30% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     36462614      3.24%     85.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     28190767      2.50%     88.04% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     22584019      2.01%     90.05% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     22816288      2.03%     92.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     89242487      7.92%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   1100104773                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total   1126186483                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts           1819780126                       # Number of instructions committed
 system.cpu.commit.committedOps             1819780126                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -318,70 +318,70 @@ system.cpu.commit.branches                  214632552                       # Nu
 system.cpu.commit.fp_insts                     805525                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                1718967519                       # Number of committed integer instructions.
 system.cpu.commit.function_calls             16767440                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events              89144280                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events              89242487                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   3518697774                       # The number of ROB reads
-system.cpu.rob.rob_writes                  5296336807                       # The number of ROB writes
-system.cpu.timesIdled                          353272                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         5151962                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                   3563986409                       # The number of ROB reads
+system.cpu.rob.rob_writes                  5337596119                       # The number of ROB writes
+system.cpu.timesIdled                          386257                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         4487465                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                  1736043781                       # Number of Instructions Simulated
 system.cpu.committedOps                    1736043781                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total            1736043781                       # Number of Instructions Simulated
-system.cpu.cpi                               0.699541                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.699541                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.429509                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.429509                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               3277031179                       # number of integer regfile reads
-system.cpu.int_regfile_writes              1915203405                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                     51821                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                      555                       # number of floating regfile writes
+system.cpu.cpi                               0.715713                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.715713                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.397208                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.397208                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               3289961910                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1921843103                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                     52840                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                      576                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                      25                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
 system.cpu.icache.replacements                      1                       # number of replacements
-system.cpu.icache.tagsinuse                769.354058                       # Cycle average of tags in use
-system.cpu.icache.total_refs                401010025                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                    968                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs               414266.554752                       # Average number of references to valid blocks.
+system.cpu.icache.tagsinuse                769.288412                       # Cycle average of tags in use
+system.cpu.icache.total_refs                402674417                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    967                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               416416.149948                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     769.354058                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.375661                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.375661                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst    401010025                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       401010025                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     401010025                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        401010025                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    401010025                       # number of overall hits
-system.cpu.icache.overall_hits::total       401010025                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         1503                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          1503                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         1503                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           1503                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         1503                       # number of overall misses
-system.cpu.icache.overall_misses::total          1503                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     50592000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     50592000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     50592000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     50592000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     50592000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     50592000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    401011528                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    401011528                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    401011528                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    401011528                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    401011528                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    401011528                       # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::cpu.inst     769.288412                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.375629                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.375629                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst    402674417                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       402674417                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     402674417                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        402674417                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    402674417                       # number of overall hits
+system.cpu.icache.overall_hits::total       402674417                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1460                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1460                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1460                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1460                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1460                       # number of overall misses
+system.cpu.icache.overall_misses::total          1460                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     51984000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     51984000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     51984000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     51984000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     51984000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     51984000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    402675877                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    402675877                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    402675877                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    402675877                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    402675877                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    402675877                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000004                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000004                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000004                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000004                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000004                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000004                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33660.678643                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 33660.678643                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 33660.678643                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 33660.678643                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 33660.678643                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 33660.678643                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35605.479452                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 35605.479452                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 35605.479452                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 35605.479452                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 35605.479452                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 35605.479452                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -390,301 +390,301 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          535                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          535                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          535                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          535                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          535                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          535                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          968                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          968                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          968                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          968                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          968                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          968                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     34430500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     34430500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     34430500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     34430500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     34430500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     34430500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          493                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          493                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          493                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          493                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          493                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          493                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          967                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          967                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          967                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          967                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          967                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          967                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     36487500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     36487500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     36487500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     36487500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     36487500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     36487500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000002                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35568.698347                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35568.698347                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35568.698347                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 35568.698347                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35568.698347                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 35568.698347                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37732.678387                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37732.678387                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37732.678387                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 37732.678387                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37732.678387                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 37732.678387                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                9176274                       # number of replacements
-system.cpu.dcache.tagsinuse               4085.917411                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                700820301                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                9180370                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  76.339004                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle             5686444000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4085.917411                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.997538                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.997538                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data    545002306                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       545002306                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    155817990                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      155817990                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data            5                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total            5                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data     700820296                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        700820296                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    700820296                       # number of overall hits
-system.cpu.dcache.overall_hits::total       700820296                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data     10067033                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total      10067033                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      4910512                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      4910512                       # number of WriteReq misses
+system.cpu.dcache.replacements                9177386                       # number of replacements
+system.cpu.dcache.tagsinuse               4086.021231                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                702056589                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                9181482                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  76.464408                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle             5710472000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4086.021231                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.997564                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.997564                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data    546233301                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       546233301                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    155823284                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      155823284                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data            4                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total            4                       # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits::cpu.data     702056585                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        702056585                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    702056585                       # number of overall hits
+system.cpu.dcache.overall_hits::total       702056585                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data     10361176                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total      10361176                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      4905218                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      4905218                       # number of WriteReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            2                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            2                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data     14977545                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total       14977545                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data     14977545                       # number of overall misses
-system.cpu.dcache.overall_misses::total      14977545                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 147978050000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 147978050000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 133621980034                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 133621980034                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        49500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total        49500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 281600030034                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 281600030034                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 281600030034                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 281600030034                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    555069339                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    555069339                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data     15266394                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total       15266394                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data     15266394                       # number of overall misses
+system.cpu.dcache.overall_misses::total      15266394                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 211386484000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 211386484000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 166231514528                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 166231514528                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        71000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total        71000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 377617998528                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 377617998528                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 377617998528                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 377617998528                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    556594477                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    556594477                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    160728502                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    160728502                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data            7                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total            7                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    715797841                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    715797841                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    715797841                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    715797841                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.018137                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.018137                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.030552                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.030552                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.285714                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.285714                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.020924                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.020924                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.020924                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.020924                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14699.271374                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14699.271374                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27211.415028                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 27211.415028                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        24750                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        24750                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 18801.481153                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 18801.481153                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 18801.481153                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 18801.481153                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs     94480762                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets   2148368000                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs             33098                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets           65117                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs  2854.576168                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 32992.429012                       # average number of cycles each access was blocked
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data            6                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total            6                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    717322979                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    717322979                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    717322979                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    717322979                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.018615                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.018615                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.030519                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.030519                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.333333                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.333333                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.021282                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.021282                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.021282                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.021282                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20401.784894                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 20401.784894                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33888.710864                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 33888.710864                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        35500                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        35500                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 24735.245175                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 24735.245175                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 24735.245175                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 24735.245175                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs    705051055                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets   1696782500                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs            102430                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets           65119                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  6883.247633                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 26056.642455                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      3416687                       # number of writebacks
-system.cpu.dcache.writebacks::total           3416687                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      2770476                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      2770476                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3026700                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      3026700                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks      3417165                       # number of writebacks
+system.cpu.dcache.writebacks::total           3417165                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      3063278                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      3063278                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3021635                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      3021635                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            1                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total            1                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      5797176                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      5797176                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      5797176                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      5797176                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7296557                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      7296557                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1883812                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      1883812                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_hits::cpu.data      6084913                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      6084913                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      6084913                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      6084913                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7297898                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      7297898                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1883583                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      1883583                       # number of WriteReq MSHR misses
 system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data            1                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.LoadLockedReq_mshr_misses::total            1                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      9180369                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      9180369                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      9180369                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      9180369                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  66994974500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  66994974500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  35740755693                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  35740755693                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data        35500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total        35500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 102735730193                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 102735730193                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 102735730193                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 102735730193                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.013145                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.013145                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.011720                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.011720                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.142857                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.142857                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.012825                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.012825                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.012825                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.012825                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  9181.724271                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  9181.724271                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 18972.570348                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 18972.570348                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data        35500                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total        35500                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11190.806186                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 11190.806186                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11190.806186                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 11190.806186                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_misses::cpu.data      9181481                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      9181481                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      9181481                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      9181481                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  97194400500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  97194400500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  53824994530                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  53824994530                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data        40500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total        40500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 151019395030                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 151019395030                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 151019395030                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 151019395030                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.013112                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.013112                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.011719                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.011719                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.166667                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.166667                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.012800                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.012800                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.012800                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.012800                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13318.136332                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13318.136332                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28575.854916                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28575.854916                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data        40500                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total        40500                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16448.260910                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 16448.260910                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16448.260910                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 16448.260910                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.replacements               2143360                       # number of replacements
-system.cpu.l2cache.tagsinuse             30894.943744                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 8540612                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs               2173057                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  3.930229                       # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle          106966841000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 14416.601656                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst     30.433263                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data  16447.908826                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.439960                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst     0.000929                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.501950                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.942839                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.data      5920236                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        5920236                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      3416687                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      3416687                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1101316                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1101316                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.data      7021552                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         7021552                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.data      7021552                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        7021552                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          968                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data      1376308                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total      1377276                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       782510                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       782510                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          968                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data      2158818                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total       2159786                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          968                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data      2158818                       # number of overall misses
-system.cpu.l2cache.overall_misses::total      2159786                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     33271000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data  47267569500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total  47300840500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  26934706500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  26934706500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     33271000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  74202276000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  74235547000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     33271000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  74202276000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  74235547000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          968                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      7296544                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      7297512                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      3416687                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      3416687                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data      1883826                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total      1883826                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          968                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      9180370                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      9181338                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          968                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      9180370                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      9181338                       # number of overall (read+write) accesses
+system.cpu.l2cache.replacements               2143567                       # number of replacements
+system.cpu.l2cache.tagsinuse             30910.999406                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 8542221                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs               2173263                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  3.930597                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle          109501601000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::writebacks 14438.768585                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst     29.814922                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data  16442.415898                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.440636                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.000910                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.501783                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.943329                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.data      5921293                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        5921293                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      3417165                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      3417165                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data      1101170                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total      1101170                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.data      7022463                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         7022463                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.data      7022463                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        7022463                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          967                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data      1376593                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total      1377560                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       782426                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       782426                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          967                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data      2159019                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total       2159986                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          967                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data      2159019                       # number of overall misses
+system.cpu.l2cache.overall_misses::total      2159986                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     35122000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data  48976797500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total  49011919500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  28448188767                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  28448188767                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     35122000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  77424986267                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  77460108267                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     35122000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  77424986267                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  77460108267                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          967                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      7297886                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      7298853                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      3417165                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      3417165                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data      1883596                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total      1883596                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          967                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      9181482                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      9182449                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          967                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      9181482                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      9182449                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst            1                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.188625                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.188732                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.415383                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.415383                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.188629                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.188737                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.415389                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.415389                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.235156                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.235237                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.235149                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.235230                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.235156                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.235237                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34370.867769                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34343.743915                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 34343.762979                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34420.910276                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34420.910276                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34370.867769                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34371.714522                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 34371.714142                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34370.867769                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34371.714522                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 34371.714142                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs     10439000                       # number of cycles access was blocked
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.235149                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.235230                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36320.579111                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 35578.270048                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 35578.791123                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 36358.951220                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 36358.951220                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36320.579111                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 35861.188006                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 35861.393670                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36320.579111                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 35861.188006                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 35861.393670                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs      7205426                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs             1011                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs              811                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10325.420376                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs  8884.618989                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks      1050093                       # number of writebacks
-system.cpu.l2cache.writebacks::total          1050093                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          968                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data      1376308                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total      1377276                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       782510                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       782510                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          968                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data      2158818                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total      2159786                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          968                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data      2158818                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total      2159786                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     30173000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  42897858500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  42928031500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  24429166000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  24429166000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     30173000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  67327024500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  67357197500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     30173000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  67327024500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  67357197500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.writebacks::writebacks      1050133                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1050133                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          967                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data      1376593                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total      1377560                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       782426                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       782426                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          967                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data      2159019                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total      2159986                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          967                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data      2159019                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total      2159986                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     32063500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  44633307000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  44665370500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  26000882433                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  26000882433                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     32063500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  70634189433                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  70666252933                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     32063500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  70634189433                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  70666252933                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.188625                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.188732                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.415383                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.415383                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.188629                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.188737                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.415389                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.415389                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.235156                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.235237                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.235149                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.235230                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.235156                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.235237                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31170.454545                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31168.792523                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31168.793691                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31218.982505                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31218.982505                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31170.454545                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31186.984961                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31186.977552                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31170.454545                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31186.984961                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31186.977552                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.235149                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.235230                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33157.704240                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32423.023363                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32423.539084                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33231.107393                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33231.107393                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33157.704240                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 32715.872085                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 32716.069888                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33157.704240                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 32715.872085                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 32716.069888                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
index 51c5aee6c..c5fc5fd4c 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
@@ -148,7 +148,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
@@ -180,7 +180,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout
index 80ad9dac8..2743afc35 100755
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:05:18
-gem5 started Jun 28 2012 22:33:25
+gem5 compiled Jul  2 2012 08:30:56
+gem5 started Jul  2 2012 10:19:14
 gem5 executing on zizzer
 command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
@@ -23,4 +23,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 2640486390000 because target called exit()
+Exiting @ tick 2642007987000 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
index 02104b02f..15b5a360c 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.640486                       # Number of seconds simulated
-sim_ticks                                2640486390000                       # Number of ticks simulated
-final_tick                               2640486390000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.642008                       # Number of seconds simulated
+sim_ticks                                2642007987000                       # Number of ticks simulated
+final_tick                               2642007987000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2162683                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2162683                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             3138035754                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 218976                       # Number of bytes of host memory used
-host_seconds                                   841.45                       # Real time elapsed on the host
+host_inst_rate                                1913242                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1913242                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2777698581                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 217920                       # Number of bytes of host memory used
+host_seconds                                   951.15                       # Real time elapsed on the host
 sim_insts                                  1819780127                       # Number of instructions simulated
 sim_ops                                    1819780127                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             51328                       # Number of bytes read from this memory
@@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data            2149692                       # Nu
 system.physmem.num_reads::total               2150494                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks         1048525                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total              1048525                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                19439                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             52104146                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                52123585                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           19439                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              19439                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          25414106                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               25414106                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          25414106                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               19439                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            52104146                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               77537690                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst                19428                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             52074138                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                52093565                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           19428                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              19428                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          25399469                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               25399469                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          25399469                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               19428                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            52074138                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               77493034                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -67,7 +67,7 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   29                       # Number of system calls
-system.cpu.numCycles                       5280972780                       # number of cpu cycles simulated
+system.cpu.numCycles                       5284015974                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                  1819780127                       # Number of instructions committed
@@ -86,16 +86,16 @@ system.cpu.num_mem_refs                     611922547                       # nu
 system.cpu.num_load_insts                   449492741                       # Number of load instructions
 system.cpu.num_store_insts                  162429806                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                 5280972780                       # Number of busy cycles
+system.cpu.num_busy_cycles                 5284015974                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                      1                       # number of replacements
-system.cpu.icache.tagsinuse                612.518964                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                612.519467                       # Cycle average of tags in use
 system.cpu.icache.total_refs               1826377708                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    802                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               2277278.937656                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     612.518964                       # Average occupied blocks per requestor
+system.cpu.icache.occ_blocks::cpu.inst     612.519467                       # Average occupied blocks per requestor
 system.cpu.icache.occ_percent::cpu.inst      0.299082                       # Average percentage of cache occupancy
 system.cpu.icache.occ_percent::total         0.299082                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst   1826377708                       # number of ReadReq hits
@@ -110,12 +110,12 @@ system.cpu.icache.demand_misses::cpu.inst          802                       # n
 system.cpu.icache.demand_misses::total            802                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          802                       # number of overall misses
 system.cpu.icache.overall_misses::total           802                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     44912000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     44912000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     44912000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     44912000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     44912000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     44912000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     45149000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     45149000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     45149000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     45149000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     45149000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     45149000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst   1826378510                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total   1826378510                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst   1826378510                       # number of demand (read+write) accesses
@@ -128,12 +128,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000000
 system.cpu.icache.demand_miss_rate::total     0.000000                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000000                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000000                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst        56000                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total        56000                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst        56000                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total        56000                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst        56000                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total        56000                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56295.511222                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 56295.511222                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 56295.511222                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 56295.511222                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 56295.511222                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 56295.511222                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -148,34 +148,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          802
 system.cpu.icache.demand_mshr_misses::total          802                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          802                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          802                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     42506000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     42506000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     42506000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     42506000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     42506000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     42506000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     42743000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     42743000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     42743000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     42743000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     42743000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     42743000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000000                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000000                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000000                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst        53000                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total        53000                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst        53000                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst        53000                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53295.511222                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53295.511222                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53295.511222                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 53295.511222                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53295.511222                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 53295.511222                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                9107638                       # number of replacements
-system.cpu.dcache.tagsinuse               4079.363452                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               4079.366966                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                596212431                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                9111734                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                  65.433476                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle            40985601000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4079.363452                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.995938                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.995938                       # Average percentage of cache occupancy
+system.cpu.dcache.warmup_cycle            40989979000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4079.366966                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.995939                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.995939                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data    437373249                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total       437373249                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data    158839182                       # number of WriteReq hits
@@ -192,14 +192,14 @@ system.cpu.dcache.demand_misses::cpu.data      9111734                       # n
 system.cpu.dcache.demand_misses::total        9111734                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data      9111734                       # number of overall misses
 system.cpu.dcache.overall_misses::total       9111734                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 158270882000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 158270882000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  59580458000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  59580458000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 217851340000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 217851340000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 217851340000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 217851340000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 158759423000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 158759423000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  59584620000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  59584620000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 218344043000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 218344043000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 218344043000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 218344043000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data    444595663                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total    444595663                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    160728502                       # number of WriteReq accesses(hits+misses)
@@ -216,14 +216,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.015053
 system.cpu.dcache.demand_miss_rate::total     0.015053                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.015053                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.015053                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21913.847918                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 21913.847918                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31535.397921                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 31535.397921                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 23908.878376                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 23908.878376                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 23908.878376                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 23908.878376                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21981.490261                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 21981.490261                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31537.600830                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 31537.600830                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 23962.951838                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 23962.951838                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 23962.951838                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 23962.951838                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -242,14 +242,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data      9111734
 system.cpu.dcache.demand_mshr_misses::total      9111734                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data      9111734                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total      9111734                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 136603640000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 136603640000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  53912498000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  53912498000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 190516138000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 190516138000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 190516138000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 190516138000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 137092181000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 137092181000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  53916660000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  53916660000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191008841000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 191008841000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191008841000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 191008841000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.016245                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.016245                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.011755                       # mshr miss rate for WriteReq accesses
@@ -258,28 +258,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.015053
 system.cpu.dcache.demand_mshr_miss_rate::total     0.015053                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.015053                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.015053                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18913.847918                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18913.847918                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28535.397921                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28535.397921                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20908.878376                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20908.878376                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20908.878376                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 20908.878376                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18981.490261                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18981.490261                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28537.600830                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28537.600830                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20962.951838                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 20962.951838                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20962.951838                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 20962.951838                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements               2133721                       # number of replacements
-system.cpu.l2cache.tagsinuse             30166.064442                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse             30166.534681                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                 8449191                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs               2163414                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  3.905490                       # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle          498208075000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 14372.212156                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst     37.660543                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data  15756.191744                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.438605                       # Average percentage of cache occupancy
+system.cpu.l2cache.warmup_cycle          498438853000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::writebacks 14372.614424                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst     37.649566                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data  15756.270691                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.438617                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.inst     0.001149                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.480841                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.920595                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.480843                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.920610                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.data      5861531                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total        5861531                       # number of ReadReq hits
 system.cpu.l2cache.Writeback_hits::writebacks      3389919                       # number of Writeback hits
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
index c94040a4a..cb0b4a9a4 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
@@ -497,7 +497,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
@@ -529,7 +529,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout
index 1148e0586..963dfaf37 100755
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:10:14
-gem5 started Jun 29 2012 01:20:26
+gem5 compiled Jul  2 2012 09:08:16
+gem5 started Jul  2 2012 16:38:23
 gem5 executing on zizzer
 command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/60.bzip2/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
@@ -24,4 +24,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 458035985000 because target called exit()
+Exiting @ tick 479150606000 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
index f8f6b4a6a..9750f5933 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
@@ -1,39 +1,39 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.458036                       # Number of seconds simulated
-sim_ticks                                458035985000                       # Number of ticks simulated
-final_tick                               458035985000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.479151                       # Number of seconds simulated
+sim_ticks                                479150606000                       # Number of ticks simulated
+final_tick                               479150606000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 197390                       # Simulator instruction rate (inst/s)
-host_op_rate                                   220203                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               58535443                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 234800                       # Number of bytes of host memory used
-host_seconds                                  7824.93                       # Real time elapsed on the host
-sim_insts                                  1544563073                       # Number of instructions simulated
-sim_ops                                    1723073885                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst             48320                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         156358784                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            156407104                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        48320                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           48320                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     71946432                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          71946432                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst                755                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            2443106                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               2443861                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1124163                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1124163                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               105494                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            341367904                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               341473398                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          105494                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             105494                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks         157075938                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              157075938                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks         157075938                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              105494                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           341367904                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              498549336                       # Total bandwidth to/from this memory (bytes/s)
+host_inst_rate                                 194711                       # Simulator instruction rate (inst/s)
+host_op_rate                                   217215                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               60402792                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 234724                       # Number of bytes of host memory used
+host_seconds                                  7932.59                       # Real time elapsed on the host
+sim_insts                                  1544563028                       # Number of instructions simulated
+sim_ops                                    1723073840                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst             48512                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         156296384                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            156344896                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        48512                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           48512                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     71934976                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          71934976                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst                758                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            2442131                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               2442889                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1123984                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1123984                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               101246                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            326194691                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               326295937                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          101246                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             101246                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks         150130199                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              150130199                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks         150130199                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              101246                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           326194691                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              476426136                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -77,322 +77,322 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                   46                       # Number of system calls
-system.cpu.numCycles                        916071971                       # number of cpu cycles simulated
+system.cpu.numCycles                        958301213                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                300386365                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted          246254548                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect           16072669                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups             170403157                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                156239351                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                302333500                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted          248015603                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect           16105989                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups             168718741                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                157776197                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                 18292614                       # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect                 219                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles          292465712                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     2157283635                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   300386365                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          174531965                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     428963032                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                83531263                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles              119911343                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                    4                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles           109                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                 283465873                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               5375761                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          908345220                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.641582                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.245010                       # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS                 18362417                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect                 231                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles          295110918                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     2170236667                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   302333500                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          176138614                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     431684517                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                85621855                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles              155290774                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                    1                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles            58                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                 285908690                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               5538082                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          950817611                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.537566                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.220819                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                479382246     52.78%     52.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 23075019      2.54%     55.32% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 38696357      4.26%     59.58% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 47758356      5.26%     64.83% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 40740735      4.49%     69.32% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 46836926      5.16%     74.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 39064245      4.30%     78.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 18137906      2.00%     80.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                174653430     19.23%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                519133170     54.60%     54.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 23531871      2.47%     57.07% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 38842821      4.09%     61.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 47928811      5.04%     66.20% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 41274787      4.34%     70.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 47187627      4.96%     75.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 39143273      4.12%     79.62% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 18340446      1.93%     81.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                175434805     18.45%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            908345220                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.327907                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.354928                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                321276302                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             100437637                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 403614016                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              16012907                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               67004358                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             46143588                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                   709                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             2345766913                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                  2404                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles               67004358                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                342772787                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                44470406                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          13938                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 396994343                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              57089388                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             2288809868                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                 21597                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                4587251                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents              43867874                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents                3                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands          2263371035                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups           10565210641                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups      10565207285                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups              3356                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps            1706320010                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                557051025                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               5363                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts           5361                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 133306732                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            624412648                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           218802984                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          85974356                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         66146404                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 2189209490                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                1708                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                2014638202                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           4851094                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       461527844                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined   1075835396                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved           1528                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     908345220                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.217921                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.925838                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            950817611                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.315489                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.264671                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                327140938                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             132753088                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 402950990                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              19241929                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               68730666                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             46279846                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                   704                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             2359084469                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                  2481                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               68730666                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                349892865                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                63780880                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          14141                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 397813217                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              70585842                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             2300380626                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                 28739                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                5556251                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents              56445912                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents                1                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands          2275326533                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups           10618275091                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups      10618272387                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups              2704                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps            1706319938                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                569006595                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               5461                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           5458                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 155601466                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            627528670                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           219567806                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          87006993                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         68089228                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 2199559403                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                1526                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                2020307102                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           5002319                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       472139724                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined   1101721580                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           1355                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     950817611                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.124810                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.914497                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           244431658     26.91%     26.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           136114338     14.98%     41.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           157116427     17.30%     59.19% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           116129005     12.78%     71.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4           125782921     13.85%     85.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            75959694      8.36%     94.19% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            39392857      4.34%     98.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7            10729861      1.18%     99.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             2688459      0.30%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           272456432     28.65%     28.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           148972541     15.67%     44.32% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           161045064     16.94%     61.26% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           117808406     12.39%     73.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4           124487858     13.09%     86.74% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            74416152      7.83%     94.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            38351621      4.03%     98.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7            10558999      1.11%     99.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             2720538      0.29%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       908345220                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       950817611                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  792596      3.16%      3.16% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                   4903      0.02%      3.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      3.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      3.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      3.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      3.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      3.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      3.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      3.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      3.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      3.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      3.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      3.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      3.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      3.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      3.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      3.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      3.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      3.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      3.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      3.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      3.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      3.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      3.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      3.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      3.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      3.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      3.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      3.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               19003801     75.87%     79.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               5245876     20.94%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  866703      3.46%      3.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                   4868      0.02%      3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      3.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               18978969     75.82%     79.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               5181359     20.70%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1233307061     61.22%     61.22% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               930228      0.05%     61.26% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     61.26% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   2      0.00%     61.26% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     61.26% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     61.26% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     61.26% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     61.26% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     61.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     61.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     61.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     61.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     61.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     61.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     61.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     61.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     61.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     61.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     61.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     61.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     61.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     61.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     61.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt              49      0.00%     61.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               3      0.00%     61.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc             28      0.00%     61.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult             10      0.00%     61.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     61.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     61.26% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            586604414     29.12%     90.38% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           193796407      9.62%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1236552318     61.21%     61.21% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               932322      0.05%     61.25% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     61.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   2      0.00%     61.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     61.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     61.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     61.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     61.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     61.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     61.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     61.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     61.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     61.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     61.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     61.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     61.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     61.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     61.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     61.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     61.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     61.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     61.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     61.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt              41      0.00%     61.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               1      0.00%     61.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc             19      0.00%     61.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              8      0.00%     61.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     61.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     61.25% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            588904292     29.15%     90.40% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           193918099      9.60%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             2014638202                       # Type of FU issued
-system.cpu.iq.rate                           2.199214                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    25047176                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.012433                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         4967519524                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        2650923657                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1956580647                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 370                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                618                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses          132                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             2039685190                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     188                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         63569960                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             2020307102                       # Type of FU issued
+system.cpu.iq.rate                           2.108217                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    25031899                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.012390                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         5021465735                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        2671886632                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1961215820                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 298                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                520                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses          112                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             2045338849                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     152                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         63654285                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    138485869                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses       280074                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       188083                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     43955929                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads    141601900                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       294123                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       189203                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     44720760                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads            2                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        515490                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads            1                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked       1137177                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               67004358                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                19766452                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               1127497                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          2189219165                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts           5544678                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             624412648                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            218802984                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               1639                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 172089                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 43011                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         188083                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        8607625                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect     10203792                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             18811417                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            1985083877                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             571977023                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          29554325                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles               68730666                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                28026748                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               1485770                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          2199569564                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           5556141                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             627528670                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            219567806                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               1463                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 343326                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 56332                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         189203                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        8602483                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect     10215552                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             18818035                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1990553449                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             574287819                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          29753653                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                          7967                       # number of nop insts executed
-system.cpu.iew.exec_refs                    762799722                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                238022734                       # Number of branches executed
-system.cpu.iew.exec_stores                  190822699                       # Number of stores executed
-system.cpu.iew.exec_rate                     2.166952                       # Inst execution rate
-system.cpu.iew.wb_sent                     1965575614                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    1956580779                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1296425776                       # num instructions producing a value
-system.cpu.iew.wb_consumers                2069436870                       # num instructions consuming a value
+system.cpu.iew.exec_nop                          8635                       # number of nop insts executed
+system.cpu.iew.exec_refs                    765252053                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                238421113                       # Number of branches executed
+system.cpu.iew.exec_stores                  190964234                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.077169                       # Inst execution rate
+system.cpu.iew.wb_sent                     1970075771                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1961215932                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1296581898                       # num instructions producing a value
+system.cpu.iew.wb_consumers                2068899277                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       2.135837                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.626463                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       2.046555                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.626701                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts     1544563091                       # The number of committed instructions
-system.cpu.commit.commitCommittedOps       1723073903                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts       466205393                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls             180                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts          16072230                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    841340863                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.048009                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.762269                       # Number of insts commited each cycle
+system.cpu.commit.commitCommittedInsts     1544563046                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps       1723073858                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts       476570852                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls             171                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts          16105557                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    882086946                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.953406                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.727739                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    352627350     41.91%     41.91% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    193034897     22.94%     64.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     73667996      8.76%     73.61% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     35236864      4.19%     77.80% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     18719576      2.22%     80.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     30675778      3.65%     83.67% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     19663987      2.34%     86.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     10964014      1.30%     87.31% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8    106750401     12.69%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    391458685     44.38%     44.38% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    194911052     22.10%     66.48% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     73858259      8.37%     74.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     35176751      3.99%     78.84% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     19156374      2.17%     81.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     30712442      3.48%     84.49% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     19230333      2.18%     86.67% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     11318069      1.28%     87.95% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8    106264981     12.05%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    841340863                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts           1544563091                       # Number of instructions committed
-system.cpu.commit.committedOps             1723073903                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    882086946                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts           1544563046                       # Number of instructions committed
+system.cpu.commit.committedOps             1723073858                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                      660773834                       # Number of memory references committed
-system.cpu.commit.loads                     485926779                       # Number of loads committed
+system.cpu.commit.refs                      660773816                       # Number of memory references committed
+system.cpu.commit.loads                     485926770                       # Number of loads committed
 system.cpu.commit.membars                          62                       # Number of memory barriers committed
-system.cpu.commit.branches                  213462373                       # Number of branches committed
+system.cpu.commit.branches                  213462364                       # Number of branches committed
 system.cpu.commit.fp_insts                         36                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                1536941881                       # Number of committed integer instructions.
+system.cpu.commit.int_insts                1536941845                       # Number of committed integer instructions.
 system.cpu.commit.function_calls             13665177                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events             106750401                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events             106264981                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   2923869159                       # The number of ROB reads
-system.cpu.rob.rob_writes                  4445740607                       # The number of ROB writes
-system.cpu.timesIdled                          753914                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         7726751                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                  1544563073                       # Number of Instructions Simulated
-system.cpu.committedOps                    1723073885                       # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total            1544563073                       # Number of Instructions Simulated
-system.cpu.cpi                               0.593095                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.593095                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.686072                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.686072                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               9944305109                       # number of integer regfile reads
-system.cpu.int_regfile_writes              1936656463                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                       139                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                      147                       # number of floating regfile writes
-system.cpu.misc_regfile_reads              2896410924                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                    144                       # number of misc regfile writes
-system.cpu.icache.replacements                     25                       # number of replacements
-system.cpu.icache.tagsinuse                627.053723                       # Cycle average of tags in use
-system.cpu.icache.total_refs                283464725                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                    785                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs               361101.560510                       # Average number of references to valid blocks.
+system.cpu.rob.rob_reads                   2975466076                       # The number of ROB reads
+system.cpu.rob.rob_writes                  4468185114                       # The number of ROB writes
+system.cpu.timesIdled                          802459                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         7483602                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                  1544563028                       # Number of Instructions Simulated
+system.cpu.committedOps                    1723073840                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total            1544563028                       # Number of Instructions Simulated
+system.cpu.cpi                               0.620435                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.620435                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.611772                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.611772                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               9971004084                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1941069131                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                       114                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                      123                       # number of floating regfile writes
+system.cpu.misc_regfile_reads              2910834876                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                    126                       # number of misc regfile writes
+system.cpu.icache.replacements                     24                       # number of replacements
+system.cpu.icache.tagsinuse                634.471646                       # Cycle average of tags in use
+system.cpu.icache.total_refs                285907562                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    789                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               362366.998733                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     627.053723                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.306179                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.306179                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst    283464725                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       283464725                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     283464725                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        283464725                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    283464725                       # number of overall hits
-system.cpu.icache.overall_hits::total       283464725                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         1148                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          1148                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         1148                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           1148                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         1148                       # number of overall misses
-system.cpu.icache.overall_misses::total          1148                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     38598000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     38598000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     38598000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     38598000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     38598000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     38598000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    283465873                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    283465873                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    283465873                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    283465873                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    283465873                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    283465873                       # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::cpu.inst     634.471646                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.309801                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.309801                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst    285907562                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       285907562                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     285907562                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        285907562                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    285907562                       # number of overall hits
+system.cpu.icache.overall_hits::total       285907562                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1128                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1128                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1128                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1128                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1128                       # number of overall misses
+system.cpu.icache.overall_misses::total          1128                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     40115500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     40115500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     40115500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     40115500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     40115500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     40115500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    285908690                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    285908690                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    285908690                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    285908690                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    285908690                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    285908690                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000004                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000004                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000004                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000004                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000004                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000004                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33621.951220                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 33621.951220                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 33621.951220                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 33621.951220                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 33621.951220                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 33621.951220                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35563.386525                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 35563.386525                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 35563.386525                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 35563.386525                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 35563.386525                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 35563.386525                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -401,309 +401,309 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          363                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          363                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          363                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          363                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          363                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          363                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          785                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          785                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          785                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          785                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          785                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          785                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     27001000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     27001000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     27001000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     27001000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     27001000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     27001000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          339                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          339                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          339                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          339                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          339                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          339                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          789                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          789                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          789                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          789                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          789                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          789                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     28841500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     28841500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     28841500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     28841500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     28841500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     28841500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000003                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000003                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000003                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000003                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000003                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000003                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34396.178344                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34396.178344                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34396.178344                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 34396.178344                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34396.178344                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 34396.178344                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36554.499366                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36554.499366                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36554.499366                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 36554.499366                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36554.499366                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 36554.499366                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                9618836                       # number of replacements
-system.cpu.dcache.tagsinuse               4087.631943                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                660703184                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                9622932                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  68.659239                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle             3346369000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4087.631943                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.997957                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.997957                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data    493290864                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       493290864                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    167412157                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      167412157                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data           92                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total           92                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data           71                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total           71                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     660703021                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        660703021                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    660703021                       # number of overall hits
-system.cpu.dcache.overall_hits::total       660703021                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data     10330521                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total      10330521                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      5173890                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      5173890                       # number of WriteReq misses
+system.cpu.dcache.replacements                9617864                       # number of replacements
+system.cpu.dcache.tagsinuse               4087.822620                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                661858061                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                9621960                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  68.786200                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle             3369466000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4087.822620                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.998004                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.998004                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data    494463197                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       494463197                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    167394718                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      167394718                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data           84                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total           84                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data           62                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total           62                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data     661857915                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        661857915                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    661857915                       # number of overall hits
+system.cpu.dcache.overall_hits::total       661857915                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data     10787388                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total      10787388                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      5191329                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      5191329                       # number of WriteReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            3                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            3                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data     15504411                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total       15504411                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data     15504411                       # number of overall misses
-system.cpu.dcache.overall_misses::total      15504411                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 163224239500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 163224239500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 124852568337                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 124852568337                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       113500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total       113500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 288076807837                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 288076807837                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 288076807837                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 288076807837                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    503621385                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    503621385                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data     15978717                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total       15978717                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data     15978717                       # number of overall misses
+system.cpu.dcache.overall_misses::total      15978717                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 258680588500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 258680588500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 196204904993                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 196204904993                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       118500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total       118500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 454885493493                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 454885493493                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 454885493493                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 454885493493                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    505250585                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    505250585                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    172586047                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    172586047                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data           95                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total           95                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data           71                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total           71                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    676207432                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    676207432                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    676207432                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    676207432                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.020512                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.020512                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.029979                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.029979                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.031579                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.031579                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.022928                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.022928                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.022928                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.022928                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15800.194346                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 15800.194346                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24131.276146                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 24131.276146                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37833.333333                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37833.333333                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 18580.312908                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 18580.312908                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 18580.312908                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 18580.312908                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs    200292336                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets       119500                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs             73738                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               8                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs  2716.270254                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 14937.500000                       # average number of cycles each access was blocked
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data           87                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total           87                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data           62                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total           62                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    677836632                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    677836632                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    677836632                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    677836632                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.021351                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.021351                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.030080                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.030080                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.034483                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.034483                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.023573                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.023573                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.023573                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.023573                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23979.909548                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 23979.909548                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37794.735220                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 37794.735220                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        39500                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        39500                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 28468.211402                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 28468.211402                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 28468.211402                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 28468.211402                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs   2516165984                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets       147500                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs            424894                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               9                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  5921.867534                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 16388.888889                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      3473805                       # number of writebacks
-system.cpu.dcache.writebacks::total           3473805                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      2601467                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      2601467                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3280012                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      3280012                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks      3474501                       # number of writebacks
+system.cpu.dcache.writebacks::total           3474501                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      3059372                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      3059372                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3297385                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      3297385                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            3                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total            3                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      5881479                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      5881479                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      5881479                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      5881479                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7729054                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      7729054                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1893878                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      1893878                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      9622932                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      9622932                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      9622932                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      9622932                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  78985396500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  78985396500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  42766465749                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  42766465749                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 121751862249                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 121751862249                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 121751862249                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 121751862249                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.015347                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.015347                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_hits::cpu.data      6356757                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      6356757                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      6356757                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      6356757                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7728016                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      7728016                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1893944                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      1893944                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      9621960                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      9621960                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      9621960                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      9621960                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 124261380000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 124261380000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  91432769312                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  91432769312                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 215694149312                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 215694149312                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 215694149312                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 215694149312                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.015295                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.015295                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.010974                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.010974                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.014231                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.014231                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.014231                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.014231                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10219.283822                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10219.283822                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22581.425915                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22581.425915                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12652.262559                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 12652.262559                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12652.262559                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 12652.262559                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.014195                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.014195                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.014195                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.014195                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16079.337827                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16079.337827                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48276.384789                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48276.384789                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22416.861982                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 22416.861982                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22416.861982                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 22416.861982                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.replacements               2428308                       # number of replacements
-system.cpu.l2cache.tagsinuse             31141.553043                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 8745111                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs               2458022                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  3.557784                       # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle           77921850000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 14050.890908                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst     15.916061                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data  17074.746074                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.428799                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst     0.000486                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.521080                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.950365                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst           29                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data      6116875                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        6116904                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      3473805                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      3473805                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1062945                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1062945                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst           29                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      7179820                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         7179849                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst           29                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      7179820                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        7179849                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          756                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data      1612178                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total      1612934                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       830934                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       830934                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          756                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data      2443112                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total       2443868                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          756                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data      2443112                       # number of overall misses
-system.cpu.l2cache.overall_misses::total      2443868                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     25970500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data  55332029500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total  55358000000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  28726375500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  28726375500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     25970500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  84058405000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  84084375500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     25970500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  84058405000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  84084375500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          785                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      7729053                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      7729838                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      3473805                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      3473805                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data      1893879                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total      1893879                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          785                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      9622932                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      9623717                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          785                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      9622932                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      9623717                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.963057                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.208587                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.208663                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.438747                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.438747                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.963057                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.253884                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.253942                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.963057                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.253884                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.253942                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34352.513228                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34321.290515                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 34321.305149                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34571.187964                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34571.187964                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34352.513228                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34406.283871                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 34406.267237                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34352.513228                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34406.283871                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 34406.267237                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs     36965500                       # number of cycles access was blocked
+system.cpu.l2cache.replacements               2427328                       # number of replacements
+system.cpu.l2cache.tagsinuse             31166.284891                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 8745751                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs               2457039                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  3.559468                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle           81028078000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::writebacks 14024.049283                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst     15.077840                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data  17127.157769                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.427980                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.000460                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.522679                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.951120                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst           30                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data      6116665                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        6116695                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      3474501                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      3474501                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data      1063157                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total      1063157                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst           30                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      7179822                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         7179852                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst           30                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      7179822                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        7179852                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          759                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data      1611350                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total      1612109                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       830788                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       830788                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          759                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data      2442138                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total       2442897                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          759                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data      2442138                       # number of overall misses
+system.cpu.l2cache.overall_misses::total      2442897                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     27450000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data  57809721000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total  57837171000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  32456622937                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  32456622937                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     27450000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  90266343937                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  90293793937                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     27450000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  90266343937                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  90293793937                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          789                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      7728015                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      7728804                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      3474501                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      3474501                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data      1893945                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total      1893945                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          789                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      9621960                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      9622749                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          789                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      9621960                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      9622749                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.961977                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.208508                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.208585                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.438655                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.438655                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.961977                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.253809                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.253867                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.961977                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.253809                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.253867                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36166.007905                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 35876.576163                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 35876.712431                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39067.274608                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39067.274608                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36166.007905                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 36962.016044                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 36961.768727                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36166.007905                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 36962.016044                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 36961.768727                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs     23316238                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs             4354                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs             2976                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs  8490.009187                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs  7834.757392                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks      1124163                       # number of writebacks
-system.cpu.l2cache.writebacks::total          1124163                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks      1123984                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1123984                       # number of writebacks
 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            1                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data            6                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total            7                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data            7                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total            8                       # number of ReadReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data            6                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total            7                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data            7                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total            8                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data            6                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total            7                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          755                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data      1612172                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total      1612927                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       830934                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       830934                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          755                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data      2443106                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total      2443861                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          755                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data      2443106                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total      2443861                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     23546000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  50285384000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  50308930000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  26141067500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  26141067500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     23546000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  76426451500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  76449997500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     23546000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  76426451500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  76449997500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.961783                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.208586                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.208662                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.438747                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.438747                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.961783                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.253884                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.253941                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.961783                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.253884                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.253941                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31186.754967                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31191.078868                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31191.076844                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31459.860230                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31459.860230                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31186.754967                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31282.495111                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31282.465533                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31186.754967                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31282.495111                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31282.465533                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_hits::cpu.data            7                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total            8                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          758                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data      1611343                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total      1612101                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       830788                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       830788                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          758                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data      2442131                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total      2442889                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          758                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data      2442131                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total      2442889                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     25025500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  52778176000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  52803201500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  29830819408                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  29830819408                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     25025500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  82608995408                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  82634020908                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     25025500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  82608995408                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  82634020908                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.960710                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.208507                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.208584                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.438655                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.438655                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.960710                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.253808                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.253866                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.960710                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.253808                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.253866                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33015.171504                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32754.153523                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32754.276252                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35906.656581                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35906.656581                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33015.171504                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33826.602835                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33826.351057                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33015.171504                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33826.602835                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33826.351057                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini
index e66f558e0..d5edd6037 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini
@@ -166,7 +166,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
@@ -198,7 +198,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout
index 4ec39cba0..2722378bf 100755
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:10:14
-gem5 started Jun 29 2012 01:25:17
+gem5 compiled Jul  2 2012 09:08:16
+gem5 started Jul  2 2012 16:44:36
 gem5 executing on zizzer
 command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
@@ -24,4 +24,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 2408512388000 because target called exit()
+Exiting @ tick 2409361491000 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
index c9d66243a..906e755f1 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.408512                       # Number of seconds simulated
-sim_ticks                                2408512388000                       # Number of ticks simulated
-final_tick                               2408512388000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.409361                       # Number of seconds simulated
+sim_ticks                                2409361491000                       # Number of ticks simulated
+final_tick                               2409361491000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1431405                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1597462                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2240478292                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 233776                       # Number of bytes of host memory used
-host_seconds                                  1075.00                       # Real time elapsed on the host
+host_inst_rate                                1494553                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1667935                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2340143235                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 233700                       # Number of bytes of host memory used
+host_seconds                                  1029.58                       # Real time elapsed on the host
 sim_insts                                  1538759601                       # Number of instructions simulated
 sim_ops                                    1717270334                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             39424                       # Number of bytes read from this memory
@@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data            2153435                       # Nu
 system.physmem.num_reads::total               2154051                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks         1050331                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total              1050331                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                16369                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             57221977                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                57238345                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           16369                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              16369                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          27909835                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               27909835                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          27909835                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               16369                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            57221977                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               85148181                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst                16363                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             57201811                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                57218174                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           16363                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              16363                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          27899999                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               27899999                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          27899999                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               16363                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            57201811                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               85118173                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -77,7 +77,7 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                   46                       # Number of system calls
-system.cpu.numCycles                       4817024776                       # number of cpu cycles simulated
+system.cpu.numCycles                       4818722982                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                  1538759601                       # Number of instructions committed
@@ -96,18 +96,18 @@ system.cpu.num_mem_refs                     660773815                       # nu
 system.cpu.num_load_insts                   485926769                       # Number of load instructions
 system.cpu.num_store_insts                  174847046                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                 4817024776                       # Number of busy cycles
+system.cpu.num_busy_cycles                 4818722982                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                      7                       # number of replacements
-system.cpu.icache.tagsinuse                515.022606                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                515.026762                       # Cycle average of tags in use
 system.cpu.icache.total_refs               1544564952                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    638                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               2420948.200627                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     515.022606                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.251476                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.251476                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst     515.026762                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.251478                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.251478                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst   1544564952                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total      1544564952                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst    1544564952                       # number of demand (read+write) hits
@@ -120,12 +120,12 @@ system.cpu.icache.demand_misses::cpu.inst          638                       # n
 system.cpu.icache.demand_misses::total            638                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          638                       # number of overall misses
 system.cpu.icache.overall_misses::total           638                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     34804000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     34804000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     34804000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     34804000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     34804000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     34804000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     34951000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     34951000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     34951000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     34951000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     34951000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     34951000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst   1544565590                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total   1544565590                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst   1544565590                       # number of demand (read+write) accesses
@@ -138,12 +138,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000000
 system.cpu.icache.demand_miss_rate::total     0.000000                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000000                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000000                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54551.724138                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 54551.724138                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 54551.724138                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 54551.724138                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 54551.724138                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 54551.724138                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54782.131661                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 54782.131661                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 54782.131661                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 54782.131661                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 54782.131661                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 54782.131661                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -158,34 +158,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          638
 system.cpu.icache.demand_mshr_misses::total          638                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          638                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          638                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     32890000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     32890000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     32890000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     32890000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     32890000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     32890000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     33037000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     33037000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     33037000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     33037000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     33037000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     33037000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000000                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000000                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000000                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51551.724138                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51551.724138                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51551.724138                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 51551.724138                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51551.724138                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 51551.724138                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51782.131661                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51782.131661                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51782.131661                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 51782.131661                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51782.131661                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 51782.131661                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                9111140                       # number of replacements
-system.cpu.dcache.tagsinuse               4083.603265                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               4083.605959                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                645855059                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                9115236                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                  70.854453                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle            25922973000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4083.603265                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.996973                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.996973                       # Average percentage of cache occupancy
+system.cpu.dcache.warmup_cycle            25924036000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4083.605959                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.996974                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.996974                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data    475158039                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total       475158039                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data    170696898                       # number of WriteReq hits
@@ -206,14 +206,14 @@ system.cpu.dcache.demand_misses::cpu.data      9115236                       # n
 system.cpu.dcache.demand_misses::total        9115236                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data      9115236                       # number of overall misses
 system.cpu.dcache.overall_misses::total       9115236                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 158470312000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 158470312000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  59587262000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  59587262000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 218057574000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 218057574000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 218057574000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 218057574000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 158944725000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 158944725000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  59599499000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  59599499000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 218544224000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 218544224000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 218544224000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 218544224000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data    482384126                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total    482384126                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    172586047                       # number of WriteReq accesses(hits+misses)
@@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.013917
 system.cpu.dcache.demand_miss_rate::total     0.013917                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.013917                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.013917                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21930.307786                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 21930.307786                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31541.854031                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 31541.854031                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 23922.317974                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 23922.317974                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 23922.317974                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 23922.317974                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21995.960608                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 21995.960608                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31548.331550                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 31548.331550                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 23975.706608                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 23975.706608                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 23975.706608                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 23975.706608                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data      9115236
 system.cpu.dcache.demand_mshr_misses::total      9115236                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data      9115236                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total      9115236                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 136792051000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 136792051000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  53919815000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  53919815000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 190711866000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 190711866000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 190711866000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 190711866000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 137266464000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 137266464000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  53932052000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  53932052000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191198516000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 191198516000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191198516000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 191198516000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.014980                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.014980                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.010946                       # mshr miss rate for WriteReq accesses
@@ -276,28 +276,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.013917
 system.cpu.dcache.demand_mshr_miss_rate::total     0.013917                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.013917                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.013917                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18930.307786                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18930.307786                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28541.854031                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28541.854031                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20922.317974                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20922.317974                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20922.317974                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 20922.317974                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18995.960608                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18995.960608                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28548.331550                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28548.331550                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20975.706608                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 20975.706608                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20975.706608                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 20975.706608                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements               2138446                       # number of replacements
-system.cpu.l2cache.tagsinuse             30628.680390                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse             30629.012311                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                 8443619                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs               2168151                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  3.894387                       # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle          437045285000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 14782.399882                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst     15.716042                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data  15830.564466                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.451123                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst     0.000480                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.483110                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.934713                       # Average percentage of cache occupancy
+system.cpu.l2cache.warmup_cycle          437178443000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::writebacks 14783.850246                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst     15.711580                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data  15829.450485                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.451167                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.000479                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.483076                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.934723                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst           22                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data      5861680                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total        5861702                       # number of ReadReq hits
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
index 643e6799d..f840aa9a4 100644
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
@@ -169,7 +169,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
@@ -201,7 +201,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
 slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
 
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout
index 5dc44ec4f..05d9e4afd 100755
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:08:09
-gem5 started Jun 28 2012 23:47:42
+gem5 compiled Jul  2 2012 08:58:39
+gem5 started Jul  2 2012 14:08:03
 gem5 executing on zizzer
 command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
@@ -24,4 +24,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 5900695290000 because target called exit()
+Exiting @ tick 5901048931000 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
index faa206e56..50b0e856f 100644
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  5.900695                       # Number of seconds simulated
-sim_ticks                                5900695290000                       # Number of ticks simulated
-final_tick                               5900695290000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  5.901049                       # Number of seconds simulated
+sim_ticks                                5901048931000                       # Number of ticks simulated
+final_tick                               5901048931000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1070782                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1668375                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2100461088                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 228516                       # Number of bytes of host memory used
-host_seconds                                  2809.24                       # Real time elapsed on the host
+host_inst_rate                                 821481                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1279942                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1611526350                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 228472                       # Number of bytes of host memory used
+host_seconds                                  3661.78                       # Real time elapsed on the host
 sim_insts                                  3008081057                       # Number of instructions simulated
 sim_ops                                    4686862651                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             43200                       # Number of bytes read from this memory
@@ -24,18 +24,18 @@ system.physmem.num_reads::total               2173231                       # Nu
 system.physmem.num_writes::writebacks         1053029                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total              1053029                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu.inst                 7321                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             23563932                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                23571253                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             23562520                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                23569841                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::cpu.inst            7321                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::total               7321                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          11421342                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               11421342                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          11421342                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::writebacks          11420657                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               11420657                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          11420657                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.inst                7321                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            23563932                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               34992595                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            23562520                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               34990498                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   46                       # Number of system calls
-system.cpu.numCycles                      11801390580                       # number of cpu cycles simulated
+system.cpu.numCycles                      11802097862                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                  3008081057                       # Number of instructions committed
@@ -54,16 +54,16 @@ system.cpu.num_mem_refs                    1677713086                       # nu
 system.cpu.num_load_insts                  1239184749                       # Number of load instructions
 system.cpu.num_store_insts                  438528337                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                11801390580                       # Number of busy cycles
+system.cpu.num_busy_cycles                11802097862                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                     10                       # number of replacements
-system.cpu.icache.tagsinuse                555.745205                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                555.745883                       # Cycle average of tags in use
 system.cpu.icache.total_refs               4013232252                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    675                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               5945529.262222                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     555.745205                       # Average occupied blocks per requestor
+system.cpu.icache.occ_blocks::cpu.inst     555.745883                       # Average occupied blocks per requestor
 system.cpu.icache.occ_percent::cpu.inst      0.271360                       # Average percentage of cache occupancy
 system.cpu.icache.occ_percent::total         0.271360                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst   4013232252                       # number of ReadReq hits
@@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst          675                       # n
 system.cpu.icache.demand_misses::total            675                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          675                       # number of overall misses
 system.cpu.icache.overall_misses::total           675                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     37800000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     37800000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     37800000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     37800000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     37800000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     37800000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     37868000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     37868000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     37868000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     37868000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     37868000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     37868000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst   4013232927                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total   4013232927                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst   4013232927                       # number of demand (read+write) accesses
@@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000000
 system.cpu.icache.demand_miss_rate::total     0.000000                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000000                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000000                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst        56000                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total        56000                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst        56000                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total        56000                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst        56000                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total        56000                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56100.740741                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 56100.740741                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 56100.740741                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 56100.740741                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 56100.740741                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 56100.740741                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -116,32 +116,32 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          675
 system.cpu.icache.demand_mshr_misses::total          675                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          675                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          675                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     35775000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     35775000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     35775000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     35775000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     35775000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     35775000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     35843000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     35843000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     35843000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     35843000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     35843000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     35843000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000000                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000000                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000000                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst        53000                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total        53000                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst        53000                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst        53000                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53100.740741                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53100.740741                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53100.740741                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 53100.740741                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53100.740741                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 53100.740741                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                9108581                       # number of replacements
-system.cpu.dcache.tagsinuse               4084.618409                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               4084.618075                       # Cycle average of tags in use
 system.cpu.dcache.total_refs               1668600409                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                9112677                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                 183.107599                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle            58862653000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4084.618409                       # Average occupied blocks per requestor
+system.cpu.dcache.warmup_cycle            58864243000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4084.618075                       # Average occupied blocks per requestor
 system.cpu.dcache.occ_percent::cpu.data      0.997221                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_percent::total         0.997221                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data   1231961899                       # number of ReadReq hits
@@ -160,14 +160,14 @@ system.cpu.dcache.demand_misses::cpu.data      9112677                       # n
 system.cpu.dcache.demand_misses::total        9112677                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data      9112677                       # number of overall misses
 system.cpu.dcache.overall_misses::total       9112677                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 159193930000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 159193930000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  59630900000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  59630900000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 218824830000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 218824830000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 218824830000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 218824830000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 159195313000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 159195313000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  59631053000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  59631053000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 218826366000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 218826366000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 218826366000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 218826366000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data   1239184749                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total   1239184749                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    438528337                       # number of WriteReq accesses(hits+misses)
@@ -184,14 +184,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.005432
 system.cpu.dcache.demand_miss_rate::total     0.005432                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.005432                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.005432                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22040.320649                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 22040.320649                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31553.628983                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 31553.628983                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 24013.232336                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 24013.232336                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 24013.232336                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 24013.232336                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22040.512125                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 22040.512125                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31553.709943                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 31553.709943                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 24013.400892                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 24013.400892                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 24013.400892                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 24013.400892                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -210,14 +210,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data      9112677
 system.cpu.dcache.demand_mshr_misses::total      9112677                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data      9112677                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total      9112677                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 137525380000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 137525380000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  53961419000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  53961419000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191486799000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 191486799000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191486799000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 191486799000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 137526763000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 137526763000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  53961572000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  53961572000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191488335000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 191488335000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191488335000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 191488335000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.005829                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.005829                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.004309                       # mshr miss rate for WriteReq accesses
@@ -226,28 +226,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.005432
 system.cpu.dcache.demand_mshr_miss_rate::total     0.005432                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.005432                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.005432                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19040.320649                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19040.320649                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28553.628983                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28553.628983                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21013.232336                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 21013.232336                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21013.232336                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 21013.232336                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19040.512125                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19040.512125                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28553.709943                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28553.709943                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21013.400892                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 21013.400892                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21013.400892                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 21013.400892                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements               2158210                       # number of replacements
-system.cpu.l2cache.tagsinuse             30851.506102                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse             30851.471232                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                 8410861                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs               2187939                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  3.844194                       # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle          1317336331000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 14661.525978                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst     21.582601                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data  16168.397523                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.447434                       # Average percentage of cache occupancy
+system.cpu.l2cache.warmup_cycle          1317386171000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::writebacks 14661.795010                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst     21.581563                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data  16168.094659                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.447442                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.inst     0.000659                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.493420                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.941513                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.493411                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.941512                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.data      5840135                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total        5840135                       # number of ReadReq hits
 system.cpu.l2cache.Writeback_hits::writebacks      3375759                       # number of Writeback hits
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini
index 4aef8f4de..db2911eab 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini
@@ -181,7 +181,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
@@ -213,7 +213,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout
index 926d51412..b50317767 100755
--- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout
@@ -1,10 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:05:18
-gem5 started Jun 28 2012 22:37:18
+gem5 compiled Jul  2 2012 08:30:56
+gem5 started Jul  2 2012 10:35:16
 gem5 executing on zizzer
 command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing
+Couldn't unlink  build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing/smred.sav
+Couldn't unlink  build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
@@ -21,4 +23,4 @@ Authors: Carl Sechen, Bill Swartz
  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
  91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
-122 123 124 Exiting @ tick 42005374000 because target called exit()
+122 123 124 Exiting @ tick 42012413000 because target called exit()
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
index 60e11bdef..c057cfc04 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.042005                       # Number of seconds simulated
-sim_ticks                                 42005374000                       # Number of ticks simulated
-final_tick                                42005374000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.042012                       # Number of seconds simulated
+sim_ticks                                 42012413000                       # Number of ticks simulated
+final_tick                                42012413000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 160903                       # Simulator instruction rate (inst/s)
-host_op_rate                                   160903                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               73542430                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 222752                       # Number of bytes of host memory used
-host_seconds                                   571.17                       # Real time elapsed on the host
+host_inst_rate                                 107145                       # Simulator instruction rate (inst/s)
+host_op_rate                                   107145                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               48980163                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 222716                       # Number of bytes of host memory used
+host_seconds                                   857.74                       # Real time elapsed on the host
 sim_insts                                    91903056                       # Number of instructions simulated
 sim_ops                                      91903056                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst            178816                       # Number of bytes read from this memory
@@ -19,34 +19,34 @@ system.physmem.bytes_inst_read::total          178816                       # Nu
 system.physmem.num_reads::cpu.inst               2794                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data               2144                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                  4938                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              4256979                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3266630                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 7523609                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         4256979                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            4256979                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             4256979                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             3266630                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                7523609                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst              4256266                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3266082                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 7522348                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         4256266                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            4256266                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             4256266                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             3266082                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                7522348                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     19996214                       # DTB read hits
+system.cpu.dtb.read_hits                     19996215                       # DTB read hits
 system.cpu.dtb.read_misses                         10                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                 19996224                       # DTB read accesses
-system.cpu.dtb.write_hits                     6501905                       # DTB write hits
+system.cpu.dtb.read_accesses                 19996225                       # DTB read accesses
+system.cpu.dtb.write_hits                     6501907                       # DTB write hits
 system.cpu.dtb.write_misses                        23                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                 6501928                       # DTB write accesses
-system.cpu.dtb.data_hits                     26498119                       # DTB hits
+system.cpu.dtb.write_accesses                 6501930                       # DTB write accesses
+system.cpu.dtb.data_hits                     26498122                       # DTB hits
 system.cpu.dtb.data_misses                         33                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                 26498152                       # DTB accesses
-system.cpu.itb.fetch_hits                    10037351                       # ITB hits
+system.cpu.dtb.data_accesses                 26498155                       # DTB accesses
+system.cpu.itb.fetch_hits                    10034924                       # ITB hits
 system.cpu.itb.fetch_misses                        49                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                10037400                       # ITB accesses
+system.cpu.itb.fetch_accesses                10034973                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -60,42 +60,42 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                  389                       # Number of system calls
-system.cpu.numCycles                         84010749                       # number of cpu cycles simulated
+system.cpu.numCycles                         84024827                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.branch_predictor.lookups          13563923                       # Number of BP lookups
-system.cpu.branch_predictor.condPredicted      9779691                       # Number of conditional branches predicted
-system.cpu.branch_predictor.condIncorrect      4496836                       # Number of conditional branches incorrect
-system.cpu.branch_predictor.BTBLookups        7950423                       # Number of BTB lookups
-system.cpu.branch_predictor.BTBHits           3848158                       # Number of BTB hits
+system.cpu.branch_predictor.lookups          13564834                       # Number of BP lookups
+system.cpu.branch_predictor.condPredicted      9782438                       # Number of conditional branches predicted
+system.cpu.branch_predictor.condIncorrect      4497092                       # Number of conditional branches incorrect
+system.cpu.branch_predictor.BTBLookups        7991226                       # Number of BTB lookups
+system.cpu.branch_predictor.BTBHits           3849853                       # Number of BTB hits
 system.cpu.branch_predictor.usedRAS           1029619                       # Number of times the RAS was used to get a target.
-system.cpu.branch_predictor.RASInCorrect          123                       # Number of incorrect RAS predictions.
-system.cpu.branch_predictor.BTBHitPct       48.401928                       # BTB Hit Percentage
-system.cpu.branch_predictor.predictedTaken      5997418                       # Number of Branches Predicted As Taken (True).
-system.cpu.branch_predictor.predictedNotTaken      7566505                       # Number of Branches Predicted As Not Taken (False).
-system.cpu.regfile_manager.intRegFileReads     73742077                       # Number of Reads from Int. Register File
+system.cpu.branch_predictor.RASInCorrect          121                       # Number of incorrect RAS predictions.
+system.cpu.branch_predictor.BTBHitPct       48.176000                       # BTB Hit Percentage
+system.cpu.branch_predictor.predictedTaken      5999065                       # Number of Branches Predicted As Taken (True).
+system.cpu.branch_predictor.predictedNotTaken      7565769                       # Number of Branches Predicted As Not Taken (False).
+system.cpu.regfile_manager.intRegFileReads     73744929                       # Number of Reads from Int. Register File
 system.cpu.regfile_manager.intRegFileWrites     62575472                       # Number of Writes to Int. Register File
-system.cpu.regfile_manager.intRegFileAccesses    136317549                       # Total Accesses (Read+Write) to the Int. Register File
-system.cpu.regfile_manager.floatRegFileReads      2206798                       # Number of Reads from FP Register File
+system.cpu.regfile_manager.intRegFileAccesses    136320401                       # Total Accesses (Read+Write) to the Int. Register File
+system.cpu.regfile_manager.floatRegFileReads      2206799                       # Number of Reads from FP Register File
 system.cpu.regfile_manager.floatRegFileWrites      5851888                       # Number of Writes to FP Register File
-system.cpu.regfile_manager.floatRegFileAccesses      8058686                       # Total Accesses (Read+Write) to the FP Register File
-system.cpu.regfile_manager.regForwards       38530251                       # Number of Registers Read Through Forwarding Logic
-system.cpu.agen_unit.agens                   26765541                       # Number of Address Generations
-system.cpu.execution_unit.predictedTakenIncorrect      3521133                       # Number of Branches Incorrectly Predicted As Taken.
-system.cpu.execution_unit.predictedNotTakenIncorrect       974845                       # Number of Branches Incorrectly Predicted As Not Taken).
-system.cpu.execution_unit.mispredicted        4495978                       # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.predicted           5744724                       # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.mispredictPct     43.903025                       # Percentage of Incorrect Branches Predicts
-system.cpu.execution_unit.executions         57471384                       # Number of Instructions Executed.
-system.cpu.mult_div_unit.multiplies            458266                       # Number of Multipy Operations Executed
+system.cpu.regfile_manager.floatRegFileAccesses      8058687                       # Total Accesses (Read+Write) to the FP Register File
+system.cpu.regfile_manager.regForwards       38529057                       # Number of Registers Read Through Forwarding Logic
+system.cpu.agen_unit.agens                   26768938                       # Number of Address Generations
+system.cpu.execution_unit.predictedTakenIncorrect      3519911                       # Number of Branches Incorrectly Predicted As Taken.
+system.cpu.execution_unit.predictedNotTakenIncorrect       976323                       # Number of Branches Incorrectly Predicted As Not Taken).
+system.cpu.execution_unit.mispredicted        4496234                       # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.predicted           5744468                       # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.mispredictPct     43.905525                       # Percentage of Incorrect Branches Predicts
+system.cpu.execution_unit.executions         57470438                       # Number of Instructions Executed.
+system.cpu.mult_div_unit.multiplies            458258                       # Number of Multipy Operations Executed
 system.cpu.mult_div_unit.divides                    0                       # Number of Divide Operations Executed
 system.cpu.contextSwitches                          1                       # Number of context switches
-system.cpu.threadCycles                      83632403                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles                      83640241                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
 system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled                           11097                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         7735993                       # Number of cycles cpu's stages were not processed
-system.cpu.runCycles                         76274756                       # Number of cycles cpu stages are processed.
-system.cpu.activity                         90.791663                       # Percentage of cycles cpu is active
+system.cpu.timesIdled                           11659                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         7743859                       # Number of cycles cpu's stages were not processed
+system.cpu.runCycles                         76280968                       # Number of cycles cpu stages are processed.
+system.cpu.activity                         90.783844                       # Percentage of cycles cpu is active
 system.cpu.comLoads                          19996198                       # Number of Load instructions committed
 system.cpu.comStores                          6501103                       # Number of Store instructions committed
 system.cpu.comBranches                       10240685                       # Number of Branches instructions committed
@@ -107,144 +107,144 @@ system.cpu.committedInsts                    91903056                       # Nu
 system.cpu.committedOps                      91903056                       # Number of Ops committed (Per-Thread)
 system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
 system.cpu.committedInsts_total              91903056                       # Number of Instructions committed (Total)
-system.cpu.cpi                               0.914124                       # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi                               0.914277                       # CPI: Cycles Per Instruction (Per-Thread)
 system.cpu.smt_cpi                                nan                       # CPI: Total SMT-CPI
-system.cpu.cpi_total                         0.914124                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.093944                       # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.cpi_total                         0.914277                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.093761                       # IPC: Instructions Per Cycle (Per-Thread)
 system.cpu.smt_ipc                                nan                       # IPC: Total SMT-IPC
-system.cpu.ipc_total                         1.093944                       # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles                 27790213                       # Number of cycles 0 instructions are processed.
-system.cpu.stage0.runCycles                  56220536                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization               66.920646                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles                 34560671                       # Number of cycles 0 instructions are processed.
-system.cpu.stage1.runCycles                  49450078                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization               58.861608                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles                 34032650                       # Number of cycles 0 instructions are processed.
-system.cpu.stage2.runCycles                  49978099                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization               59.490124                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles                 65981194                       # Number of cycles 0 instructions are processed.
-system.cpu.stage3.runCycles                  18029555                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization               21.461010                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles                 30068425                       # Number of cycles 0 instructions are processed.
-system.cpu.stage4.runCycles                  53942324                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization               64.208836                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.icache.replacements                   8111                       # number of replacements
-system.cpu.icache.tagsinuse               1492.322334                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 10025618                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                   9996                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                1002.962985                       # Average number of references to valid blocks.
+system.cpu.ipc_total                         1.093761                       # IPC: Total IPC of All Threads
+system.cpu.stage0.idleCycles                 27805541                       # Number of cycles 0 instructions are processed.
+system.cpu.stage0.runCycles                  56219286                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.utilization               66.907946                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles                 34577681                       # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles                  49447146                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization               58.848257                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles                 34047365                       # Number of cycles 0 instructions are processed.
+system.cpu.stage2.runCycles                  49977462                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage2.utilization               59.479399                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles                 65995198                       # Number of cycles 0 instructions are processed.
+system.cpu.stage3.runCycles                  18029629                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage3.utilization               21.457502                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles                 30080947                       # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles                  53943880                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization               64.199930                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.icache.replacements                   8128                       # number of replacements
+system.cpu.icache.tagsinuse               1492.257079                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 10023168                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                  10013                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                1001.015480                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst    1492.322334                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.728673                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.728673                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst     10025618                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        10025618                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      10025618                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         10025618                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     10025618                       # number of overall hits
-system.cpu.icache.overall_hits::total        10025618                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        11728                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         11728                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        11728                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          11728                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        11728                       # number of overall misses
-system.cpu.icache.overall_misses::total         11728                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    295393500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    295393500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    295393500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    295393500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    295393500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    295393500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     10037346                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     10037346                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     10037346                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     10037346                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     10037346                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     10037346                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.001168                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.001168                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.001168                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.001168                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.001168                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.001168                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25187.031037                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 25187.031037                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 25187.031037                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 25187.031037                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 25187.031037                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 25187.031037                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst    1492.257079                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.728641                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.728641                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst     10023168                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        10023168                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      10023168                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         10023168                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     10023168                       # number of overall hits
+system.cpu.icache.overall_hits::total        10023168                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        11752                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         11752                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        11752                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          11752                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        11752                       # number of overall misses
+system.cpu.icache.overall_misses::total         11752                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    302404500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    302404500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    302404500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    302404500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    302404500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    302404500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     10034920                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     10034920                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     10034920                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     10034920                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     10034920                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     10034920                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.001171                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.001171                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.001171                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.001171                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.001171                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.001171                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25732.173247                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 25732.173247                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 25732.173247                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 25732.173247                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 25732.173247                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 25732.173247                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets        97000                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets        91000                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               6                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets 16166.666667                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets 15166.666667                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1732                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         1732                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         1732                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         1732                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         1732                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         1732                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         9996                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         9996                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         9996                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         9996                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         9996                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         9996                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    228898000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    228898000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    228898000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    228898000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    228898000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    228898000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000996                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000996                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000996                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000996                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000996                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000996                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22898.959584                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22898.959584                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22898.959584                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 22898.959584                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22898.959584                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 22898.959584                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1739                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         1739                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         1739                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         1739                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         1739                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         1739                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        10013                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        10013                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        10013                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        10013                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        10013                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        10013                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    234933000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    234933000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    234933000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    234933000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    234933000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    234933000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000998                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000998                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000998                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000998                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000998                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000998                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23462.798362                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23462.798362                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23462.798362                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 23462.798362                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23462.798362                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 23462.798362                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                    157                       # number of replacements
-system.cpu.dcache.tagsinuse               1441.511431                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 26491208                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse               1441.425760                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 26491190                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                   2223                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs               11916.872695                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs               11916.864597                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    1441.511431                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.351932                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.351932                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data     19995646                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        19995646                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      6495562                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        6495562                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      26491208                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         26491208                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     26491208                       # number of overall hits
-system.cpu.dcache.overall_hits::total        26491208                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          552                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           552                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data         5541                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         5541                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data         6093                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           6093                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         6093                       # number of overall misses
-system.cpu.dcache.overall_misses::total          6093                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     28391500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     28391500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    303790500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    303790500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    332182000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    332182000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    332182000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    332182000                       # number of overall miss cycles
+system.cpu.dcache.occ_blocks::cpu.data    1441.425760                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.351911                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.351911                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     19995640                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        19995640                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      6495550                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        6495550                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      26491190                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         26491190                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     26491190                       # number of overall hits
+system.cpu.dcache.overall_hits::total        26491190                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          558                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           558                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data         5553                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         5553                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data         6111                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           6111                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         6111                       # number of overall misses
+system.cpu.dcache.overall_misses::total          6111                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     29911500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     29911500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    335932500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    335932500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    365844000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    365844000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    365844000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    365844000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data     19996198                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total     19996198                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data      6501103                       # number of WriteReq accesses(hits+misses)
@@ -255,38 +255,38 @@ system.cpu.dcache.overall_accesses::cpu.data     26497301
 system.cpu.dcache.overall_accesses::total     26497301                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000028                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.000028                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000852                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.000852                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.000230                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.000230                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.000230                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.000230                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51433.876812                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 51433.876812                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54825.933947                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 54825.933947                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 54518.627934                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 54518.627934                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 54518.627934                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 54518.627934                       # average overall miss latency
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000854                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.000854                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.000231                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.000231                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.000231                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.000231                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53604.838710                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 53604.838710                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60495.678012                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 60495.678012                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 59866.470299                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 59866.470299                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 59866.470299                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 59866.470299                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets     41043500                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets     41291000                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets             823                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets             827                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 49870.595383                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 49928.657799                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks          107                       # number of writebacks
 system.cpu.dcache.writebacks::total               107                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data           77                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           77                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data         3793                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total         3793                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data         3870                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total         3870                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data         3870                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total         3870                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           83                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           83                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data         3805                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total         3805                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data         3888                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total         3888                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data         3888                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total         3888                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data          475                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total          475                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1748                       # number of WriteReq MSHR misses
@@ -295,14 +295,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data         2223
 system.cpu.dcache.demand_mshr_misses::total         2223                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data         2223                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total         2223                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     23216000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     23216000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     92995500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total     92995500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    116211500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    116211500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    116211500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    116211500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     24206500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     24206500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     96919000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total     96919000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    121125500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    121125500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    121125500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    121125500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000024                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000024                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000269                       # mshr miss rate for WriteReq accesses
@@ -311,41 +311,41 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000084
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000084                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000084                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000084                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48875.789474                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48875.789474                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53201.086957                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53201.086957                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52276.878093                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 52276.878093                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52276.878093                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 52276.878093                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50961.052632                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50961.052632                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 55445.652174                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 55445.652174                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54487.404408                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 54487.404408                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54487.404408                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 54487.404408                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse              2189.730470                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                    7269                       # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse              2189.621103                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                    7286                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                  3282                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  2.214808                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                  2.219988                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks    17.847253                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst   1820.879596                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data    351.003621                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::writebacks    17.844366                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst   1820.786741                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    350.989996                       # Average occupied blocks per requestor
 system.cpu.l2cache.occ_percent::writebacks     0.000545                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst     0.055569                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.010712                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.066825                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst         7202                       # number of ReadReq hits
+system.cpu.l2cache.occ_percent::cpu.inst     0.055566                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.010711                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.066822                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst         7219                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data           53                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total           7255                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total           7272                       # number of ReadReq hits
 system.cpu.l2cache.Writeback_hits::writebacks          107                       # number of Writeback hits
 system.cpu.l2cache.Writeback_hits::total          107                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data           26                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total           26                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         7202                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst         7219                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.data           79                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total            7281                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         7202                       # number of overall hits
+system.cpu.l2cache.demand_hits::total            7298                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         7219                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.data           79                       # number of overall hits
-system.cpu.l2cache.overall_hits::total           7281                       # number of overall hits
+system.cpu.l2cache.overall_hits::total           7298                       # number of overall hits
 system.cpu.l2cache.ReadReq_misses::cpu.inst         2794                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.data          422                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::total         3216                       # number of ReadReq misses
@@ -357,52 +357,52 @@ system.cpu.l2cache.demand_misses::total          4938                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst         2794                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data         2144                       # number of overall misses
 system.cpu.l2cache.overall_misses::total         4938                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    146177000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     22139000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    168316000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     90566000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total     90566000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    146177000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    112705000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    258882000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    146177000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    112705000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    258882000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst         9996                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    149287500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     23083500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    172371000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     94426500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total     94426500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    149287500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    117510000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    266797500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    149287500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    117510000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    266797500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst        10013                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data          475                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total        10471                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total        10488                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::writebacks          107                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::total          107                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data         1748                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total         1748                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         9996                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst        10013                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data         2223                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total        12219                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         9996                       # number of overall (read+write) accesses
+system.cpu.l2cache.demand_accesses::total        12236                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        10013                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data         2223                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total        12219                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.279512                       # miss rate for ReadReq accesses
+system.cpu.l2cache.overall_accesses::total        12236                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.279037                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.888421                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.307134                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.306636                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.985126                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.985126                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.279512                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.279037                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.964462                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.404125                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.279512                       # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::total     0.403563                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.279037                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.964462                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.404125                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52318.181818                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52462.085308                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 52337.064677                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52593.495935                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52593.495935                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52318.181818                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52567.630597                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52426.488457                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52318.181818                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52567.630597                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52426.488457                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total     0.403563                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53431.460272                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54700.236967                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 53597.947761                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54835.365854                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54835.365854                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53431.460272                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54808.768657                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 54029.465371                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53431.460272                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54808.768657                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 54029.465371                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -422,39 +422,39 @@ system.cpu.l2cache.demand_mshr_misses::total         4938
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         2794                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data         2144                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total         4938                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    112070000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     16981000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    129051000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     69345500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     69345500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    112070000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     86326500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    198396500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    112070000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     86326500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    198396500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.279512                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    115196500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     17936000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    133132500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     73235000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     73235000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    115196500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     91171000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    206367500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    115196500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     91171000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    206367500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.279037                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.888421                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.307134                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.306636                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.985126                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.985126                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.279512                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.279037                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.964462                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.404125                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.279512                       # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.403563                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.279037                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.964462                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.404125                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40110.952040                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40239.336493                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40127.798507                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40270.325203                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40270.325203                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40110.952040                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40264.225746                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40177.501013                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40110.952040                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40264.225746                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40177.501013                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.403563                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41229.957051                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42502.369668                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41396.921642                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42529.036005                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42529.036005                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41229.957051                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42523.787313                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41791.717294                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41229.957051                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42523.787313                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41791.717294                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini
index d1830cc83..064828e12 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini
@@ -479,7 +479,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
@@ -511,7 +511,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout
index 157ee9690..bbfeb5540 100755
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout
@@ -1,10 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:05:18
-gem5 started Jun 28 2012 22:41:57
+gem5 compiled Jul  2 2012 08:30:56
+gem5 started Jul  2 2012 10:49:45
 gem5 executing on zizzer
 command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing
+Couldn't unlink  build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing/smred.sav
+Couldn't unlink  build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
@@ -21,4 +23,4 @@ Authors: Carl Sechen, Bill Swartz
  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
  91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
-122 123 124 Exiting @ tick 23635060000 because target called exit()
+122 123 124 Exiting @ tick 23661066000 because target called exit()
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
index 42e01362d..dcc05c5e6 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,52 +1,52 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.023635                       # Number of seconds simulated
-sim_ticks                                 23635060000                       # Number of ticks simulated
-final_tick                                23635060000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.023661                       # Number of seconds simulated
+sim_ticks                                 23661066000                       # Number of ticks simulated
+final_tick                                23661066000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 242450                       # Simulator instruction rate (inst/s)
-host_op_rate                                   242450                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               68072464                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 223772                       # Number of bytes of host memory used
-host_seconds                                   347.20                       # Real time elapsed on the host
+host_inst_rate                                 163409                       # Simulator instruction rate (inst/s)
+host_op_rate                                   163409                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               45930776                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 223740                       # Number of bytes of host memory used
+host_seconds                                   515.15                       # Real time elapsed on the host
 sim_insts                                    84179709                       # Number of instructions simulated
 sim_ops                                      84179709                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst            197248                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data            138496                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst            197312                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data            138432                       # Number of bytes read from this memory
 system.physmem.bytes_read::total               335744                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       197248                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          197248                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               3082                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               2164                       # Number of read requests responded to by this memory
+system.physmem.bytes_inst_read::cpu.inst       197312                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          197312                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               3083                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               2163                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                  5246                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              8345568                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              5859769                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                14205337                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         8345568                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            8345568                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             8345568                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             5859769                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               14205337                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst              8339100                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              5850624                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                14189724                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         8339100                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            8339100                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             8339100                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             5850624                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               14189724                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     23228346                       # DTB read hits
-system.cpu.dtb.read_misses                     200425                       # DTB read misses
-system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                 23428771                       # DTB read accesses
-system.cpu.dtb.write_hits                     7078031                       # DTB write hits
-system.cpu.dtb.write_misses                      1393                       # DTB write misses
-system.cpu.dtb.write_acv                            5                       # DTB write access violations
-system.cpu.dtb.write_accesses                 7079424                       # DTB write accesses
-system.cpu.dtb.data_hits                     30306377                       # DTB hits
-system.cpu.dtb.data_misses                     201818                       # DTB misses
+system.cpu.dtb.read_hits                     23226472                       # DTB read hits
+system.cpu.dtb.read_misses                     199471                       # DTB read misses
+system.cpu.dtb.read_acv                             2                       # DTB read access violations
+system.cpu.dtb.read_accesses                 23425943                       # DTB read accesses
+system.cpu.dtb.write_hits                     7079215                       # DTB write hits
+system.cpu.dtb.write_misses                      1341                       # DTB write misses
+system.cpu.dtb.write_acv                            3                       # DTB write access violations
+system.cpu.dtb.write_accesses                 7080556                       # DTB write accesses
+system.cpu.dtb.data_hits                     30305687                       # DTB hits
+system.cpu.dtb.data_misses                     200812                       # DTB misses
 system.cpu.dtb.data_acv                             5                       # DTB access violations
-system.cpu.dtb.data_accesses                 30508195                       # DTB accesses
-system.cpu.itb.fetch_hits                    14951144                       # ITB hits
+system.cpu.dtb.data_accesses                 30506499                       # DTB accesses
+system.cpu.itb.fetch_hits                    14950241                       # ITB hits
 system.cpu.itb.fetch_misses                       107                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                14951251                       # ITB accesses
+system.cpu.itb.fetch_accesses                14950348                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -60,146 +60,146 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                  389                       # Number of system calls
-system.cpu.numCycles                         47270121                       # number of cpu cycles simulated
+system.cpu.numCycles                         47322133                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                 15030146                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted           10897396                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect             964237                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups               8689796                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                  7074632                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                 15026940                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           10894124                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect             964629                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups               8768677                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                  7072325                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                  1488592                       # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect                3325                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles           15628273                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      128247685                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    15030146                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            8563224                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      22387448                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 4637135                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles                5522059                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                   48                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          1901                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                  14951144                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                336879                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples           47178795                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.718333                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.372984                       # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS                  1489344                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect                3225                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles           15650036                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      128237375                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    15026940                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            8561669                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      22385381                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 4637420                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles                5548184                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                   49                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles          2165                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                  14950241                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                337394                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples           47225069                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.715451                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.372476                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 24791347     52.55%     52.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  2391230      5.07%     57.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  1207932      2.56%     60.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  1776893      3.77%     63.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  2805490      5.95%     69.89% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  1170846      2.48%     72.37% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  1228782      2.60%     74.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                   789170      1.67%     76.65% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 11017105     23.35%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 24839688     52.60%     52.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  2391446      5.06%     57.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  1209126      2.56%     60.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  1776446      3.76%     63.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  2802962      5.94%     69.92% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  1171165      2.48%     72.40% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  1227887      2.60%     75.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                   787448      1.67%     76.67% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 11018901     23.33%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total             47178795                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.317963                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.713081                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 17466562                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles               4227162                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  20770000                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               1087804                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                3627267                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              2544055                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 12184                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              125158453                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                 31894                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                3627267                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 18628524                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                  960250                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           8367                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  20673426                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               3280961                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              122187472                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                    13                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 401237                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               2407508                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands            89717314                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             158683253                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        148939266                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups           9743987                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total             47225069                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.317546                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.709882                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 17490874                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles               4250840                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  20765641                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               1090220                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                3627494                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              2542741                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 12176                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              125152088                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                 32110                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                3627494                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 18655906                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                  966254                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           8182                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  20668416                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               3298817                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              122169743                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                     4                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 401900                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               2424267                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands            89702215                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             158657740                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        148914395                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups           9743345                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps              68427361                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 21289953                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               1139                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts           1148                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                   8701053                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             25559054                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores             8299979                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           2600508                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores           916071                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  106169681                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                2314                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                  96996119                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            187372                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        21529768                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     16156839                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved           1925                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples      47178795                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.055926                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.875880                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                 21274854                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               1091                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           1100                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                   8739612                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             25558040                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores             8300974                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           2604808                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores           921406                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  106164029                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                2236                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                  96990974                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            187003                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        21520200                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     16153199                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           1847                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples      47225069                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.053803                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.875376                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            12439775     26.37%     26.37% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1             9421207     19.97%     46.34% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             8463269     17.94%     64.28% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             6318044     13.39%     77.67% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             4948438     10.49%     88.16% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             2848262      6.04%     94.19% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             1729160      3.67%     97.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              800900      1.70%     99.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              209740      0.44%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            12469931     26.41%     26.41% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1             9437048     19.98%     46.39% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             8469534     17.93%     64.32% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             6320288     13.38%     77.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             4943441     10.47%     88.17% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             2849790      6.03%     94.21% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             1723941      3.65%     97.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              801134      1.70%     99.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              209962      0.44%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total        47178795                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        47225069                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  186062     11.86%     11.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     11.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     11.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                   228      0.01%     11.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     11.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                  7118      0.45%     12.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                 5890      0.38%     12.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                842932     53.71%     66.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     66.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     66.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     66.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     66.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     66.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     66.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     66.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     66.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     66.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     66.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     66.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     66.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     66.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     66.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     66.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     66.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     66.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     66.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     66.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     66.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     66.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                 447788     28.53%     94.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                 79372      5.06%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  187127     11.94%     11.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     11.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     11.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                   172      0.01%     11.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     11.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                  7127      0.45%     12.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                 5609      0.36%     12.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                843370     53.79%     66.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     66.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     66.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     66.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     66.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     66.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     66.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     66.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     66.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     66.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     66.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     66.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     66.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     66.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     66.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     66.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     66.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     66.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     66.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     66.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     66.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     66.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 445220     28.40%     94.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                 79228      5.05%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 7      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              58995521     60.82%     60.82% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               480822      0.50%     61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              58991306     60.82%     60.82% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               480706      0.50%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd             2802067      2.89%     64.21% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp              115555      0.12%     64.33% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt             2385721      2.46%     66.79% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult             311403      0.32%     67.11% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv              759596      0.78%     67.89% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd             2802495      2.89%     64.21% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp              115483      0.12%     64.33% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt             2386219      2.46%     66.79% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult             311493      0.32%     67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv              759735      0.78%     67.89% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatSqrt                319      0.00%     67.89% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.89% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.89% # Type of FU issued
@@ -221,86 +221,86 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.89% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.89% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.89% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.89% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             23975443     24.72%     92.61% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             7169665      7.39%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             23972181     24.72%     92.61% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             7171030      7.39%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total               96996119                       # Type of FU issued
-system.cpu.iq.rate                           2.051954                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     1569390                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.016180                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          227797779                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         118919368                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     87372371                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads            15130016                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes            8817376                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses      7067715                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses               90571077                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                 7994425                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          1518936                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total               96990974                       # Type of FU issued
+system.cpu.iq.rate                           2.049590                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     1567853                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.016165                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          227829224                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         118898019                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     87368354                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads            15132649                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes            8823096                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses      7068677                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses               90563080                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 7995740                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1518780                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      5562856                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        19876                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        35099                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      1798876                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      5561842                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        19579                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        34790                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      1799871                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        10509                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        10514                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked             5                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                3627267                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                  134249                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                 17377                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           116472912                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            393481                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              25559054                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts              8299979                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               2314                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                   2868                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                    32                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          35099                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         569232                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       508759                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1077991                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts              95699624                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              23429474                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           1296495                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                3627494                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                  132338                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                 17118                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           116467170                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            392102                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              25558040                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts              8300974                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               2236                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                   2929                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                    49                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          34790                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         570155                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       508194                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              1078349                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts              95694648                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              23426609                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1296326                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                      10300917                       # number of nop insts executed
-system.cpu.iew.exec_refs                     30509089                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 12078604                       # Number of branches executed
-system.cpu.iew.exec_stores                    7079615                       # Number of stores executed
-system.cpu.iew.exec_rate                     2.024527                       # Inst execution rate
-system.cpu.iew.wb_sent                       94984897                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      94440086                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  64627368                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  90016132                       # num instructions consuming a value
+system.cpu.iew.exec_nop                      10300905                       # number of nop insts executed
+system.cpu.iew.exec_refs                     30507339                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 12077728                       # Number of branches executed
+system.cpu.iew.exec_stores                    7080730                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.022196                       # Inst execution rate
+system.cpu.iew.wb_sent                       94980194                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      94437031                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  64621172                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  90003030                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.997881                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.717953                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.995621                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.717989                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts       91903055                       # The number of committed instructions
 system.cpu.commit.commitCommittedOps         91903055                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts        24570867                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts        24565165                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             389                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            952438                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples     43551528                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.110214                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.736227                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts            952869                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples     43597575                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.107985                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.734489                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     17031202     39.11%     39.11% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1      9950887     22.85%     61.95% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      4509538     10.35%     72.31% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      2291714      5.26%     77.57% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1611645      3.70%     81.27% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1125442      2.58%     83.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       722499      1.66%     85.51% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       819642      1.88%     87.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      5488959     12.60%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     17052737     39.11%     39.11% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1      9973933     22.88%     61.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      4509329     10.34%     72.33% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      2295130      5.26%     77.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1618190      3.71%     81.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1123694      2.58%     83.89% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       722585      1.66%     85.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       817482      1.88%     87.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      5484495     12.58%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total     43551528                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total     43597575                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts             91903055                       # Number of instructions committed
 system.cpu.commit.committedOps               91903055                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -311,70 +311,70 @@ system.cpu.commit.branches                   10240685                       # Nu
 system.cpu.commit.fp_insts                    6862061                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                  79581076                       # Number of committed integer instructions.
 system.cpu.commit.function_calls              1029620                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events               5488959                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events               5484495                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    154535451                       # The number of ROB reads
-system.cpu.rob.rob_writes                   236599608                       # The number of ROB writes
+system.cpu.rob.rob_reads                    154580260                       # The number of ROB reads
+system.cpu.rob.rob_writes                   236588154                       # The number of ROB writes
 system.cpu.timesIdled                            2240                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           91326                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles                           97064                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                    84179709                       # Number of Instructions Simulated
 system.cpu.committedOps                      84179709                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total              84179709                       # Number of Instructions Simulated
-system.cpu.cpi                               0.561538                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.561538                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.780823                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.780823                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                129477590                       # number of integer regfile reads
-system.cpu.int_regfile_writes                70782663                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                   6191536                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                  6049328                       # number of floating regfile writes
-system.cpu.misc_regfile_reads                  714291                       # number of misc regfile reads
+system.cpu.cpi                               0.562156                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.562156                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.778865                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.778865                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                129472042                       # number of integer regfile reads
+system.cpu.int_regfile_writes                70778136                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                   6192217                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                  6050128                       # number of floating regfile writes
+system.cpu.misc_regfile_reads                  714420                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.icache.replacements                  10215                       # number of replacements
-system.cpu.icache.tagsinuse               1600.385722                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 14937616                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                  12152                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                1229.231073                       # Average number of references to valid blocks.
+system.cpu.icache.replacements                  10236                       # number of replacements
+system.cpu.icache.tagsinuse               1604.355346                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 14936697                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                  12175                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                1226.833429                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst    1600.385722                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.781438                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.781438                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst     14937616                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        14937616                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      14937616                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         14937616                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     14937616                       # number of overall hits
-system.cpu.icache.overall_hits::total        14937616                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        13528                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         13528                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        13528                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          13528                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        13528                       # number of overall misses
-system.cpu.icache.overall_misses::total         13528                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    201479500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    201479500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    201479500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    201479500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    201479500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    201479500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     14951144                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     14951144                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     14951144                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     14951144                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     14951144                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     14951144                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000905                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000905                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000905                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000905                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000905                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000905                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14893.517150                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 14893.517150                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 14893.517150                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 14893.517150                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 14893.517150                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 14893.517150                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst    1604.355346                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.783377                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.783377                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst     14936697                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        14936697                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      14936697                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         14936697                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     14936697                       # number of overall hits
+system.cpu.icache.overall_hits::total        14936697                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        13544                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         13544                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        13544                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          13544                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        13544                       # number of overall misses
+system.cpu.icache.overall_misses::total         13544                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    214516500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    214516500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    214516500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    214516500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    214516500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    214516500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     14950241                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     14950241                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     14950241                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     14950241                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     14950241                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     14950241                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000906                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000906                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000906                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000906                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000906                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000906                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15838.489368                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 15838.489368                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 15838.489368                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 15838.489368                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 15838.489368                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 15838.489368                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -383,300 +383,300 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1376                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         1376                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         1376                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         1376                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         1376                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         1376                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        12152                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        12152                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        12152                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        12152                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        12152                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        12152                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    130219500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    130219500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    130219500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    130219500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    130219500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    130219500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000813                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000813                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000813                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000813                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000813                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000813                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10715.890388                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10715.890388                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10715.890388                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 10715.890388                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10715.890388                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 10715.890388                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1369                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         1369                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         1369                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         1369                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         1369                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         1369                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        12175                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        12175                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        12175                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        12175                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        12175                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        12175                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    142455000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    142455000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    142455000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    142455000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    142455000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    142455000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000814                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000814                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000814                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000814                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000814                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000814                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11700.616016                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11700.616016                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11700.616016                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11700.616016                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11700.616016                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11700.616016                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                    158                       # number of replacements
-system.cpu.dcache.tagsinuse               1459.321585                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 28191010                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                   2244                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs               12562.838681                       # Average number of references to valid blocks.
+system.cpu.dcache.tagsinuse               1456.192464                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 28189208                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                   2243                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs               12567.636202                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    1459.321585                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.356280                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.356280                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data     21697441                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        21697441                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      6493044                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        6493044                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data          525                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total          525                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data      28190485                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         28190485                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     28190485                       # number of overall hits
-system.cpu.dcache.overall_hits::total        28190485                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          934                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           934                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data         8059                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         8059                       # number of WriteReq misses
+system.cpu.dcache.occ_blocks::cpu.data    1456.192464                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.355516                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.355516                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     21695723                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        21695723                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      6493020                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        6493020                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data          465                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total          465                       # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits::cpu.data      28188743                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         28188743                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     28188743                       # number of overall hits
+system.cpu.dcache.overall_hits::total        28188743                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          984                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           984                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data         8083                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         8083                       # number of WriteReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            1                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            1                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data         8993                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           8993                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         8993                       # number of overall misses
-system.cpu.dcache.overall_misses::total          8993                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     27907000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     27907000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    290105500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    290105500                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        38000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total        38000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    318012500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    318012500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    318012500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    318012500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     21698375                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     21698375                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data         9067                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           9067                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         9067                       # number of overall misses
+system.cpu.dcache.overall_misses::total          9067                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     32711000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     32711000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    344620000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    344620000                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        45000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total        45000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    377331000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    377331000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    377331000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    377331000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     21696707                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     21696707                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data      6501103                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total      6501103                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data          526                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total          526                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     28199478                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     28199478                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     28199478                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     28199478                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000043                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.000043                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001240                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.001240                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.001901                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.001901                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.000319                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.000319                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.000319                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.000319                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 29879.014989                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 29879.014989                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35997.704430                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 35997.704430                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        38000                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        38000                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 35362.226176                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 35362.226176                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 35362.226176                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 35362.226176                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs         1000                       # number of cycles access was blocked
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data          466                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total          466                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     28197810                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     28197810                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     28197810                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     28197810                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000045                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.000045                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001243                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.001243                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.002146                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.002146                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.000322                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.000322                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.000322                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.000322                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33242.886179                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 33242.886179                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42635.160213                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 42635.160213                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        45000                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        45000                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 41615.859711                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 41615.859711                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 41615.859711                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 41615.859711                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        12500                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 1                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs         1000                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs        12500                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks          108                       # number of writebacks
 system.cpu.dcache.writebacks::total               108                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          421                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          421                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data         6329                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total         6329                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data         6750                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total         6750                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data         6750                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total         6750                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data          513                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          513                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1730                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total         1730                       # number of WriteReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          474                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          474                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data         6351                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total         6351                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data         6825                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total         6825                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data         6825                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total         6825                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          510                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          510                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1732                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         1732                       # number of WriteReq MSHR misses
 system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data            1                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.LoadLockedReq_mshr_misses::total            1                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data         2243                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total         2243                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data         2243                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total         2243                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     16519000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     16519000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     61611500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total     61611500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data        35000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total        35000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     78130500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     78130500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     78130500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     78130500                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data         2242                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         2242                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data         2242                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         2242                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     18104500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     18104500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     68881000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total     68881000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data        42000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total        42000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     86985500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     86985500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     86985500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     86985500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000024                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000024                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000266                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000266                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.001901                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.001901                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.002146                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.002146                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000080                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000080                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000080                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000080                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32200.779727                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32200.779727                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35613.583815                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35613.583815                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data        35000                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total        35000                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34833.036112                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 34833.036112                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34833.036112                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 34833.036112                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35499.019608                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35499.019608                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39769.630485                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39769.630485                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data        42000                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total        42000                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38798.171276                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 38798.171276                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38798.171276                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 38798.171276                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse              2418.588292                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                    9138                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                  3608                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  2.532705                       # Average number of references to valid blocks.
+system.cpu.l2cache.tagsinuse              2417.634669                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                    9160                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                  3606                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  2.540211                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks    17.698469                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst   2020.214461                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data    380.675363                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::writebacks    17.697335                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst   2024.265560                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    375.671774                       # Average occupied blocks per requestor
 system.cpu.l2cache.occ_percent::writebacks     0.000540                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst     0.061652                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.011617                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.073809                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst         9070                       # number of ReadReq hits
+system.cpu.l2cache.occ_percent::cpu.inst     0.061776                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.011465                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.073780                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst         9092                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data           54                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total           9124                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total           9146                       # number of ReadReq hits
 system.cpu.l2cache.Writeback_hits::writebacks          108                       # number of Writeback hits
 system.cpu.l2cache.Writeback_hits::total          108                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data           26                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total           26                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         9070                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst         9092                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.data           80                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total            9150                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         9070                       # number of overall hits
+system.cpu.l2cache.demand_hits::total            9172                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         9092                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.data           80                       # number of overall hits
-system.cpu.l2cache.overall_hits::total           9150                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         3082                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data          460                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         3542                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data         1704                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total         1704                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         3082                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data         2164                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_hits::total           9172                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         3083                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data          457                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total         3540                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data         1706                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total         1706                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         3083                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data         2163                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::total          5246                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         3082                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data         2164                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.inst         3083                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data         2163                       # number of overall misses
 system.cpu.l2cache.overall_misses::total         5246                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    105790500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     15832500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    121623000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     59198500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total     59198500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    105790500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     75031000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    180821500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    105790500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     75031000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    180821500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst        12152                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data          514                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total        12666                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    108859500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     17384500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    126244000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     66352500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total     66352500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    108859500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     83737000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    192596500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    108859500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     83737000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    192596500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst        12175                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data          511                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total        12686                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::writebacks          108                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::total          108                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data         1730                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total         1730                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        12152                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data         2244                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total        14396                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        12152                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data         2244                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total        14396                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.253621                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.894942                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.279646                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.984971                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.984971                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.253621                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.964349                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.364407                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.253621                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.964349                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.364407                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34325.275795                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34418.478261                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 34337.380011                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34740.903756                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34740.903756                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34325.275795                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34672.365989                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 34468.452154                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34325.275795                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34672.365989                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 34468.452154                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.ReadExReq_accesses::cpu.data         1732                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total         1732                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        12175                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data         2243                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total        14418                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        12175                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data         2243                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total        14418                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.253224                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.894325                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.279048                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.984988                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.984988                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.253224                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.964333                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.363851                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.253224                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.964333                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.363851                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35309.601038                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 38040.481400                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 35662.146893                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 38893.610785                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 38893.610785                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35309.601038                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 38713.361073                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 36713.019443                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35309.601038                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 38713.361073                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 36713.019443                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs         7500                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                1                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs         7500                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3082                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          460                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         3542                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1704                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total         1704                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3082                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data         2164                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3083                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          457                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         3540                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1706                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         1706                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3083                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data         2163                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::total         5246                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3082                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data         2164                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3083                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data         2163                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total         5246                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     95761000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     14382500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    110143500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     53772000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     53772000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     95761000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     68154500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    163915500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     95761000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     68154500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    163915500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.253621                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.894942                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.279646                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.984971                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.984971                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.253621                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.964349                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.364407                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.253621                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.964349                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.364407                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31071.057755                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31266.304348                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31096.414455                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31556.338028                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31556.338028                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31071.057755                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31494.685767                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31245.806329                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31071.057755                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31494.685767                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31245.806329                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     98880000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     15955500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    114835500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     60925000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     60925000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     98880000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     76880500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    175760500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     98880000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     76880500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    175760500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.253224                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.894325                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.279048                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.984988                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.984988                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.253224                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.964333                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.363851                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.253224                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.964333                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.363851                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32072.656503                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 34913.566740                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32439.406780                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35712.192263                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35712.192263                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32072.656503                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35543.458160                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33503.717118                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32072.656503                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35543.458160                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33503.717118                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini
index 7fbc3a2c7..218e77206 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini
@@ -148,7 +148,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
@@ -180,7 +180,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout
index 0bb9be5b6..86e423df3 100755
--- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout
@@ -1,10 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:05:18
-gem5 started Jun 28 2012 22:47:30
+gem5 compiled Jul  2 2012 08:30:56
+gem5 started Jul  2 2012 10:59:12
 gem5 executing on zizzer
 command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-timing
+Couldn't unlink  build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-timing/smred.sav
+Couldn't unlink  build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
@@ -21,4 +23,4 @@ Authors: Carl Sechen, Bill Swartz
  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
  91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
-122 123 124 Exiting @ tick 118740049000 because target called exit()
+122 123 124 Exiting @ tick 118779533000 because target called exit()
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
index b947ca514..d3e99f110 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.118740                       # Number of seconds simulated
-sim_ticks                                118740049000                       # Number of ticks simulated
-final_tick                               118740049000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.118780                       # Number of seconds simulated
+sim_ticks                                118779533000                       # Number of ticks simulated
+final_tick                               118779533000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2205371                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2205370                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2849367775                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 222752                       # Number of bytes of host memory used
-host_seconds                                    41.67                       # Real time elapsed on the host
+host_inst_rate                                1503058                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1503057                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1942616372                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 222720                       # Number of bytes of host memory used
+host_seconds                                    61.14                       # Real time elapsed on the host
 sim_insts                                    91903056                       # Number of instructions simulated
 sim_ops                                      91903056                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst            167744                       # Number of bytes read from this memory
@@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total          167744                       # Nu
 system.physmem.num_reads::cpu.inst               2621                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data               2144                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                  4765                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              1412699                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1155600                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2568299                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         1412699                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1412699                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             1412699                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1155600                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2568299                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst              1412230                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1155216                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2567446                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1412230                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1412230                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             1412230                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1155216                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2567446                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -60,7 +60,7 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                  389                       # Number of system calls
-system.cpu.numCycles                        237480098                       # number of cpu cycles simulated
+system.cpu.numCycles                        237559066                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                    91903056                       # Number of instructions committed
@@ -79,18 +79,18 @@ system.cpu.num_mem_refs                      26497334                       # nu
 system.cpu.num_load_insts                    19996208                       # Number of load instructions
 system.cpu.num_store_insts                    6501126                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  237480098                       # Number of busy cycles
+system.cpu.num_busy_cycles                  237559066                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                   6681                       # number of replacements
-system.cpu.icache.tagsinuse               1418.037996                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse               1417.992791                       # Cycle average of tags in use
 system.cpu.icache.total_refs                 91894580                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                   8510                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               10798.423032                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst    1418.037996                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.692401                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.692401                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst    1417.992791                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.692379                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.692379                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst     91894580                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total        91894580                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst      91894580                       # number of demand (read+write) hits
@@ -103,12 +103,12 @@ system.cpu.icache.demand_misses::cpu.inst         8510                       # n
 system.cpu.icache.demand_misses::total           8510                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst         8510                       # number of overall misses
 system.cpu.icache.overall_misses::total          8510                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    229222000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    229222000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    229222000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    229222000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    229222000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    229222000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    229226000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    229226000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    229226000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    229226000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    229226000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    229226000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst     91903090                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total     91903090                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst     91903090                       # number of demand (read+write) accesses
@@ -121,12 +121,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000093
 system.cpu.icache.demand_miss_rate::total     0.000093                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000093                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000093                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26935.605170                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 26935.605170                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 26935.605170                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 26935.605170                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 26935.605170                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 26935.605170                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26936.075206                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 26936.075206                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 26936.075206                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 26936.075206                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 26936.075206                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 26936.075206                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -141,34 +141,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst         8510
 system.cpu.icache.demand_mshr_misses::total         8510                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst         8510                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total         8510                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    203692000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    203692000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    203692000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    203692000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    203692000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    203692000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    203696000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    203696000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    203696000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    203696000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    203696000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    203696000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000093                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000093                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000093                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000093                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000093                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000093                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23935.605170                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23935.605170                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23935.605170                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 23935.605170                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23935.605170                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 23935.605170                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23936.075206                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23936.075206                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23936.075206                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 23936.075206                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23936.075206                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 23936.075206                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                    157                       # number of replacements
-system.cpu.dcache.tagsinuse               1442.028823                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               1441.982871                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                 26495078                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                   2223                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs               11918.613585                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    1442.028823                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.352058                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.352058                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::cpu.data    1441.982871                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.352047                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.352047                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data     19995723                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        19995723                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data      6499355                       # number of WriteReq hits
@@ -185,14 +185,14 @@ system.cpu.dcache.demand_misses::cpu.data         2223                       # n
 system.cpu.dcache.demand_misses::total           2223                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data         2223                       # number of overall misses
 system.cpu.dcache.overall_misses::total          2223                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     24374000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     24374000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     24380000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     24380000                       # number of ReadReq miss cycles
 system.cpu.dcache.WriteReq_miss_latency::cpu.data     96796000                       # number of WriteReq miss cycles
 system.cpu.dcache.WriteReq_miss_latency::total     96796000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    121170000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    121170000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    121170000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    121170000                       # number of overall miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    121176000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    121176000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    121176000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    121176000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data     19996198                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total     19996198                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data      6501103                       # number of WriteReq accesses(hits+misses)
@@ -209,14 +209,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.000084
 system.cpu.dcache.demand_miss_rate::total     0.000084                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.000084                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.000084                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51313.684211                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 51313.684211                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51326.315789                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 51326.315789                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55375.286041                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::total 55375.286041                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 54507.422402                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 54507.422402                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 54507.422402                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 54507.422402                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 54510.121457                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 54510.121457                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 54510.121457                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 54510.121457                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -235,14 +235,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data         2223
 system.cpu.dcache.demand_mshr_misses::total         2223                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data         2223                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total         2223                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     22949000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     22949000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     22955000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     22955000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     91552000                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_latency::total     91552000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    114501000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    114501000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    114501000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    114501000                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    114507000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    114507000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    114507000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    114507000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000024                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000024                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000269                       # mshr miss rate for WriteReq accesses
@@ -251,28 +251,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000084
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000084                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000084                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000084                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48313.684211                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48313.684211                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48326.315789                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48326.315789                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52375.286041                       # average WriteReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52375.286041                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51507.422402                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 51507.422402                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51507.422402                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 51507.422402                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51510.121457                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 51510.121457                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51510.121457                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 51510.121457                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse              2074.048594                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse              2073.981313                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                    5956                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                  3109                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  1.915729                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks    17.795183                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst   1704.999565                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data    351.253845                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::writebacks    17.795350                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst   1704.943449                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    351.242515                       # Average occupied blocks per requestor
 system.cpu.l2cache.occ_percent::writebacks     0.000543                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst     0.052032                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.052031                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.data     0.010719                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.063295                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.063293                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst         5889                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data           53                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total           5942                       # number of ReadReq hits
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
index bf679d420..3f37afa6e 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
@@ -497,7 +497,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
@@ -529,7 +529,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout
index 6b424cab1..e4047fa1c 100755
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout
@@ -1,10 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:10:14
-gem5 started Jun 29 2012 01:29:26
+gem5 compiled Jul  2 2012 09:08:16
+gem5 started Jul  2 2012 16:47:08
 gem5 executing on zizzer
 command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing
+Couldn't unlink  build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing/smred.sav
+Couldn't unlink  build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
@@ -21,4 +23,4 @@ info: Increasing stack size by one page.
  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
  91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
-122 123 124 Exiting @ tick 76049800000 because target called exit()
+122 123 124 Exiting @ tick 76017712000 because target called exit()
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
index a9dc709bb..5df5997a1 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
@@ -1,32 +1,32 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.076050                       # Number of seconds simulated
-sim_ticks                                 76049800000                       # Number of ticks simulated
-final_tick                                76049800000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.076018                       # Number of seconds simulated
+sim_ticks                                 76017712000                       # Number of ticks simulated
+final_tick                                76017712000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 156056                       # Simulator instruction rate (inst/s)
-host_op_rate                                   170865                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               68866655                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 238096                       # Number of bytes of host memory used
-host_seconds                                  1104.31                       # Real time elapsed on the host
-sim_insts                                   172333196                       # Number of instructions simulated
-sim_ops                                     188686678                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst            132416                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data            112128                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               244544                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       132416                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          132416                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               2069                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               1752                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  3821                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              1741175                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1474402                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3215577                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         1741175                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1741175                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             1741175                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1474402                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3215577                       # Total bandwidth to/from this memory (bytes/s)
+host_inst_rate                                 156722                       # Simulator instruction rate (inst/s)
+host_op_rate                                   171594                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               69131199                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 238024                       # Number of bytes of host memory used
+host_seconds                                  1099.62                       # Real time elapsed on the host
+sim_insts                                   172333351                       # Number of instructions simulated
+sim_ops                                     188686833                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst            131968                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data            112192                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               244160                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       131968                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          131968                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               2062                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               1753                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  3815                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              1736016                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1475867                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 3211883                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1736016                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1736016                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             1736016                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1475867                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3211883                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -70,323 +70,323 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  400                       # Number of system calls
-system.cpu.numCycles                        152099601                       # number of cpu cycles simulated
+system.cpu.numCycles                        152035425                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                 96837963                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted           76071776                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect            6557528                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups              46441082                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                 44202196                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                 96736502                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           76001405                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect            6554044                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              46407824                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                 44181263                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                  4477911                       # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect               89401                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles           40623947                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      388565051                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    96837963                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           48680107                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      82289244                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                28490098                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles                7220589                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                    9                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          8612                       # Number of stall cycles due to pending traps
+system.cpu.BPredUnit.usedRAS                  4475583                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect               89477                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles           40615724                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      388321121                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    96736502                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           48656846                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      82257766                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                28468285                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles                7213696                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                    6                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles          8844                       # Number of stall cycles due to pending traps
 system.cpu.fetch.PendingQuiesceStallCycles            1                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.CacheLines                  37659031                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               1889609                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          152039589                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.799223                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.154384                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines                  37645633                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               1886253                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          151974828                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.798620                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.154172                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 69920012     45.99%     45.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  5487559      3.61%     49.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 10685692      7.03%     56.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 10438123      6.87%     63.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  8795207      5.78%     69.28% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  6832085      4.49%     73.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  6301825      4.14%     77.91% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  8365502      5.50%     83.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 25213584     16.58%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 69887899     45.99%     45.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  5501348      3.62%     49.61% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 10684945      7.03%     56.64% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 10435662      6.87%     63.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  8784636      5.78%     69.28% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  6836908      4.50%     73.78% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  6295744      4.14%     77.93% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  8337493      5.49%     83.41% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 25210193     16.59%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            152039589                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.636675                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.554675                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 46670430                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles               5932664                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  76574160                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               1118361                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               21743974                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             14821262                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                162795                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              401681988                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                736800                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles               21743974                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 52193760                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                  715909                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         791714                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  72108942                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               4485290                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              379159906                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                     8                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 316677                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               3600241                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents                1                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           642535255                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1615137204                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1597539210                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups          17597994                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             298092419                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                344442836                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts              52681                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts          52677                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  12879836                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             44010443                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            16892323                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           5849879                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          3738879                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  334925831                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded               74527                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 252866200                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            897062                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       145077714                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    374156671                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved          23276                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     152039589                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.663160                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.758894                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            151974828                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.636276                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.554149                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 46658969                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles               5920762                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  76552571                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               1116980                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               21725546                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             14796577                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                162492                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              401466473                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                736417                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               21725546                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 52184597                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                  714677                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         792157                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  72083528                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               4474323                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              378974639                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                     5                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 320673                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               3580560                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents               14                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           642268895                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1614410837                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1596806412                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups          17604425                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             298092667                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                344176228                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts              52668                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts          52665                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  12854506                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             43974668                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            16894662                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           5833133                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          3767851                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  334792286                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               74530                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 252791404                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            896561                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       144952187                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    373840168                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved          23248                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     151974828                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.663377                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.758905                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            58521655     38.49%     38.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            23034636     15.15%     53.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            25191735     16.57%     70.21% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            20480082     13.47%     83.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            12877411      8.47%     92.15% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             6577788      4.33%     96.48% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             4065173      2.67%     99.15% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             1110646      0.73%     99.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              180463      0.12%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            58489364     38.49%     38.49% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            23011540     15.14%     53.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            25193746     16.58%     70.21% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            20486028     13.48%     83.69% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            12864515      8.46%     92.15% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             6577319      4.33%     96.48% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             4059001      2.67%     99.15% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             1110893      0.73%     99.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              182422      0.12%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       152039589                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       151974828                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  967418     37.56%     37.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                   5599      0.22%     37.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     37.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     37.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     37.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     37.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     37.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     37.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     37.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     37.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     37.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     37.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     37.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     37.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     37.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     37.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     37.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     37.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     37.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     37.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd               146      0.01%     37.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     37.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     37.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     37.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     37.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc               21      0.00%     37.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     37.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     37.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     37.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                1198100     46.52%     84.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                404230     15.70%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  966666     37.58%     37.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                   5596      0.22%     37.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     37.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     37.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     37.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     37.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     37.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     37.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     37.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     37.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     37.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     37.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     37.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     37.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     37.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     37.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     37.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     37.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     37.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     37.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd               136      0.01%     37.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     37.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     37.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     37.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     37.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc               25      0.00%     37.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     37.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     37.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     37.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                1199658     46.64%     84.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                400010     15.55%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             197377765     78.06%     78.06% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               996285      0.39%     78.45% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     78.45% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     78.45% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     78.45% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     78.45% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     78.45% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     78.45% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     78.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     78.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     78.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     78.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     78.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     78.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     78.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     78.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     78.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     78.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     78.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     78.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd           33143      0.01%     78.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     78.46% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp          164246      0.06%     78.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt          255557      0.10%     78.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv           76455      0.03%     78.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc         467877      0.19%     78.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult         206463      0.08%     78.93% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc        71866      0.03%     78.95% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt            319      0.00%     78.95% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             39025783     15.43%     94.39% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            14190441      5.61%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             197331718     78.06%     78.06% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               995910      0.39%     78.46% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     78.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     78.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     78.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     78.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     78.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     78.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     78.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     78.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     78.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     78.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     78.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     78.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     78.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     78.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     78.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     78.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     78.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     78.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd           33152      0.01%     78.47% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     78.47% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp          164284      0.06%     78.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt          255235      0.10%     78.63% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv           76457      0.03%     78.66% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc         467994      0.19%     78.85% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult         206483      0.08%     78.93% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc        71867      0.03%     78.96% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt            320      0.00%     78.96% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             38997717     15.43%     94.39% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            14190267      5.61%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              252866200                       # Type of FU issued
-system.cpu.iq.rate                           1.662504                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     2575514                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.010185                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          657470724                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         477849498                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    240611060                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads             3773841                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes            2247636                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses      1852910                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              253547208                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                 1894506                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          2021626                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              252791404                       # Type of FU issued
+system.cpu.iq.rate                           1.662714                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2572091                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.010175                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          657257029                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         477588320                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    240562315                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             3769259                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes            2249868                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses      1852626                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              253473620                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 1889875                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          2022881                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     14154924                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        16760                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        19840                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      4241654                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     14119118                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        17181                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        19942                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      4243962                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads           11                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.rescheduledLoads            7                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               21743974                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                   13418                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                   622                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           335058586                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            832362                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              44010443                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             16892323                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts              51985                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                    162                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                   263                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          19840                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        4108839                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      3946041                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              8054880                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             245860683                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              37402341                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           7005517                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles               21725546                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                   15871                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                   654                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           334925114                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            838955                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              43974668                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             16894662                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts              51980                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                    159                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                   265                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          19942                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        4105078                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      3945464                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              8050542                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             245797206                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              37379001                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           6994198                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                         58228                       # number of nop insts executed
-system.cpu.iew.exec_refs                     51211338                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 54022808                       # Number of branches executed
-system.cpu.iew.exec_stores                   13808997                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.616445                       # Inst execution rate
-system.cpu.iew.wb_sent                      243598204                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     242463970                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 150083518                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 269173561                       # num instructions consuming a value
+system.cpu.iew.exec_nop                         58298                       # number of nop insts executed
+system.cpu.iew.exec_refs                     51189045                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 54004994                       # Number of branches executed
+system.cpu.iew.exec_stores                   13810044                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.616710                       # Inst execution rate
+system.cpu.iew.wb_sent                      243546363                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     242414941                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 150055684                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 269132262                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.594113                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.557572                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.594464                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.557554                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts      172347584                       # The number of committed instructions
-system.cpu.commit.commitCommittedOps        188701066                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts       146357504                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls           51251                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           6423604                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    130295616                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.448253                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.160604                       # Number of insts commited each cycle
+system.cpu.commit.commitCommittedInsts      172347739                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps        188701221                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts       146223871                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls           51282                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts           6420079                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    130249283                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.448770                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.161298                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     60033353     46.07%     46.07% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     32093498     24.63%     70.71% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     14006031     10.75%     81.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      7653781      5.87%     87.33% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      4421161      3.39%     90.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1332201      1.02%     91.75% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      1737103      1.33%     93.08% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      1282008      0.98%     94.06% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      7736480      5.94%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     60006705     46.07%     46.07% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     32087583     24.64%     70.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     13984606     10.74%     81.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      7660285      5.88%     87.32% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      4414959      3.39%     90.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1331514      1.02%     91.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      1740633      1.34%     93.07% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      1281617      0.98%     94.06% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      7741381      5.94%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    130295616                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            172347584                       # Number of instructions committed
-system.cpu.commit.committedOps              188701066                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    130249283                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            172347739                       # Number of instructions committed
+system.cpu.commit.committedOps              188701221                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       42506188                       # Number of memory references committed
-system.cpu.commit.loads                      29855519                       # Number of loads committed
+system.cpu.commit.refs                       42506250                       # Number of memory references committed
+system.cpu.commit.loads                      29855550                       # Number of loads committed
 system.cpu.commit.membars                       22408                       # Number of memory barriers committed
-system.cpu.commit.branches                   40287717                       # Number of branches committed
+system.cpu.commit.branches                   40287748                       # Number of branches committed
 system.cpu.commit.fp_insts                    1752310                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 150130357                       # Number of committed integer instructions.
+system.cpu.commit.int_insts                 150130481                       # Number of committed integer instructions.
 system.cpu.commit.function_calls              1848934                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events               7736480                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events               7741381                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    457612505                       # The number of ROB reads
-system.cpu.rob.rob_writes                   691979598                       # The number of ROB writes
-system.cpu.timesIdled                            1775                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           60012                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                   172333196                       # Number of Instructions Simulated
-system.cpu.committedOps                     188686678                       # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total             172333196                       # Number of Instructions Simulated
-system.cpu.cpi                               0.882590                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.882590                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.133029                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.133029                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               1092071141                       # number of integer regfile reads
-system.cpu.int_regfile_writes               388656879                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                   2914235                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                  2512527                       # number of floating regfile writes
-system.cpu.misc_regfile_reads               474801777                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                 832106                       # number of misc regfile writes
-system.cpu.icache.replacements                   2596                       # number of replacements
-system.cpu.icache.tagsinuse               1365.085421                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 37653918                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                   4338                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                8680.017981                       # Average number of references to valid blocks.
+system.cpu.rob.rob_reads                    457427793                       # The number of ROB reads
+system.cpu.rob.rob_writes                   691694403                       # The number of ROB writes
+system.cpu.timesIdled                            1790                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           60597                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                   172333351                       # Number of Instructions Simulated
+system.cpu.committedOps                     188686833                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total             172333351                       # Number of Instructions Simulated
+system.cpu.cpi                               0.882217                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.882217                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.133508                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.133508                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               1091781968                       # number of integer regfile reads
+system.cpu.int_regfile_writes               388588148                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                   2914249                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                  2512479                       # number of floating regfile writes
+system.cpu.misc_regfile_reads               474590594                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                 832168                       # number of misc regfile writes
+system.cpu.icache.replacements                   2661                       # number of replacements
+system.cpu.icache.tagsinuse               1361.223505                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 37640447                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                   4399                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                8556.591725                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst    1365.085421                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.666546                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.666546                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst     37653921                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        37653921                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      37653921                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         37653921                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     37653921                       # number of overall hits
-system.cpu.icache.overall_hits::total        37653921                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         5110                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          5110                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         5110                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           5110                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         5110                       # number of overall misses
-system.cpu.icache.overall_misses::total          5110                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    111334000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    111334000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    111334000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    111334000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    111334000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    111334000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     37659031                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     37659031                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     37659031                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     37659031                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     37659031                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     37659031                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000136                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000136                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000136                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000136                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000136                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000136                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21787.475538                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 21787.475538                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 21787.475538                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 21787.475538                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 21787.475538                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 21787.475538                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst    1361.223505                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.664660                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.664660                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst     37640447                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        37640447                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      37640447                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         37640447                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     37640447                       # number of overall hits
+system.cpu.icache.overall_hits::total        37640447                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         5186                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          5186                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         5186                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           5186                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         5186                       # number of overall misses
+system.cpu.icache.overall_misses::total          5186                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    114498500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    114498500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    114498500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    114498500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    114498500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    114498500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     37645633                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     37645633                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     37645633                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     37645633                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     37645633                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     37645633                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000138                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000138                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000138                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000138                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000138                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000138                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22078.384111                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 22078.384111                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 22078.384111                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 22078.384111                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 22078.384111                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 22078.384111                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -395,110 +395,110 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          768                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          768                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          768                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          768                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          768                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          768                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4342                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         4342                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         4342                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         4342                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         4342                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         4342                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     78323000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     78323000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     78323000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     78323000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     78323000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     78323000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000115                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000115                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000115                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000115                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000115                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000115                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18038.461538                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18038.461538                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18038.461538                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 18038.461538                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18038.461538                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 18038.461538                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          786                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          786                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          786                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          786                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          786                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          786                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4400                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         4400                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         4400                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         4400                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         4400                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         4400                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     80222500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     80222500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     80222500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     80222500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     80222500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     80222500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000117                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000117                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000117                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000117                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000117                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000117                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18232.386364                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18232.386364                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18232.386364                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 18232.386364                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18232.386364                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 18232.386364                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                     58                       # number of replacements
-system.cpu.dcache.tagsinuse               1413.439257                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 47316793                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                   1865                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs               25370.934584                       # Average number of references to valid blocks.
+system.cpu.dcache.replacements                     57                       # number of replacements
+system.cpu.dcache.tagsinuse               1415.756952                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 47292959                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                   1864                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs               25371.759120                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    1413.439257                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.345078                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.345078                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data     34901837                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        34901837                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     12356702                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       12356702                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data        29806                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total        29806                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data        28442                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total        28442                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      47258539                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         47258539                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     47258539                       # number of overall hits
-system.cpu.dcache.overall_hits::total        47258539                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data         1853                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total          1853                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data         7585                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         7585                       # number of WriteReq misses
+system.cpu.dcache.occ_blocks::cpu.data    1415.756952                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.345644                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.345644                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     34877985                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        34877985                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     12356653                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       12356653                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data        29848                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total        29848                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data        28473                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total        28473                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      47234638                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         47234638                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     47234638                       # number of overall hits
+system.cpu.dcache.overall_hits::total        47234638                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data         1937                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total          1937                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data         7634                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         7634                       # number of WriteReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            2                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            2                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data         9438                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           9438                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         9438                       # number of overall misses
-system.cpu.dcache.overall_misses::total          9438                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     59897500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     59897500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    237415000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    237415000                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        64000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total        64000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    297312500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    297312500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    297312500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    297312500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     34903690                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     34903690                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data         9571                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           9571                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         9571                       # number of overall misses
+system.cpu.dcache.overall_misses::total          9571                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     71164500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     71164500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    282690000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    282690000                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        80500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total        80500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    353854500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    353854500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    353854500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    353854500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     34879922                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     34879922                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     12364287                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     12364287                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data        29808                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total        29808                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data        28442                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total        28442                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     47267977                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     47267977                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     47267977                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     47267977                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000053                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.000053                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000613                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.000613                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data        29850                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total        29850                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data        28473                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total        28473                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     47244209                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     47244209                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     47244209                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     47244209                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000056                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.000056                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000617                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.000617                       # miss rate for WriteReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000067                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000067                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.000200                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.000200                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.000200                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.000200                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32324.608743                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 32324.608743                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31300.593276                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 31300.593276                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        32000                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        32000                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 31501.642297                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 31501.642297                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 31501.642297                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 31501.642297                       # average overall miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.000203                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.000203                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.000203                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.000203                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36739.545689                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 36739.545689                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37030.390359                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 37030.390359                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        40250                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        40250                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 36971.528576                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 36971.528576                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 36971.528576                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 36971.528576                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets        10000                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -507,138 +507,134 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets         5000                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks           18                       # number of writebacks
-system.cpu.dcache.writebacks::total                18                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data         1071                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total         1071                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data         6498                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total         6498                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks           16                       # number of writebacks
+system.cpu.dcache.writebacks::total                16                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data         1154                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total         1154                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data         6553                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total         6553                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            2                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total            2                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data         7569                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total         7569                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data         7569                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total         7569                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data          782                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          782                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1087                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total         1087                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data         1869                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total         1869                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data         1869                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total         1869                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     24727500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     24727500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     38087000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total     38087000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     62814500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     62814500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     62814500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     62814500                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_hits::cpu.data         7707                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total         7707                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data         7707                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total         7707                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          783                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          783                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1081                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         1081                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data         1864                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         1864                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data         1864                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         1864                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     26652500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     26652500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     38548000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total     38548000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     65200500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     65200500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     65200500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     65200500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000022                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000022                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000088                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000088                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000040                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.000040                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000040                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.000040                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31620.843990                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31620.843990                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35038.638454                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35038.638454                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33608.614232                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 33608.614232                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33608.614232                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 33608.614232                       # average overall mshr miss latency
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000087                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000087                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000039                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.000039                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000039                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.000039                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34038.952746                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34038.952746                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35659.574468                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35659.574468                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34978.809013                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 34978.809013                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34978.809013                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 34978.809013                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse              1980.325503                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                    2358                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                  2751                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  0.857143                       # Average number of references to valid blocks.
+system.cpu.l2cache.tagsinuse              1983.510934                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                    2423                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                  2749                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.881411                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks     3.028951                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst   1438.887241                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data    538.409312                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.000092                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst     0.043911                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.016431                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.060435                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst         2267                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data           92                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total           2359                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks           18                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total           18                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data            4                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total            4                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data            9                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total            9                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         2267                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data          101                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total            2368                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         2267                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data          101                       # number of overall hits
-system.cpu.l2cache.overall_hits::total           2368                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         2073                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data          689                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         2762                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data         1075                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total         1075                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         2073                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data         1764                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total          3837                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         2073                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data         1764                       # number of overall misses
-system.cpu.l2cache.overall_misses::total         3837                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     71046500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     23679500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     94726000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     36948500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total     36948500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     71046500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     60628000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    131674500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     71046500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     60628000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    131674500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst         4340                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data          781                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total         5121                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks           18                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total           18                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data            4                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total            4                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data         1084                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total         1084                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         4340                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data         1865                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total         6205                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         4340                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data         1865                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total         6205                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.477650                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.882202                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.539348                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.991697                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.991697                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.477650                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.945845                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.618372                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.477650                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.945845                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.618372                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34272.310661                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34367.924528                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 34296.162201                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34370.697674                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34370.697674                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34272.310661                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34369.614512                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 34317.044566                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34272.310661                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34369.614512                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 34317.044566                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks     4.019168                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst   1437.049576                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    542.442189                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.000123                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.043855                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.016554                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.060532                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst         2332                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data           90                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total           2422                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks           16                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total           16                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data            7                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total            7                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst         2332                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data           97                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total            2429                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         2332                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data           97                       # number of overall hits
+system.cpu.l2cache.overall_hits::total           2429                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         2068                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data          693                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total         2761                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data         1074                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total         1074                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         2068                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data         1767                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total          3835                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         2068                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data         1767                       # number of overall misses
+system.cpu.l2cache.overall_misses::total         3835                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     72826000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     25403500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     98229500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     37378500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total     37378500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     72826000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     62782000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    135608000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     72826000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     62782000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    135608000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst         4400                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data          783                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total         5183                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks           16                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total           16                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data         1081                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total         1081                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         4400                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data         1864                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total         6264                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         4400                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data         1864                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total         6264                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.470000                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.885057                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.532703                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.993525                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.993525                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.470000                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.947961                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.612229                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.470000                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.947961                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.612229                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35215.667311                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 36657.287157                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 35577.508149                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34803.072626                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34803.072626                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35215.667311                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 35530.277306                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 35360.625815                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35215.667311                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 35530.277306                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 35360.625815                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -647,59 +643,59 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            4                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           12                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total           16                       # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst            4                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data           12                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           16                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst            4                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data           12                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           16                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2069                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          677                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         2746                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1075                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total         1075                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         2069                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data         1752                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         3821                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         2069                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data         1752                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total         3821                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     64256500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     21124000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     85380500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     33377000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     33377000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     64256500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     54501000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    118757500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     64256500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     54501000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    118757500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.476728                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.866837                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.536223                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.991697                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.991697                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.476728                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.939410                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.615794                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.476728                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.939410                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.615794                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31056.790720                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31202.363368                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31092.680262                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31048.372093                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31048.372093                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31056.790720                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31107.876712                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31080.214604                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31056.790720                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31107.876712                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31080.214604                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            6                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           14                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total           20                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst            6                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data           14                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           20                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst            6                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data           14                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total           20                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2062                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          679                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         2741                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1074                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         1074                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         2062                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data         1753                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         3815                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         2062                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data         1753                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total         3815                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     66124000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     22800500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     88924500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     33930000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     33930000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     66124000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     56730500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    122854500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     66124000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     56730500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    122854500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.468636                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.867178                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.528844                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.993525                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.993525                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.468636                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.940451                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.609036                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.468636                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.940451                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.609036                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32067.895247                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33579.528719                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32442.356804                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31592.178771                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31592.178771                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32067.895247                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 32361.950941                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 32203.014417                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32067.895247                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 32361.950941                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 32203.014417                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini
index 7a871da2f..e101e797a 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini
@@ -166,7 +166,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
@@ -198,7 +198,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout
index 0e8fdda90..fe3f7fc4c 100755
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout
@@ -1,10 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:10:14
-gem5 started Jun 29 2012 01:30:46
+gem5 compiled Jul  2 2012 09:08:16
+gem5 started Jul  2 2012 17:03:03
 gem5 executing on zizzer
 command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-timing
+Couldn't unlink  build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-timing/smred.sav
+Couldn't unlink  build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
@@ -21,4 +23,4 @@ info: Increasing stack size by one page.
  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
  91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
-122 123 124 Exiting @ tick 232077144000 because target called exit()
+122 123 124 Exiting @ tick 232089948000 because target called exit()
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
index 4c3bb52b8..709a3b23f 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.232077                       # Number of seconds simulated
-sim_ticks                                232077144000                       # Number of ticks simulated
-final_tick                               232077144000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.232090                       # Number of seconds simulated
+sim_ticks                                232089948000                       # Number of ticks simulated
+final_tick                               232089948000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1482014                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1622964                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2001492603                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 236052                       # Number of bytes of host memory used
-host_seconds                                   115.95                       # Real time elapsed on the host
+host_inst_rate                                1678684                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1838338                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2267224735                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 235976                       # Number of bytes of host memory used
+host_seconds                                   102.37                       # Real time elapsed on the host
 sim_insts                                   171842483                       # Number of instructions simulated
 sim_ops                                     188185920                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst            110656                       # Number of bytes read from this memory
@@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total          110656                       # Nu
 system.physmem.num_reads::cpu.inst               1729                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data               1724                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                  3453                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst               476807                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data               475428                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                  952235                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          476807                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             476807                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              476807                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data              475428                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                 952235                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               476781                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data               475402                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                  952183                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          476781                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             476781                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              476781                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data              475402                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                 952183                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -70,7 +70,7 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  400                       # Number of system calls
-system.cpu.numCycles                        464154288                       # number of cpu cycles simulated
+system.cpu.numCycles                        464179896                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   171842483                       # Number of instructions committed
@@ -89,18 +89,18 @@ system.cpu.num_mem_refs                      42494119                       # nu
 system.cpu.num_load_insts                    29849484                       # Number of load instructions
 system.cpu.num_store_insts                   12644635                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  464154288                       # Number of busy cycles
+system.cpu.num_busy_cycles                  464179896                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                   1506                       # number of replacements
-system.cpu.icache.tagsinuse               1147.981203                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse               1147.971530                       # Cycle average of tags in use
 system.cpu.icache.total_refs                189857001                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                   3051                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               62227.794494                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst    1147.981203                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.560538                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.560538                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst    1147.971530                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.560533                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.560533                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst    189857001                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total       189857001                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst     189857001                       # number of demand (read+write) hits
@@ -171,14 +171,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34801.376598
 system.cpu.icache.overall_avg_mshr_miss_latency::total 34801.376598                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                     40                       # number of replacements
-system.cpu.dcache.tagsinuse               1363.604373                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               1363.590777                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                 42007358                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                   1789                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs               23480.915595                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    1363.604373                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.332911                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.332911                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::cpu.data    1363.590777                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.332908                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.332908                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data     29599357                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        29599357                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     12363187                       # number of WriteReq hits
@@ -199,14 +199,14 @@ system.cpu.dcache.demand_misses::cpu.data         1789                       # n
 system.cpu.dcache.demand_misses::total           1789                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data         1789                       # number of overall misses
 system.cpu.dcache.overall_misses::total          1789                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     36190000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     36190000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     36195000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     36195000                       # number of ReadReq miss cycles
 system.cpu.dcache.WriteReq_miss_latency::cpu.data     61264000                       # number of WriteReq miss cycles
 system.cpu.dcache.WriteReq_miss_latency::total     61264000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     97454000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     97454000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     97454000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     97454000                       # number of overall miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     97459000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     97459000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     97459000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     97459000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data     29600046                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total     29600046                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     12364287                       # number of WriteReq accesses(hits+misses)
@@ -227,14 +227,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.000043
 system.cpu.dcache.demand_miss_rate::total     0.000043                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.000043                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.000043                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52525.399129                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 52525.399129                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52532.656023                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 52532.656023                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55694.545455                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::total 55694.545455                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 54474.007826                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 54474.007826                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 54474.007826                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 54474.007826                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 54476.802683                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 54476.802683                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 54476.802683                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 54476.802683                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -253,14 +253,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data         1789
 system.cpu.dcache.demand_mshr_misses::total         1789                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data         1789                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total         1789                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     34123000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     34123000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     34128000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     34128000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     57964000                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_latency::total     57964000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     92087000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     92087000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     92087000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     92087000                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     92092000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     92092000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     92092000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     92092000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000023                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000023                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000089                       # mshr miss rate for WriteReq accesses
@@ -269,28 +269,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000043
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000043                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000043                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000043                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49525.399129                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49525.399129                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49532.656023                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49532.656023                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52694.545455                       # average WriteReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52694.545455                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51474.007826                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 51474.007826                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51474.007826                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 51474.007826                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51476.802683                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 51476.802683                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51476.802683                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 51476.802683                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse              1675.648101                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse              1675.633213                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                    1380                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                  2369                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.582524                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks     3.038048                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst   1169.027783                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data    503.582269                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::writebacks     3.038052                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst   1169.018140                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    503.577021                       # Average occupied blocks per requestor
 system.cpu.l2cache.occ_percent::writebacks     0.000093                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.inst     0.035676                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.data     0.015368                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.051137                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.051136                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst         1322                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data           57                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total           1379                       # number of ReadReq hits
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini
index 35d8a380c..fd32216ef 100644
--- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini
@@ -148,7 +148,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
@@ -158,7 +158,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=twolf smred
-cwd=build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing
+cwd=build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-timing
 egid=100
 env=
 errout=cerr
@@ -180,7 +180,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout
index 8467606a8..123985114 100755
--- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun  4 2012 12:01:47
-gem5 started Jun  4 2012 15:02:43
+gem5 compiled Jul  2 2012 08:54:18
+gem5 started Jul  2 2012 12:35:14
 gem5 executing on zizzer
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing
-Couldn't unlink  build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing/smred.sav
-Couldn't unlink  build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing/smred.sv2
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-timing
+Couldn't unlink  build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-timing/smred.sav
+Couldn't unlink  build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
@@ -23,4 +23,4 @@ Authors: Carl Sechen, Bill Swartz
  91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
 info: Increasing stack size by one page.
-122 123 124 Exiting @ tick 270576960000 because target called exit()
+122 123 124 Exiting @ tick 270628681000 because target called exit()
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt
index 170992582..23f251d47 100644
--- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.270577                       # Number of seconds simulated
-sim_ticks                                270576960000                       # Number of ticks simulated
-final_tick                               270576960000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.270629                       # Number of seconds simulated
+sim_ticks                                270628681000                       # Number of ticks simulated
+final_tick                               270628681000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1394951                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1394952                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1951161352                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 227304                       # Number of bytes of host memory used
-host_seconds                                   138.67                       # Real time elapsed on the host
+host_inst_rate                                1015199                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1015200                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1420261450                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 225612                       # Number of bytes of host memory used
+host_seconds                                   190.55                       # Real time elapsed on the host
 sim_insts                                   193444531                       # Number of instructions simulated
 sim_ops                                     193444769                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst            230208                       # Number of bytes read from this memory
@@ -19,16 +19,16 @@ system.physmem.bytes_inst_read::total          230208                       # Nu
 system.physmem.num_reads::cpu.inst               3597                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data               1576                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                  5173                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst               850804                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data               372774                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1223578                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          850804                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             850804                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              850804                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data              372774                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                1223578                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               850642                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data               372703                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1223344                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          850642                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             850642                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              850642                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data              372703                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                1223344                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                  401                       # Number of system calls
-system.cpu.numCycles                        541153920                       # number of cpu cycles simulated
+system.cpu.numCycles                        541257362                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   193444531                       # Number of instructions committed
@@ -47,18 +47,18 @@ system.cpu.num_mem_refs                      76733959                       # nu
 system.cpu.num_load_insts                    57735092                       # Number of load instructions
 system.cpu.num_store_insts                   18998867                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  541153920                       # Number of busy cycles
+system.cpu.num_busy_cycles                  541257362                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                  10362                       # number of replacements
-system.cpu.icache.tagsinuse               1591.571713                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse               1591.549936                       # Cycle average of tags in use
 system.cpu.icache.total_refs                193433261                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                  12288                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               15741.639079                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst    1591.571713                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.777135                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.777135                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst    1591.549936                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.777124                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.777124                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst    193433261                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total       193433261                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst     193433261                       # number of demand (read+write) hits
@@ -129,14 +129,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23294.433594
 system.cpu.icache.overall_avg_mshr_miss_latency::total 23294.433594                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      2                       # number of replacements
-system.cpu.dcache.tagsinuse               1237.197455                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               1237.179086                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                 76732338                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                   1576                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs               48688.031726                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    1237.197455                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.302050                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.302050                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::cpu.data    1237.179086                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.302046                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.302046                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data     57734571                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        57734571                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     18975362                       # number of WriteReq hits
@@ -249,18 +249,18 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        53000
 system.cpu.dcache.overall_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse              2678.327135                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse              2678.289467                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                    8691                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                  4097                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  2.121308                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks     0.000454                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst   2275.271466                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data    403.055215                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::writebacks     0.000456                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst   2275.240506                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    403.048505                       # Average occupied blocks per requestor
 system.cpu.l2cache.occ_percent::writebacks     0.000000                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst     0.069436                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.069435                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.data     0.012300                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.081736                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.081735                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst         8691                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total           8691                       # number of ReadReq hits
 system.cpu.l2cache.Writeback_hits::writebacks            2                       # number of Writeback hits
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
index 24899e6d1..c72ea59c4 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
@@ -500,7 +500,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
@@ -532,7 +532,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
 slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
 
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
index 34329ed9e..6f015db37 100755
--- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
@@ -1,10 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:08:09
-gem5 started Jun 29 2012 00:01:11
+gem5 compiled Jul  2 2012 08:58:39
+gem5 started Jul  2 2012 14:16:35
 gem5 executing on zizzer
 command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing
+Couldn't unlink  build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing/smred.sav
+Couldn't unlink  build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
@@ -22,4 +24,4 @@ info: Increasing stack size by one page.
  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
  91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
-122 123 124 Exiting @ tick 87734048000 because target called exit()
+122 123 124 Exiting @ tick 87870590500 because target called exit()
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
index 963d9307c..d6435aa8f 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
@@ -1,130 +1,130 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.087734                       # Number of seconds simulated
-sim_ticks                                 87734048000                       # Number of ticks simulated
-final_tick                                87734048000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.087871                       # Number of seconds simulated
+sim_ticks                                 87870590500                       # Number of ticks simulated
+final_tick                                87870590500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 104988                       # Simulator instruction rate (inst/s)
-host_op_rate                                   175969                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               69742772                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 239080                       # Number of bytes of host memory used
-host_seconds                                  1257.97                       # Real time elapsed on the host
+host_inst_rate                                  71260                       # Simulator instruction rate (inst/s)
+host_op_rate                                   119437                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               47410913                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 239040                       # Number of bytes of host memory used
+host_seconds                                  1853.38                       # Real time elapsed on the host
 sim_insts                                   132071227                       # Number of instructions simulated
 sim_ops                                     221363017                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst            219520                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data            125504                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               345024                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       219520                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          219520                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               3430                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               1961                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  5391                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              2502107                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1430505                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3932612                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         2502107                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            2502107                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             2502107                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1430505                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3932612                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst            219328                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data            125312                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               344640                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       219328                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          219328                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               3427                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               1958                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  5385                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              2496034                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1426097                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 3922131                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         2496034                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            2496034                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             2496034                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1426097                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3922131                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                  400                       # Number of system calls
-system.cpu.numCycles                        175468097                       # number of cpu cycles simulated
+system.cpu.numCycles                        175741182                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                 20936810                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted           20936810                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect            2209025                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups              15519452                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                 13863485                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                 20899544                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           20899544                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect            2209301                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              15564510                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                 13831117                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
 system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles           27317448                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      226954156                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    20936810                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           13863485                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      59860939                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                19465594                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles               71226359                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                  837                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          7164                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                  25821692                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                473022                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          175391237                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.137569                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.300907                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           27321618                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      227238507                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    20899544                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           13831117                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      59893533                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                19501221                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               71423982                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                  856                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles          5992                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                  25806035                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                465205                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          175660343                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.136482                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.300848                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                117206877     66.83%     66.83% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  3231358      1.84%     68.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  2482815      1.42%     70.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  3136542      1.79%     71.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  3542923      2.02%     73.89% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  3767949      2.15%     76.04% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  4531829      2.58%     78.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  2825666      1.61%     80.24% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 34665278     19.76%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                117444586     66.86%     66.86% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  3198914      1.82%     68.68% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  2491940      1.42%     70.10% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  3160979      1.80%     71.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  3538324      2.01%     73.91% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  3753773      2.14%     76.05% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  4538217      2.58%     78.63% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  2790941      1.59%     80.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 34742669     19.78%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            175391237                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.119320                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.293421                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 40660130                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              61009372                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  46541390                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              10201855                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               16978490                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts              366073396                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles               16978490                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 48547252                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                16251189                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          23056                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  48155491                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              45435759                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              356858942                       # Number of instructions processed by rename
+system.cpu.fetch.rateDist::total            175660343                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.118922                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.293029                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 40683921                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              61195549                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  46567945                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              10198566                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               17014362                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts              366345235                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles               17014362                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 48576080                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                16382165                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          23120                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  48162732                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              45501884                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              357078991                       # Number of instructions processed by rename
 system.cpu.rename.ROBFullEvents                    31                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents               20674050                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents              22523448                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents             2249                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           506627728                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1130775437                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1120479419                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups          10296018                       # Number of floating rename lookups
+system.cpu.rename.IQFullEvents               20682611                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents              22563031                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents             2159                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           507023115                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1130829367                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1120559538                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups          10269829                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             320143989                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                186483739                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               1903                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts           1897                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  95061023                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             89836107                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            33126554                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          59108509                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         19466725                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  344545895                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                7937                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 270906839                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            256776                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       122697293                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    297019638                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved           6691                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     175391237                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.544586                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.467556                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                186879126                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               1752                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           1748                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  95224460                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             89733433                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            33126423                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          59021419                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         19494501                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  344814343                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                7981                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 271092174                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            252461                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       122957683                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    297045432                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           6735                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     175660343                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.543275                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.467777                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            49119269     28.01%     28.01% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            52565616     29.97%     57.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            34331484     19.57%     77.55% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            18982131     10.82%     88.37% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            12721464      7.25%     95.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             4942775      2.82%     98.44% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             2076613      1.18%     99.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              542627      0.31%     99.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              109258      0.06%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            49300631     28.07%     28.07% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            52565821     29.92%     57.99% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            34438082     19.60%     77.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            18985110     10.81%     88.40% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            12671961      7.21%     95.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             4951895      2.82%     98.44% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             2092177      1.19%     99.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              542850      0.31%     99.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              111816      0.06%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       175391237                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       175660343                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                   90563      3.50%      3.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   90987      3.50%      3.50% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                      0      0.00%      3.50% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%      3.50% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatAdd                     0      0.00%      3.50% # attempts to use FU when none available
@@ -153,120 +153,120 @@ system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      3.50% # at
 system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      3.50% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      3.50% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      3.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                2225289     85.92%     89.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                273998     10.58%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                2226720     85.76%     89.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                278883     10.74%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass           1212985      0.45%      0.45% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             176266302     65.07%     65.51% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    0      0.00%     65.51% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     65.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd             1595268      0.59%     66.10% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.10% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.10% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     66.10% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     66.10% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     66.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     66.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     66.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     66.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     66.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     66.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     66.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     66.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     66.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     66.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     66.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     66.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     66.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     66.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     66.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     66.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     66.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.10% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             68329319     25.22%     91.32% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            23502965      8.68%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass           1212971      0.45%      0.45% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             176440740     65.09%     65.53% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    0      0.00%     65.53% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     65.53% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd             1591628      0.59%     66.12% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.12% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.12% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     66.12% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     66.12% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     66.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     66.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     66.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     66.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     66.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     66.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     66.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     66.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     66.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     66.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     66.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     66.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     66.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     66.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     66.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     66.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     66.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.12% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.12% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             68336239     25.21%     91.33% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            23510596      8.67%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              270906839                       # Type of FU issued
-system.cpu.iq.rate                           1.543909                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     2589850                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.009560                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          714739567                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         462675137                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    263287653                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads             5311974                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes            4876750                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses      2553148                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              269622080                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                 2661624                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         18915593                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              271092174                       # Type of FU issued
+system.cpu.iq.rate                           1.542565                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2596590                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.009578                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          715388458                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         463212218                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    263468773                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             5305284                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes            4868318                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses      2548590                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              269817574                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 2658219                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         18900853                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     33186517                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        30708                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       305892                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     12610838                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     33083843                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        30126                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       305710                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     12610707                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        47515                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.rescheduledLoads        47697                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               16978490                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                  517280                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                233874                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           344553832                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            297077                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              89836107                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             33126554                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               1857                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 147591                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 33364                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         305892                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        1298592                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      1028927                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              2327519                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             267790575                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              67240366                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           3116264                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles               17014362                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                  531971                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                245364                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           344822324                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            299116                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              89733433                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             33126423                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               1715                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 158423                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 34384                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         305710                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        1300553                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      1025953                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              2326506                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             267978293                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              67258020                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           3113881                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                     90351837                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 14775060                       # Number of branches executed
-system.cpu.iew.exec_stores                   23111471                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.526150                       # Inst execution rate
-system.cpu.iew.wb_sent                      266714598                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     265840801                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 214478617                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 504376698                       # num instructions consuming a value
+system.cpu.iew.exec_refs                     90379162                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 14791945                       # Number of branches executed
+system.cpu.iew.exec_stores                   23121142                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.524846                       # Inst execution rate
+system.cpu.iew.wb_sent                      266905236                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     266017363                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 214552655                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 504482299                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.515038                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.425235                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.513688                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.425293                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts      132071227                       # The number of committed instructions
 system.cpu.commit.commitCommittedOps        221363017                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts       123301880                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       123572958                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls            1246                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           2209791                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    158412747                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.397381                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.795092                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           2210019                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    158645981                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.395327                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.792270                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     54206628     34.22%     34.22% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     60400758     38.13%     72.35% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     15586261      9.84%     82.19% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     12707072      8.02%     90.21% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      4534557      2.86%     93.07% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      2957745      1.87%     94.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      2082808      1.31%     96.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      1250624      0.79%     97.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      4686294      2.96%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     54337756     34.25%     34.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     60487783     38.13%     72.38% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     15594396      9.83%     82.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     12721179      8.02%     90.23% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      4547355      2.87%     93.09% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      2966330      1.87%     94.96% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      2094139      1.32%     96.28% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      1239343      0.78%     97.06% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      4657700      2.94%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    158412747                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    158645981                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            132071227                       # Number of instructions committed
 system.cpu.commit.committedOps              221363017                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -277,70 +277,70 @@ system.cpu.commit.branches                   12326943                       # Nu
 system.cpu.commit.fp_insts                    2162459                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                 220339606                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                    0                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events               4686294                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events               4657700                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    498391350                       # The number of ROB reads
-system.cpu.rob.rob_writes                   706346628                       # The number of ROB writes
-system.cpu.timesIdled                            1678                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           76860                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                    498924256                       # The number of ROB reads
+system.cpu.rob.rob_writes                   706924128                       # The number of ROB writes
+system.cpu.timesIdled                            1775                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           80839                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   132071227                       # Number of Instructions Simulated
 system.cpu.committedOps                     221363017                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total             132071227                       # Number of Instructions Simulated
-system.cpu.cpi                               1.328587                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.328587                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.752679                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.752679                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                657568441                       # number of integer regfile reads
-system.cpu.int_regfile_writes               365395599                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                   3514318                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                  2225520                       # number of floating regfile writes
-system.cpu.misc_regfile_reads               139440665                       # number of misc regfile reads
+system.cpu.cpi                               1.330655                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.330655                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.751510                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.751510                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                657690172                       # number of integer regfile reads
+system.cpu.int_regfile_writes               365563414                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                   3506965                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                  2222676                       # number of floating regfile writes
+system.cpu.misc_regfile_reads               139526646                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                    844                       # number of misc regfile writes
-system.cpu.icache.replacements                   5526                       # number of replacements
-system.cpu.icache.tagsinuse               1631.257386                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 25812694                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                   7496                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                3443.529082                       # Average number of references to valid blocks.
+system.cpu.icache.replacements                   5610                       # number of replacements
+system.cpu.icache.tagsinuse               1629.478377                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 25796956                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                   7578                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                3404.190552                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst    1631.257386                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.796512                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.796512                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst     25812694                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        25812694                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      25812694                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         25812694                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     25812694                       # number of overall hits
-system.cpu.icache.overall_hits::total        25812694                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         8998                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          8998                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         8998                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           8998                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         8998                       # number of overall misses
-system.cpu.icache.overall_misses::total          8998                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    186818500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    186818500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    186818500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    186818500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    186818500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    186818500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     25821692                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     25821692                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     25821692                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     25821692                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     25821692                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     25821692                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000348                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000348                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000348                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000348                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000348                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000348                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20762.224939                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 20762.224939                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 20762.224939                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 20762.224939                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 20762.224939                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 20762.224939                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst    1629.478377                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.795644                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.795644                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst     25796956                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        25796956                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      25796956                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         25796956                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     25796956                       # number of overall hits
+system.cpu.icache.overall_hits::total        25796956                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         9079                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          9079                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         9079                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           9079                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         9079                       # number of overall misses
+system.cpu.icache.overall_misses::total          9079                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    194493000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    194493000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    194493000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    194493000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    194493000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    194493000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     25806035                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     25806035                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     25806035                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     25806035                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     25806035                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     25806035                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000352                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000352                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000352                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000352                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000352                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000352                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21422.293204                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 21422.293204                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 21422.293204                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 21422.293204                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 21422.293204                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 21422.293204                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -349,78 +349,78 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1359                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         1359                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         1359                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         1359                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         1359                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         1359                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         7639                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         7639                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         7639                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         7639                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         7639                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         7639                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    130438500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    130438500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    130438500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    130438500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    130438500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    130438500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000296                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000296                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000296                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000296                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000296                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000296                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17075.337086                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17075.337086                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17075.337086                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 17075.337086                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17075.337086                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 17075.337086                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1363                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         1363                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         1363                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         1363                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         1363                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         1363                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         7716                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         7716                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         7716                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         7716                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         7716                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         7716                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    136466500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    136466500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    136466500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    136466500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    136466500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    136466500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000299                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000299                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000299                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000299                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000299                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000299                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17686.171591                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17686.171591                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17686.171591                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 17686.171591                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17686.171591                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 17686.171591                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                     57                       # number of replacements
-system.cpu.dcache.tagsinuse               1425.887115                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 68669194                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                   1998                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs               34368.965966                       # Average number of references to valid blocks.
+system.cpu.dcache.tagsinuse               1427.277065                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 68700923                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                   1995                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs               34436.552882                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    1425.887115                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.348117                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.348117                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data     48154983                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        48154983                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     20514026                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       20514026                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      68669009                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         68669009                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     68669009                       # number of overall hits
-system.cpu.dcache.overall_hits::total        68669009                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          768                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           768                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data         1704                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         1704                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data         2472                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           2472                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         2472                       # number of overall misses
-system.cpu.dcache.overall_misses::total          2472                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     24800000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     24800000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     64672500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     64672500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     89472500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     89472500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     89472500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     89472500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     48155751                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     48155751                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.occ_blocks::cpu.data    1427.277065                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.348456                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.348456                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     48186723                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        48186723                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     20514032                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       20514032                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      68700755                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         68700755                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     68700755                       # number of overall hits
+system.cpu.dcache.overall_hits::total        68700755                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          751                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           751                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data         1698                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         1698                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data         2449                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           2449                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         2449                       # number of overall misses
+system.cpu.dcache.overall_misses::total          2449                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     26925000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     26925000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     64818000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     64818000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     91743000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     91743000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     91743000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     91743000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     48187474                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     48187474                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     20515730                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     20515730                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     68671481                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     68671481                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     68671481                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     68671481                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data     68703204                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     68703204                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     68703204                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     68703204                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000016                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.000016                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000083                       # miss rate for WriteReq accesses
@@ -429,14 +429,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.000036
 system.cpu.dcache.demand_miss_rate::total     0.000036                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.000036                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.000036                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32291.666667                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 32291.666667                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37953.345070                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 37953.345070                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 36194.377023                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 36194.377023                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 36194.377023                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 36194.377023                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35852.197071                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 35852.197071                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38173.144876                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 38173.144876                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 37461.412822                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 37461.412822                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 37461.412822                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 37461.412822                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -445,32 +445,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks           14                       # number of writebacks
-system.cpu.dcache.writebacks::total                14                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          326                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          326                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data            3                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total            3                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          329                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          329                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          329                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          329                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data          442                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          442                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1701                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total         1701                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data         2143                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total         2143                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data         2143                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total         2143                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     14580500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     14580500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     59464500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total     59464500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     74045000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     74045000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     74045000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     74045000                       # number of overall MSHR miss cycles
+system.cpu.dcache.writebacks::writebacks           13                       # number of writebacks
+system.cpu.dcache.writebacks::total                13                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          310                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          310                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data            4                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total            4                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          314                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          314                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          314                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          314                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          441                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          441                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1694                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         1694                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data         2135                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         2135                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data         2135                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         2135                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     15484500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     15484500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     59638500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total     59638500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     75123000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     75123000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     75123000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     75123000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000009                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000009                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000083                       # mshr miss rate for WriteReq accesses
@@ -479,104 +479,104 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000031
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000031                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000031                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000031                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32987.556561                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32987.556561                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34958.553792                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34958.553792                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34552.029865                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 34552.029865                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34552.029865                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 34552.029865                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35112.244898                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35112.244898                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35205.726092                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35205.726092                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35186.416862                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 35186.416862                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35186.416862                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 35186.416862                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse              2578.525319                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                    4100                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                  3842                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  1.067153                       # Average number of references to valid blocks.
+system.cpu.l2cache.tagsinuse              2583.556674                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                    4185                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                  3837                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  1.090696                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks     1.139953                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst   2280.306781                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data    297.078586                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.000035                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst     0.069589                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.009066                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.078690                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst         4066                       # number of ReadReq hits
+system.cpu.l2cache.occ_blocks::writebacks     1.869475                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst   2280.566529                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    301.120670                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.000057                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.069597                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.009189                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.078844                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst         4151                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data           31                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total           4097                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks           14                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total           14                       # number of Writeback hits
+system.cpu.l2cache.ReadReq_hits::total           4182                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks           13                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total           13                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data            8                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total            8                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         4066                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst         4151                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.data           39                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total            4105                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         4066                       # number of overall hits
+system.cpu.l2cache.demand_hits::total            4190                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         4151                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.data           39                       # number of overall hits
-system.cpu.l2cache.overall_hits::total           4105                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         3430                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data          410                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         3840                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data          143                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total          143                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data         1551                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total         1551                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         3430                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data         1961                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total          5391                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         3430                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data         1961                       # number of overall misses
-system.cpu.l2cache.overall_misses::total         5391                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    117492500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     14011500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    131504000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     52997000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total     52997000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    117492500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     67008500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    184501000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    117492500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     67008500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    184501000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst         7496                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data          441                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total         7937                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks           14                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total           14                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data          143                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total          143                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data         1559                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total         1559                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         7496                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data         2000                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total         9496                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         7496                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data         2000                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total         9496                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.457577                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.929705                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.483810                       # miss rate for ReadReq accesses
+system.cpu.l2cache.overall_hits::total           4190                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         3427                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data          409                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total         3836                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data          138                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total          138                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data         1549                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total         1549                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         3427                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data         1958                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total          5385                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         3427                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data         1958                       # number of overall misses
+system.cpu.l2cache.overall_misses::total         5385                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    120377000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     14853500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    135230500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     53266000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total     53266000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    120377000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     68119500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    188496500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    120377000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     68119500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    188496500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst         7578                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data          440                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total         8018                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks           13                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total           13                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data          138                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total          138                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data         1557                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total         1557                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         7578                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data         1997                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total         9575                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         7578                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data         1997                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total         9575                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.452230                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.929545                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.478424                       # miss rate for ReadReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data            1                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.994869                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.994869                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.457577                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.980500                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.567713                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.457577                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.980500                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.567713                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34254.373178                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34174.390244                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 34245.833333                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34169.568021                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34169.568021                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34254.373178                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34170.576237                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 34223.891671                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34254.373178                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34170.576237                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 34223.891671                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.994862                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.994862                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.452230                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.980471                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.562402                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.452230                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.980471                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.562402                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35126.057776                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 36316.625917                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 35252.997914                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34387.346675                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34387.346675                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35126.057776                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34790.347293                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 35003.992572                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35126.057776                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34790.347293                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 35003.992572                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -585,58 +585,58 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3430                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          410                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         3840                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data          143                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total          143                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1551                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total         1551                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3430                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data         1961                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         5391                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3430                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data         1961                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total         5391                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    106414500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     12709500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    119124000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      4433000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      4433000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     48110500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     48110500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    106414500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     60820000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    167234500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    106414500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     60820000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    167234500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.457577                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.929705                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.483810                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3427                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          409                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         3836                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data          138                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total          138                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1549                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         1549                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3427                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data         1958                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         5385                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3427                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data         1958                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total         5385                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    109445000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     13559500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    123004500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      4278000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      4278000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     48463000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     48463000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    109445000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     62022500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    171467500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    109445000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     62022500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    171467500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.452230                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.929545                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.478424                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.994869                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.994869                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.457577                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.980500                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.567713                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.457577                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.980500                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.567713                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31024.635569                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30998.780488                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31021.875000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.994862                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.994862                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.452230                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.980471                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.562402                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.452230                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.980471                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.562402                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31936.095711                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33152.811736                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32065.823775                       # average ReadReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        31000                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        31000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31019.019987                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31019.019987                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31024.635569                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31014.788373                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31021.053608                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31024.635569                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31014.788373                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31021.053608                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31286.636540                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31286.636540                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31936.095711                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31676.455567                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31841.689879                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31936.095711                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31676.455567                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31841.689879                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini
index 168d19d0f..1ebce5cb8 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini
@@ -169,7 +169,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
@@ -201,7 +201,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
 slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
 
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout
index c17116a39..2dfefd0be 100755
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout
@@ -1,10 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:08:09
-gem5 started Jun 29 2012 00:23:42
+gem5 compiled Jul  2 2012 08:58:39
+gem5 started Jul  2 2012 14:50:18
 gem5 executing on zizzer
 command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-timing
+Couldn't unlink  build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-timing/smred.sav
+Couldn't unlink  build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
@@ -22,4 +24,4 @@ info: Increasing stack size by one page.
  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
  91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
-122 123 124 Exiting @ tick 250960631000 because target called exit()
+122 123 124 Exiting @ tick 250981042000 because target called exit()
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
index 8e544f41c..f0166c804 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.250961                       # Number of seconds simulated
-sim_ticks                                250960631000                       # Number of ticks simulated
-final_tick                               250960631000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.250981                       # Number of seconds simulated
+sim_ticks                                250981042000                       # Number of ticks simulated
+final_tick                               250981042000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1047161                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1755134                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1989805633                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 234988                       # Number of bytes of host memory used
-host_seconds                                   126.12                       # Real time elapsed on the host
+host_inst_rate                                 522050                       # Simulator instruction rate (inst/s)
+host_op_rate                                   875003                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              992076486                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 235972                       # Number of bytes of host memory used
+host_seconds                                   252.99                       # Real time elapsed on the host
 sim_insts                                   132071228                       # Number of instructions simulated
 sim_ops                                     221363018                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst            181760                       # Number of bytes read from this memory
@@ -19,16 +19,16 @@ system.physmem.bytes_inst_read::total          181760                       # Nu
 system.physmem.num_reads::cpu.inst               2840                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data               1895                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                  4735                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst               724257                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data               483263                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1207520                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          724257                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             724257                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              724257                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data              483263                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                1207520                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               724198                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data               483224                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1207422                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          724198                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             724198                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              724198                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data              483224                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                1207422                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                  400                       # Number of system calls
-system.cpu.numCycles                        501921262                       # number of cpu cycles simulated
+system.cpu.numCycles                        501962084                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   132071228                       # Number of instructions committed
@@ -47,18 +47,18 @@ system.cpu.num_mem_refs                      77165306                       # nu
 system.cpu.num_load_insts                    56649590                       # Number of load instructions
 system.cpu.num_store_insts                   20515716                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  501921262                       # Number of busy cycles
+system.cpu.num_busy_cycles                  501962084                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                   2836                       # number of replacements
-system.cpu.icache.tagsinuse               1455.289108                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse               1455.271683                       # Cycle average of tags in use
 system.cpu.icache.total_refs                173489718                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                   4694                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               36959.888794                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst    1455.289108                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.710590                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.710590                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst    1455.271683                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.710582                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.710582                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst    173489718                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total       173489718                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst     173489718                       # number of demand (read+write) hits
@@ -71,12 +71,12 @@ system.cpu.icache.demand_misses::cpu.inst         4694                       # n
 system.cpu.icache.demand_misses::total           4694                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst         4694                       # number of overall misses
 system.cpu.icache.overall_misses::total          4694                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    185041500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    185041500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    185041500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    185041500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    185041500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    185041500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    185042500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    185042500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    185042500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    185042500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    185042500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    185042500                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst    173494412                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total    173494412                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst    173494412                       # number of demand (read+write) accesses
@@ -89,12 +89,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000027
 system.cpu.icache.demand_miss_rate::total     0.000027                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000027                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000027                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39420.856412                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 39420.856412                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 39420.856412                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 39420.856412                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 39420.856412                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 39420.856412                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39421.069450                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 39421.069450                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 39421.069450                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 39421.069450                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 39421.069450                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 39421.069450                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -109,34 +109,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst         4694
 system.cpu.icache.demand_mshr_misses::total         4694                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst         4694                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total         4694                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    170928000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    170928000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    170928000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    170928000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    170928000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    170928000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    170929000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    170929000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    170929000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    170929000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    170929000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    170929000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000027                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000027                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000027                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000027                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000027                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000027                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36414.145718                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36414.145718                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36414.145718                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 36414.145718                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36414.145718                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 36414.145718                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36414.358756                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36414.358756                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36414.358756                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 36414.358756                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36414.358756                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 36414.358756                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                     41                       # number of replacements
-system.cpu.dcache.tagsinuse               1363.451495                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse               1363.438791                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                 77195833                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                   1905                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs               40522.746982                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    1363.451495                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.332874                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.332874                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::cpu.data    1363.438791                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.332871                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.332871                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data     56681681                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        56681681                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     20514152                       # number of WriteReq hits
@@ -155,12 +155,12 @@ system.cpu.dcache.overall_misses::cpu.data         1905                       #
 system.cpu.dcache.overall_misses::total          1905                       # number of overall misses
 system.cpu.dcache.ReadReq_miss_latency::cpu.data     18020000                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_latency::total     18020000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     88242000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     88242000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    106262000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    106262000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    106262000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    106262000                       # number of overall miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     88243000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     88243000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    106263000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    106263000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    106263000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    106263000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data     56682008                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total     56682008                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     20515730                       # number of WriteReq accesses(hits+misses)
@@ -179,12 +179,12 @@ system.cpu.dcache.overall_miss_rate::cpu.data     0.000025
 system.cpu.dcache.overall_miss_rate::total     0.000025                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55107.033639                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_miss_latency::total 55107.033639                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55920.152091                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 55920.152091                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 55780.577428                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 55780.577428                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 55780.577428                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 55780.577428                       # average overall miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55920.785805                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 55920.785805                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 55781.102362                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 55781.102362                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 55781.102362                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 55781.102362                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -205,12 +205,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.data         1905
 system.cpu.dcache.overall_mshr_misses::total         1905                       # number of overall MSHR misses
 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     17038500                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_latency::total     17038500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     83508000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total     83508000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    100546500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    100546500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    100546500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    100546500                       # number of overall MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     83509000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total     83509000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    100547500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    100547500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    100547500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    100547500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000006                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000006                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000077                       # mshr miss rate for WriteReq accesses
@@ -221,22 +221,22 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000025
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000025                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52105.504587                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52105.504587                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52920.152091                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52920.152091                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52780.314961                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 52780.314961                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52780.314961                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 52780.314961                       # average overall mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52920.785805                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52920.785805                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52780.839895                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 52780.839895                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52780.839895                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 52780.839895                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse              2058.168190                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse              2058.146079                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                    1862                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                  3164                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.588496                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks     0.021756                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst   1829.968899                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data    228.177535                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::writebacks     0.021788                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst   1829.948431                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    228.175860                       # Average occupied blocks per requestor
 system.cpu.l2cache.occ_percent::writebacks     0.000001                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.inst     0.055846                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.data     0.006963                       # Average percentage of cache occupancy
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
index 090f52454..b6c3eb879 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
@@ -279,7 +279,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=true
-width=64
+width=8
 default=system.tsunami.pciconfig.pio
 master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
 slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
@@ -341,7 +341,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 default=system.membus.badaddr_responder.pio
 master=system.bridge.slave system.physmem.port[0]
 slave=system.system_port system.iocache.mem_side system.l2c.mem_side
@@ -398,7 +398,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.l2c.cpu_side
 slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side
 
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
index 4abaeca9d..e633d965f 100755
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:05:18
-gem5 started Jun 28 2012 22:10:10
+gem5 compiled Jul  2 2012 08:30:56
+gem5 started Jul  2 2012 09:09:26
 gem5 executing on zizzer
 command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/vmlinux
 info: Entering event queue @ 0.  Starting simulation...
-info: Launching CPU 1 @ 562628000
-Exiting @ tick 1957577582000 because m5_exit instruction encountered
+info: Launching CPU 1 @ 573593000
+Exiting @ tick 1954209106000 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
index 9611b47c5..e64aeb301 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
@@ -1,218 +1,218 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.957578                       # Number of seconds simulated
-sim_ticks                                1957577582000                       # Number of ticks simulated
-final_tick                               1957577582000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.954209                       # Number of seconds simulated
+sim_ticks                                1954209106000                       # Number of ticks simulated
+final_tick                               1954209106000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1866861                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1866860                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            61595044213                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 296940                       # Number of bytes of host memory used
-host_seconds                                    31.78                       # Real time elapsed on the host
-sim_insts                                    59331415                       # Number of instructions simulated
-sim_ops                                      59331415                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu0.inst           825984                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         24749824                       # Number of bytes read from this memory
-system.physmem.bytes_read::tsunami.ide        2650816                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst            37440                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data           398080                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             28662144                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       825984                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst        37440                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          863424                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7684736                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7684736                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst             12906                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            386716                       # Number of read requests responded to by this memory
-system.physmem.num_reads::tsunami.ide           41419                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst               585                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data              6220                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                447846                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          120074                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               120074                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst              421942                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            12643087                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide           1354131                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               19126                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              203353                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                14641639                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         421942                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          19126                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             441068                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3925635                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3925635                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3925635                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             421942                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           12643087                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide          1354131                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              19126                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             203353                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               18567274                       # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements                        340832                       # number of replacements
-system.l2c.tagsinuse                     65295.945000                       # Cycle average of tags in use
-system.l2c.total_refs                         2492123                       # Total number of references to valid blocks.
-system.l2c.sampled_refs                        405944                       # Sample count of references to valid blocks.
-system.l2c.avg_refs                          6.139081                       # Average number of references to valid blocks.
-system.l2c.warmup_cycle                    7739998000                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks        55466.932424                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst          4795.907583                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data          4852.495880                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.inst           163.850290                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.data            16.758824                       # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks           0.846358                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.inst            0.073180                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.data            0.074043                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.inst            0.002500                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.data            0.000256                       # Average percentage of cache occupancy
-system.l2c.occ_percent::total                0.996337                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0.inst             902441                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             771400                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst              86210                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data              33732                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1793783                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          821051                       # number of Writeback hits
-system.l2c.Writeback_hits::total               821051                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data             166                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data              54                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                 220                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data            14                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data            20                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                34                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           172323                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            12709                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               185032                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.inst              902441                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              943723                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst               86210                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data               46441                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1978815                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst             902441                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             943723                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst              86210                       # number of overall hits
-system.l2c.overall_hits::cpu1.data              46441                       # number of overall hits
-system.l2c.overall_hits::total                1978815                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.inst            12906                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data           271613                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst              596                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data              192                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total               285307                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data          2453                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data           486                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              2939                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data           16                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data           72                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total              88                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data         115483                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data           6047                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             121530                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.inst             12906                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            387096                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst               596                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data              6239                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                406837                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst            12906                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           387096                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst              596                       # number of overall misses
-system.l2c.overall_misses::cpu1.data             6239                       # number of overall misses
-system.l2c.overall_misses::total               406837                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.inst    671157500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data  14128859000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst     30971000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data     10024000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total    14841011500                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0.data      2088000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data       624000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total      2712000                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data       260000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data       208000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total       468000                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data   6005389000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data    314450000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   6319839000                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.inst    671157500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data  20134248000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst     30971000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data    324474000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total     21160850500                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.inst    671157500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data  20134248000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst     30971000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data    324474000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    21160850500                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.inst         915347                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data        1043013                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst          86806                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data          33924                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2079090                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       821051                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           821051                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data         2619                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data          540                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            3159                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data           30                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data           92                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total           122                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       287806                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data        18756                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           306562                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst          915347                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data         1330819                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst           86806                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data           52680                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2385652                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         915347                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data        1330819                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst          86806                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data          52680                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2385652                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.014100                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.260412                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.006866                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.005660                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.137227                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.936617                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.900000                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.930358                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.533333                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.782609                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.721311                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.401253                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.322403                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.396429                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.014100                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.290871                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.006866                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.118432                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.170535                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.014100                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.290871                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.006866                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.118432                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.170535                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52003.525492                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 52018.345955                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51964.765101                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 52208.333333                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 52017.691469                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   851.202609                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  1283.950617                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total   922.762845                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data        16250                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  2888.888889                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  5318.181818                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52002.363984                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52000.992228                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 52002.295729                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 52003.525492                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 52013.578027                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 51964.765101                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 52007.372976                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 52013.092467                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 52003.525492                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 52013.578027                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 51964.765101                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 52007.372976                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 52013.092467                       # average overall miss latency
+host_inst_rate                                1820229                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1820228                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            59866957581                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 296900                       # Number of bytes of host memory used
+host_seconds                                    32.64                       # Real time elapsed on the host
+sim_insts                                    59416827                       # Number of instructions simulated
+sim_ops                                      59416827                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu0.inst           717056                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         23797184                       # Number of bytes read from this memory
+system.physmem.bytes_read::tsunami.ide        2649344                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           145856                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          1424768                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             28734208                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       717056                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       145856                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          862912                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7745216                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7745216                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst             11204                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            371831                       # Number of read requests responded to by this memory
+system.physmem.num_reads::tsunami.ide           41396                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              2279                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             22262                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                448972                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          121019                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               121019                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst              366929                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data            12177399                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide           1355712                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               74637                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              729077                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                14703753                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         366929                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          74637                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             441566                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3963351                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                3963351                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3963351                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             366929                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           12177399                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide          1355712                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              74637                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             729077                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               18667104                       # Total bandwidth to/from this memory (bytes/s)
+system.l2c.replacements                        342059                       # number of replacements
+system.l2c.tagsinuse                     65268.179703                       # Cycle average of tags in use
+system.l2c.total_refs                         2559285                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                        407065                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                          6.287165                       # Average number of references to valid blocks.
+system.l2c.warmup_cycle                    7752825000                       # Cycle when the warmup percentage was hit.
+system.l2c.occ_blocks::writebacks        55637.656104                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst          3742.496714                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data          4175.529809                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst          1176.827938                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.data           535.669138                       # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks           0.848963                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.inst            0.057106                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.data            0.063714                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.inst            0.017957                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.data            0.008174                       # Average percentage of cache occupancy
+system.l2c.occ_percent::total                0.995913                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu0.inst             478629                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data             342574                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst             511941                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data             491320                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1824464                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          858732                       # number of Writeback hits
+system.l2c.Writeback_hits::total               858732                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data             137                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data              95                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                 232                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data            22                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data            24                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total                46                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data           101383                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            99295                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               200678                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.inst              478629                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              443957                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              511941                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              590615                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 2025142                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.inst             478629                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             443957                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             511941                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             590615                       # number of overall hits
+system.l2c.overall_hits::total                2025142                       # number of overall hits
+system.l2c.ReadReq_misses::cpu0.inst            11204                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data           270589                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst             2290                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data             1211                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total               285294                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data          2576                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data           476                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              3052                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data           85                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data           88                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total             173                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data         101598                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data          21093                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             122691                       # number of ReadExReq misses
+system.l2c.demand_misses::cpu0.inst             11204                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data            372187                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst              2290                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data             22304                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                407985                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.inst            11204                       # number of overall misses
+system.l2c.overall_misses::cpu0.data           372187                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst             2290                       # number of overall misses
+system.l2c.overall_misses::cpu1.data            22304                       # number of overall misses
+system.l2c.overall_misses::total               407985                       # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu0.inst    582910000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.data  14075669000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst    119002000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data     63420000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total    14841001000                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu0.data      1144000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data      1924000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total      3068000                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data       695000                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data       156000                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total       851000                       # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data   5283374000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data   1096874000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   6380248000                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu0.inst    582910000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data  19359043000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst    119002000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data   1160294000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total     21221249000                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.inst    582910000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data  19359043000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst    119002000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data   1160294000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total    21221249000                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.inst         489833                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data         613163                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst         514231                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data         492531                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            2109758                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       858732                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           858732                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data         2713                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data          571                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            3284                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data          107                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data          112                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total           219                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       202981                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data       120388                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           323369                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.inst          489833                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data          816144                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          514231                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data          612919                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             2433127                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         489833                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data         816144                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         514231                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data         612919                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            2433127                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.022873                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.441300                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.004453                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data      0.002459                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.135226                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.949502                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.833625                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.929354                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.794393                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.785714                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.789954                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.500530                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.175208                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.379415                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.022873                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.456031                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.004453                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.036390                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.167679                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.022873                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.456031                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.004453                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.036390                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.167679                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52026.954659                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.data 52018.629730                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51965.938865                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 52369.942197                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 52020.024957                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   444.099379                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  4042.016807                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  1005.242464                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  8176.470588                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  1772.727273                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total  4919.075145                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52002.736274                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52001.801546                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 52002.575576                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 52026.954659                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 52014.291203                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 51965.938865                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 52021.789813                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 52014.777504                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 52026.954659                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 52014.291203                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 51965.938865                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 52021.789813                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 52014.777504                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -221,119 +221,119 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               78554                       # number of writebacks
-system.l2c.writebacks::total                    78554                       # number of writebacks
+system.l2c.writebacks::writebacks               79488                       # number of writebacks
+system.l2c.writebacks::total                    79488                       # number of writebacks
 system.l2c.ReadReq_mshr_hits::cpu1.inst            11                       # number of ReadReq MSHR hits
 system.l2c.ReadReq_mshr_hits::total                11                       # number of ReadReq MSHR hits
 system.l2c.demand_mshr_hits::cpu1.inst             11                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_hits::total                 11                       # number of demand (read+write) MSHR hits
 system.l2c.overall_mshr_hits::cpu1.inst            11                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::total                11                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu0.inst        12906                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.data       271613                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst          585                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data          192                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total          285296                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data         2453                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data          486                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total         2939                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data           16                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data           72                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total           88                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data       115483                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data         6047                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        121530                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst        12906                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data       387096                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst          585                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data         6239                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           406826                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst        12906                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data       387096                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst          585                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data         6239                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          406826                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    516282000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.data  10869503000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst     23400000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data      7720000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total  11416905000                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     98186000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     19446000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total    117632000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data       640000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      2880000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total      3520000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   4619593000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    241886000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   4861479000                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst    516282000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data  15489096000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst     23400000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data    249606000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  16278384000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst    516282000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data  15489096000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst     23400000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data    249606000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  16278384000                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data    792098000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data     10214500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total    802312500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   1122098500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    269224500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   1391323000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   1914196500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data    279439000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   2193635500                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.014100                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.260412                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.006739                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.005660                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.137222                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.936617                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.900000                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.930358                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.533333                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.782609                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.721311                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.401253                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.322403                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.396429                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.014100                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.290871                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.006739                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.118432                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.170530                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.014100                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.290871                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.006739                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.118432                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.170530                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40003.254300                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40018.345955                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst        40000                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40208.333333                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 40017.753491                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40026.905830                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40012.345679                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40024.498129                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        40000                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadReq_mshr_misses::cpu0.inst        11204                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.data       270589                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.inst         2279                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.data         1211                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total          285283                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data         2576                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data          476                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total         3052                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data           85                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data           88                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total          173                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data       101598                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data        21093                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        122691                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst        11204                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data       372187                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst         2279                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data        22304                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           407974                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst        11204                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data       372187                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst         2279                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data        22304                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          407974                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    448459000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.data  10828601000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst     91164000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data     48888000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total  11417112000                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    103144000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     19089000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    122233000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      3419000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      3520000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total      6939000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   4064198000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    843758000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   4907956000                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst    448459000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data  14892799000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst     91164000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data    892646000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  16325068000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst    448459000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data  14892799000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst     91164000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data    892646000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  16325068000                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data    538312030                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    264188000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total    802500030                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data    914387000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    465201000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   1379588000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   1452699030                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data    729389000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   2182088030                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.022873                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.441300                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.004432                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.002459                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.135221                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.949502                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.833625                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.929354                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.794393                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.785714                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.789954                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.500530                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.175208                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.379415                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.022873                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.456031                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.004432                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.036390                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.167675                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.022873                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.456031                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.004432                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.036390                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.167675                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40026.686898                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40018.629730                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40001.755156                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40369.942197                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 40020.302647                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40040.372671                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40102.941176                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40050.131062                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40223.529412                       # average SCUpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        40000                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        40000                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40002.363984                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40000.992228                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 40002.295729                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40003.254300                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40013.578027                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst        40000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40007.372976                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 40013.135837                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40003.254300                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40013.578027                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst        40000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40007.372976                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 40013.135837                       # average overall mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40109.826590                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40002.736274                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40001.801546                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 40002.575576                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40026.686898                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40014.291203                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40001.755156                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40021.789813                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 40014.971542                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40026.686898                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40014.291203                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40001.755156                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40021.789813                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 40014.971542                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -344,39 +344,39 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.iocache.replacements                     41694                       # number of replacements
-system.iocache.tagsinuse                     0.563379                       # Cycle average of tags in use
+system.iocache.replacements                     41707                       # number of replacements
+system.iocache.tagsinuse                     1.261560                       # Cycle average of tags in use
 system.iocache.total_refs                           0                       # Total number of references to valid blocks.
-system.iocache.sampled_refs                     41710                       # Sample count of references to valid blocks.
+system.iocache.sampled_refs                     41723                       # Sample count of references to valid blocks.
 system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
-system.iocache.warmup_cycle              1750565168000                       # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::tsunami.ide       0.563379                       # Average occupied blocks per requestor
-system.iocache.occ_percent::tsunami.ide      0.035211                       # Average percentage of cache occupancy
-system.iocache.occ_percent::total            0.035211                       # Average percentage of cache occupancy
-system.iocache.ReadReq_misses::tsunami.ide          174                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              174                       # number of ReadReq misses
+system.iocache.warmup_cycle              1747651126000                       # Cycle when the warmup percentage was hit.
+system.iocache.occ_blocks::tsunami.ide       1.261560                       # Average occupied blocks per requestor
+system.iocache.occ_percent::tsunami.ide      0.078847                       # Average percentage of cache occupancy
+system.iocache.occ_percent::total            0.078847                       # Average percentage of cache occupancy
+system.iocache.ReadReq_misses::tsunami.ide          176                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              176                       # number of ReadReq misses
 system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
-system.iocache.demand_misses::tsunami.ide        41726                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             41726                       # number of demand (read+write) misses
-system.iocache.overall_misses::tsunami.ide        41726                       # number of overall misses
-system.iocache.overall_misses::total            41726                       # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide     20052998                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     20052998                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::tsunami.ide   5719883806                       # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total   5719883806                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide   5739936804                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   5739936804                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide   5739936804                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   5739936804                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::tsunami.ide          174                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            174                       # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::tsunami.ide        41728                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             41728                       # number of demand (read+write) misses
+system.iocache.overall_misses::tsunami.ide        41728                       # number of overall misses
+system.iocache.overall_misses::total            41728                       # number of overall misses
+system.iocache.ReadReq_miss_latency::tsunami.ide     21013998                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     21013998                       # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::tsunami.ide   7626020806                       # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total   7626020806                       # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide   7647034804                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   7647034804                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide   7647034804                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   7647034804                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::tsunami.ide          176                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            176                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::tsunami.ide        41726                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           41726                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::tsunami.ide        41726                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          41726                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::tsunami.ide        41728                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           41728                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::tsunami.ide        41728                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          41728                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
@@ -385,40 +385,40 @@ system.iocache.demand_miss_rate::tsunami.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115247.114943                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 115247.114943                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137656.040768                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 137656.040768                       # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 137562.594162                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 137562.594162                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 137562.594162                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 137562.594162                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs      64630068                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119397.715909                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 119397.715909                       # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183529.572728                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 183529.572728                       # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 183259.077933                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 183259.077933                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 183259.077933                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 183259.077933                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs       7245000                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                10459                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 7076                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs  6179.373554                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs  1023.883550                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks           41520                       # number of writebacks
-system.iocache.writebacks::total                41520                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::tsunami.ide          174                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          174                       # number of ReadReq MSHR misses
+system.iocache.writebacks::writebacks           41531                       # number of writebacks
+system.iocache.writebacks::total                41531                       # number of writebacks
+system.iocache.ReadReq_mshr_misses::tsunami.ide          176                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          176                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::tsunami.ide        41552                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total        41552                       # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses::tsunami.ide        41726                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total        41726                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::tsunami.ide        41726                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total        41726                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     11004998                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     11004998                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::tsunami.ide   3559028000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total   3559028000                       # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide   3570032998                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   3570032998                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide   3570032998                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   3570032998                       # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::tsunami.ide        41728                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total        41728                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::tsunami.ide        41728                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total        41728                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     11861000                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     11861000                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::tsunami.ide   5465163000                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total   5465163000                       # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide   5477024000                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   5477024000                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide   5477024000                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   5477024000                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
@@ -427,14 +427,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63247.114943                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 63247.114943                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85652.387370                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 85652.387370                       # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85558.955999                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 85558.955999                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85558.955999                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 85558.955999                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67392.045455                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 67392.045455                       # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131525.871198                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 131525.871198                       # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131255.368098                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 131255.368098                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131255.368098                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 131255.368098                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -452,22 +452,22 @@ system.cpu0.dtb.fetch_hits                          0                       # IT
 system.cpu0.dtb.fetch_misses                        0                       # ITB misses
 system.cpu0.dtb.fetch_acv                           0                       # ITB acv
 system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu0.dtb.read_hits                     8630502                       # DTB read hits
-system.cpu0.dtb.read_misses                      7443                       # DTB read misses
-system.cpu0.dtb.read_acv                          210                       # DTB read access violations
-system.cpu0.dtb.read_accesses                  490673                       # DTB read accesses
-system.cpu0.dtb.write_hits                    6043026                       # DTB write hits
-system.cpu0.dtb.write_misses                      813                       # DTB write misses
-system.cpu0.dtb.write_acv                         134                       # DTB write access violations
-system.cpu0.dtb.write_accesses                 187452                       # DTB write accesses
-system.cpu0.dtb.data_hits                    14673528                       # DTB hits
-system.cpu0.dtb.data_misses                      8256                       # DTB misses
-system.cpu0.dtb.data_acv                          344                       # DTB access violations
-system.cpu0.dtb.data_accesses                  678125                       # DTB accesses
-system.cpu0.itb.fetch_hits                    3852973                       # ITB hits
-system.cpu0.itb.fetch_misses                     3871                       # ITB misses
-system.cpu0.itb.fetch_acv                         184                       # ITB acv
-system.cpu0.itb.fetch_accesses                3856844                       # ITB accesses
+system.cpu0.dtb.read_hits                     5733478                       # DTB read hits
+system.cpu0.dtb.read_misses                      7687                       # DTB read misses
+system.cpu0.dtb.read_acv                          174                       # DTB read access violations
+system.cpu0.dtb.read_accesses                  524201                       # DTB read accesses
+system.cpu0.dtb.write_hits                    3961950                       # DTB write hits
+system.cpu0.dtb.write_misses                      798                       # DTB write misses
+system.cpu0.dtb.write_acv                         115                       # DTB write access violations
+system.cpu0.dtb.write_accesses                 195659                       # DTB write accesses
+system.cpu0.dtb.data_hits                     9695428                       # DTB hits
+system.cpu0.dtb.data_misses                      8485                       # DTB misses
+system.cpu0.dtb.data_acv                          289                       # DTB access violations
+system.cpu0.dtb.data_accesses                  719860                       # DTB accesses
+system.cpu0.itb.fetch_hits                    3214168                       # ITB hits
+system.cpu0.itb.fetch_misses                     3841                       # ITB misses
+system.cpu0.itb.fetch_acv                         143                       # ITB acv
+system.cpu0.itb.fetch_accesses                3218009                       # ITB accesses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.read_acv                            0                       # DTB read access violations
@@ -480,117 +480,118 @@ system.cpu0.itb.data_hits                           0                       # DT
 system.cpu0.itb.data_misses                         0                       # DTB misses
 system.cpu0.itb.data_acv                            0                       # DTB access violations
 system.cpu0.itb.data_accesses                       0                       # DTB accesses
-system.cpu0.numCycles                      3914070794                       # number of cpu cycles simulated
+system.cpu0.numCycles                      3908418212                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   54051547                       # Number of instructions committed
-system.cpu0.committedOps                     54051547                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             50023130                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                293967                       # Number of float alu accesses
-system.cpu0.num_func_calls                    1426247                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      6235141                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    50023130                       # number of integer instructions
-system.cpu0.num_fp_insts                       293967                       # number of float instructions
-system.cpu0.num_int_register_reads           68498295                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          37064173                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads              143353                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes             146452                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                     14719518                       # number of memory refs
-system.cpu0.num_load_insts                    8661793                       # Number of load instructions
-system.cpu0.num_store_insts                   6057725                       # Number of store instructions
-system.cpu0.num_idle_cycles              3679914036.735006                       # Number of idle cycles
-system.cpu0.num_busy_cycles              234156757.264994                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.059824                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.940176                       # Percentage of idle cycles
+system.cpu0.committedInsts                   36160823                       # Number of instructions committed
+system.cpu0.committedOps                     36160823                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses             33648358                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                143029                       # Number of float alu accesses
+system.cpu0.num_func_calls                     874754                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      4239281                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    33648358                       # number of integer instructions
+system.cpu0.num_fp_insts                       143029                       # number of float instructions
+system.cpu0.num_int_register_reads           46246578                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          25142775                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads               70823                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes              71471                       # number of times the floating registers were written
+system.cpu0.num_mem_refs                      9726012                       # number of memory refs
+system.cpu0.num_load_insts                    5755191                       # Number of load instructions
+system.cpu0.num_store_insts                   3970821                       # Number of store instructions
+system.cpu0.num_idle_cycles              3741416410.998085                       # Number of idle cycles
+system.cpu0.num_busy_cycles              167001801.001915                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.042729                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.957271                       # Percentage of idle cycles
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    6362                       # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei                    202969                       # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0                   72743     40.62%     40.62% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::21                    131      0.07%     40.70% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22                   1974      1.10%     41.80% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::30                      6      0.00%     41.80% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31                 104206     58.20%    100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total              179060                       # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0                    71376     49.27%     49.27% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::21                     131      0.09%     49.36% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22                    1974      1.36%     50.73% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::30                       6      0.00%     50.73% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31                   71370     49.27%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total               144857                       # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0            1898820258500     97.03%     97.03% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21               78970000      0.00%     97.03% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22              565865000      0.03%     97.06% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::30                4687500      0.00%     97.06% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31            57565586000      2.94%    100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total        1957035367000                       # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0                 0.981208                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.inst.quiesce                    4839                       # number of quiesce instructions executed
+system.cpu0.kern.inst.hwrei                    129052                       # number of hwrei instructions executed
+system.cpu0.kern.ipl_count::0                   41012     38.31%     38.31% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::21                    131      0.12%     38.43% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::22                   1971      1.84%     40.28% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::30                     17      0.02%     40.29% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31                  63918     59.71%    100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total              107049                       # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0                    40581     48.74%     48.74% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::21                     131      0.16%     48.90% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::22                    1971      2.37%     51.26% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::30                      17      0.02%     51.28% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::31                   40564     48.72%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::total                83264                       # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks::0            1905787793000     97.52%     97.52% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21               88207500      0.00%     97.53% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22              590484500      0.03%     97.56% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::30               12827000      0.00%     97.56% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31            47728938000      2.44%    100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total        1954208250000                       # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used::0                 0.989491                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31                0.684893                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total             0.808986                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.syscall::2                         8      3.60%      3.60% # number of syscalls executed
-system.cpu0.kern.syscall::3                        19      8.56%     12.16% # number of syscalls executed
-system.cpu0.kern.syscall::4                         4      1.80%     13.96% # number of syscalls executed
-system.cpu0.kern.syscall::6                        32     14.41%     28.38% # number of syscalls executed
-system.cpu0.kern.syscall::12                        1      0.45%     28.83% # number of syscalls executed
-system.cpu0.kern.syscall::17                        9      4.05%     32.88% # number of syscalls executed
-system.cpu0.kern.syscall::19                       10      4.50%     37.39% # number of syscalls executed
-system.cpu0.kern.syscall::20                        6      2.70%     40.09% # number of syscalls executed
-system.cpu0.kern.syscall::23                        1      0.45%     40.54% # number of syscalls executed
-system.cpu0.kern.syscall::24                        3      1.35%     41.89% # number of syscalls executed
-system.cpu0.kern.syscall::33                        7      3.15%     45.05% # number of syscalls executed
-system.cpu0.kern.syscall::41                        2      0.90%     45.95% # number of syscalls executed
-system.cpu0.kern.syscall::45                       36     16.22%     62.16% # number of syscalls executed
-system.cpu0.kern.syscall::47                        3      1.35%     63.51% # number of syscalls executed
-system.cpu0.kern.syscall::48                       10      4.50%     68.02% # number of syscalls executed
-system.cpu0.kern.syscall::54                       10      4.50%     72.52% # number of syscalls executed
-system.cpu0.kern.syscall::58                        1      0.45%     72.97% # number of syscalls executed
-system.cpu0.kern.syscall::59                        6      2.70%     75.68% # number of syscalls executed
-system.cpu0.kern.syscall::71                       23     10.36%     86.04% # number of syscalls executed
-system.cpu0.kern.syscall::73                        3      1.35%     87.39% # number of syscalls executed
-system.cpu0.kern.syscall::74                        6      2.70%     90.09% # number of syscalls executed
-system.cpu0.kern.syscall::87                        1      0.45%     90.54% # number of syscalls executed
-system.cpu0.kern.syscall::90                        3      1.35%     91.89% # number of syscalls executed
-system.cpu0.kern.syscall::92                        9      4.05%     95.95% # number of syscalls executed
-system.cpu0.kern.syscall::97                        2      0.90%     96.85% # number of syscalls executed
-system.cpu0.kern.syscall::98                        2      0.90%     97.75% # number of syscalls executed
-system.cpu0.kern.syscall::132                       1      0.45%     98.20% # number of syscalls executed
-system.cpu0.kern.syscall::144                       2      0.90%     99.10% # number of syscalls executed
-system.cpu0.kern.syscall::147                       2      0.90%    100.00% # number of syscalls executed
-system.cpu0.kern.syscall::total                   222                       # number of syscalls executed
+system.cpu0.kern.ipl_used::31                0.634626                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::total             0.777812                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.syscall::2                         6      2.68%      2.68% # number of syscalls executed
+system.cpu0.kern.syscall::3                        19      8.48%     11.16% # number of syscalls executed
+system.cpu0.kern.syscall::4                         3      1.34%     12.50% # number of syscalls executed
+system.cpu0.kern.syscall::6                        30     13.39%     25.89% # number of syscalls executed
+system.cpu0.kern.syscall::12                        1      0.45%     26.34% # number of syscalls executed
+system.cpu0.kern.syscall::15                        1      0.45%     26.79% # number of syscalls executed
+system.cpu0.kern.syscall::17                       10      4.46%     31.25% # number of syscalls executed
+system.cpu0.kern.syscall::19                        6      2.68%     33.93% # number of syscalls executed
+system.cpu0.kern.syscall::20                        4      1.79%     35.71% # number of syscalls executed
+system.cpu0.kern.syscall::23                        2      0.89%     36.61% # number of syscalls executed
+system.cpu0.kern.syscall::24                        4      1.79%     38.39% # number of syscalls executed
+system.cpu0.kern.syscall::33                        8      3.57%     41.96% # number of syscalls executed
+system.cpu0.kern.syscall::41                        2      0.89%     42.86% # number of syscalls executed
+system.cpu0.kern.syscall::45                       39     17.41%     60.27% # number of syscalls executed
+system.cpu0.kern.syscall::47                        4      1.79%     62.05% # number of syscalls executed
+system.cpu0.kern.syscall::48                        7      3.12%     65.18% # number of syscalls executed
+system.cpu0.kern.syscall::54                        9      4.02%     69.20% # number of syscalls executed
+system.cpu0.kern.syscall::58                        1      0.45%     69.64% # number of syscalls executed
+system.cpu0.kern.syscall::59                        5      2.23%     71.88% # number of syscalls executed
+system.cpu0.kern.syscall::71                       32     14.29%     86.16% # number of syscalls executed
+system.cpu0.kern.syscall::73                        3      1.34%     87.50% # number of syscalls executed
+system.cpu0.kern.syscall::74                        9      4.02%     91.52% # number of syscalls executed
+system.cpu0.kern.syscall::87                        1      0.45%     91.96% # number of syscalls executed
+system.cpu0.kern.syscall::90                        2      0.89%     92.86% # number of syscalls executed
+system.cpu0.kern.syscall::92                        7      3.12%     95.98% # number of syscalls executed
+system.cpu0.kern.syscall::97                        2      0.89%     96.87% # number of syscalls executed
+system.cpu0.kern.syscall::98                        2      0.89%     97.77% # number of syscalls executed
+system.cpu0.kern.syscall::132                       2      0.89%     98.66% # number of syscalls executed
+system.cpu0.kern.syscall::144                       1      0.45%     99.11% # number of syscalls executed
+system.cpu0.kern.syscall::147                       2      0.89%    100.00% # number of syscalls executed
+system.cpu0.kern.syscall::total                   224                       # number of syscalls executed
 system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu0.kern.callpal::wripir                   88      0.05%      0.05% # number of callpals executed
-system.cpu0.kern.callpal::wrmces                    1      0.00%      0.05% # number of callpals executed
-system.cpu0.kern.callpal::wrfen                     1      0.00%      0.05% # number of callpals executed
-system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.05% # number of callpals executed
-system.cpu0.kern.callpal::swpctx                 3894      2.07%      2.12% # number of callpals executed
-system.cpu0.kern.callpal::tbi                      51      0.03%      2.15% # number of callpals executed
-system.cpu0.kern.callpal::wrent                     7      0.00%      2.15% # number of callpals executed
-system.cpu0.kern.callpal::swpipl               172198     91.50%     93.65% # number of callpals executed
-system.cpu0.kern.callpal::rdps                   6677      3.55%     97.19% # number of callpals executed
-system.cpu0.kern.callpal::wrkgp                     1      0.00%     97.19% # number of callpals executed
-system.cpu0.kern.callpal::wrusp                     3      0.00%     97.20% # number of callpals executed
-system.cpu0.kern.callpal::rdusp                     9      0.00%     97.20% # number of callpals executed
-system.cpu0.kern.callpal::whami                     2      0.00%     97.20% # number of callpals executed
-system.cpu0.kern.callpal::rti                    4750      2.52%     99.73% # number of callpals executed
-system.cpu0.kern.callpal::callsys                 381      0.20%     99.93% # number of callpals executed
-system.cpu0.kern.callpal::imb                     136      0.07%    100.00% # number of callpals executed
-system.cpu0.kern.callpal::total                188201                       # number of callpals executed
-system.cpu0.kern.mode_switch::kernel             7301                       # number of protection mode switches
-system.cpu0.kern.mode_switch::user               1283                       # number of protection mode switches
+system.cpu0.kern.callpal::wripir                   91      0.08%      0.08% # number of callpals executed
+system.cpu0.kern.callpal::wrmces                    1      0.00%      0.08% # number of callpals executed
+system.cpu0.kern.callpal::wrfen                     1      0.00%      0.08% # number of callpals executed
+system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.08% # number of callpals executed
+system.cpu0.kern.callpal::swpctx                 1959      1.72%      1.80% # number of callpals executed
+system.cpu0.kern.callpal::tbi                      44      0.04%      1.84% # number of callpals executed
+system.cpu0.kern.callpal::wrent                     7      0.01%      1.84% # number of callpals executed
+system.cpu0.kern.callpal::swpipl               101151     88.59%     90.44% # number of callpals executed
+system.cpu0.kern.callpal::rdps                   6620      5.80%     96.24% # number of callpals executed
+system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.24% # number of callpals executed
+system.cpu0.kern.callpal::wrusp                     4      0.00%     96.24% # number of callpals executed
+system.cpu0.kern.callpal::rdusp                     7      0.01%     96.25% # number of callpals executed
+system.cpu0.kern.callpal::whami                     2      0.00%     96.25% # number of callpals executed
+system.cpu0.kern.callpal::rti                    3778      3.31%     99.56% # number of callpals executed
+system.cpu0.kern.callpal::callsys                 356      0.31%     99.87% # number of callpals executed
+system.cpu0.kern.callpal::imb                     149      0.13%    100.00% # number of callpals executed
+system.cpu0.kern.callpal::total                114173                       # number of callpals executed
+system.cpu0.kern.mode_switch::kernel             5323                       # number of protection mode switches
+system.cpu0.kern.mode_switch::user               1230                       # number of protection mode switches
 system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
-system.cpu0.kern.mode_good::kernel               1283                      
-system.cpu0.kern.mode_good::user                 1283                      
+system.cpu0.kern.mode_good::kernel               1229                      
+system.cpu0.kern.mode_good::user                 1230                      
 system.cpu0.kern.mode_good::idle                    0                      
-system.cpu0.kern.mode_switch_good::kernel     0.175729                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::kernel     0.230885                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total     0.298928                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel      1953310949000     99.83%     99.83% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user          3370111000      0.17%    100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_switch_good::total     0.375248                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel      1950524029000     99.81%     99.81% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user          3684214000      0.19%    100.00% # number of ticks spent at the given mode
 system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context                    3895                       # number of times the context was actually changed
+system.cpu0.kern.swap_context                    1960                       # number of times the context was actually changed
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
 system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
@@ -622,51 +623,51 @@ system.tsunami.ethernet.totalRxOrn                  0                       # to
 system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
 system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.cpu0.icache.replacements                914734                       # number of replacements
-system.cpu0.icache.tagsinuse               508.814250                       # Cycle average of tags in use
-system.cpu0.icache.total_refs                53144779                       # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs                915246                       # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs                 58.066114                       # Average number of references to valid blocks.
-system.cpu0.icache.warmup_cycle           35914239000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst   508.814250                       # Average occupied blocks per requestor
-system.cpu0.icache.occ_percent::cpu0.inst     0.993778                       # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::total        0.993778                       # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst     53144779                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       53144779                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     53144779                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        53144779                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     53144779                       # number of overall hits
-system.cpu0.icache.overall_hits::total       53144779                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       915368                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       915368                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       915368                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        915368                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       915368                       # number of overall misses
-system.cpu0.icache.overall_misses::total       915368                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  13361799000                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  13361799000                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  13361799000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  13361799000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  13361799000                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  13361799000                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     54060147                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     54060147                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     54060147                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     54060147                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     54060147                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     54060147                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.016932                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.016932                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.016932                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.016932                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.016932                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.016932                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14597.188235                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 14597.188235                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14597.188235                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 14597.188235                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14597.188235                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 14597.188235                       # average overall miss latency
+system.cpu0.icache.replacements                489211                       # number of replacements
+system.cpu0.icache.tagsinuse               508.795621                       # Cycle average of tags in use
+system.cpu0.icache.total_refs                35679745                       # Total number of references to valid blocks.
+system.cpu0.icache.sampled_refs                489723                       # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs                 72.856993                       # Average number of references to valid blocks.
+system.cpu0.icache.warmup_cycle           36113258000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.occ_blocks::cpu0.inst   508.795621                       # Average occupied blocks per requestor
+system.cpu0.icache.occ_percent::cpu0.inst     0.993741                       # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::total        0.993741                       # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits::cpu0.inst     35679745                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       35679745                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     35679745                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        35679745                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     35679745                       # number of overall hits
+system.cpu0.icache.overall_hits::total       35679745                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       489853                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       489853                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       489853                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        489853                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       489853                       # number of overall misses
+system.cpu0.icache.overall_misses::total       489853                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   7462564000                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total   7462564000                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst   7462564000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total   7462564000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst   7462564000                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total   7462564000                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     36169598                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     36169598                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     36169598                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     36169598                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     36169598                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     36169598                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.013543                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.013543                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.013543                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.013543                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.013543                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.013543                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15234.292737                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 15234.292737                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15234.292737                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 15234.292737                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15234.292737                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 15234.292737                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -675,114 +676,114 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.writebacks::writebacks           55                       # number of writebacks
-system.cpu0.icache.writebacks::total               55                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       915368                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       915368                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       915368                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       915368                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       915368                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       915368                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  10614998000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  10614998000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  10614998000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  10614998000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  10614998000                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  10614998000                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.016932                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.016932                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.016932                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.016932                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.016932                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.016932                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11596.426792                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11596.426792                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11596.426792                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 11596.426792                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11596.426792                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 11596.426792                       # average overall mshr miss latency
+system.cpu0.icache.writebacks::writebacks           58                       # number of writebacks
+system.cpu0.icache.writebacks::total               58                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       489853                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       489853                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       489853                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       489853                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       489853                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       489853                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   5992343500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total   5992343500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   5992343500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total   5992343500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   5992343500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   5992343500                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.013543                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.013543                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.013543                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.013543                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.013543                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.013543                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12232.942332                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12232.942332                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12232.942332                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12232.942332                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12232.942332                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12232.942332                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.replacements               1337419                       # number of replacements
-system.cpu0.dcache.tagsinuse               506.341163                       # Cycle average of tags in use
-system.cpu0.dcache.total_refs                13344261                       # Total number of references to valid blocks.
-system.cpu0.dcache.sampled_refs               1337832                       # Sample count of references to valid blocks.
-system.cpu0.dcache.avg_refs                  9.974542                       # Average number of references to valid blocks.
-system.cpu0.dcache.warmup_cycle              83958000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::cpu0.data   506.341163                       # Average occupied blocks per requestor
-system.cpu0.dcache.occ_percent::cpu0.data     0.988948                       # Average percentage of cache occupancy
-system.cpu0.dcache.occ_percent::total        0.988948                       # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::cpu0.data      7419012                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        7419012                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      5558431                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       5558431                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       176349                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       176349                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       191666                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       191666                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     12977443                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        12977443                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     12977443                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       12977443                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      1034980                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      1034980                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       291529                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       291529                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        16694                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        16694                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data          411                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total          411                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      1326509                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       1326509                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      1326509                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      1326509                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  25827814500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  25827814500                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   9022984000                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total   9022984000                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    234039000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    234039000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data      2995000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total      2995000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  34850798500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  34850798500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  34850798500                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  34850798500                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      8453992                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      8453992                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      5849960                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      5849960                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       193043                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       193043                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       192077                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       192077                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     14303952                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     14303952                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     14303952                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     14303952                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.122425                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.122425                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.049834                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.049834                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.086478                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.086478                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.002140                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.002140                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.092737                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.092737                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.092737                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.092737                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 24954.892365                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 24954.892365                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30950.553804                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 30950.553804                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14019.348269                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14019.348269                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  7287.104623                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  7287.104623                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26272.568448                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 26272.568448                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26272.568448                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 26272.568448                       # average overall miss latency
+system.cpu0.dcache.replacements                817835                       # number of replacements
+system.cpu0.dcache.tagsinuse               479.881432                       # Cycle average of tags in use
+system.cpu0.dcache.total_refs                 8879650                       # Total number of references to valid blocks.
+system.cpu0.dcache.sampled_refs                818347                       # Sample count of references to valid blocks.
+system.cpu0.dcache.avg_refs                 10.850715                       # Average number of references to valid blocks.
+system.cpu0.dcache.warmup_cycle              85697000                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.occ_blocks::cpu0.data   479.881432                       # Average occupied blocks per requestor
+system.cpu0.dcache.occ_percent::cpu0.data     0.937268                       # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::total        0.937268                       # Average percentage of cache occupancy
+system.cpu0.dcache.ReadReq_hits::cpu0.data      5008280                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        5008280                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      3627742                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       3627742                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       117045                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       117045                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       122538                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       122538                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data      8636022                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total         8636022                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data      8636022                       # number of overall hits
+system.cpu0.dcache.overall_hits::total        8636022                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       610615                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       610615                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       207039                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       207039                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         6562                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total         6562                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data          580                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total          580                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data       817654                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total        817654                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data       817654                       # number of overall misses
+system.cpu0.dcache.overall_misses::total       817654                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  19940488000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  19940488000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   7282919000                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total   7282919000                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data     92852000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total     92852000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data      8304000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total      8304000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  27223407000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  27223407000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  27223407000                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  27223407000                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      5618895                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      5618895                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      3834781                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      3834781                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       123607                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       123607                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       123118                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       123118                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data      9453676                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total      9453676                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data      9453676                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total      9453676                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.108672                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.108672                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.053990                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.053990                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.053088                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.053088                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.004711                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.004711                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.086491                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.086491                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.086491                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.086491                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 32656.400514                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 32656.400514                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35176.556108                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 35176.556108                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14149.954282                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14149.954282                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 14317.241379                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14317.241379                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33294.531672                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 33294.531672                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33294.531672                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 33294.531672                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -791,62 +792,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       790358                       # number of writebacks
-system.cpu0.dcache.writebacks::total           790358                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      1034980                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      1034980                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       291529                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       291529                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        16694                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total        16694                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data          411                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total          411                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      1326509                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      1326509                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      1326509                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      1326509                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  22722836500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  22722836500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   8148397000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   8148397000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    183957000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    183957000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data      1762000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      1762000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  30871233500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  30871233500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  30871233500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  30871233500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data    884470000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total    884470000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1241998500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1241998500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   2126468500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   2126468500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.122425                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.122425                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.049834                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.049834                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.086478                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.086478                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.002140                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.002140                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.092737                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.092737                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.092737                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.092737                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 21954.855649                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 21954.855649                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27950.553804                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27950.553804                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11019.348269                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11019.348269                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  4287.104623                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  4287.104623                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23272.539802                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23272.539802                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23272.539802                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23272.539802                       # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks       359699                       # number of writebacks
+system.cpu0.dcache.writebacks::total           359699                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       610615                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       610615                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       207039                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       207039                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6562                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6562                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data          580                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total          580                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       817654                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       817654                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       817654                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       817654                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  18108577524                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  18108577524                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   6661800002                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   6661800002                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     73166000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     73166000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data      6564000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      6564000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  24770377526                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  24770377526                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  24770377526                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  24770377526                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data    601208500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total    601208500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1014438500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1014438500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   1615647000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   1615647000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.108672                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.108672                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.053990                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.053990                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.053088                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.053088                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.004711                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.004711                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.086491                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.086491                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.086491                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.086491                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29656.293285                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29656.293285                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32176.546457                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32176.546457                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11149.954282                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11149.954282                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11317.241379                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11317.241379                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30294.449151                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30294.449151                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30294.449151                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30294.449151                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
@@ -858,22 +859,22 @@ system.cpu1.dtb.fetch_hits                          0                       # IT
 system.cpu1.dtb.fetch_misses                        0                       # ITB misses
 system.cpu1.dtb.fetch_acv                           0                       # ITB acv
 system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu1.dtb.read_hits                     1049963                       # DTB read hits
-system.cpu1.dtb.read_misses                      2992                       # DTB read misses
-system.cpu1.dtb.read_acv                            0                       # DTB read access violations
-system.cpu1.dtb.read_accesses                  239363                       # DTB read accesses
-system.cpu1.dtb.write_hits                     651106                       # DTB write hits
-system.cpu1.dtb.write_misses                      341                       # DTB write misses
-system.cpu1.dtb.write_acv                          29                       # DTB write access violations
-system.cpu1.dtb.write_accesses                 105247                       # DTB write accesses
-system.cpu1.dtb.data_hits                     1701069                       # DTB hits
-system.cpu1.dtb.data_misses                      3333                       # DTB misses
-system.cpu1.dtb.data_acv                           29                       # DTB access violations
-system.cpu1.dtb.data_accesses                  344610                       # DTB accesses
-system.cpu1.itb.fetch_hits                    1493400                       # ITB hits
-system.cpu1.itb.fetch_misses                     1216                       # ITB misses
-system.cpu1.itb.fetch_acv                           0                       # ITB acv
-system.cpu1.itb.fetch_accesses                1494616                       # ITB accesses
+system.cpu1.dtb.read_hits                     3958078                       # DTB read hits
+system.cpu1.dtb.read_misses                      2750                       # DTB read misses
+system.cpu1.dtb.read_acv                           36                       # DTB read access violations
+system.cpu1.dtb.read_accesses                  205838                       # DTB read accesses
+system.cpu1.dtb.write_hits                    2742847                       # DTB write hits
+system.cpu1.dtb.write_misses                      356                       # DTB write misses
+system.cpu1.dtb.write_acv                          48                       # DTB write access violations
+system.cpu1.dtb.write_accesses                  97040                       # DTB write accesses
+system.cpu1.dtb.data_hits                     6700925                       # DTB hits
+system.cpu1.dtb.data_misses                      3106                       # DTB misses
+system.cpu1.dtb.data_acv                           84                       # DTB access violations
+system.cpu1.dtb.data_accesses                  302878                       # DTB accesses
+system.cpu1.itb.fetch_hits                    2128502                       # ITB hits
+system.cpu1.itb.fetch_misses                     1246                       # ITB misses
+system.cpu1.itb.fetch_acv                          41                       # ITB acv
+system.cpu1.itb.fetch_accesses                2129748                       # ITB accesses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.read_acv                            0                       # DTB read access violations
@@ -886,141 +887,150 @@ system.cpu1.itb.data_hits                           0                       # DT
 system.cpu1.itb.data_misses                         0                       # DTB misses
 system.cpu1.itb.data_acv                            0                       # DTB access violations
 system.cpu1.itb.data_accesses                       0                       # DTB accesses
-system.cpu1.numCycles                      3915155164                       # number of cpu cycles simulated
+system.cpu1.numCycles                      3908222380                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                    5279868                       # Number of instructions committed
-system.cpu1.committedOps                      5279868                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses              4945263                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                 34031                       # Number of float alu accesses
-system.cpu1.num_func_calls                     157997                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts       510441                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                     4945263                       # number of integer instructions
-system.cpu1.num_fp_insts                        34031                       # number of float instructions
-system.cpu1.num_int_register_reads            6880916                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes           3730475                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads               22062                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes              21862                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                      1710522                       # number of memory refs
-system.cpu1.num_load_insts                    1055970                       # Number of load instructions
-system.cpu1.num_store_insts                    654552                       # Number of store instructions
-system.cpu1.num_idle_cycles              3896226886.998010                       # Number of idle cycles
-system.cpu1.num_busy_cycles              18928277.001990                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.004835                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.995165                       # Percentage of idle cycles
+system.cpu1.committedInsts                   23256004                       # Number of instructions committed
+system.cpu1.committedOps                     23256004                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             21401422                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                186242                       # Number of float alu accesses
+system.cpu1.num_func_calls                     709842                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      2519926                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    21401422                       # number of integer instructions
+system.cpu1.num_fp_insts                       186242                       # number of float instructions
+system.cpu1.num_int_register_reads           29248159                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          15707401                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads               95219                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes              97489                       # number of times the floating registers were written
+system.cpu1.num_mem_refs                      6725970                       # number of memory refs
+system.cpu1.num_load_insts                    3973767                       # Number of load instructions
+system.cpu1.num_store_insts                   2752203                       # Number of store instructions
+system.cpu1.num_idle_cycles              3808684025.637170                       # Number of idle cycles
+system.cpu1.num_busy_cycles              99538354.362830                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.025469                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.974531                       # Percentage of idle cycles
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    2314                       # number of quiesce instructions executed
-system.cpu1.kern.inst.hwrei                     36187                       # number of hwrei instructions executed
-system.cpu1.kern.ipl_count::0                    9288     32.15%     32.15% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::22                   1969      6.81%     38.96% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::30                     88      0.30%     39.27% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31                  17548     60.73%    100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total               28893                       # number of times we switched to this ipl
-system.cpu1.kern.ipl_good::0                     9278     45.20%     45.20% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::22                    1969      9.59%     54.80% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::30                      88      0.43%     55.23% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::31                    9190     44.77%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::total                20525                       # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0            1917614123000     97.96%     97.96% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22              507941000      0.03%     97.98% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30               53691000      0.00%     97.99% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31            39401069000      2.01%    100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total        1957576824000                       # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used::0                 0.998923                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.inst.quiesce                    3849                       # number of quiesce instructions executed
+system.cpu1.kern.inst.hwrei                    109556                       # number of hwrei instructions executed
+system.cpu1.kern.ipl_count::0                   40729     40.60%     40.60% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::22                   1966      1.96%     42.56% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::30                     91      0.09%     42.65% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::31                  57540     57.35%    100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::total              100326                       # number of times we switched to this ipl
+system.cpu1.kern.ipl_good::0                    39783     48.79%     48.79% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::22                    1966      2.41%     51.21% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::30                      91      0.11%     51.32% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::31                   39692     48.68%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::total                81532                       # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks::0            1901560823500     97.31%     97.31% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::22              537428500      0.03%     97.34% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::30               59036000      0.00%     97.34% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::31            51953872000      2.66%    100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total        1954111160000                       # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used::0                 0.976773                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31                0.523706                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::total             0.710380                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.syscall::3                        11     10.58%     10.58% # number of syscalls executed
-system.cpu1.kern.syscall::6                        10      9.62%     20.19% # number of syscalls executed
-system.cpu1.kern.syscall::15                        1      0.96%     21.15% # number of syscalls executed
-system.cpu1.kern.syscall::17                        6      5.77%     26.92% # number of syscalls executed
-system.cpu1.kern.syscall::23                        3      2.88%     29.81% # number of syscalls executed
-system.cpu1.kern.syscall::24                        3      2.88%     32.69% # number of syscalls executed
-system.cpu1.kern.syscall::33                        4      3.85%     36.54% # number of syscalls executed
-system.cpu1.kern.syscall::45                       18     17.31%     53.85% # number of syscalls executed
-system.cpu1.kern.syscall::47                        3      2.88%     56.73% # number of syscalls executed
-system.cpu1.kern.syscall::59                        1      0.96%     57.69% # number of syscalls executed
-system.cpu1.kern.syscall::71                       31     29.81%     87.50% # number of syscalls executed
-system.cpu1.kern.syscall::74                       10      9.62%     97.12% # number of syscalls executed
-system.cpu1.kern.syscall::132                       3      2.88%    100.00% # number of syscalls executed
-system.cpu1.kern.syscall::total                   104                       # number of syscalls executed
+system.cpu1.kern.ipl_used::31                0.689816                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::total             0.812671                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.syscall::2                         2      1.96%      1.96% # number of syscalls executed
+system.cpu1.kern.syscall::3                        11     10.78%     12.75% # number of syscalls executed
+system.cpu1.kern.syscall::4                         1      0.98%     13.73% # number of syscalls executed
+system.cpu1.kern.syscall::6                        12     11.76%     25.49% # number of syscalls executed
+system.cpu1.kern.syscall::17                        5      4.90%     30.39% # number of syscalls executed
+system.cpu1.kern.syscall::19                        4      3.92%     34.31% # number of syscalls executed
+system.cpu1.kern.syscall::20                        2      1.96%     36.27% # number of syscalls executed
+system.cpu1.kern.syscall::23                        2      1.96%     38.24% # number of syscalls executed
+system.cpu1.kern.syscall::24                        2      1.96%     40.20% # number of syscalls executed
+system.cpu1.kern.syscall::33                        3      2.94%     43.14% # number of syscalls executed
+system.cpu1.kern.syscall::45                       15     14.71%     57.84% # number of syscalls executed
+system.cpu1.kern.syscall::47                        2      1.96%     59.80% # number of syscalls executed
+system.cpu1.kern.syscall::48                        3      2.94%     62.75% # number of syscalls executed
+system.cpu1.kern.syscall::54                        1      0.98%     63.73% # number of syscalls executed
+system.cpu1.kern.syscall::59                        2      1.96%     65.69% # number of syscalls executed
+system.cpu1.kern.syscall::71                       22     21.57%     87.25% # number of syscalls executed
+system.cpu1.kern.syscall::74                        7      6.86%     94.12% # number of syscalls executed
+system.cpu1.kern.syscall::90                        1      0.98%     95.10% # number of syscalls executed
+system.cpu1.kern.syscall::92                        2      1.96%     97.06% # number of syscalls executed
+system.cpu1.kern.syscall::132                       2      1.96%     99.02% # number of syscalls executed
+system.cpu1.kern.syscall::144                       1      0.98%    100.00% # number of syscalls executed
+system.cpu1.kern.syscall::total                   102                       # number of syscalls executed
 system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu1.kern.callpal::wripir                    6      0.02%      0.02% # number of callpals executed
-system.cpu1.kern.callpal::wrmces                    1      0.00%      0.03% # number of callpals executed
-system.cpu1.kern.callpal::wrfen                     1      0.00%      0.03% # number of callpals executed
-system.cpu1.kern.callpal::swpctx                  337      1.14%      1.17% # number of callpals executed
-system.cpu1.kern.callpal::tbi                       3      0.01%      1.18% # number of callpals executed
-system.cpu1.kern.callpal::wrent                     7      0.02%      1.20% # number of callpals executed
-system.cpu1.kern.callpal::swpipl                24305     82.25%     83.46% # number of callpals executed
-system.cpu1.kern.callpal::rdps                   2170      7.34%     90.80% # number of callpals executed
-system.cpu1.kern.callpal::wrkgp                     1      0.00%     90.80% # number of callpals executed
-system.cpu1.kern.callpal::wrusp                     4      0.01%     90.82% # number of callpals executed
-system.cpu1.kern.callpal::whami                     3      0.01%     90.83% # number of callpals executed
-system.cpu1.kern.callpal::rti                    2530      8.56%     99.39% # number of callpals executed
-system.cpu1.kern.callpal::callsys                 136      0.46%     99.85% # number of callpals executed
-system.cpu1.kern.callpal::imb                      44      0.15%    100.00% # number of callpals executed
+system.cpu1.kern.callpal::wripir                   17      0.02%      0.02% # number of callpals executed
+system.cpu1.kern.callpal::wrmces                    1      0.00%      0.02% # number of callpals executed
+system.cpu1.kern.callpal::wrfen                     1      0.00%      0.02% # number of callpals executed
+system.cpu1.kern.callpal::swpctx                 2292      2.22%      2.24% # number of callpals executed
+system.cpu1.kern.callpal::tbi                      10      0.01%      2.25% # number of callpals executed
+system.cpu1.kern.callpal::wrent                     7      0.01%      2.26% # number of callpals executed
+system.cpu1.kern.callpal::swpipl                94758     91.98%     94.24% # number of callpals executed
+system.cpu1.kern.callpal::rdps                   2221      2.16%     96.40% # number of callpals executed
+system.cpu1.kern.callpal::wrkgp                     1      0.00%     96.40% # number of callpals executed
+system.cpu1.kern.callpal::wrusp                     3      0.00%     96.40% # number of callpals executed
+system.cpu1.kern.callpal::rdusp                     2      0.00%     96.40% # number of callpals executed
+system.cpu1.kern.callpal::whami                     3      0.00%     96.41% # number of callpals executed
+system.cpu1.kern.callpal::rti                    3510      3.41%     99.81% # number of callpals executed
+system.cpu1.kern.callpal::callsys                 161      0.16%     99.97% # number of callpals executed
+system.cpu1.kern.callpal::imb                      31      0.03%    100.00% # number of callpals executed
 system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
-system.cpu1.kern.callpal::total                 29550                       # number of callpals executed
-system.cpu1.kern.mode_switch::kernel              803                       # number of protection mode switches
-system.cpu1.kern.mode_switch::user                463                       # number of protection mode switches
-system.cpu1.kern.mode_switch::idle               2065                       # number of protection mode switches
-system.cpu1.kern.mode_good::kernel                476                      
-system.cpu1.kern.mode_good::user                  463                      
-system.cpu1.kern.mode_good::idle                   13                      
-system.cpu1.kern.mode_switch_good::kernel     0.592777                       # fraction of useful protection mode switches
+system.cpu1.kern.callpal::total                103020                       # number of callpals executed
+system.cpu1.kern.mode_switch::kernel             2836                       # number of protection mode switches
+system.cpu1.kern.mode_switch::user                515                       # number of protection mode switches
+system.cpu1.kern.mode_switch::idle               2038                       # number of protection mode switches
+system.cpu1.kern.mode_good::kernel                568                      
+system.cpu1.kern.mode_good::user                  515                      
+system.cpu1.kern.mode_good::idle                   53                      
+system.cpu1.kern.mode_switch_good::kernel     0.200282                       # fraction of useful protection mode switches
 system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::idle      0.006295                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::total     0.285800                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel        3531821000      0.18%      0.18% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user          1727088000      0.09%      0.27% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle        1952317913000     99.73%    100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context                     338                       # number of times the context was actually changed
-system.cpu1.icache.replacements                 86261                       # number of replacements
-system.cpu1.icache.tagsinuse               419.419440                       # Cycle average of tags in use
-system.cpu1.icache.total_refs                 5196422                       # Total number of references to valid blocks.
-system.cpu1.icache.sampled_refs                 86773                       # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs                 59.885241                       # Average number of references to valid blocks.
-system.cpu1.icache.warmup_cycle          1941709468000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::cpu1.inst   419.419440                       # Average occupied blocks per requestor
-system.cpu1.icache.occ_percent::cpu1.inst     0.819179                       # Average percentage of cache occupancy
-system.cpu1.icache.occ_percent::total        0.819179                       # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst      5196422                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total        5196422                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst      5196422                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total         5196422                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst      5196422                       # number of overall hits
-system.cpu1.icache.overall_hits::total        5196422                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst        86809                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total        86809                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst        86809                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total         86809                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst        86809                       # number of overall misses
-system.cpu1.icache.overall_misses::total        86809                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   1248608500                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   1248608500                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   1248608500                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   1248608500                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   1248608500                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   1248608500                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst      5283231                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total      5283231                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst      5283231                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total      5283231                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst      5283231                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total      5283231                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.016431                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.016431                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.016431                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.016431                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.016431                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.016431                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14383.399187                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 14383.399187                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14383.399187                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 14383.399187                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14383.399187                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 14383.399187                       # average overall miss latency
+system.cpu1.kern.mode_switch_good::idle      0.026006                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good::total     0.210800                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_ticks::kernel       72316980000      3.70%      3.70% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::user          1607803000      0.08%      3.78% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::idle        1879348629000     96.22%    100.00% # number of ticks spent at the given mode
+system.cpu1.kern.swap_context                    2293                       # number of times the context was actually changed
+system.cpu1.icache.replacements                513695                       # number of replacements
+system.cpu1.icache.tagsinuse               501.294136                       # Cycle average of tags in use
+system.cpu1.icache.total_refs                22744962                       # Total number of references to valid blocks.
+system.cpu1.icache.sampled_refs                514207                       # Sample count of references to valid blocks.
+system.cpu1.icache.avg_refs                 44.233085                       # Average number of references to valid blocks.
+system.cpu1.icache.warmup_cycle           96225204000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.occ_blocks::cpu1.inst   501.294136                       # Average occupied blocks per requestor
+system.cpu1.icache.occ_percent::cpu1.inst     0.979090                       # Average percentage of cache occupancy
+system.cpu1.icache.occ_percent::total        0.979090                       # Average percentage of cache occupancy
+system.cpu1.icache.ReadReq_hits::cpu1.inst     22744962                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total       22744962                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst     22744962                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total        22744962                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst     22744962                       # number of overall hits
+system.cpu1.icache.overall_hits::total       22744962                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       514232                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       514232                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       514232                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        514232                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       514232                       # number of overall misses
+system.cpu1.icache.overall_misses::total       514232                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   7551962500                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   7551962500                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   7551962500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   7551962500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   7551962500                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   7551962500                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst     23259194                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total     23259194                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst     23259194                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total     23259194                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst     23259194                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total     23259194                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.022109                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.022109                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.022109                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.022109                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.022109                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.022109                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14685.905389                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 14685.905389                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14685.905389                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 14685.905389                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14685.905389                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 14685.905389                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1029,114 +1039,114 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.writebacks::writebacks           14                       # number of writebacks
-system.cpu1.icache.writebacks::total               14                       # number of writebacks
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst        86809                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total        86809                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst        86809                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total        86809                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst        86809                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total        86809                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst    988145500                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total    988145500                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst    988145500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total    988145500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst    988145500                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total    988145500                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.016431                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.016431                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.016431                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.016431                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.016431                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.016431                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11382.984483                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11382.984483                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11382.984483                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 11382.984483                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11382.984483                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 11382.984483                       # average overall mshr miss latency
+system.cpu1.icache.writebacks::writebacks           11                       # number of writebacks
+system.cpu1.icache.writebacks::total               11                       # number of writebacks
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       514232                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       514232                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       514232                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       514232                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       514232                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       514232                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   6009201500                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   6009201500                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   6009201500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   6009201500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   6009201500                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   6009201500                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.022109                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.022109                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.022109                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.022109                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.022109                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.022109                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11685.778987                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11685.778987                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11685.778987                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 11685.778987                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11685.778987                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 11685.778987                       # average overall mshr miss latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.replacements                 52782                       # number of replacements
-system.cpu1.dcache.tagsinuse               416.168626                       # Cycle average of tags in use
-system.cpu1.dcache.total_refs                 1644833                       # Total number of references to valid blocks.
-system.cpu1.dcache.sampled_refs                 53294                       # Sample count of references to valid blocks.
-system.cpu1.dcache.avg_refs                 30.863380                       # Average number of references to valid blocks.
-system.cpu1.dcache.warmup_cycle          1922770151000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::cpu1.data   416.168626                       # Average occupied blocks per requestor
-system.cpu1.dcache.occ_percent::cpu1.data     0.812829                       # Average percentage of cache occupancy
-system.cpu1.dcache.occ_percent::total        0.812829                       # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::cpu1.data      1003125                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        1003125                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data       616808                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total        616808                       # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        11818                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        11818                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        11519                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        11519                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data      1619933                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total         1619933                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data      1619933                       # number of overall hits
-system.cpu1.dcache.overall_hits::total        1619933                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data        36999                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total        36999                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data        20414                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total        20414                       # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data          944                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total          944                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data          507                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total          507                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data        57413                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total         57413                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data        57413                       # number of overall misses
-system.cpu1.dcache.overall_misses::total        57413                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data    492506000                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total    492506000                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data    549958000                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total    549958000                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     11305000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total     11305000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data      6352000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total      6352000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data   1042464000                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total   1042464000                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data   1042464000                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total   1042464000                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      1040124                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      1040124                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data       637222                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total       637222                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        12762                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        12762                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        12026                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        12026                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data      1677346                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total      1677346                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data      1677346                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total      1677346                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.035572                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.035572                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.032036                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.032036                       # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.073970                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.073970                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.042159                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.042159                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.034228                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.034228                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.034228                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.034228                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13311.332739                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 13311.332739                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26940.237092                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 26940.237092                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11975.635593                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11975.635593                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 12528.599606                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 12528.599606                       # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18157.281452                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 18157.281452                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18157.281452                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 18157.281452                       # average overall miss latency
+system.cpu1.dcache.replacements                642543                       # number of replacements
+system.cpu1.dcache.tagsinuse               493.349744                       # Cycle average of tags in use
+system.cpu1.dcache.total_refs                 6059288                       # Total number of references to valid blocks.
+system.cpu1.dcache.sampled_refs                642980                       # Sample count of references to valid blocks.
+system.cpu1.dcache.avg_refs                  9.423758                       # Average number of references to valid blocks.
+system.cpu1.dcache.warmup_cycle           54205321000                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.occ_blocks::cpu1.data   493.349744                       # Average occupied blocks per requestor
+system.cpu1.dcache.occ_percent::cpu1.data     0.963574                       # Average percentage of cache occupancy
+system.cpu1.dcache.occ_percent::total        0.963574                       # Average percentage of cache occupancy
+system.cpu1.dcache.ReadReq_hits::cpu1.data      3370942                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        3370942                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      2541026                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       2541026                       # number of WriteReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        71125                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        71125                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        80221                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        80221                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data      5911968                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total         5911968                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data      5911968                       # number of overall hits
+system.cpu1.dcache.overall_hits::total        5911968                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       513440                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       513440                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data       122215                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total       122215                       # number of WriteReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        13103                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total        13103                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data          640                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total          640                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       635655                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        635655                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       635655                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       635655                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   7202447500                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   7202447500                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   2665469000                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total   2665469000                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    183740000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total    183740000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data      8466000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total      8466000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data   9867916500                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total   9867916500                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data   9867916500                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total   9867916500                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      3884382                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      3884382                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      2663241                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      2663241                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        84228                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        84228                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        80861                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        80861                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data      6547623                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total      6547623                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data      6547623                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total      6547623                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.132181                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.132181                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.045890                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.045890                       # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.155566                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.155566                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.007915                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.007915                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.097082                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.097082                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.097082                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.097082                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14027.827010                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 14027.827010                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21809.671481                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 21809.671481                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14022.742883                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14022.742883                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13228.125000                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 13228.125000                       # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15524.013026                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 15524.013026                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15524.013026                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 15524.013026                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1145,62 +1155,66 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks        30624                       # number of writebacks
-system.cpu1.dcache.writebacks::total            30624                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data        36999                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total        36999                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        20414                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total        20414                       # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data          944                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total          944                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data          507                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total          507                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data        57413                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total        57413                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data        57413                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total        57413                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data    381507000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total    381507000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data    488716000                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total    488716000                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data      8473000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total      8473000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data      4831000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total      4831000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data    870223000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total    870223000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data    870223000                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total    870223000                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     11412500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     11412500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    298066500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    298066500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    309479000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total    309479000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035572                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.035572                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.032036                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.032036                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.073970                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.073970                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.042159                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.042159                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.034228                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.034228                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.034228                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.034228                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10311.278683                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10311.278683                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23940.237092                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23940.237092                       # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  8975.635593                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8975.635593                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  9528.599606                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  9528.599606                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15157.246617                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15157.246617                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15157.246617                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15157.246617                       # average overall mshr miss latency
+system.cpu1.dcache.writebacks::writebacks       498964                       # number of writebacks
+system.cpu1.dcache.writebacks::total           498964                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       513440                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total       513440                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       122215                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total       122215                       # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data        13103                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total        13103                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data          640                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total          640                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       635655                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       635655                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       635655                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       635655                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   5662112010                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   5662112010                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2298824000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2298824000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data    144431000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total    144431000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data      6549000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total      6549000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data         5000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total         5000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   7960936010                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   7960936010                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   7960936010                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   7960936010                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    295035500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    295035500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    516397500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    516397500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    811433000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total    811433000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.132181                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.132181                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.045890                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.045890                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.155566                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.155566                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.007915                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.007915                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.097082                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.097082                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.097082                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.097082                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11027.796841                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11027.796841                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18809.671481                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18809.671481                       # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11022.742883                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11022.742883                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 10232.812500                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 10232.812500                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
+system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12523.988657                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12523.988657                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12523.988657                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12523.988657                       # average overall mshr miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
index d6cd88975..a60709d68 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
@@ -186,7 +186,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=true
-width=64
+width=8
 default=system.tsunami.pciconfig.pio
 master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
 slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
@@ -248,7 +248,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 default=system.membus.badaddr_responder.pio
 master=system.bridge.slave system.physmem.port[0]
 slave=system.system_port system.iocache.mem_side system.l2c.mem_side
@@ -305,7 +305,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.l2c.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
index c4cb3c061..c99186441 100755
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
@@ -1,11 +1,11 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:05:18
-gem5 started Jun 28 2012 22:10:05
+gem5 compiled Jul  2 2012 08:30:56
+gem5 started Jul  2 2012 09:09:16
 gem5 executing on zizzer
 command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/vmlinux
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 1915492819000 because m5_exit instruction encountered
+Exiting @ tick 1920852274000 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
index abedba373..8d476d641 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
@@ -1,138 +1,138 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.915493                       # Number of seconds simulated
-sim_ticks                                1915492819000                       # Number of ticks simulated
-final_tick                               1915492819000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.920852                       # Number of seconds simulated
+sim_ticks                                1920852274000                       # Number of ticks simulated
+final_tick                               1920852274000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1853108                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1853107                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            63179819624                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 294892                       # Number of bytes of host memory used
-host_seconds                                    30.32                       # Real time elapsed on the host
-sim_insts                                    56182681                       # Number of instructions simulated
-sim_ops                                      56182681                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst            850496                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          24846208                       # Number of bytes read from this memory
+host_inst_rate                                1904642                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1904641                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            65112526106                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 294856                       # Number of bytes of host memory used
+host_seconds                                    29.50                       # Real time elapsed on the host
+sim_insts                                    56187824                       # Number of instructions simulated
+sim_ops                                      56187824                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst            850688                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          24847552                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide        2652352                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             28349056                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       850496                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          850496                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7388480                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7388480                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst              13289                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             388222                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total             28350592                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       850688                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          850688                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7389056                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7389056                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst              13292                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             388243                       # Number of read requests responded to by this memory
 system.physmem.num_reads::tsunami.ide           41443                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                442954                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          115445                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               115445                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               444009                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             12971183                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide           1384684                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                14799876                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          444009                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             444009                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3857221                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3857221                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3857221                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              444009                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            12971183                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide          1384684                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               18657097                       # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements                        336041                       # number of replacements
-system.l2c.tagsinuse                     65311.191779                       # Cycle average of tags in use
-system.l2c.total_refs                         2447812                       # Total number of references to valid blocks.
-system.l2c.sampled_refs                        401203                       # Sample count of references to valid blocks.
-system.l2c.avg_refs                          6.101181                       # Average number of references to valid blocks.
-system.l2c.warmup_cycle                    5933228000                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks        55666.496606                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.inst           4774.109125                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.data           4870.586047                       # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks           0.849403                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.inst             0.072847                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.data             0.074319                       # Average percentage of cache occupancy
-system.l2c.occ_percent::total                0.996570                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu.inst              915368                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.data              814896                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1730264                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          835591                       # number of Writeback hits
-system.l2c.Writeback_hits::total               835591                       # number of Writeback hits
+system.physmem.num_reads::total                442978                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          115454                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               115454                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               442870                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             12935691                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide           1380820                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                14759382                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          442870                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             442870                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3846759                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                3846759                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3846759                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              442870                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            12935691                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide          1380820                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               18606141                       # Total bandwidth to/from this memory (bytes/s)
+system.l2c.replacements                        336066                       # number of replacements
+system.l2c.tagsinuse                     65311.816256                       # Cycle average of tags in use
+system.l2c.total_refs                         2448229                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                        401229                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                          6.101825                       # Average number of references to valid blocks.
+system.l2c.warmup_cycle                    5946056000                       # Cycle when the warmup percentage was hit.
+system.l2c.occ_blocks::writebacks        55675.740322                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.inst           4768.394145                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.data           4867.681789                       # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks           0.849544                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.inst             0.072760                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.data             0.074275                       # Average percentage of cache occupancy
+system.l2c.occ_percent::total                0.996579                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu.inst              916210                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.data              814879                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1731089                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          835223                       # number of Writeback hits
+system.l2c.Writeback_hits::total               835223                       # number of Writeback hits
 system.l2c.UpgradeReq_hits::cpu.data                6                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::total                   6                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu.data            187658                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               187658                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu.inst               915368                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.data              1002554                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1917922                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu.inst              915368                       # number of overall hits
-system.l2c.overall_hits::cpu.data             1002554                       # number of overall hits
-system.l2c.overall_hits::total                1917922                       # number of overall hits
-system.l2c.ReadReq_misses::cpu.inst             13289                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu.data            271916                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total               285205                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu.data              7                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total                 7                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu.data          116692                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             116692                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu.inst              13289                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu.data             388608                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                401897                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu.inst             13289                       # number of overall misses
-system.l2c.overall_misses::cpu.data            388608                       # number of overall misses
-system.l2c.overall_misses::total               401897                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu.inst    691068000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu.data  14144627000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total    14835695000                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu.data       248000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total       248000                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu.data   6068427000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   6068427000                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu.inst    691068000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.data  20213054000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total     20904122000                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu.inst    691068000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu.data  20213054000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    20904122000                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu.inst          928657                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.data         1086812                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2015469                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       835591                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           835591                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu.data           13                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total              13                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu.data        304350                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           304350                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu.inst           928657                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.data          1391162                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2319819                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu.inst          928657                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.data         1391162                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2319819                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu.inst       0.014310                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.data       0.250196                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.141508                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu.data     0.538462                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.538462                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu.data     0.383414                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.383414                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu.inst        0.014310                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.data        0.279341                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.173245                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu.inst       0.014310                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.data       0.279341                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.173245                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu.inst 52003.010008                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu.data 52018.369644                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 52017.653968                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu.data 35428.571429                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 35428.571429                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu.data 52003.796319                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 52003.796319                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu.inst 52003.010008                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu.data 52013.993536                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 52013.630358                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.inst 52003.010008                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.data 52013.993536                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 52013.630358                       # average overall miss latency
+system.l2c.ReadExReq_hits::cpu.data            187457                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               187457                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu.inst               916210                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.data              1002336                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 1918546                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu.inst              916210                       # number of overall hits
+system.l2c.overall_hits::cpu.data             1002336                       # number of overall hits
+system.l2c.overall_hits::total                1918546                       # number of overall hits
+system.l2c.ReadReq_misses::cpu.inst             13292                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.data            271915                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total               285207                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu.data              8                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total                 8                       # number of UpgradeReq misses
+system.l2c.ReadExReq_misses::cpu.data          116714                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             116714                       # number of ReadExReq misses
+system.l2c.demand_misses::cpu.inst              13292                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.data             388629                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                401921                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu.inst             13292                       # number of overall misses
+system.l2c.overall_misses::cpu.data            388629                       # number of overall misses
+system.l2c.overall_misses::total               401921                       # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu.inst    691773000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.data  14144855000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total    14836628000                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu.data       320000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total       320000                       # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu.data   6069807000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   6069807000                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu.inst    691773000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.data  20214662000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total     20906435000                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu.inst    691773000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu.data  20214662000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total    20906435000                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu.inst          929502                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.data         1086794                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            2016296                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       835223                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           835223                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu.data           14                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total              14                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu.data        304171                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           304171                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu.inst           929502                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.data          1390965                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             2320467                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu.inst          929502                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.data         1390965                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            2320467                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu.inst       0.014300                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.data       0.250199                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.141451                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu.data     0.571429                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.571429                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu.data     0.383712                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.383712                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu.inst        0.014300                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.data        0.279395                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.173207                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu.inst       0.014300                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.data       0.279395                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.173207                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu.inst 52044.312368                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.data 52019.399445                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 52020.560505                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu.data        40000                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total        40000                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu.data 52005.817640                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 52005.817640                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu.inst 52044.312368                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.data 52015.320524                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 52016.279319                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.inst 52044.312368                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.data 52015.320524                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 52016.279319                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -141,66 +141,66 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               73933                       # number of writebacks
-system.l2c.writebacks::total                    73933                       # number of writebacks
-system.l2c.ReadReq_mshr_misses::cpu.inst        13289                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu.data       271916                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total          285205                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu.data            7                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total            7                       # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu.data       116692                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        116692                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu.inst         13289                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu.data        388608                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           401897                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu.inst        13289                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu.data       388608                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          401897                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu.inst    531597000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu.data  10881635000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total  11413232000                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu.data       320000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total       320000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu.data   4668123000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   4668123000                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.inst    531597000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.data  15549758000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  16081355000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.inst    531597000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.data  15549758000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  16081355000                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data    772673000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total    772673000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data   1083816500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   1083816500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu.data   1856489500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   1856489500                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.014310                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.250196                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.141508                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.538462                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.538462                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.383414                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.383414                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu.inst     0.014310                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu.data     0.279341                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.173245                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu.inst     0.014310                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu.data     0.279341                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.173245                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40002.784258                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40018.369644                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 40017.643449                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 45714.285714                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 45714.285714                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40003.796319                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 40003.796319                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40002.784258                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.data 40013.993536                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 40013.622893                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40002.784258                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.data 40013.993536                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 40013.622893                       # average overall mshr miss latency
+system.l2c.writebacks::writebacks               73942                       # number of writebacks
+system.l2c.writebacks::total                    73942                       # number of writebacks
+system.l2c.ReadReq_mshr_misses::cpu.inst        13292                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.data       271915                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total          285207                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu.data            8                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total            8                       # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu.data       116714                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        116714                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu.inst         13292                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu.data        388629                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           401921                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu.inst        13292                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu.data       388629                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          401921                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu.inst    532266000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.data  10881875000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total  11414141000                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu.data       380000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total       380000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu.data   4669239000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   4669239000                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.inst    532266000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.data  15551114000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  16083380000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.inst    532266000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.data  15551114000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  16083380000                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data    772639030                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total    772639030                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data   1072677000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   1072677000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu.data   1845316030                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   1845316030                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.014300                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.250199                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.141451                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.571429                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.571429                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.383712                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.383712                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu.inst     0.014300                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.data     0.279395                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.173207                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu.inst     0.014300                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.data     0.279395                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.173207                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40044.086669                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40019.399445                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 40020.549987                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data        47500                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total        47500                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40005.817640                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 40005.817640                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40044.086669                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.data 40015.320524                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 40016.271854                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40044.086669                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.data 40015.320524                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 40016.271854                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -209,14 +209,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data          inf
 system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.iocache.replacements                     41685                       # number of replacements
-system.iocache.tagsinuse                     1.340010                       # Cycle average of tags in use
+system.iocache.tagsinuse                     1.356962                       # Cycle average of tags in use
 system.iocache.total_refs                           0                       # Total number of references to valid blocks.
 system.iocache.sampled_refs                     41701                       # Sample count of references to valid blocks.
 system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
-system.iocache.warmup_cycle              1750543570000                       # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::tsunami.ide       1.340010                       # Average occupied blocks per requestor
-system.iocache.occ_percent::tsunami.ide      0.083751                       # Average percentage of cache occupancy
-system.iocache.occ_percent::total            0.083751                       # Average percentage of cache occupancy
+system.iocache.warmup_cycle              1753491316000                       # Cycle when the warmup percentage was hit.
+system.iocache.occ_blocks::tsunami.ide       1.356962                       # Average occupied blocks per requestor
+system.iocache.occ_percent::tsunami.ide      0.084810                       # Average percentage of cache occupancy
+system.iocache.occ_percent::total            0.084810                       # Average percentage of cache occupancy
 system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
 system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
@@ -225,14 +225,14 @@ system.iocache.demand_misses::tsunami.ide        41725                       # n
 system.iocache.demand_misses::total             41725                       # number of demand (read+write) misses
 system.iocache.overall_misses::tsunami.ide        41725                       # number of overall misses
 system.iocache.overall_misses::total            41725                       # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide     19939998                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     19939998                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::tsunami.ide   5720017806                       # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total   5720017806                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide   5739957804                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   5739957804                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide   5739957804                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   5739957804                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::tsunami.ide     20672998                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     20672998                       # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::tsunami.ide   7638105806                       # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total   7638105806                       # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide   7658778804                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   7658778804                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide   7658778804                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   7658778804                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
@@ -249,19 +249,19 @@ system.iocache.demand_miss_rate::tsunami.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115260.104046                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 115260.104046                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137659.265643                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 137659.265643                       # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 137566.394344                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 137566.394344                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 137566.394344                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 137566.394344                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs      64633068                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119497.098266                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 119497.098266                       # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183820.413121                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 183820.413121                       # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 183553.716093                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 183553.716093                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 183553.716093                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 183553.716093                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs       7453000                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                10476                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 7118                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs  6169.632302                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs  1047.063782                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -275,14 +275,14 @@ system.iocache.demand_mshr_misses::tsunami.ide        41725
 system.iocache.demand_mshr_misses::total        41725                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::tsunami.ide        41725                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total        41725                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     10943998                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     10943998                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::tsunami.ide   3559163998                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total   3559163998                       # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide   3570107996                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   3570107996                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide   3570107996                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   3570107996                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     11676000                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     11676000                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::tsunami.ide   5477251000                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total   5477251000                       # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide   5488927000                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   5488927000                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide   5488927000                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   5488927000                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
@@ -291,14 +291,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63260.104046                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 63260.104046                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85655.660329                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 85655.660329                       # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85562.803978                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 85562.803978                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85562.803978                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 85562.803978                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67491.329480                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 67491.329480                       # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131816.783789                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 131816.783789                       # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131550.077891                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 131550.077891                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131550.077891                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 131550.077891                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -316,22 +316,22 @@ system.cpu.dtb.fetch_hits                           0                       # IT
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                      9064877                       # DTB read hits
-system.cpu.dtb.read_misses                      10317                       # DTB read misses
+system.cpu.dtb.read_hits                      9065773                       # DTB read hits
+system.cpu.dtb.read_misses                      10329                       # DTB read misses
 system.cpu.dtb.read_acv                           210                       # DTB read access violations
-system.cpu.dtb.read_accesses                   728824                       # DTB read accesses
-system.cpu.dtb.write_hits                     6356219                       # DTB write hits
-system.cpu.dtb.write_misses                      1140                       # DTB write misses
+system.cpu.dtb.read_accesses                   728856                       # DTB read accesses
+system.cpu.dtb.write_hits                     6357048                       # DTB write hits
+system.cpu.dtb.write_misses                      1142                       # DTB write misses
 system.cpu.dtb.write_acv                          157                       # DTB write access violations
-system.cpu.dtb.write_accesses                  291929                       # DTB write accesses
-system.cpu.dtb.data_hits                     15421096                       # DTB hits
-system.cpu.dtb.data_misses                      11457                       # DTB misses
+system.cpu.dtb.write_accesses                  291931                       # DTB write accesses
+system.cpu.dtb.data_hits                     15422821                       # DTB hits
+system.cpu.dtb.data_misses                      11471                       # DTB misses
 system.cpu.dtb.data_acv                           367                       # DTB access violations
-system.cpu.dtb.data_accesses                  1020753                       # DTB accesses
-system.cpu.itb.fetch_hits                     4974034                       # ITB hits
-system.cpu.itb.fetch_misses                      4997                       # ITB misses
+system.cpu.dtb.data_accesses                  1020787                       # DTB accesses
+system.cpu.itb.fetch_hits                     4975760                       # ITB hits
+system.cpu.itb.fetch_misses                      5006                       # ITB misses
 system.cpu.itb.fetch_acv                          184                       # ITB acv
-system.cpu.itb.fetch_accesses                 4979031                       # ITB accesses
+system.cpu.itb.fetch_accesses                 4980766                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -344,51 +344,51 @@ system.cpu.itb.data_hits                            0                       # DT
 system.cpu.itb.data_misses                          0                       # DTB misses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.numCycles                       3830985638                       # number of cpu cycles simulated
+system.cpu.numCycles                       3841704548                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                    56182681                       # Number of instructions committed
-system.cpu.committedOps                      56182681                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses              52054721                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                 324259                       # Number of float alu accesses
-system.cpu.num_func_calls                     1483282                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts      6468098                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                     52054721                       # number of integer instructions
-system.cpu.num_fp_insts                        324259                       # number of float instructions
-system.cpu.num_int_register_reads            71321767                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           38521612                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads               163543                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes              166418                       # number of times the floating registers were written
-system.cpu.num_mem_refs                      15473677                       # number of memory refs
-system.cpu.num_load_insts                     9101706                       # Number of load instructions
-system.cpu.num_store_insts                    6371971                       # Number of store instructions
-system.cpu.num_idle_cycles               3589415321.998127                       # Number of idle cycles
-system.cpu.num_busy_cycles               241570316.001874                       # Number of busy cycles
-system.cpu.not_idle_fraction                 0.063057                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.936943                       # Percentage of idle cycles
+system.cpu.committedInsts                    56187824                       # Number of instructions committed
+system.cpu.committedOps                      56187824                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses              52059470                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                 324460                       # Number of float alu accesses
+system.cpu.num_func_calls                     1483670                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts      6469221                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                     52059470                       # number of integer instructions
+system.cpu.num_fp_insts                        324460                       # number of float instructions
+system.cpu.num_int_register_reads            71329755                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           38524240                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads               163642                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes              166520                       # number of times the floating registers were written
+system.cpu.num_mem_refs                      15475451                       # number of memory refs
+system.cpu.num_load_insts                     9102635                       # Number of load instructions
+system.cpu.num_store_insts                    6372816                       # Number of store instructions
+system.cpu.num_idle_cycles               3589583028.998131                       # Number of idle cycles
+system.cpu.num_busy_cycles               252121519.001869                       # Number of busy cycles
+system.cpu.not_idle_fraction                 0.065628                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.934372                       # Percentage of idle cycles
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                     6374                       # number of quiesce instructions executed
-system.cpu.kern.inst.hwrei                     211976                       # number of hwrei instructions executed
-system.cpu.kern.ipl_count::0                    74903     40.89%     40.89% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::21                     131      0.07%     40.96% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::22                    1931      1.05%     42.02% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31                  106219     57.98%    100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total               183184                       # number of times we switched to this ipl
-system.cpu.kern.ipl_good::0                     73536     49.31%     49.31% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.inst.quiesce                     6379                       # number of quiesce instructions executed
+system.cpu.kern.inst.hwrei                     212104                       # number of hwrei instructions executed
+system.cpu.kern.ipl_count::0                    74929     40.88%     40.88% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::21                     131      0.07%     40.95% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::22                    1936      1.06%     42.01% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::31                  106285     57.99%    100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::total               183281                       # number of times we switched to this ipl
+system.cpu.kern.ipl_good::0                     73562     49.31%     49.31% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::21                      131      0.09%     49.40% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::22                     1931      1.29%     50.69% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::31                    73536     49.31%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::total                149134                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0             1857766748000     96.99%     96.99% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21                79985500      0.00%     96.99% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22               554565500      0.03%     97.02% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31             57090762000      2.98%    100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total         1915492061000                       # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used::0                  0.981750                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_good::22                     1936      1.30%     50.69% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::31                    73562     49.31%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::total                149191                       # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks::0             1861395067500     96.90%     96.90% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::21                90398000      0.00%     96.91% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22               587303500      0.03%     96.94% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31             58778672000      3.06%    100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total         1920851441000                       # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used::0                  0.981756                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31                 0.692306                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::total              0.814121                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::31                 0.692120                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::total              0.814001                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
 system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
 system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
@@ -424,33 +424,33 @@ system.cpu.kern.callpal::cserve                     1      0.00%      0.00% # nu
 system.cpu.kern.callpal::wrmces                     1      0.00%      0.00% # number of callpals executed
 system.cpu.kern.callpal::wrfen                      1      0.00%      0.00% # number of callpals executed
 system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # number of callpals executed
-system.cpu.kern.callpal::swpctx                  4174      2.16%      2.17% # number of callpals executed
+system.cpu.kern.callpal::swpctx                  4177      2.16%      2.17% # number of callpals executed
 system.cpu.kern.callpal::tbi                       54      0.03%      2.19% # number of callpals executed
 system.cpu.kern.callpal::wrent                      7      0.00%      2.20% # number of callpals executed
-system.cpu.kern.callpal::swpipl                175965     91.22%     93.41% # number of callpals executed
-system.cpu.kern.callpal::rdps                    6832      3.54%     96.96% # number of callpals executed
+system.cpu.kern.callpal::swpipl                176052     91.22%     93.41% # number of callpals executed
+system.cpu.kern.callpal::rdps                    6837      3.54%     96.96% # number of callpals executed
 system.cpu.kern.callpal::wrkgp                      1      0.00%     96.96% # number of callpals executed
 system.cpu.kern.callpal::wrusp                      7      0.00%     96.96% # number of callpals executed
-system.cpu.kern.callpal::rdusp                      9      0.00%     96.97% # number of callpals executed
+system.cpu.kern.callpal::rdusp                      9      0.00%     96.96% # number of callpals executed
 system.cpu.kern.callpal::whami                      2      0.00%     96.97% # number of callpals executed
-system.cpu.kern.callpal::rti                     5156      2.67%     99.64% # number of callpals executed
+system.cpu.kern.callpal::rti                     5161      2.67%     99.64% # number of callpals executed
 system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
 system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
-system.cpu.kern.callpal::total                 192907                       # number of callpals executed
-system.cpu.kern.mode_switch::kernel              5900                       # number of protection mode switches
-system.cpu.kern.mode_switch::user                1740                       # number of protection mode switches
-system.cpu.kern.mode_switch::idle                2096                       # number of protection mode switches
-system.cpu.kern.mode_good::kernel                1909                      
-system.cpu.kern.mode_good::user                  1740                      
-system.cpu.kern.mode_good::idle                   169                      
-system.cpu.kern.mode_switch_good::kernel     0.323559                       # fraction of useful protection mode switches
+system.cpu.kern.callpal::total                 193007                       # number of callpals executed
+system.cpu.kern.mode_switch::kernel              5906                       # number of protection mode switches
+system.cpu.kern.mode_switch::user                1738                       # number of protection mode switches
+system.cpu.kern.mode_switch::idle                2098                       # number of protection mode switches
+system.cpu.kern.mode_good::kernel                1908                      
+system.cpu.kern.mode_good::user                  1738                      
+system.cpu.kern.mode_good::idle                   170                      
+system.cpu.kern.mode_switch_good::kernel     0.323061                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::idle       0.080630                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total      0.392153                       # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel        45078055000      2.35%      2.35% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user           5087693000      0.27%      2.62% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle         1865326311000     97.38%    100.00% # number of ticks spent at the given mode
-system.cpu.kern.swap_context                     4175                       # number of times the context was actually changed
+system.cpu.kern.mode_switch_good::idle       0.081030                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::total      0.391706                       # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks::kernel        46234544000      2.41%      2.41% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user           5257252000      0.27%      2.68% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle         1869359638000     97.32%    100.00% # number of ticks spent at the given mode
+system.cpu.kern.swap_context                     4178                       # number of times the context was actually changed
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
 system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
@@ -482,51 +482,51 @@ system.tsunami.ethernet.totalRxOrn                  0                       # to
 system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
 system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.cpu.icache.replacements                 928006                       # number of replacements
-system.cpu.icache.tagsinuse                508.737243                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 55265829                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                 928517                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                  59.520535                       # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle            35693107000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     508.737243                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.993627                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.993627                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst     55265829                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        55265829                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      55265829                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         55265829                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     55265829                       # number of overall hits
-system.cpu.icache.overall_hits::total        55265829                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       928677                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        928677                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       928677                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         928677                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       928677                       # number of overall misses
-system.cpu.icache.overall_misses::total        928677                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  13560162500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  13560162500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  13560162500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  13560162500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  13560162500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  13560162500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     56194506                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     56194506                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     56194506                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     56194506                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     56194506                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     56194506                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.016526                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.016526                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.016526                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.016526                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.016526                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.016526                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14601.591834                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 14601.591834                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 14601.591834                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 14601.591834                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 14601.591834                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 14601.591834                       # average overall miss latency
+system.cpu.icache.replacements                 928851                       # number of replacements
+system.cpu.icache.tagsinuse                508.732124                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 55270141                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                 929362                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                  59.471058                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle            35877190000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::cpu.inst     508.732124                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.993617                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.993617                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst     55270141                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        55270141                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      55270141                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         55270141                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     55270141                       # number of overall hits
+system.cpu.icache.overall_hits::total        55270141                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       929522                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        929522                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       929522                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         929522                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       929522                       # number of overall misses
+system.cpu.icache.overall_misses::total        929522                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  13854472500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  13854472500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  13854472500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  13854472500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  13854472500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  13854472500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     56199663                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     56199663                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     56199663                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     56199663                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     56199663                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     56199663                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.016540                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.016540                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.016540                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.016540                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.016540                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.016540                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14904.943078                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 14904.943078                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 14904.943078                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 14904.943078                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 14904.943078                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 14904.943078                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -537,104 +537,104 @@ system.cpu.icache.fast_writes                       0                       # nu
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks           85                       # number of writebacks
 system.cpu.icache.writebacks::total                85                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       928677                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       928677                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       928677                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       928677                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       928677                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       928677                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  10773446000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  10773446000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  10773446000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  10773446000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  10773446000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  10773446000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.016526                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.016526                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.016526                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.016526                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.016526                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.016526                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11600.853688                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11600.853688                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11600.853688                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11600.853688                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11600.853688                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11600.853688                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       929522                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       929522                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       929522                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       929522                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       929522                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       929522                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  11065220000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  11065220000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  11065220000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  11065220000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  11065220000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  11065220000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.016540                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.016540                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.016540                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.016540                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.016540                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.016540                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11904.204527                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11904.204527                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11904.204527                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11904.204527                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11904.204527                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11904.204527                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                1390840                       # number of replacements
-system.cpu.dcache.tagsinuse                511.984022                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 14048762                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                1391352                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  10.097202                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle               84029000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data     511.984022                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.999969                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.999969                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data      7814456                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total         7814456                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      5852131                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        5852131                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       182935                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       182935                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       199223                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       199223                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      13666587                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         13666587                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     13666587                       # number of overall hits
-system.cpu.dcache.overall_hits::total        13666587                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1069547                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1069547                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       304513                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       304513                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        17311                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        17311                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      1374060                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1374060                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1374060                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1374060                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  26396026000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  26396026000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   9163670000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   9163670000                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    245084000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    245084000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  35559696000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  35559696000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  35559696000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  35559696000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data      8884003                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total      8884003                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      6156644                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      6156644                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       200246                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       200246                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       199223                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       199223                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     15040647                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     15040647                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     15040647                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     15040647                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.120390                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.120390                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.049461                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.049461                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.086449                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.086449                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.091356                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.091356                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.091356                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.091356                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24679.631657                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 24679.631657                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30092.869598                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 30092.869598                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14157.703195                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14157.703195                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 25879.289114                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 25879.289114                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 25879.289114                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 25879.289114                       # average overall miss latency
+system.cpu.dcache.replacements                1390643                       # number of replacements
+system.cpu.dcache.tagsinuse                511.983813                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 14050710                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                1391155                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  10.100032                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle               85768000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data     511.983813                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.999968                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.999968                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data      7815347                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total         7815347                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      5853082                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        5853082                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       182979                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       182979                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       199284                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       199284                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      13668429                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         13668429                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     13668429                       # number of overall hits
+system.cpu.dcache.overall_hits::total        13668429                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1069514                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1069514                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       304335                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       304335                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        17326                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        17326                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data      1373849                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1373849                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1373849                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1373849                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  26655510000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  26655510000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   9230954000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   9230954000                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    248493000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    248493000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  35886464000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  35886464000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  35886464000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  35886464000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data      8884861                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total      8884861                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      6157417                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      6157417                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       200305                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       200305                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       199284                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       199284                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     15042278                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     15042278                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     15042278                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     15042278                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.120375                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.120375                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.049426                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.049426                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.086498                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.086498                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.091333                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.091333                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.091333                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.091333                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24923.011760                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 24923.011760                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30331.555687                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 30331.555687                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14342.202470                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14342.202470                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 26121.112291                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 26121.112291                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 26121.112291                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 26121.112291                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -643,54 +643,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       835506                       # number of writebacks
-system.cpu.dcache.writebacks::total            835506                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1069547                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1069547                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       304513                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       304513                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        17311                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total        17311                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1374060                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1374060                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1374060                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1374060                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  23187340000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  23187340000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8250131000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   8250131000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    193151000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    193151000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  31437471000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  31437471000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  31437471000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  31437471000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data    862763000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total    862763000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   1199604500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   1199604500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   2062367500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total   2062367500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.120390                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.120390                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.049461                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.049461                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.086449                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.086449                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091356                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.091356                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091356                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.091356                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21679.589583                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21679.589583                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27092.869598                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27092.869598                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11157.703195                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11157.703195                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22879.256364                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 22879.256364                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22879.256364                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 22879.256364                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks       835138                       # number of writebacks
+system.cpu.dcache.writebacks::total            835138                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1069514                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1069514                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       304335                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       304335                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        17326                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total        17326                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1373849                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1373849                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1373849                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1373849                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  23446923000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  23446923000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8317949000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   8317949000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    196515000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    196515000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  31764872000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  31764872000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  31764872000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  31764872000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data    862831000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total    862831000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   1190523500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   1190523500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   2053354500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   2053354500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.120375                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.120375                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.049426                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.049426                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.086498                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.086498                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091333                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.091333                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091333                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.091333                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21922.969685                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21922.969685                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27331.555687                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27331.555687                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11342.202470                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11342.202470                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23121.079536                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 23121.079536                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23121.079536                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 23121.079536                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
index f78b6a8fb..363bd4c66 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
@@ -20,7 +20,7 @@ kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 load_addr_mask=268435455
 machine_type=RealView_PBX
 mem_mode=timing
-memories=system.realview.nvmem system.physmem
+memories=system.physmem system.realview.nvmem
 midr_regval=890224640
 multi_proc=true
 num_work_ids=16
@@ -298,7 +298,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
 
@@ -359,7 +359,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 default=system.membus.badaddr_responder.pio
 master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
 slave=system.system_port system.iocache.mem_side system.l2c.mem_side
@@ -772,7 +772,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.l2c.cpu_side
 slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
 
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
index ccc6b6e90..70032b595 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:10:14
-gem5 started Jun 29 2012 00:37:10
+gem5 compiled Jul  2 2012 09:08:16
+gem5 started Jul  2 2012 15:21:03
 gem5 executing on zizzer
 command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 info: Using bootloader at address 0x80000000
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 1169301297000 because m5_exit instruction encountered
+Exiting @ tick 1171612619000 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
index a92b3a054..bf3a52c45 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
@@ -1,320 +1,320 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.169301                       # Number of seconds simulated
-sim_ticks                                1169301297000                       # Number of ticks simulated
-final_tick                               1169301297000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.171613                       # Number of seconds simulated
+sim_ticks                                1171612619000                       # Number of ticks simulated
+final_tick                               1171612619000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 971844                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1242825                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            18805861990                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 384788                       # Number of bytes of host memory used
-host_seconds                                    62.18                       # Real time elapsed on the host
-sim_insts                                    60426768                       # Number of instructions simulated
-sim_ops                                      77275723                       # Number of ops (including micro ops) simulated
-system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu1.inst           48                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total            68                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu1.inst           48                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total           68                       # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu1.inst           12                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total             17                       # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst           17                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.inst           41                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total               58                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst           17                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst           41                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total           58                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst           17                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst           41                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total              58                       # Total bandwidth to/from this memory (bytes/s)
+host_inst_rate                                 639669                       # Simulator instruction rate (inst/s)
+host_op_rate                                   818158                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            12399663305                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 384708                       # Number of bytes of host memory used
+host_seconds                                    94.49                       # Real time elapsed on the host
+sim_insts                                    60440687                       # Number of instructions simulated
+sim_ops                                      77305655                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::realview.clcd     50331648                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.dtb.walker           64                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           394404                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          4694964                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           395940                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          4717108                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.dtb.walker          256                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           322780                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          4800816                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             60545060                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       394404                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       322780                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          717184                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      4092224                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu1.inst           321948                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          4794672                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             60561764                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       395940                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       321948                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          717888                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      4107520                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         17000                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data       3010344                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7119568                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7134864                       # Number of bytes written to this memory
 system.physmem.num_reads::realview.clcd       6291456                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.dtb.walker            1                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             12381                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             73431                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             12405                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             73777                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.dtb.walker            4                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              5125                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             75039                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               6457439                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           63941                       # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              5112                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             74943                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               6457700                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           64180                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             4250                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data           752586                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               820777                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd        43044208                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               821016                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        42959291                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.dtb.walker            55                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker           109                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              337299                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             4015188                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              337944                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             4026167                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu1.dtb.walker           219                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst              276045                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             4105713                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                51778836                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         337299                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst         276045                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             613344                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3499717                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data              14539                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data            2574481                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                6088737                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3499717                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd       43044208                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst              274790                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             4092370                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                51690945                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         337944                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst         274790                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             612735                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3505869                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data              14510                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data            2569402                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                6089781                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3505869                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       42959291                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.dtb.walker           55                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker          109                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             337299                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            4029726                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             337944                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            4040677                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu1.dtb.walker          219                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst             276045                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            6680194                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               57867573                       # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements                         69045                       # number of replacements
-system.l2c.tagsinuse                     52660.415221                       # Cycle average of tags in use
-system.l2c.total_refs                         1684870                       # Total number of references to valid blocks.
-system.l2c.sampled_refs                        134185                       # Sample count of references to valid blocks.
-system.l2c.avg_refs                         12.556321                       # Average number of references to valid blocks.
+system.physmem.bw_total::cpu1.inst             274790                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            6661772                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               57780726                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu1.inst           48                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total            68                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu1.inst           48                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total           68                       # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu1.inst           12                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total             17                       # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst           17                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.inst           41                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total               58                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst           17                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu1.inst           41                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total           58                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst           17                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.inst           41                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total              58                       # Total bandwidth to/from this memory (bytes/s)
+system.l2c.replacements                         69306                       # number of replacements
+system.l2c.tagsinuse                     52659.016481                       # Cycle average of tags in use
+system.l2c.total_refs                         1685686                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                        134505                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                         12.532516                       # Average number of references to valid blocks.
 system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks        39883.931908                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.dtb.walker       0.000281                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.itb.walker       0.001232                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst          3733.911815                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data          4222.338805                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.dtb.walker       2.732261                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.inst          2761.000373                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.data          2056.498545                       # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks           0.608581                       # Average percentage of cache occupancy
+system.l2c.occ_blocks::writebacks        39891.573384                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.dtb.walker       0.000282                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.itb.walker       0.001243                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst          3742.951187                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data          4216.912189                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.dtb.walker       2.733680                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst          2750.765696                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.data          2054.078820                       # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks           0.608697                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu0.dtb.walker      0.000000                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu0.itb.walker      0.000000                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.inst            0.056975                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.data            0.064428                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.inst            0.057113                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.data            0.064345                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu1.dtb.walker      0.000042                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.inst            0.042130                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.data            0.031380                       # Average percentage of cache occupancy
-system.l2c.occ_percent::total                0.803534                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0.dtb.walker         4332                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker         1875                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst             401384                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             204711                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker         5503                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker         1891                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             448240                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data             143182                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1211118                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          615916                       # number of Writeback hits
-system.l2c.Writeback_hits::total               615916                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data            1171                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data             482                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                1653                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data           214                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data           105                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total               319                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            56705                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            52894                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               109599                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker          4332                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker          1875                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              401384                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              261416                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker          5503                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          1891                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              448240                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              196076                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1320717                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker         4332                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker         1875                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             401384                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             261416                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker         5503                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         1891                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             448240                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             196076                       # number of overall hits
-system.l2c.overall_hits::total                1320717                       # number of overall hits
+system.l2c.occ_percent::cpu1.inst            0.041973                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.data            0.031343                       # Average percentage of cache occupancy
+system.l2c.occ_percent::total                0.803513                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu0.dtb.walker         4104                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker         1844                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.inst             401511                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data             204865                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker         5725                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker         1962                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst             448415                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data             143316                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1211742                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          616867                       # number of Writeback hits
+system.l2c.Writeback_hits::total               616867                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data            1168                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data             575                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                1743                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data           210                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data           101                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total               311                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data            56775                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            52975                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               109750                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.dtb.walker          4104                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker          1844                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst              401511                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              261640                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker          5725                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker          1962                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              448415                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              196291                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 1321492                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker         4104                       # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker         1844                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst             401511                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             261640                       # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker         5725                       # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker         1962                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             448415                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             196291                       # number of overall hits
+system.l2c.overall_hits::total                1321492                       # number of overall hits
 system.l2c.ReadReq_misses::cpu0.dtb.walker            1                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu0.itb.walker            2                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst             5749                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data             7868                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.inst             5773                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data             7865                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu1.dtb.walker            4                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst             5038                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data             3631                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                22293                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data          4671                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data          3578                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              8249                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data          565                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data          471                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total            1036                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          66836                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          72487                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             139323                       # number of ReadExReq misses
+system.l2c.ReadReq_misses::cpu1.inst             5025                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data             3646                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                22316                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data          4668                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data          3562                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              8230                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data          564                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data          479                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total            1043                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data          67164                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data          72393                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             139557                       # number of ReadExReq misses
 system.l2c.demand_misses::cpu0.dtb.walker            1                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst              5749                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data             74704                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst              5773                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data             75029                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu1.dtb.walker            4                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              5038                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             76118                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                161616                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst              5025                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data             76039                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                161873                       # number of demand (read+write) misses
 system.l2c.overall_misses::cpu0.dtb.walker            1                       # number of overall misses
 system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst             5749                       # number of overall misses
-system.l2c.overall_misses::cpu0.data            74704                       # number of overall misses
+system.l2c.overall_misses::cpu0.inst             5773                       # number of overall misses
+system.l2c.overall_misses::cpu0.data            75029                       # number of overall misses
 system.l2c.overall_misses::cpu1.dtb.walker            4                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             5038                       # number of overall misses
-system.l2c.overall_misses::cpu1.data            76118                       # number of overall misses
-system.l2c.overall_misses::total               161616                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst             5025                       # number of overall misses
+system.l2c.overall_misses::cpu1.data            76039                       # number of overall misses
+system.l2c.overall_misses::total               161873                       # number of overall misses
 system.l2c.ReadReq_miss_latency::cpu0.dtb.walker        52000                       # number of ReadReq miss cycles
 system.l2c.ReadReq_miss_latency::cpu0.itb.walker       104000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.inst    299700000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data    409350000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.dtb.walker       211000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst    263300500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data    189429000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total     1162146500                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0.data     29698000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data     27084000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total     56782000                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data      4004000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data      5670000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total      9674000                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data   3477668000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data   3777626000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   7255294000                       # number of ReadExReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.inst    300844500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.data    409319998                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.dtb.walker       208500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst    262047000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data    190080500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total     1162656498                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu0.data     28957997                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data     27214000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total     56171997                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data      3588000                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data      6004000                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total      9592000                       # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data   3493801976                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data   3769288495                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   7263090471                       # number of ReadExReq miss cycles
 system.l2c.demand_miss_latency::cpu0.dtb.walker        52000                       # number of demand (read+write) miss cycles
 system.l2c.demand_miss_latency::cpu0.itb.walker       104000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst    299700000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data   3887018000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker       211000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst    263300500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data   3967055000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total      8417440500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.inst    300844500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data   3903121974                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.dtb.walker       208500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst    262047000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data   3959368995                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total      8425746969                       # number of demand (read+write) miss cycles
 system.l2c.overall_miss_latency::cpu0.dtb.walker        52000                       # number of overall miss cycles
 system.l2c.overall_miss_latency::cpu0.itb.walker       104000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst    299700000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data   3887018000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker       211000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst    263300500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data   3967055000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total     8417440500                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.dtb.walker         4333                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker         1877                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst         407133                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data         212579                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker         5507                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker         1891                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst         453278                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data         146813                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            1233411                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       615916                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           615916                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data         5842                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data         4060                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            9902                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data          779                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data          576                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total          1355                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       123541                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data       125381                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           248922                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker         4333                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker         1877                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          407133                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data          336120                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker         5507                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker         1891                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          453278                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          272194                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             1482333                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker         4333                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker         1877                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         407133                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data         336120                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker         5507                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker         1891                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         453278                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         272194                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            1482333                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000231                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.001066                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.014121                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.037012                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000726                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.011115                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.024732                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.018074                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.799555                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.881281                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.833064                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.725289                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.817708                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.764576                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.541003                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.578134                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.559705                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000231                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.001066                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.014121                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.222254                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000726                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.011115                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.279646                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.109028                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000231                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.001066                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.014121                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.222254                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000726                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.011115                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.279646                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.109028                       # miss rate for overall accesses
+system.l2c.overall_miss_latency::cpu0.inst    300844500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data   3903121974                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.dtb.walker       208500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst    262047000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data   3959368995                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total     8425746969                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.dtb.walker         4105                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker         1846                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.inst         407284                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data         212730                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker         5729                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker         1962                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst         453440                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data         146962                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            1234058                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       616867                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           616867                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data         5836                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data         4137                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            9973                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data          774                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data          580                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total          1354                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       123939                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data       125368                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           249307                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker         4105                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker         1846                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst          407284                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data          336669                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker         5729                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker         1962                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          453440                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data          272330                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             1483365                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker         4105                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker         1846                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         407284                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data         336669                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker         5729                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker         1962                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         453440                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data         272330                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            1483365                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000244                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.001083                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.014174                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.036972                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000698                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.011082                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data      0.024809                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.018083                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.799863                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.861010                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.825228                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.728682                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.825862                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.770310                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.541912                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.577444                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.559780                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000244                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.001083                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.014174                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.222857                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000698                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.011082                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.279216                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.109126                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000244                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.001083                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.014174                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.222857                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000698                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.011082                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.279216                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.109126                       # miss rate for overall accesses
 system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker        52000                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        52000                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52130.805357                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 52027.198780                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        52750                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52262.901945                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 52169.925640                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 52130.556677                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  6357.953329                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  7569.591951                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  6883.501030                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  7086.725664                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 12038.216561                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  9337.837838                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52032.856544                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52114.530881                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 52075.350086                       # average ReadExReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52112.333276                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.data 52043.229243                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        52125                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52148.656716                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 52133.982447                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 52099.681753                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  6203.512639                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  7640.089837                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  6825.273026                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  6361.702128                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 12534.446764                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total  9196.548418                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52018.968138                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52067.029892                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 52043.899417                       # average ReadExReq miss latency
 system.l2c.demand_avg_miss_latency::cpu0.dtb.walker        52000                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu0.itb.walker        52000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 52130.805357                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 52032.260655                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        52750                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 52262.901945                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 52117.173336                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 52082.965177                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 52112.333276                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 52021.511336                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        52125                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 52148.656716                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 52070.240206                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 52051.589635                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu0.dtb.walker        52000                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu0.itb.walker        52000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 52130.805357                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 52032.260655                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        52750                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 52262.901945                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 52117.173336                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 52082.965177                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 52112.333276                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 52021.511336                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        52125                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 52148.656716                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 52070.240206                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 52051.589635                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -323,8 +323,8 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               63941                       # number of writebacks
-system.l2c.writebacks::total                    63941                       # number of writebacks
+system.l2c.writebacks::writebacks               64180                       # number of writebacks
+system.l2c.writebacks::total                    64180                       # number of writebacks
 system.l2c.ReadReq_mshr_hits::cpu0.inst             1                       # number of ReadReq MSHR hits
 system.l2c.ReadReq_mshr_hits::total                 1                       # number of ReadReq MSHR hits
 system.l2c.demand_mshr_hits::cpu0.inst              1                       # number of demand (read+write) MSHR hits
@@ -333,149 +333,149 @@ system.l2c.overall_mshr_hits::cpu0.inst             1                       # nu
 system.l2c.overall_mshr_hits::total                 1                       # number of overall MSHR hits
 system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker            1                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            2                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.inst         5748                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.data         7868                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.inst         5772                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.data         7865                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker            4                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst         5038                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data         3631                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total           22292                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data         4671                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data         3578                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total         8249                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          565                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          471                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total         1036                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data        66836                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data        72487                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        139323                       # number of ReadExReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.inst         5025                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.data         3646                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total           22315                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data         4668                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data         3562                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total         8230                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          564                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          479                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total         1043                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data        67164                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data        72393                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        139557                       # number of ReadExReq MSHR misses
 system.l2c.demand_mshr_misses::cpu0.dtb.walker            1                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu0.itb.walker            2                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst         5748                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data        74704                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst         5772                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data        75029                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu1.dtb.walker            4                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst         5038                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data        76118                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           161615                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst         5025                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data        76039                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           161872                       # number of demand (read+write) MSHR misses
 system.l2c.overall_mshr_misses::cpu0.dtb.walker            1                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu0.itb.walker            2                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst         5748                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data        74704                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst         5772                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data        75029                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu1.dtb.walker            4                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst         5038                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data        76118                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          161615                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst         5025                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data        76039                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          161872                       # number of overall MSHR misses
 system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker        40000                       # number of ReadReq MSHR miss cycles
 system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker        80000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    230696000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.data    314934000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker       163000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    202841000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data    145857000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total    894611000                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    186977000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    143294000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total    330271000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     22610000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     18883000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total     41493000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   2675636000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   2907782000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   5583418000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    231552000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.data    314935000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker       160000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    201743000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data    146326000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total    894836000                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    186889000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    142710000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    329599000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     22593000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     19208000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total     41801000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   2687800500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   2900558000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   5588358500                       # number of ReadExReq MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker        40000                       # number of demand (read+write) MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu0.itb.walker        80000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst    230696000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data   2990570000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       163000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst    202841000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data   3053639000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total   6478029000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst    231552000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data   3002735500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       160000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst    201743000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data   3046884000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   6483194500                       # number of demand (read+write) MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker        40000                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu0.itb.walker        80000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst    230696000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data   2990570000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       163000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst    202841000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data   3053639000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total   6478029000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst    231552000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data   3002735500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       160000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    201743000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data   3046884000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   6483194500                       # number of overall MSHR miss cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    265520000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   9317572500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   9312662000                       # number of ReadReq MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      3961000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 122235998500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 131823052000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data    699470000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data  30625900500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total  31325370500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 122159781000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 131741924000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data    694882000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data  30588601000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total  31283483000                       # number of WriteReq MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    265520000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data  10017042500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data  10007544000                       # number of overall MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      3961000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data 152861899000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 163148422500                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000231                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.001066                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.014118                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.037012                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000726                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.011115                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.024732                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.018073                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.799555                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.881281                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.833064                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.725289                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.817708                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.764576                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.541003                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.578134                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.559705                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000231                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.001066                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.014118                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.222254                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000726                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.011115                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.279646                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.109027                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000231                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.001066                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.014118                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.222254                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000726                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.011115                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.279646                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.109027                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data 152748382000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 163025407000                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000244                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.001083                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.014172                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.036972                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000698                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.011082                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.024809                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.018083                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.799863                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.861010                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.825228                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.728682                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.825862                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.770310                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.541912                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.577444                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.559780                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000244                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.001083                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.014172                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.222857                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000698                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.011082                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.279216                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.109125                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000244                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.001083                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.014172                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.222857                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000698                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.011082                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.279216                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.109125                       # mshr miss rate for overall accesses
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker        40000                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        40000                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40135.003479                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40027.198780                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        40750                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40262.207225                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40169.925640                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 40131.482146                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40029.329908                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40048.630520                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40037.701540                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40017.699115                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40091.295117                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40051.158301                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40032.856544                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40114.530881                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 40075.350086                       # average ReadExReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40116.424116                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40042.593770                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        40000                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40147.860697                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40133.296764                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 40100.201658                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40036.203942                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40064.570466                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40048.481166                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40058.510638                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40100.208768                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40077.660594                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40018.469716                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40066.829666                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 40043.555680                       # average ReadExReq mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker        40000                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        40000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40135.003479                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40032.260655                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        40750                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40262.207225                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40117.173336                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 40083.092535                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40116.424116                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40020.998547                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        40000                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40147.860697                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40070.016702                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 40051.364658                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker        40000                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        40000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40135.003479                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40032.260655                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        40750                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40262.207225                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40117.173336                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 40083.092535                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40116.424116                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40020.998547                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        40000                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40147.860697                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40070.016702                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 40051.364658                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
@@ -498,10 +498,10 @@ system.cf0.dma_write_bytes                          0                       # Nu
 system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                     7070010                       # DTB read hits
-system.cpu0.dtb.read_misses                      3742                       # DTB read misses
-system.cpu0.dtb.write_hits                    5655317                       # DTB write hits
-system.cpu0.dtb.write_misses                      808                       # DTB write misses
+system.cpu0.dtb.read_hits                     7077919                       # DTB read hits
+system.cpu0.dtb.read_misses                      3740                       # DTB read misses
+system.cpu0.dtb.write_hits                    5661726                       # DTB write hits
+system.cpu0.dtb.write_misses                      804                       # DTB write misses
 system.cpu0.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
@@ -511,13 +511,13 @@ system.cpu0.dtb.align_faults                        0                       # Nu
 system.cpu0.dtb.prefetch_faults                   141                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.dtb.perms_faults                      204                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                 7073752                       # DTB read accesses
-system.cpu0.dtb.write_accesses                5656125                       # DTB write accesses
+system.cpu0.dtb.read_accesses                 7081659                       # DTB read accesses
+system.cpu0.dtb.write_accesses                5662530                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         12725327                       # DTB hits
-system.cpu0.dtb.misses                           4550                       # DTB misses
-system.cpu0.dtb.accesses                     12729877                       # DTB accesses
-system.cpu0.itb.inst_hits                    29439174                       # ITB inst hits
+system.cpu0.dtb.hits                         12739645                       # DTB hits
+system.cpu0.dtb.misses                           4544                       # DTB misses
+system.cpu0.dtb.accesses                     12744189                       # DTB accesses
+system.cpu0.itb.inst_hits                    29451654                       # ITB inst hits
 system.cpu0.itb.inst_misses                      2205                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
@@ -534,79 +534,79 @@ system.cpu0.itb.domain_faults                       0                       # Nu
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                29441379                       # ITB inst accesses
-system.cpu0.itb.hits                         29439174                       # DTB hits
+system.cpu0.itb.inst_accesses                29453859                       # ITB inst accesses
+system.cpu0.itb.hits                         29451654                       # DTB hits
 system.cpu0.itb.misses                           2205                       # DTB misses
-system.cpu0.itb.accesses                     29441379                       # DTB accesses
-system.cpu0.numCycles                      2338602594                       # number of cpu cycles simulated
+system.cpu0.itb.accesses                     29453859                       # DTB accesses
+system.cpu0.numCycles                      2343225238                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   28746820                       # Number of instructions committed
-system.cpu0.committedOps                     37084824                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             33031249                       # Number of integer alu accesses
+system.cpu0.committedInsts                   28759206                       # Number of instructions committed
+system.cpu0.committedOps                     37112849                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses             33058293                       # Number of integer alu accesses
 system.cpu0.num_fp_alu_accesses                  3860                       # Number of float alu accesses
-system.cpu0.num_func_calls                    1241704                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      4321371                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    33031249                       # number of integer instructions
+system.cpu0.num_func_calls                    1242118                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      4322812                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    33058293                       # number of integer instructions
 system.cpu0.num_fp_insts                         3860                       # number of float instructions
-system.cpu0.num_int_register_reads          189614137                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          36088732                       # number of times the integer registers were written
+system.cpu0.num_int_register_reads          189772382                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          36110779                       # number of times the integer registers were written
 system.cpu0.num_fp_register_reads                3022                       # number of times the floating registers were read
 system.cpu0.num_fp_register_writes                840                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                     13393278                       # number of memory refs
-system.cpu0.num_load_insts                    7407523                       # Number of load instructions
-system.cpu0.num_store_insts                   5985755                       # Number of store instructions
-system.cpu0.num_idle_cycles              2203295398.340116                       # Number of idle cycles
-system.cpu0.num_busy_cycles              135307195.659884                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.057858                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.942142                       # Percentage of idle cycles
+system.cpu0.num_mem_refs                     13408219                       # number of memory refs
+system.cpu0.num_load_insts                    7415624                       # Number of load instructions
+system.cpu0.num_store_insts                   5992595                       # Number of store instructions
+system.cpu0.num_idle_cycles              2203054927.350120                       # Number of idle cycles
+system.cpu0.num_busy_cycles              140170310.649880                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.059819                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.940181                       # Percentage of idle cycles
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   46685                       # number of quiesce instructions executed
-system.cpu0.icache.replacements                408143                       # number of replacements
-system.cpu0.icache.tagsinuse               509.526052                       # Cycle average of tags in use
-system.cpu0.icache.total_refs                29030502                       # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs                408655                       # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs                 71.039145                       # Average number of references to valid blocks.
-system.cpu0.icache.warmup_cycle           74905211000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst   509.526052                       # Average occupied blocks per requestor
-system.cpu0.icache.occ_percent::cpu0.inst     0.995168                       # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::total        0.995168                       # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst     29030502                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       29030502                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     29030502                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        29030502                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     29030502                       # number of overall hits
-system.cpu0.icache.overall_hits::total       29030502                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       408655                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       408655                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       408655                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        408655                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       408655                       # number of overall misses
-system.cpu0.icache.overall_misses::total       408655                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   5965025000                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total   5965025000                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst   5965025000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total   5965025000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst   5965025000                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total   5965025000                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     29439157                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     29439157                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     29439157                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     29439157                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     29439157                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     29439157                       # number of overall (read+write) accesses
+system.cpu0.kern.inst.quiesce                   46686                       # number of quiesce instructions executed
+system.cpu0.icache.replacements                408292                       # number of replacements
+system.cpu0.icache.tagsinuse               509.494086                       # Cycle average of tags in use
+system.cpu0.icache.total_refs                29042833                       # Total number of references to valid blocks.
+system.cpu0.icache.sampled_refs                408804                       # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs                 71.043417                       # Average number of references to valid blocks.
+system.cpu0.icache.warmup_cycle           75128321000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.occ_blocks::cpu0.inst   509.494086                       # Average occupied blocks per requestor
+system.cpu0.icache.occ_percent::cpu0.inst     0.995106                       # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::total        0.995106                       # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits::cpu0.inst     29042833                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       29042833                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     29042833                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        29042833                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     29042833                       # number of overall hits
+system.cpu0.icache.overall_hits::total       29042833                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       408804                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       408804                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       408804                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        408804                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       408804                       # number of overall misses
+system.cpu0.icache.overall_misses::total       408804                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   6099412500                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total   6099412500                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst   6099412500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total   6099412500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst   6099412500                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total   6099412500                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     29451637                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     29451637                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     29451637                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     29451637                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     29451637                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     29451637                       # number of overall (read+write) accesses
 system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.013881                       # miss rate for ReadReq accesses
 system.cpu0.icache.ReadReq_miss_rate::total     0.013881                       # miss rate for ReadReq accesses
 system.cpu0.icache.demand_miss_rate::cpu0.inst     0.013881                       # miss rate for demand accesses
 system.cpu0.icache.demand_miss_rate::total     0.013881                       # miss rate for demand accesses
 system.cpu0.icache.overall_miss_rate::cpu0.inst     0.013881                       # miss rate for overall accesses
 system.cpu0.icache.overall_miss_rate::total     0.013881                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14596.725845                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 14596.725845                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14596.725845                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 14596.725845                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14596.725845                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 14596.725845                       # average overall miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14920.138991                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 14920.138991                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14920.138991                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 14920.138991                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14920.138991                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 14920.138991                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -615,20 +615,20 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.writebacks::writebacks        20759                       # number of writebacks
-system.cpu0.icache.writebacks::total            20759                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       408655                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       408655                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       408655                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       408655                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       408655                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       408655                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   4737808500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total   4737808500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   4737808500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total   4737808500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   4737808500                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total   4737808500                       # number of overall MSHR miss cycles
+system.cpu0.icache.writebacks::writebacks        20827                       # number of writebacks
+system.cpu0.icache.writebacks::total            20827                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       408804                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       408804                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       408804                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       408804                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       408804                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       408804                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   4872150503                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total   4872150503                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   4872150503                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total   4872150503                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   4872150503                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   4872150503                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    351814000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    351814000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    351814000                       # number of overall MSHR uncacheable cycles
@@ -639,98 +639,98 @@ system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.013881
 system.cpu0.icache.demand_mshr_miss_rate::total     0.013881                       # mshr miss rate for demand accesses
 system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.013881                       # mshr miss rate for overall accesses
 system.cpu0.icache.overall_mshr_miss_rate::total     0.013881                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11593.663359                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11593.663359                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11593.663359                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 11593.663359                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11593.663359                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 11593.663359                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11918.059762                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11918.059762                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11918.059762                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 11918.059762                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11918.059762                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 11918.059762                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.replacements                330129                       # number of replacements
-system.cpu0.dcache.tagsinuse               459.697251                       # Cycle average of tags in use
-system.cpu0.dcache.total_refs                12270461                       # Total number of references to valid blocks.
-system.cpu0.dcache.sampled_refs                330641                       # Sample count of references to valid blocks.
-system.cpu0.dcache.avg_refs                 37.111130                       # Average number of references to valid blocks.
-system.cpu0.dcache.warmup_cycle             663204000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::cpu0.data   459.697251                       # Average occupied blocks per requestor
-system.cpu0.dcache.occ_percent::cpu0.data     0.897846                       # Average percentage of cache occupancy
-system.cpu0.dcache.occ_percent::total        0.897846                       # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::cpu0.data      6600245                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        6600245                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      5350394                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       5350394                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       147923                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       147923                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       149677                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       149677                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     11950639                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        11950639                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     11950639                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       11950639                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       227470                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       227470                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       141496                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       141496                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         9302                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total         9302                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data         7489                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total         7489                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       368966                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total        368966                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       368966                       # number of overall misses
-system.cpu0.dcache.overall_misses::total       368966                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   3341792500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total   3341792500                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   4877331500                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total   4877331500                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data     98417500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total     98417500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     68140000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total     68140000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data   8219124000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total   8219124000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data   8219124000                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total   8219124000                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      6827715                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      6827715                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      5491890                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      5491890                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       157225                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       157225                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       157166                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       157166                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     12319605                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     12319605                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     12319605                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     12319605                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.033316                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.033316                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.025765                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.025765                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.059164                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.059164                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.047650                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.047650                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.029949                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.029949                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.029949                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.029949                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14691.135095                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 14691.135095                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34469.748261                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 34469.748261                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10580.251559                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10580.251559                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  9098.678061                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  9098.678061                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 22276.101321                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 22276.101321                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 22276.101321                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 22276.101321                       # average overall miss latency
+system.cpu0.dcache.replacements                330880                       # number of replacements
+system.cpu0.dcache.tagsinuse               457.764906                       # Cycle average of tags in use
+system.cpu0.dcache.total_refs                12284019                       # Total number of references to valid blocks.
+system.cpu0.dcache.sampled_refs                331392                       # Sample count of references to valid blocks.
+system.cpu0.dcache.avg_refs                 37.067941                       # Average number of references to valid blocks.
+system.cpu0.dcache.warmup_cycle             664264000                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.occ_blocks::cpu0.data   457.764906                       # Average occupied blocks per requestor
+system.cpu0.dcache.occ_percent::cpu0.data     0.894072                       # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::total        0.894072                       # Average percentage of cache occupancy
+system.cpu0.dcache.ReadReq_hits::cpu0.data      6607497                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        6607497                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      5356507                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       5356507                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       147994                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       147994                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       149732                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       149732                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     11964004                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        11964004                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     11964004                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       11964004                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       228069                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       228069                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       141727                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       141727                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         9289                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total         9289                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data         7498                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total         7498                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data       369796                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total        369796                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data       369796                       # number of overall misses
+system.cpu0.dcache.overall_misses::total       369796                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   3436407000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total   3436407000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   4917296000                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total   4917296000                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    100570500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    100570500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     74480000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total     74480000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data   8353703000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total   8353703000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data   8353703000                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total   8353703000                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      6835566                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      6835566                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      5498234                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      5498234                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       157283                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       157283                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       157230                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       157230                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     12333800                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     12333800                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     12333800                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     12333800                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.033365                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.033365                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.025777                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.025777                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.059059                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.059059                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.047688                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.047688                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.029982                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.029982                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.029982                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.029982                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15067.400655                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 15067.400655                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34695.548484                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 34695.548484                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10826.838196                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10826.838196                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  9933.315551                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  9933.315551                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 22590.030720                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 22590.030720                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 22590.030720                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 22590.030720                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -739,62 +739,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       306018                       # number of writebacks
-system.cpu0.dcache.writebacks::total           306018                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       227470                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       227470                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       141496                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       141496                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         9302                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         9302                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         7484                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total         7484                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       368966                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       368966                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       368966                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       368966                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2659287000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2659287000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   4452739000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4452739000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     70511500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     70511500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     45688000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     45688000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   7112026000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total   7112026000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   7112026000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total   7112026000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  10424499500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  10424499500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data    822589000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total    822589000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  11247088500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11247088500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.033316                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.033316                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.025765                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.025765                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.059164                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059164                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.047618                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.047618                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.029949                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.029949                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.029949                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.029949                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11690.715259                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11690.715259                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31469.009725                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31469.009725                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data  7580.251559                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  7580.251559                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  6104.756815                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  6104.756815                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19275.559266                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19275.559266                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19275.559266                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19275.559266                       # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks       306522                       # number of writebacks
+system.cpu0.dcache.writebacks::total           306522                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       228069                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       228069                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       141727                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       141727                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         9289                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         9289                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         7492                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total         7492                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       369796                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       369796                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       369796                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       369796                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2751577168                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2751577168                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   4491927564                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4491927564                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     72683507                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     72683507                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     51983021                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     51983021                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   7243504732                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total   7243504732                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   7243504732                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total   7243504732                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  10423590500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  10423590500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data    819778500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total    819778500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  11243369000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11243369000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.033365                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.033365                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.025777                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.025777                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.059059                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059059                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.047650                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.047650                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.029982                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.029982                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.029982                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.029982                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12064.669762                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12064.669762                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31694.225970                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31694.225970                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data  7824.685865                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  7824.685865                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  6938.470502                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  6938.470502                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19587.839598                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19587.839598                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19587.839598                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19587.839598                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
@@ -804,26 +804,26 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                     8311514                       # DTB read hits
-system.cpu1.dtb.read_misses                      3660                       # DTB read misses
-system.cpu1.dtb.write_hits                    5828200                       # DTB write hits
-system.cpu1.dtb.write_misses                     1442                       # DTB write misses
+system.cpu1.dtb.read_hits                     8311872                       # DTB read hits
+system.cpu1.dtb.read_misses                      3663                       # DTB read misses
+system.cpu1.dtb.write_hits                    5828412                       # DTB write hits
+system.cpu1.dtb.write_misses                     1436                       # DTB write misses
 system.cpu1.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
 system.cpu1.dtb.flush_entries                    1967                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   134                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                   140                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.dtb.perms_faults                      248                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                 8315174                       # DTB read accesses
-system.cpu1.dtb.write_accesses                5829642                       # DTB write accesses
+system.cpu1.dtb.read_accesses                 8315535                       # DTB read accesses
+system.cpu1.dtb.write_accesses                5829848                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         14139714                       # DTB hits
-system.cpu1.dtb.misses                           5102                       # DTB misses
-system.cpu1.dtb.accesses                     14144816                       # DTB accesses
-system.cpu1.itb.inst_hits                    32283727                       # ITB inst hits
+system.cpu1.dtb.hits                         14140284                       # DTB hits
+system.cpu1.dtb.misses                           5099                       # DTB misses
+system.cpu1.dtb.accesses                     14145383                       # DTB accesses
+system.cpu1.itb.inst_hits                    32285286                       # ITB inst hits
 system.cpu1.itb.inst_misses                      2171                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
@@ -840,79 +840,79 @@ system.cpu1.itb.domain_faults                       0                       # Nu
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                32285898                       # ITB inst accesses
-system.cpu1.itb.hits                         32283727                       # DTB hits
+system.cpu1.itb.inst_accesses                32287457                       # ITB inst accesses
+system.cpu1.itb.hits                         32285286                       # DTB hits
 system.cpu1.itb.misses                           2171                       # DTB misses
-system.cpu1.itb.accesses                     32285898                       # DTB accesses
-system.cpu1.numCycles                      2337184534                       # number of cpu cycles simulated
+system.cpu1.itb.accesses                     32287457                       # DTB accesses
+system.cpu1.numCycles                      2341739150                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   31679948                       # Number of instructions committed
-system.cpu1.committedOps                     40190899                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             36862651                       # Number of integer alu accesses
+system.cpu1.committedInsts                   31681481                       # Number of instructions committed
+system.cpu1.committedOps                     40192806                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             36864445                       # Number of integer alu accesses
 system.cpu1.num_fp_alu_accesses                  6793                       # Number of float alu accesses
-system.cpu1.num_func_calls                     962114                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      3486829                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    36862651                       # number of integer instructions
+system.cpu1.num_func_calls                     962202                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      3487066                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    36864445                       # number of integer instructions
 system.cpu1.num_fp_insts                         6793                       # number of float instructions
-system.cpu1.num_int_register_reads          210732518                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          38542658                       # number of times the integer registers were written
+system.cpu1.num_int_register_reads          210742691                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          38544620                       # number of times the integer registers were written
 system.cpu1.num_fp_register_reads                4535                       # number of times the floating registers were read
 system.cpu1.num_fp_register_writes               2260                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                     14677413                       # number of memory refs
-system.cpu1.num_load_insts                    8633313                       # Number of load instructions
-system.cpu1.num_store_insts                   6044100                       # Number of store instructions
-system.cpu1.num_idle_cycles              1859139408.190032                       # Number of idle cycles
-system.cpu1.num_busy_cycles              478045125.809968                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.204539                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.795461                       # Percentage of idle cycles
+system.cpu1.num_mem_refs                     14678127                       # number of memory refs
+system.cpu1.num_load_insts                    8633777                       # Number of load instructions
+system.cpu1.num_store_insts                   6044350                       # Number of store instructions
+system.cpu1.num_idle_cycles              1858809543.114650                       # Number of idle cycles
+system.cpu1.num_busy_cycles              482929606.885350                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.206227                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.793773                       # Percentage of idle cycles
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                   43902                       # number of quiesce instructions executed
-system.cpu1.icache.replacements                454250                       # number of replacements
-system.cpu1.icache.tagsinuse               478.426272                       # Cycle average of tags in use
-system.cpu1.icache.total_refs                31828961                       # Total number of references to valid blocks.
-system.cpu1.icache.sampled_refs                454762                       # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs                 69.990371                       # Average number of references to valid blocks.
-system.cpu1.icache.warmup_cycle           91827158000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::cpu1.inst   478.426272                       # Average occupied blocks per requestor
-system.cpu1.icache.occ_percent::cpu1.inst     0.934426                       # Average percentage of cache occupancy
-system.cpu1.icache.occ_percent::total        0.934426                       # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst     31828961                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total       31828961                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst     31828961                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total        31828961                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst     31828961                       # number of overall hits
-system.cpu1.icache.overall_hits::total       31828961                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       454762                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       454762                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       454762                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        454762                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       454762                       # number of overall misses
-system.cpu1.icache.overall_misses::total       454762                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   6579254500                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   6579254500                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   6579254500                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   6579254500                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   6579254500                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   6579254500                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst     32283723                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total     32283723                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst     32283723                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total     32283723                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst     32283723                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total     32283723                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.014086                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.014086                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.014086                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.014086                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.014086                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.014086                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14467.467598                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 14467.467598                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14467.467598                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 14467.467598                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14467.467598                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 14467.467598                       # average overall miss latency
+system.cpu1.kern.inst.quiesce                   43917                       # number of quiesce instructions executed
+system.cpu1.icache.replacements                454429                       # number of replacements
+system.cpu1.icache.tagsinuse               478.358537                       # Cycle average of tags in use
+system.cpu1.icache.total_refs                31830341                       # Total number of references to valid blocks.
+system.cpu1.icache.sampled_refs                454941                       # Sample count of references to valid blocks.
+system.cpu1.icache.avg_refs                 69.965866                       # Average number of references to valid blocks.
+system.cpu1.icache.warmup_cycle           92993102000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.occ_blocks::cpu1.inst   478.358537                       # Average occupied blocks per requestor
+system.cpu1.icache.occ_percent::cpu1.inst     0.934294                       # Average percentage of cache occupancy
+system.cpu1.icache.occ_percent::total        0.934294                       # Average percentage of cache occupancy
+system.cpu1.icache.ReadReq_hits::cpu1.inst     31830341                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total       31830341                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst     31830341                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total        31830341                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst     31830341                       # number of overall hits
+system.cpu1.icache.overall_hits::total       31830341                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       454941                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       454941                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       454941                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        454941                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       454941                       # number of overall misses
+system.cpu1.icache.overall_misses::total       454941                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   6716097000                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   6716097000                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   6716097000                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   6716097000                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   6716097000                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   6716097000                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst     32285282                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total     32285282                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst     32285282                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total     32285282                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst     32285282                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total     32285282                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.014091                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.014091                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.014091                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.014091                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.014091                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.014091                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14762.567014                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 14762.567014                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14762.567014                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 14762.567014                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14762.567014                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 14762.567014                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -921,122 +921,122 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.writebacks::writebacks        23283                       # number of writebacks
-system.cpu1.icache.writebacks::total            23283                       # number of writebacks
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       454762                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       454762                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       454762                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       454762                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       454762                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       454762                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   5213754000                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   5213754000                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   5213754000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   5213754000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   5213754000                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   5213754000                       # number of overall MSHR miss cycles
+system.cpu1.icache.writebacks::writebacks        23436                       # number of writebacks
+system.cpu1.icache.writebacks::total            23436                       # number of writebacks
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       454941                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       454941                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       454941                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       454941                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       454941                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       454941                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   5350372502                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   5350372502                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   5350372502                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   5350372502                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   5350372502                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   5350372502                       # number of overall MSHR miss cycles
 system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      5250000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      5250000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      5250000                       # number of overall MSHR uncacheable cycles
 system.cpu1.icache.overall_mshr_uncacheable_latency::total      5250000                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.014086                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.014086                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.014086                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.014086                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.014086                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.014086                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11464.796971                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11464.796971                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11464.796971                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 11464.796971                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11464.796971                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 11464.796971                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.014091                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.014091                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.014091                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.014091                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.014091                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.014091                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11760.585443                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11760.585443                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11760.585443                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 11760.585443                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11760.585443                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 11760.585443                       # average overall mshr miss latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.replacements                292077                       # number of replacements
-system.cpu1.dcache.tagsinuse               472.260521                       # Cycle average of tags in use
-system.cpu1.dcache.total_refs                11962886                       # Total number of references to valid blocks.
-system.cpu1.dcache.sampled_refs                292453                       # Sample count of references to valid blocks.
-system.cpu1.dcache.avg_refs                 40.905328                       # Average number of references to valid blocks.
-system.cpu1.dcache.warmup_cycle           83467733000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::cpu1.data   472.260521                       # Average occupied blocks per requestor
-system.cpu1.dcache.occ_percent::cpu1.data     0.922384                       # Average percentage of cache occupancy
-system.cpu1.dcache.occ_percent::total        0.922384                       # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::cpu1.data      6946947                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        6946947                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      4827784                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       4827784                       # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        81815                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        81815                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        82770                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        82770                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data     11774731                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total        11774731                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data     11774731                       # number of overall hits
-system.cpu1.dcache.overall_hits::total       11774731                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       170577                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       170577                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data       150060                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total       150060                       # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        11061                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total        11061                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data        10037                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total        10037                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       320637                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        320637                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       320637                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       320637                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2293338000                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   2293338000                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   5119779000                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total   5119779000                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    102150000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total    102150000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     75382000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total     75382000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data   7413117000                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total   7413117000                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data   7413117000                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total   7413117000                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      7117524                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      7117524                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      4977844                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      4977844                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        92876                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        92876                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        92807                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        92807                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data     12095368                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total     12095368                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data     12095368                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total     12095368                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.023966                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.023966                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.030146                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.030146                       # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.119094                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.119094                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.108149                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.108149                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.026509                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.026509                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.026509                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.026509                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13444.591006                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 13444.591006                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34118.212715                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 34118.212715                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  9235.150529                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  9235.150529                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  7510.411478                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  7510.411478                       # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23119.967440                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 23119.967440                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23119.967440                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 23119.967440                       # average overall miss latency
+system.cpu1.dcache.replacements                292285                       # number of replacements
+system.cpu1.dcache.tagsinuse               472.233445                       # Cycle average of tags in use
+system.cpu1.dcache.total_refs                11962904                       # Total number of references to valid blocks.
+system.cpu1.dcache.sampled_refs                292625                       # Sample count of references to valid blocks.
+system.cpu1.dcache.avg_refs                 40.881346                       # Average number of references to valid blocks.
+system.cpu1.dcache.warmup_cycle           84136899000                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.occ_blocks::cpu1.data   472.233445                       # Average occupied blocks per requestor
+system.cpu1.dcache.occ_percent::cpu1.data     0.922331                       # Average percentage of cache occupancy
+system.cpu1.dcache.occ_percent::total        0.922331                       # Average percentage of cache occupancy
+system.cpu1.dcache.ReadReq_hits::cpu1.data      6947233                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        6947233                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      4827936                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       4827936                       # number of WriteReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        81814                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        81814                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        82788                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        82788                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data     11775169                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total        11775169                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data     11775169                       # number of overall hits
+system.cpu1.dcache.overall_hits::total       11775169                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       170612                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       170612                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data       150091                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total       150091                       # number of WriteReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        11098                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total        11098                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data        10047                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total        10047                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       320703                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        320703                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       320703                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       320703                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2368289000                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   2368289000                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   5141096000                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total   5141096000                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    106270500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total    106270500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     87322000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total     87322000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data   7509385000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total   7509385000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data   7509385000                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total   7509385000                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      7117845                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      7117845                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      4978027                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      4978027                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        92912                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        92912                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        92835                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        92835                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data     12095872                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total     12095872                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data     12095872                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total     12095872                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.023970                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.023970                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.030151                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.030151                       # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.119446                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.119446                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.108224                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.108224                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.026513                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.026513                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.026513                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.026513                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13881.139662                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 13881.139662                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34253.193063                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 34253.193063                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  9575.644260                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  9575.644260                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  8691.350652                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  8691.350652                       # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23415.387446                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 23415.387446                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23415.387446                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 23415.387446                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1045,66 +1045,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks       265856                       # number of writebacks
-system.cpu1.dcache.writebacks::total           265856                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       170577                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       170577                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       150060                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total       150060                       # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data        11061                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total        11061                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        10033                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total        10033                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       320637                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       320637                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       320637                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       320637                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1781497000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1781497000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   4669562000                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   4669562000                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     68967000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     68967000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     45286000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     45286000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data         1000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total         1000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   6451059000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   6451059000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   6451059000                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   6451059000                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 136551200000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 136551200000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  39714194000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total  39714194000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 176265394000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 176265394000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.023966                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.023966                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.030146                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.030146                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.119094                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.119094                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.108106                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.108106                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.026509                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.026509                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.026509                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.026509                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10443.946136                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10443.946136                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31117.966147                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31117.966147                       # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  6235.150529                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  6235.150529                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  4513.704774                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  4513.704774                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20119.508977                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20119.508977                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20119.508977                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20119.508977                       # average overall mshr miss latency
+system.cpu1.dcache.writebacks::writebacks       266082                       # number of writebacks
+system.cpu1.dcache.writebacks::total           266082                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       170612                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total       170612                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       150091                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total       150091                       # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data        11098                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total        11098                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        10038                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total        10038                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       320703                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       320703                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       320703                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       320703                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1855824122                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1855824122                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   4690597670                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   4690597670                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     72957002                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     72957002                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     57198010                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     57198010                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   6546421792                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   6546421792                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   6546421792                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   6546421792                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 136480079000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 136480079000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  39677118500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total  39677118500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 176157197500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 176157197500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.023970                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.023970                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.030151                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.030151                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.119446                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.119446                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.108127                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.108127                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.026513                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.026513                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.026513                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.026513                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10877.453649                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10877.453649                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31251.691774                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31251.691774                       # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  6573.887367                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  6573.887367                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  5698.148037                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  5698.148037                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20412.723897                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20412.723897                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20412.723897                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20412.723897                       # average overall mshr miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1126,10 +1122,10 @@ system.iocache.avg_blocked_cycles::no_mshrs          nan                       #
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 550273882646                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 550273882646                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 550273882646                       # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 550273882646                       # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 550047772786                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 550047772786                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 550047772786                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 550047772786                       # number of overall MSHR uncacheable cycles
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
index d41ee2fc6..b0e885f8a 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
@@ -20,7 +20,7 @@ kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 load_addr_mask=268435455
 machine_type=RealView_PBX
 mem_mode=timing
-memories=system.physmem system.realview.nvmem
+memories=system.realview.nvmem system.physmem
 midr_regval=890224640
 multi_proc=true
 num_work_ids=16
@@ -187,7 +187,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side
 slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
 
@@ -248,7 +248,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 default=system.membus.badaddr_responder.pio
 master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
 slave=system.system_port system.iocache.mem_side system.l2c.mem_side
@@ -661,7 +661,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.l2c.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
index 4f563f8f5..a0fa03c1d 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:10:14
-gem5 started Jun 29 2012 00:36:57
+gem5 compiled Jul  2 2012 09:08:16
+gem5 started Jul  2 2012 15:20:44
 gem5 executing on zizzer
 command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 info: Using bootloader at address 0x80000000
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 2591087067000 because m5_exit instruction encountered
+Exiting @ tick 2593402521000 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
index f1beadd55..5473fafb1 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
@@ -1,54 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.591087                       # Number of seconds simulated
-sim_ticks                                2591087067000                       # Number of ticks simulated
-final_tick                               2591087067000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.593403                       # Number of seconds simulated
+sim_ticks                                2593402521000                       # Number of ticks simulated
+final_tick                               2593402521000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 814871                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1040723                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            35675794467                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 385812                       # Number of bytes of host memory used
-host_seconds                                    72.63                       # Real time elapsed on the host
-sim_insts                                    59182970                       # Number of instructions simulated
-sim_ops                                      75586355                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::realview.clcd    122683392                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker          320                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker          192                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst            706144                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9051344                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            132441392                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       706144                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          706144                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      3678592                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu.data        3016072                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6694664                       # Number of bytes written to this memory
-system.physmem.num_reads::realview.clcd      15335424                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker            5                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker            3                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              17236                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             141461                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total              15494129                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           57478                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu.data            754018                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               811496                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd        47348232                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker            124                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker             74                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               272528                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3493261                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                51114219                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          272528                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             272528                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1419710                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data             1164018                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2583728                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1419710                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd       47348232                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker           124                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker            74                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              272528                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             4657279                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               53697947                       # Total bandwidth to/from this memory (bytes/s)
+host_inst_rate                                 766927                       # Simulator instruction rate (inst/s)
+host_op_rate                                   979485                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            33608362861                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 384708                       # Number of bytes of host memory used
+host_seconds                                    77.17                       # Real time elapsed on the host
+sim_insts                                    59180230                       # Number of instructions simulated
+sim_ops                                      75582343                       # Number of ops (including micro ops) simulated
 system.realview.nvmem.bytes_read::cpu.inst           20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_inst_read::cpu.inst           20                       # Number of instructions bytes read from this memory
@@ -61,141 +23,179 @@ system.realview.nvmem.bw_inst_read::cpu.inst            8
 system.realview.nvmem.bw_inst_read::total            8                       # Instruction read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu.inst            8                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total               8                       # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements                         61946                       # number of replacements
-system.l2c.tagsinuse                     50741.194054                       # Cycle average of tags in use
-system.l2c.total_refs                         1730603                       # Total number of references to valid blocks.
-system.l2c.sampled_refs                        127327                       # Sample count of references to valid blocks.
-system.l2c.avg_refs                         13.591799                       # Average number of references to valid blocks.
-system.l2c.warmup_cycle                  2543210574000                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks        37737.574743                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.dtb.walker        3.884961                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.itb.walker        0.001325                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.inst           6978.831431                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.data           6020.901593                       # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks           0.575830                       # Average percentage of cache occupancy
+system.physmem.bytes_read::realview.clcd    122683392                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker          320                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst            704224                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9067536                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            132455600                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       704224                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          704224                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      3695808                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu.data        3016072                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           6711880                       # Number of bytes written to this memory
+system.physmem.num_reads::realview.clcd      15335424                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker            5                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker            2                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              17206                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             141714                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total              15494351                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           57747                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu.data            754018                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               811765                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        47305958                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker            123                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker             49                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               271544                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3496386                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                51074062                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          271544                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             271544                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1425081                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data             1162979                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2588059                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1425081                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       47305958                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker           123                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker            49                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              271544                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             4659365                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               53662121                       # Total bandwidth to/from this memory (bytes/s)
+system.l2c.replacements                         62163                       # number of replacements
+system.l2c.tagsinuse                     51413.022429                       # Cycle average of tags in use
+system.l2c.total_refs                         1730961                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                        127547                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                         13.571162                       # Average number of references to valid blocks.
+system.l2c.warmup_cycle                  2544159444000                       # Cycle when the warmup percentage was hit.
+system.l2c.occ_blocks::writebacks        38018.047073                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.dtb.walker        3.884744                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.itb.walker        0.000558                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.inst           7004.232123                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.data           6386.857931                       # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks           0.580109                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu.dtb.walker       0.000059                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu.itb.walker       0.000000                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.inst             0.106489                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.data             0.091872                       # Average percentage of cache occupancy
-system.l2c.occ_percent::total                0.774249                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu.dtb.walker          8734                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.itb.walker          3552                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.inst              843850                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.data              367763                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1223899                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          646100                       # number of Writeback hits
-system.l2c.Writeback_hits::total               646100                       # number of Writeback hits
+system.l2c.occ_percent::cpu.inst             0.106876                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.data             0.097456                       # Average percentage of cache occupancy
+system.l2c.occ_percent::total                0.784500                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu.dtb.walker          8759                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.itb.walker          3544                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.inst              843511                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.data              367799                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1223613                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          646378                       # number of Writeback hits
+system.l2c.Writeback_hits::total               646378                       # number of Writeback hits
 system.l2c.UpgradeReq_hits::cpu.data               26                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::total                  26                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu.data            114412                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               114412                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu.dtb.walker           8734                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.itb.walker           3552                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.inst               843850                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.data               482175                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1338311                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu.dtb.walker          8734                       # number of overall hits
-system.l2c.overall_hits::cpu.itb.walker          3552                       # number of overall hits
-system.l2c.overall_hits::cpu.inst              843850                       # number of overall hits
-system.l2c.overall_hits::cpu.data              482175                       # number of overall hits
-system.l2c.overall_hits::total                1338311                       # number of overall hits
+system.l2c.ReadExReq_hits::cpu.data            114402                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               114402                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu.dtb.walker           8759                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.itb.walker           3544                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.inst               843511                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.data               482201                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 1338015                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu.dtb.walker          8759                       # number of overall hits
+system.l2c.overall_hits::cpu.itb.walker          3544                       # number of overall hits
+system.l2c.overall_hits::cpu.inst              843511                       # number of overall hits
+system.l2c.overall_hits::cpu.data              482201                       # number of overall hits
+system.l2c.overall_hits::total                1338015                       # number of overall hits
 system.l2c.ReadReq_misses::cpu.dtb.walker            5                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu.itb.walker            3                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu.inst             10620                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu.data              9861                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                20489                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu.data           2867                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              2867                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu.data          133208                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             133208                       # number of ReadExReq misses
+system.l2c.ReadReq_misses::cpu.itb.walker            2                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.inst             10590                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.data             10247                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                20844                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu.data           2881                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              2881                       # number of UpgradeReq misses
+system.l2c.ReadExReq_misses::cpu.data          133061                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             133061                       # number of ReadExReq misses
 system.l2c.demand_misses::cpu.dtb.walker            5                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu.itb.walker            3                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu.inst              10620                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu.data             143069                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                153697                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.itb.walker            2                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.inst              10590                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.data             143308                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                153905                       # number of demand (read+write) misses
 system.l2c.overall_misses::cpu.dtb.walker            5                       # number of overall misses
-system.l2c.overall_misses::cpu.itb.walker            3                       # number of overall misses
-system.l2c.overall_misses::cpu.inst             10620                       # number of overall misses
-system.l2c.overall_misses::cpu.data            143069                       # number of overall misses
-system.l2c.overall_misses::total               153697                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu.dtb.walker       260000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu.itb.walker       156000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu.inst    554111000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu.data    513428000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total     1067955000                       # number of ReadReq miss cycles
+system.l2c.overall_misses::cpu.itb.walker            2                       # number of overall misses
+system.l2c.overall_misses::cpu.inst             10590                       # number of overall misses
+system.l2c.overall_misses::cpu.data            143308                       # number of overall misses
+system.l2c.overall_misses::total               153905                       # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu.dtb.walker       260500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.itb.walker       104000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.inst    552215500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.data    533568500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total     1086148500                       # number of ReadReq miss cycles
 system.l2c.UpgradeReq_miss_latency::cpu.data      1040000                       # number of UpgradeReq miss cycles
 system.l2c.UpgradeReq_miss_latency::total      1040000                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu.data   6945514000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   6945514000                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu.dtb.walker       260000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.itb.walker       156000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.inst    554111000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.data   7458942000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total      8013469000                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu.dtb.walker       260000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu.itb.walker       156000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu.inst    554111000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu.data   7458942000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total     8013469000                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu.dtb.walker         8739                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.itb.walker         3555                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.inst          854470                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.data          377624                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            1244388                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       646100                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           646100                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu.data         2893                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            2893                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu.data        247620                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           247620                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu.dtb.walker         8739                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.itb.walker         3555                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.inst           854470                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.data           625244                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             1492008                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu.dtb.walker         8739                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.itb.walker         3555                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.inst          854470                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.data          625244                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            1492008                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu.dtb.walker     0.000572                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.itb.walker     0.000844                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.inst       0.012429                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.data       0.026113                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.016465                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu.data     0.991013                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.991013                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu.data     0.537953                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.537953                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu.dtb.walker     0.000572                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.itb.walker     0.000844                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.inst        0.012429                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.data        0.228821                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.103014                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu.dtb.walker     0.000572                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.itb.walker     0.000844                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.inst       0.012429                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.data       0.228821                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.103014                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker        52000                       # average ReadReq miss latency
+system.l2c.ReadExReq_miss_latency::cpu.data   6924755000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   6924755000                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu.dtb.walker       260500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.itb.walker       104000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.inst    552215500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.data   7458323500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total      8010903500                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu.dtb.walker       260500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu.itb.walker       104000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu.inst    552215500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu.data   7458323500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total     8010903500                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu.dtb.walker         8764                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.itb.walker         3546                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.inst          854101                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.data          378046                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            1244457                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       646378                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           646378                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu.data         2907                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            2907                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu.data        247463                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           247463                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu.dtb.walker         8764                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.itb.walker         3546                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.inst           854101                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.data           625509                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             1491920                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu.dtb.walker         8764                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.itb.walker         3546                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.inst          854101                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.data          625509                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            1491920                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu.dtb.walker     0.000571                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.itb.walker     0.000564                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.inst       0.012399                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.data       0.027105                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.016749                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu.data     0.991056                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.991056                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu.data     0.537701                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.537701                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu.dtb.walker     0.000571                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.itb.walker     0.000564                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.inst        0.012399                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.data        0.229106                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.103159                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu.dtb.walker     0.000571                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.itb.walker     0.000564                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.inst       0.012399                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.data       0.229106                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.103159                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker        52100                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker        52000                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu.inst 52176.177024                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu.data 52066.524693                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 52123.334472                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu.data   362.748518                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total   362.748518                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu.data 52140.366945                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 52140.366945                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu.dtb.walker        52000                       # average overall miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.inst 52144.995279                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.data 52070.703621                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 52108.448474                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu.data   360.985769                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total   360.985769                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu.data 52041.958200                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 52041.958200                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu.dtb.walker        52100                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu.itb.walker        52000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu.inst 52176.177024                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu.data 52135.277384                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 52138.096384                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.dtb.walker        52000                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.inst 52144.995279                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.data 52044.013593                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 52050.963257                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.dtb.walker        52100                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu.itb.walker        52000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.inst 52176.177024                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.data 52135.277384                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 52138.096384                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.inst 52144.995279                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.data 52044.013593                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 52050.963257                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -204,92 +204,92 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               57478                       # number of writebacks
-system.l2c.writebacks::total                    57478                       # number of writebacks
+system.l2c.writebacks::writebacks               57747                       # number of writebacks
+system.l2c.writebacks::total                    57747                       # number of writebacks
 system.l2c.ReadReq_mshr_misses::cpu.dtb.walker            5                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu.itb.walker            3                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu.inst        10620                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu.data         9861                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total           20489                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu.data         2867                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total         2867                       # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu.data       133208                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        133208                       # number of ReadExReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.itb.walker            2                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.inst        10590                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.data        10247                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total           20844                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu.data         2881                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total         2881                       # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu.data       133061                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        133061                       # number of ReadExReq MSHR misses
 system.l2c.demand_mshr_misses::cpu.dtb.walker            5                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu.itb.walker            3                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu.inst         10620                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu.data        143069                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           153697                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu.itb.walker            2                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu.inst         10590                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu.data        143308                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           153905                       # number of demand (read+write) MSHR misses
 system.l2c.overall_mshr_misses::cpu.dtb.walker            5                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu.itb.walker            3                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu.inst        10620                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu.data       143069                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          153697                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu.itb.walker            2                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu.inst        10590                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu.data       143308                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          153905                       # number of overall MSHR misses
 system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker       200000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker       120000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu.inst    426667000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu.data    395096000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total    822083000                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu.data    114844000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total    114844000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu.data   5347018000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   5347018000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker        80000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.inst    425129000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.data    410601000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total    836010000                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu.data    115527000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    115527000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu.data   5328003000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   5328003000                       # number of ReadExReq MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu.dtb.walker       200000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.itb.walker       120000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.inst    426667000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.data   5742114000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total   6169101000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.itb.walker        80000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.inst    425129000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.data   5738604000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   6164013000                       # number of demand (read+write) MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu.dtb.walker       200000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.itb.walker       120000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.inst    426667000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.data   5742114000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total   6169101000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.itb.walker        80000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.inst    425129000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.data   5738604000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   6164013000                       # number of overall MSHR miss cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst    264840000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131542089000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 131806929000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data  31206790500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total  31206790500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131438638000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 131703478000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data  31164555000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total  31164555000                       # number of WriteReq MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu.inst    264840000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu.data 162748879500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 163013719500                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000572                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000844                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.012429                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.026113                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.016465                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.991013                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.991013                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.537953                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.537953                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu.dtb.walker     0.000572                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu.itb.walker     0.000844                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu.inst     0.012429                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu.data     0.228821                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.103014                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu.dtb.walker     0.000572                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu.itb.walker     0.000844                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu.inst     0.012429                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu.data     0.228821                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.103014                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_uncacheable_latency::cpu.data 162603193000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 162868033000                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000571                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000564                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.012399                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.027105                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.016749                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.991056                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.991056                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.537701                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.537701                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu.dtb.walker     0.000571                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.itb.walker     0.000564                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.inst     0.012399                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.data     0.229106                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.103159                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu.dtb.walker     0.000571                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.itb.walker     0.000564                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.inst     0.012399                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.data     0.229106                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.103159                       # mshr miss rate for overall accesses
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker        40000                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        40000                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40175.800377                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40066.524693                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 40123.139245                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40057.202651                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40057.202651                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40140.366945                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 40140.366945                       # average ReadExReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40144.381492                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40070.362057                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 40107.944732                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40099.618188                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40099.618188                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40041.807893                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 40041.807893                       # average ReadExReq mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker        40000                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker        40000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40175.800377                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.data 40135.277384                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 40138.070359                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40144.381492                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.data 40043.849611                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 40050.765082                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker        40000                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker        40000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40175.800377                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.data 40135.277384                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 40138.070359                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40144.381492                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.data 40043.849611                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 40050.765082                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -307,26 +307,26 @@ system.cf0.dma_write_bytes                          0                       # Nu
 system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     14996145                       # DTB read hits
-system.cpu.dtb.read_misses                       7343                       # DTB read misses
-system.cpu.dtb.write_hits                    11231074                       # DTB write hits
-system.cpu.dtb.write_misses                      2209                       # DTB write misses
+system.cpu.dtb.read_hits                     14995175                       # DTB read hits
+system.cpu.dtb.read_misses                       7360                       # DTB read misses
+system.cpu.dtb.write_hits                    11229808                       # DTB write hits
+system.cpu.dtb.write_misses                      2205                       # DTB write misses
 system.cpu.dtb.flush_tlb                            2                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
 system.cpu.dtb.flush_entries                     3488                       # Number of entries that have been flushed from TLB
 system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                    184                       # Number of TLB faults due to prefetch
+system.cpu.dtb.prefetch_faults                    182                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
 system.cpu.dtb.perms_faults                       452                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 15003488                       # DTB read accesses
-system.cpu.dtb.write_accesses                11233283                       # DTB write accesses
+system.cpu.dtb.read_accesses                 15002535                       # DTB read accesses
+system.cpu.dtb.write_accesses                11232013                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          26227219                       # DTB hits
-system.cpu.dtb.misses                            9552                       # DTB misses
-system.cpu.dtb.accesses                      26236771                       # DTB accesses
-system.cpu.itb.inst_hits                     60464772                       # ITB inst hits
+system.cpu.dtb.hits                          26224983                       # DTB hits
+system.cpu.dtb.misses                            9565                       # DTB misses
+system.cpu.dtb.accesses                      26234548                       # DTB accesses
+system.cpu.itb.inst_hits                     60461981                       # ITB inst hits
 system.cpu.itb.inst_misses                       4471                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
@@ -343,79 +343,79 @@ system.cpu.itb.domain_faults                        0                       # Nu
 system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                 60469243                       # ITB inst accesses
-system.cpu.itb.hits                          60464772                       # DTB hits
+system.cpu.itb.inst_accesses                 60466452                       # ITB inst accesses
+system.cpu.itb.hits                          60461981                       # DTB hits
 system.cpu.itb.misses                            4471                       # DTB misses
-system.cpu.itb.accesses                      60469243                       # DTB accesses
-system.cpu.numCycles                       5182174134                       # number of cpu cycles simulated
+system.cpu.itb.accesses                      60466452                       # DTB accesses
+system.cpu.numCycles                       5186805042                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                    59182970                       # Number of instructions committed
-system.cpu.committedOps                      75586355                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses              68355817                       # Number of integer alu accesses
+system.cpu.committedInsts                    59180230                       # Number of instructions committed
+system.cpu.committedOps                      75582343                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses              68351784                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                  10269                       # Number of float alu accesses
-system.cpu.num_func_calls                     2139775                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts      7653714                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                     68355817                       # number of integer instructions
+system.cpu.num_func_calls                     2139562                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts      7653493                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                     68351784                       # number of integer instructions
 system.cpu.num_fp_insts                         10269                       # number of float instructions
-system.cpu.num_int_register_reads           391424329                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           73137723                       # number of times the integer registers were written
+system.cpu.num_int_register_reads           391402858                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           73137157                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                 7493                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                2780                       # number of times the floating registers were written
-system.cpu.num_mem_refs                      27394520                       # number of memory refs
-system.cpu.num_load_insts                    15660068                       # Number of load instructions
-system.cpu.num_store_insts                   11734452                       # Number of store instructions
-system.cpu.num_idle_cycles               4574883884.570234                       # Number of idle cycles
-system.cpu.num_busy_cycles               607290249.429766                       # Number of busy cycles
-system.cpu.not_idle_fraction                 0.117188                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.882812                       # Percentage of idle cycles
+system.cpu.num_mem_refs                      27392171                       # number of memory refs
+system.cpu.num_load_insts                    15659029                       # Number of load instructions
+system.cpu.num_store_insts                   11733142                       # Number of store instructions
+system.cpu.num_idle_cycles               4570470450.554237                       # Number of idle cycles
+system.cpu.num_busy_cycles               616334591.445762                       # Number of busy cycles
+system.cpu.not_idle_fraction                 0.118827                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.881173                       # Percentage of idle cycles
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                    82997                       # number of quiesce instructions executed
-system.cpu.icache.replacements                 855597                       # number of replacements
-system.cpu.icache.tagsinuse                510.944278                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 59608663                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                 856109                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                  69.627422                       # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle            18496284000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     510.944278                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.997938                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.997938                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst     59608663                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        59608663                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      59608663                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         59608663                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     59608663                       # number of overall hits
-system.cpu.icache.overall_hits::total        59608663                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       856109                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        856109                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       856109                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         856109                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       856109                       # number of overall misses
-system.cpu.icache.overall_misses::total        856109                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  12422495000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  12422495000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  12422495000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  12422495000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  12422495000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  12422495000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     60464772                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     60464772                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     60464772                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     60464772                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     60464772                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     60464772                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.014159                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.014159                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.014159                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.014159                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.014159                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.014159                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14510.412810                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 14510.412810                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 14510.412810                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 14510.412810                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 14510.412810                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 14510.412810                       # average overall miss latency
+system.cpu.kern.inst.quiesce                    82989                       # number of quiesce instructions executed
+system.cpu.icache.replacements                 855209                       # number of replacements
+system.cpu.icache.tagsinuse                510.928777                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 59606260                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                 855721                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                  69.656185                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle            18855254000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::cpu.inst     510.928777                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.997908                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.997908                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst     59606260                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        59606260                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      59606260                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         59606260                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     59606260                       # number of overall hits
+system.cpu.icache.overall_hits::total        59606260                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       855721                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        855721                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       855721                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         855721                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       855721                       # number of overall misses
+system.cpu.icache.overall_misses::total        855721                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  12570164500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  12570164500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  12570164500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  12570164500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  12570164500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  12570164500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     60461981                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     60461981                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     60461981                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     60461981                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     60461981                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     60461981                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.014153                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.014153                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.014153                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.014153                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.014153                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.014153                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14689.559448                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 14689.559448                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 14689.559448                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 14689.559448                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 14689.559448                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 14689.559448                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -424,114 +424,114 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks        50189                       # number of writebacks
-system.cpu.icache.writebacks::total             50189                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       856109                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       856109                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       856109                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       856109                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       856109                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       856109                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   9851777000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total   9851777000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst   9851777000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total   9851777000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst   9851777000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total   9851777000                       # number of overall MSHR miss cycles
+system.cpu.icache.writebacks::writebacks        50294                       # number of writebacks
+system.cpu.icache.writebacks::total             50294                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       855721                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       855721                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       855721                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       855721                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       855721                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       855721                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  10001095500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  10001095500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  10001095500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  10001095500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  10001095500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  10001095500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    350913000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    350913000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    350913000                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_latency::total    350913000                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.014159                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.014159                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.014159                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.014159                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.014159                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.014159                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11507.619941                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11507.619941                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11507.619941                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11507.619941                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11507.619941                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11507.619941                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.014153                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.014153                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.014153                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.014153                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.014153                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.014153                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11687.332086                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11687.332086                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11687.332086                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11687.332086                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11687.332086                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11687.332086                       # average overall mshr miss latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                 627131                       # number of replacements
-system.cpu.dcache.tagsinuse                511.875575                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 23655898                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                 627643                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  37.690053                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              660309000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data     511.875575                       # Average occupied blocks per requestor
+system.cpu.dcache.replacements                 627384                       # number of replacements
+system.cpu.dcache.tagsinuse                511.875582                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 23653412                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 627896                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  37.670907                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              661351000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data     511.875582                       # Average occupied blocks per requestor
 system.cpu.dcache.occ_percent::cpu.data      0.999757                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_percent::total         0.999757                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data     13195741                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        13195741                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      9973243                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        9973243                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       236320                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       236320                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       247701                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       247701                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      23168984                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         23168984                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     23168984                       # number of overall hits
-system.cpu.dcache.overall_hits::total        23168984                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       368641                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        368641                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       250513                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       250513                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        11382                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        11382                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data       619154                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         619154                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       619154                       # number of overall misses
-system.cpu.dcache.overall_misses::total        619154                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   5550266500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   5550266500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   9238505500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   9238505500                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    165952500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    165952500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  14788772000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  14788772000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  14788772000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  14788772000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     13564382                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     13564382                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     10223756                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     10223756                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       247702                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       247702                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       247701                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       247701                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     23788138                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     23788138                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     23788138                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     23788138                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.027177                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.027177                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.024503                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.024503                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.045950                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.045950                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.026028                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.026028                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.026028                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.026028                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15056.020627                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 15056.020627                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36878.347631                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 36878.347631                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14580.258303                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14580.258303                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 23885.450146                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 23885.450146                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 23885.450146                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 23885.450146                       # average overall miss latency
+system.cpu.dcache.ReadReq_hits::cpu.data     13194595                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        13194595                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      9972161                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        9972161                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       236089                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       236089                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       247660                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       247660                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      23166756                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         23166756                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     23166756                       # number of overall hits
+system.cpu.dcache.overall_hits::total        23166756                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       368861                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        368861                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       250370                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       250370                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        11572                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        11572                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data       619231                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         619231                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       619231                       # number of overall misses
+system.cpu.dcache.overall_misses::total        619231                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   5722405000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   5722405000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   9232056000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   9232056000                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    172133500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    172133500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  14954461000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  14954461000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  14954461000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  14954461000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     13563456                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     13563456                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     10222531                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     10222531                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       247661                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       247661                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       247660                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       247660                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     23785987                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     23785987                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     23785987                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     23785987                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.027195                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.027195                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.024492                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.024492                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.046725                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.046725                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.026033                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.026033                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.026033                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.026033                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15513.716549                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 15513.716549                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36873.650997                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 36873.650997                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        14875                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        14875                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 24150.052242                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 24150.052242                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 24150.052242                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 24150.052242                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -540,54 +540,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       595911                       # number of writebacks
-system.cpu.dcache.writebacks::total            595911                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       368641                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       368641                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       250513                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       250513                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        11382                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total        11382                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       619154                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       619154                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       619154                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       619154                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   4444216000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   4444216000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8486921500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   8486921500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    131806500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    131806500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  12931137500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  12931137500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  12931137500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  12931137500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 146935431000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 146935431000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data  40367480000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  40367480000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 187302911000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 187302911000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.027177                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.027177                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.024503                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.024503                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.045950                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.045950                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.026028                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.026028                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.026028                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.026028                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12055.674762                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12055.674762                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33878.167999                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33878.167999                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11580.258303                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11580.258303                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20885.171541                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20885.171541                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20885.171541                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 20885.171541                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks       596084                       # number of writebacks
+system.cpu.dcache.writebacks::total            596084                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       368861                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       368861                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       250370                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       250370                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        11572                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total        11572                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       619231                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       619231                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       619231                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       619231                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   4614667500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   4614667500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8480868000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   8480868000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    137416000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    137416000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  13095535500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  13095535500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  13095535500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  13095535500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 146835601000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 146835601000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data  40324843500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  40324843500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 187160444500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 187160444500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.027195                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.027195                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.024492                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.024492                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.046725                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.046725                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.026033                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.026033                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.026033                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.026033                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12510.586644                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12510.586644                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33873.339458                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33873.339458                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11874.870377                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11874.870377                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21148.061870                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 21148.061870                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21148.061870                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 21148.061870                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -609,10 +609,10 @@ system.iocache.avg_blocked_cycles::no_mshrs          nan                       #
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1341944663355                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1341944663355                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1341944663355                       # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1341944663355                       # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1341484384445                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1341484384445                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1341484384445                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1341484384445                       # number of overall MSHR uncacheable cycles
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
index 8437cb6eb..04a12f8a0 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
@@ -604,7 +604,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=true
-width=64
+width=8
 default=system.pc.pciconfig.pio
 master=system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
 slave=system.bridge.master system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master
@@ -666,7 +666,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 default=system.membus.badaddr_responder.pio
 master=system.physmem.port[0] system.bridge.slave system.cpu.interrupts.pio system.cpu.interrupts.int_slave
 slave=system.apicbridge.master system.system_port system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.int_master
@@ -1146,7 +1146,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.l2c.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walker_cache.mem_side system.cpu.dtb_walker_cache.mem_side
 
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
index d9a666d01..66f0cf496 100755
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:08:09
-gem5 started Jun 28 2012 23:04:41
+gem5 compiled Jul  2 2012 08:58:39
+gem5 started Jul  2 2012 12:41:46
 gem5 executing on zizzer
 command line: build/X86/gem5.fast -d build/X86/tests/fast/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86/tests/fast/quick/fs/10.linux-boot/x86/linux/pc-simple-timing
 warning: add_child('terminal'): child 'terminal' already has parent
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 5187414160000 because m5_exit instruction encountered
+Exiting @ tick 5191766314000 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
index 78491477d..b0d3b38b0 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
@@ -1,168 +1,168 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  5.187414                       # Number of seconds simulated
-sim_ticks                                5187414160000                       # Number of ticks simulated
-final_tick                               5187414160000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  5.191766                       # Number of seconds simulated
+sim_ticks                                5191766314000                       # Number of ticks simulated
+final_tick                               5191766314000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1218225                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2338274                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            45751964384                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 354108                       # Number of bytes of host memory used
-host_seconds                                   113.38                       # Real time elapsed on the host
-sim_insts                                   138123832                       # Number of instructions simulated
-sim_ops                                     265116381                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::pc.south_bridge.ide      2873600                       # Number of bytes read from this memory
+host_inst_rate                                 843973                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1619974                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            31713438762                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 354068                       # Number of bytes of host memory used
+host_seconds                                   163.71                       # Real time elapsed on the host
+sim_insts                                   138165779                       # Number of instructions simulated
+sim_ops                                     265203823                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::pc.south_bridge.ide      2891072                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker          320                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst            823872                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9013056                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             12710848                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       823872                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          823872                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      8119168                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8119168                       # Number of bytes written to this memory
-system.physmem.num_reads::pc.south_bridge.ide        44900                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::cpu.inst            821248                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           8939328                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             12651968                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       821248                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          821248                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8080768                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           8080768                       # Number of bytes written to this memory
+system.physmem.num_reads::pc.south_bridge.ide        45173                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker            5                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              12873                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             140829                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                198607                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          126862                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               126862                       # Number of write requests responded to by this memory
-system.physmem.bw_read::pc.south_bridge.ide       553956                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::cpu.inst              12832                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             139677                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                197687                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          126262                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               126262                       # Number of write requests responded to by this memory
+system.physmem.bw_read::pc.south_bridge.ide       556857                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.itb.walker             62                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               158821                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1737485                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2450324                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          158821                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             158821                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1565167                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1565167                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1565167                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide       553956                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               158183                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1721828                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2436929                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          158183                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             158183                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1556458                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1556458                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1556458                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide       556857                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.itb.walker            62                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              158821                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1737485                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4015491                       # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements                         87121                       # number of replacements
-system.l2c.tagsinuse                     64744.373482                       # Cycle average of tags in use
-system.l2c.total_refs                         3489902                       # Total number of references to valid blocks.
-system.l2c.sampled_refs                        151833                       # Sample count of references to valid blocks.
-system.l2c.avg_refs                         22.985135                       # Average number of references to valid blocks.
+system.physmem.bw_total::cpu.inst              158183                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1721828                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3993388                       # Total bandwidth to/from this memory (bytes/s)
+system.l2c.replacements                         86221                       # number of replacements
+system.l2c.tagsinuse                     64766.656106                       # Cycle average of tags in use
+system.l2c.total_refs                         3491041                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                        150947                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                         23.127594                       # Average number of references to valid blocks.
 system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks        50159.542434                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.itb.walker        0.140418                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.inst           3477.361346                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.data          11107.329284                       # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks           0.765374                       # Average percentage of cache occupancy
+system.l2c.occ_blocks::writebacks        50170.355132                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.itb.walker        0.141198                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.inst           3484.481213                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.data          11111.678563                       # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks           0.765539                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu.itb.walker       0.000002                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.inst             0.053060                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.data             0.169484                       # Average percentage of cache occupancy
-system.l2c.occ_percent::total                0.987921                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu.dtb.walker          6932                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.itb.walker          2996                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.inst              775163                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.data             1280771                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                2065862                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks         1543668                       # number of Writeback hits
-system.l2c.Writeback_hits::total              1543668                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu.data              305                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                 305                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu.data            199243                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               199243                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu.dtb.walker           6932                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.itb.walker           2996                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.inst               775163                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.data              1480014                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2265105                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu.dtb.walker          6932                       # number of overall hits
-system.l2c.overall_hits::cpu.itb.walker          2996                       # number of overall hits
-system.l2c.overall_hits::cpu.inst              775163                       # number of overall hits
-system.l2c.overall_hits::cpu.data             1480014                       # number of overall hits
-system.l2c.overall_hits::total                2265105                       # number of overall hits
+system.l2c.occ_percent::cpu.inst             0.053169                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.data             0.169551                       # Average percentage of cache occupancy
+system.l2c.occ_percent::total                0.988261                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu.dtb.walker          6306                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.itb.walker          2757                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.inst              777565                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.data             1279350                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                2065978                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks         1542134                       # number of Writeback hits
+system.l2c.Writeback_hits::total              1542134                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu.data              319                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                 319                       # number of UpgradeReq hits
+system.l2c.ReadExReq_hits::cpu.data            200451                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               200451                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu.dtb.walker           6306                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.itb.walker           2757                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.inst               777565                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.data              1479801                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 2266429                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu.dtb.walker          6306                       # number of overall hits
+system.l2c.overall_hits::cpu.itb.walker          2757                       # number of overall hits
+system.l2c.overall_hits::cpu.inst              777565                       # number of overall hits
+system.l2c.overall_hits::cpu.data             1479801                       # number of overall hits
+system.l2c.overall_hits::total                2266429                       # number of overall hits
 system.l2c.ReadReq_misses::cpu.itb.walker            5                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu.inst             12874                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu.data             28308                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                41187                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu.data           1396                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              1396                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu.data          113412                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             113412                       # number of ReadExReq misses
+system.l2c.ReadReq_misses::cpu.inst             12833                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.data             28373                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                41211                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu.data           1346                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              1346                       # number of UpgradeReq misses
+system.l2c.ReadExReq_misses::cpu.data          112235                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             112235                       # number of ReadExReq misses
 system.l2c.demand_misses::cpu.itb.walker            5                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu.inst              12874                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu.data             141720                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                154599                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.inst              12833                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.data             140608                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                153446                       # number of demand (read+write) misses
 system.l2c.overall_misses::cpu.itb.walker            5                       # number of overall misses
-system.l2c.overall_misses::cpu.inst             12874                       # number of overall misses
-system.l2c.overall_misses::cpu.data            141720                       # number of overall misses
-system.l2c.overall_misses::total               154599                       # number of overall misses
+system.l2c.overall_misses::cpu.inst             12833                       # number of overall misses
+system.l2c.overall_misses::cpu.data            140608                       # number of overall misses
+system.l2c.overall_misses::total               153446                       # number of overall misses
 system.l2c.ReadReq_miss_latency::cpu.itb.walker       260000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu.inst    669606000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu.data   1484839000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total     2154705000                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu.data     34108000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total     34108000                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu.data   5898009000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   5898009000                       # number of ReadExReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.inst    667948500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.data   1489806000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total     2158014500                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu.data     32975000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total     32975000                       # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu.data   5839097000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   5839097000                       # number of ReadExReq miss cycles
 system.l2c.demand_miss_latency::cpu.itb.walker       260000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.inst    669606000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.data   7382848000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total      8052714000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.inst    667948500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.data   7328903000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total      7997111500                       # number of demand (read+write) miss cycles
 system.l2c.overall_miss_latency::cpu.itb.walker       260000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu.inst    669606000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu.data   7382848000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total     8052714000                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu.dtb.walker         6932                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.itb.walker         3001                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.inst          788037                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.data         1309079                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2107049                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks      1543668                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total          1543668                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu.data         1701                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            1701                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu.data        312655                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           312655                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu.dtb.walker         6932                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.itb.walker         3001                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.inst           788037                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.data          1621734                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2419704                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu.dtb.walker         6932                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.itb.walker         3001                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.inst          788037                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.data         1621734                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2419704                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu.itb.walker     0.001666                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.inst       0.016337                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.data       0.021624                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.019547                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu.data     0.820694                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.820694                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu.data     0.362738                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.362738                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu.itb.walker     0.001666                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.inst        0.016337                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.data        0.087388                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.063892                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu.itb.walker     0.001666                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.inst       0.016337                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.data       0.087388                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.063892                       # miss rate for overall accesses
+system.l2c.overall_miss_latency::cpu.inst    667948500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu.data   7328903000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total     7997111500                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu.dtb.walker         6306                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.itb.walker         2762                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.inst          790398                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.data         1307723                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            2107189                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks      1542134                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total          1542134                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu.data         1665                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            1665                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu.data        312686                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           312686                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu.dtb.walker         6306                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.itb.walker         2762                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.inst           790398                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.data          1620409                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             2419875                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu.dtb.walker         6306                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.itb.walker         2762                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.inst          790398                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.data         1620409                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            2419875                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu.itb.walker     0.001810                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.inst       0.016236                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.data       0.021696                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.019557                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu.data     0.808408                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.808408                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu.data     0.358938                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.358938                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu.itb.walker     0.001810                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.inst        0.016236                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.data        0.086773                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.063411                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu.itb.walker     0.001810                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.inst       0.016236                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.data       0.086773                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.063411                       # miss rate for overall accesses
 system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker        52000                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu.inst 52012.272798                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu.data 52452.981489                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 52315.172263                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu.data 24432.664756                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 24432.664756                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu.data 52005.158184                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 52005.158184                       # average ReadExReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.inst 52049.286994                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.data 52507.877207                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 52365.011769                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu.data 24498.514116                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 24498.514116                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu.data 52025.633715                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 52025.633715                       # average ReadExReq miss latency
 system.l2c.demand_avg_miss_latency::cpu.itb.walker        52000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu.inst 52012.272798                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu.data 52094.609088                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 52087.749597                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.inst 52049.286994                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.data 52122.944640                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 52116.780496                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu.itb.walker        52000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.inst 52012.272798                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.data 52094.609088                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 52087.749597                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.inst 52049.286994                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.data 52122.944640                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 52116.780496                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -171,78 +171,78 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               80195                       # number of writebacks
-system.l2c.writebacks::total                    80195                       # number of writebacks
+system.l2c.writebacks::writebacks               79595                       # number of writebacks
+system.l2c.writebacks::total                    79595                       # number of writebacks
 system.l2c.ReadReq_mshr_misses::cpu.itb.walker            5                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu.inst        12874                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu.data        28308                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total           41187                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu.data         1396                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total         1396                       # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu.data       113412                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        113412                       # number of ReadExReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.inst        12833                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.data        28373                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total           41211                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu.data         1346                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total         1346                       # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu.data       112235                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        112235                       # number of ReadExReq MSHR misses
 system.l2c.demand_mshr_misses::cpu.itb.walker            5                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu.inst         12874                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu.data        141720                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           154599                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu.inst         12833                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu.data        140608                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           153446                       # number of demand (read+write) MSHR misses
 system.l2c.overall_mshr_misses::cpu.itb.walker            5                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu.inst        12874                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu.data       141720                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          154599                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu.inst        12833                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu.data       140608                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          153446                       # number of overall MSHR misses
 system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker       200000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu.inst    515107000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu.data   1145138000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total   1660445000                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu.data     56204000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total     56204000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu.data   4537062000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   4537062000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.inst    513944000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.data   1149325000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total   1663469000                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu.data     54216000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total     54216000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu.data   4492274000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   4492274000                       # number of ReadExReq MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu.itb.walker       200000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.inst    515107000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.data   5682200000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total   6197507000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.inst    513944000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.data   5641599000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   6155743000                       # number of demand (read+write) MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu.itb.walker       200000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.inst    515107000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.data   5682200000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total   6197507000                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data  56051788000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total  56051788000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data   1218002000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   1218002000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu.data  57269790000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  57269790000                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker     0.001666                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.016337                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.021624                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.019547                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.820694                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.820694                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.362738                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.362738                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu.itb.walker     0.001666                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu.inst     0.016337                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu.data     0.087388                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.063892                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu.itb.walker     0.001666                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu.inst     0.016337                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu.data     0.087388                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.063892                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_latency::cpu.inst    513944000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.data   5641599000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   6155743000                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data  56050191064                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total  56050191064                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data   1204378000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   1204378000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu.data  57254569064                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  57254569064                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker     0.001810                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.016236                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.021696                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.019557                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.808408                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.808408                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.358938                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.358938                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu.itb.walker     0.001810                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.inst     0.016236                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.data     0.086773                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.063411                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu.itb.walker     0.001810                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.inst     0.016236                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.data     0.086773                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.063411                       # mshr miss rate for overall accesses
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        40000                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40011.418363                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40452.804861                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 40314.783791                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40260.744986                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40260.744986                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40005.131732                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 40005.131732                       # average ReadExReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40048.624640                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40507.700983                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 40364.684186                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40279.346211                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40279.346211                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40025.606985                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 40025.606985                       # average ReadExReq mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker        40000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40011.418363                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.data 40094.552639                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 40087.626699                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40048.624640                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.data 40122.887745                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 40116.672966                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker        40000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40011.418363                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.data 40094.552639                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 40087.626699                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40048.624640                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.data 40122.887745                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 40116.672966                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -251,14 +251,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data          inf
 system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.iocache.replacements                     47504                       # number of replacements
-system.iocache.tagsinuse                     0.096008                       # Cycle average of tags in use
+system.iocache.tagsinuse                     0.108710                       # Cycle average of tags in use
 system.iocache.total_refs                           0                       # Total number of references to valid blocks.
 system.iocache.sampled_refs                     47520                       # Sample count of references to valid blocks.
 system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
-system.iocache.warmup_cycle              5048726357000                       # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::pc.south_bridge.ide     0.096008                       # Average occupied blocks per requestor
-system.iocache.occ_percent::pc.south_bridge.ide     0.006001                       # Average percentage of cache occupancy
-system.iocache.occ_percent::total            0.006001                       # Average percentage of cache occupancy
+system.iocache.warmup_cycle              5048944307000                       # Cycle when the warmup percentage was hit.
+system.iocache.occ_blocks::pc.south_bridge.ide     0.108710                       # Average occupied blocks per requestor
+system.iocache.occ_percent::pc.south_bridge.ide     0.006794                       # Average percentage of cache occupancy
+system.iocache.occ_percent::total            0.006794                       # Average percentage of cache occupancy
 system.iocache.ReadReq_misses::pc.south_bridge.ide          839                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              839                       # number of ReadReq misses
 system.iocache.WriteReq_misses::pc.south_bridge.ide        46720                       # number of WriteReq misses
@@ -267,14 +267,14 @@ system.iocache.demand_misses::pc.south_bridge.ide        47559
 system.iocache.demand_misses::total             47559                       # number of demand (read+write) misses
 system.iocache.overall_misses::pc.south_bridge.ide        47559                       # number of overall misses
 system.iocache.overall_misses::total            47559                       # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    105990932                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total    105990932                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::pc.south_bridge.ide   6391870160                       # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total   6391870160                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide   6497861092                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   6497861092                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide   6497861092                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   6497861092                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    128944932                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total    128944932                       # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::pc.south_bridge.ide   7159405160                       # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total   7159405160                       # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide   7288350092                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   7288350092                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide   7288350092                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   7288350092                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::pc.south_bridge.ide          839                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            839                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::pc.south_bridge.ide        46720                       # number of WriteReq accesses(hits+misses)
@@ -291,19 +291,19 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 126330.073897                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 126330.073897                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 136812.289384                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 136812.289384                       # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 136627.370046                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 136627.370046                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 136627.370046                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 136627.370046                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs      69487644                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 153688.834327                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 153688.834327                       # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 153240.692637                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 153240.692637                       # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 153248.598415                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 153248.598415                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 153248.598415                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 153248.598415                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs        372008                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                11303                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                   38                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs  6147.716889                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs  9789.684211                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -317,14 +317,14 @@ system.iocache.demand_mshr_misses::pc.south_bridge.ide        47559
 system.iocache.demand_mshr_misses::total        47559                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::pc.south_bridge.ide        47559                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total        47559                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     62341978                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     62341978                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide   3962173996                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total   3962173996                       # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide   4024515974                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   4024515974                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide   4024515974                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   4024515974                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     85286000                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     85286000                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide   4729709976                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total   4729709976                       # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide   4814995976                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   4814995976                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide   4814995976                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   4814995976                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteReq accesses
@@ -333,14 +333,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 74305.098927                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 74305.098927                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 84806.806421                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 84806.806421                       # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 84621.543220                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 84621.543220                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 84621.543220                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 84621.543220                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 101651.966627                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 101651.966627                       # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 101235.230651                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 101235.230651                       # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 101242.582392                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 101242.582392                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 101242.582392                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 101242.582392                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
@@ -354,75 +354,75 @@ system.pc.south_bridge.ide.disks1.dma_read_txs            0
 system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
-system.cpu.numCycles                      10374828320                       # number of cpu cycles simulated
+system.cpu.numCycles                      10383532628                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   138123832                       # Number of instructions committed
-system.cpu.committedOps                     265116381                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             249524959                       # Number of integer alu accesses
+system.cpu.committedInsts                   138165779                       # Number of instructions committed
+system.cpu.committedOps                     265203823                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             249613018                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
 system.cpu.num_func_calls                           0                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     24879442                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    249524959                       # number of integer instructions
+system.cpu.num_conditional_control_insts     24887740                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    249613018                       # number of integer instructions
 system.cpu.num_fp_insts                             0                       # number of float instructions
-system.cpu.num_int_register_reads           777989618                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          422868687                       # number of times the integer registers were written
+system.cpu.num_int_register_reads           778264797                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          423017345                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_mem_refs                      23163323                       # number of memory refs
-system.cpu.num_load_insts                    14806608                       # Number of load instructions
-system.cpu.num_store_insts                    8356715                       # Number of store instructions
-system.cpu.num_idle_cycles               9773126970.350117                       # Number of idle cycles
-system.cpu.num_busy_cycles               601701349.649884                       # Number of busy cycles
-system.cpu.not_idle_fraction                 0.057996                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.942004                       # Percentage of idle cycles
+system.cpu.num_mem_refs                      23180618                       # number of memory refs
+system.cpu.num_load_insts                    14822217                       # Number of load instructions
+system.cpu.num_store_insts                    8358401                       # Number of store instructions
+system.cpu.num_idle_cycles               9771874940.286118                       # Number of idle cycles
+system.cpu.num_busy_cycles               611657687.713882                       # Number of busy cycles
+system.cpu.not_idle_fraction                 0.058907                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.941093                       # Percentage of idle cycles
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
 system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed
-system.cpu.icache.replacements                 787531                       # number of replacements
-system.cpu.icache.tagsinuse                510.360069                       # Cycle average of tags in use
-system.cpu.icache.total_refs                158416168                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                 788043                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                 201.024777                       # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle           159962400000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     510.360069                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.996797                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.996797                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst    158416168                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       158416168                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     158416168                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        158416168                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    158416168                       # number of overall hits
-system.cpu.icache.overall_hits::total       158416168                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       788050                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        788050                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       788050                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         788050                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       788050                       # number of overall misses
-system.cpu.icache.overall_misses::total        788050                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  11574503000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  11574503000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  11574503000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  11574503000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  11574503000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  11574503000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    159204218                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    159204218                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    159204218                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    159204218                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    159204218                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    159204218                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.004950                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.004950                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.004950                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.004950                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.004950                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.004950                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14687.523634                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 14687.523634                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 14687.523634                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 14687.523634                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 14687.523634                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 14687.523634                       # average overall miss latency
+system.cpu.icache.replacements                 789892                       # number of replacements
+system.cpu.icache.tagsinuse                510.351457                       # Cycle average of tags in use
+system.cpu.icache.total_refs                158472874                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                 790404                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                 200.496043                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle           160421907000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::cpu.inst     510.351457                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.996780                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.996780                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst    158472874                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       158472874                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     158472874                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        158472874                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    158472874                       # number of overall hits
+system.cpu.icache.overall_hits::total       158472874                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       790411                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        790411                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       790411                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         790411                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       790411                       # number of overall misses
+system.cpu.icache.overall_misses::total        790411                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  11780929500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  11780929500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  11780929500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  11780929500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  11780929500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  11780929500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    159263285                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    159263285                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    159263285                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    159263285                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    159263285                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    159263285                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.004963                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.004963                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.004963                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.004963                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.004963                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.004963                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14904.814710                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 14904.814710                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 14904.814710                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 14904.814710                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 14904.814710                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 14904.814710                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -431,82 +431,82 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks         1027                       # number of writebacks
-system.cpu.icache.writebacks::total              1027                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       788050                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       788050                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       788050                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       788050                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       788050                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       788050                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   9209308000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total   9209308000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst   9209308000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total   9209308000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst   9209308000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total   9209308000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.004950                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.004950                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.004950                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.004950                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.004950                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.004950                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11686.197576                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11686.197576                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11686.197576                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11686.197576                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11686.197576                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11686.197576                       # average overall mshr miss latency
+system.cpu.icache.writebacks::writebacks          806                       # number of writebacks
+system.cpu.icache.writebacks::total               806                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       790411                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       790411                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       790411                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       790411                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       790411                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       790411                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   9408678500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total   9408678500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   9408678500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   9408678500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst   9408678500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total   9408678500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.004963                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.004963                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.004963                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.004963                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.004963                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.004963                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11903.526773                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11903.526773                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11903.526773                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11903.526773                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11903.526773                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11903.526773                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.itb_walker_cache.replacements         3928                       # number of replacements
-system.cpu.itb_walker_cache.tagsinuse        3.062395                       # Cycle average of tags in use
-system.cpu.itb_walker_cache.total_refs           7428                       # Total number of references to valid blocks.
-system.cpu.itb_walker_cache.sampled_refs         3940                       # Sample count of references to valid blocks.
-system.cpu.itb_walker_cache.avg_refs         1.885279                       # Average number of references to valid blocks.
-system.cpu.itb_walker_cache.warmup_cycle 5163621004000                       # Cycle when the warmup percentage was hit.
-system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker     3.062395                       # Average occupied blocks per requestor
-system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker     0.191400                       # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.occ_percent::total     0.191400                       # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker         7428                       # number of ReadReq hits
-system.cpu.itb_walker_cache.ReadReq_hits::total         7428                       # number of ReadReq hits
+system.cpu.itb_walker_cache.replacements         3403                       # number of replacements
+system.cpu.itb_walker_cache.tagsinuse        3.070913                       # Cycle average of tags in use
+system.cpu.itb_walker_cache.total_refs           8040                       # Total number of references to valid blocks.
+system.cpu.itb_walker_cache.sampled_refs         3415                       # Sample count of references to valid blocks.
+system.cpu.itb_walker_cache.avg_refs         2.354319                       # Average number of references to valid blocks.
+system.cpu.itb_walker_cache.warmup_cycle 5164836909000                       # Cycle when the warmup percentage was hit.
+system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker     3.070913                       # Average occupied blocks per requestor
+system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker     0.191932                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.occ_percent::total     0.191932                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker         8060                       # number of ReadReq hits
+system.cpu.itb_walker_cache.ReadReq_hits::total         8060                       # number of ReadReq hits
 system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            2                       # number of WriteReq hits
 system.cpu.itb_walker_cache.WriteReq_hits::total            2                       # number of WriteReq hits
-system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker         7430                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.demand_hits::total         7430                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker         7430                       # number of overall hits
-system.cpu.itb_walker_cache.overall_hits::total         7430                       # number of overall hits
-system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker         4796                       # number of ReadReq misses
-system.cpu.itb_walker_cache.ReadReq_misses::total         4796                       # number of ReadReq misses
-system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker         4796                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.demand_misses::total         4796                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker         4796                       # number of overall misses
-system.cpu.itb_walker_cache.overall_misses::total         4796                       # number of overall misses
-system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker     51199000                       # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.ReadReq_miss_latency::total     51199000                       # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker     51199000                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::total     51199000                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker     51199000                       # number of overall miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::total     51199000                       # number of overall miss cycles
-system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        12224                       # number of ReadReq accesses(hits+misses)
-system.cpu.itb_walker_cache.ReadReq_accesses::total        12224                       # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker         8062                       # number of demand (read+write) hits
+system.cpu.itb_walker_cache.demand_hits::total         8062                       # number of demand (read+write) hits
+system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker         8062                       # number of overall hits
+system.cpu.itb_walker_cache.overall_hits::total         8062                       # number of overall hits
+system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker         4266                       # number of ReadReq misses
+system.cpu.itb_walker_cache.ReadReq_misses::total         4266                       # number of ReadReq misses
+system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker         4266                       # number of demand (read+write) misses
+system.cpu.itb_walker_cache.demand_misses::total         4266                       # number of demand (read+write) misses
+system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker         4266                       # number of overall misses
+system.cpu.itb_walker_cache.overall_misses::total         4266                       # number of overall misses
+system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker     50418000                       # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.ReadReq_miss_latency::total     50418000                       # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker     50418000                       # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::total     50418000                       # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker     50418000                       # number of overall miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::total     50418000                       # number of overall miss cycles
+system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        12326                       # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.ReadReq_accesses::total        12326                       # number of ReadReq accesses(hits+misses)
 system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            2                       # number of WriteReq accesses(hits+misses)
 system.cpu.itb_walker_cache.WriteReq_accesses::total            2                       # number of WriteReq accesses(hits+misses)
-system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        12226                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.demand_accesses::total        12226                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        12226                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::total        12226                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.392343                       # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.392343                       # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.392279                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_miss_rate::total     0.392279                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.392279                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_miss_rate::total     0.392279                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10675.354462                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10675.354462                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10675.354462                       # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10675.354462                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10675.354462                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10675.354462                       # average overall miss latency
+system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        12328                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.demand_accesses::total        12328                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        12328                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::total        12328                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.346098                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.346098                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.346042                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_miss_rate::total     0.346042                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.346042                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_miss_rate::total     0.346042                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11818.565401                       # average ReadReq miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11818.565401                       # average ReadReq miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11818.565401                       # average overall miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11818.565401                       # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11818.565401                       # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11818.565401                       # average overall miss latency
 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -515,78 +515,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.itb_walker_cache.writebacks::writebacks          763                       # number of writebacks
-system.cpu.itb_walker_cache.writebacks::total          763                       # number of writebacks
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker         4796                       # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::total         4796                       # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker         4796                       # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::total         4796                       # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker         4796                       # number of overall MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::total         4796                       # number of overall MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker     36811000                       # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total     36811000                       # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker     36811000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::total     36811000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker     36811000                       # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::total     36811000                       # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.392343                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.392343                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.392279                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.392279                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.392279                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.392279                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  7675.354462                       # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  7675.354462                       # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  7675.354462                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  7675.354462                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  7675.354462                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  7675.354462                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.writebacks::writebacks          726                       # number of writebacks
+system.cpu.itb_walker_cache.writebacks::total          726                       # number of writebacks
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker         4266                       # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::total         4266                       # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker         4266                       # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::total         4266                       # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker         4266                       # number of overall MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::total         4266                       # number of overall MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker     37620000                       # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total     37620000                       # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker     37620000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::total     37620000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker     37620000                       # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::total     37620000                       # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.346098                       # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.346098                       # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.346042                       # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.346042                       # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.346042                       # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.346042                       # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  8818.565401                       # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  8818.565401                       # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  8818.565401                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  8818.565401                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  8818.565401                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  8818.565401                       # average overall mshr miss latency
 system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.dtb_walker_cache.replacements         8715                       # number of replacements
-system.cpu.dtb_walker_cache.tagsinuse        5.044713                       # Cycle average of tags in use
-system.cpu.dtb_walker_cache.total_refs          12138                       # Total number of references to valid blocks.
-system.cpu.dtb_walker_cache.sampled_refs         8729                       # Sample count of references to valid blocks.
-system.cpu.dtb_walker_cache.avg_refs         1.390537                       # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.warmup_cycle 5162053528000                       # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker     5.044713                       # Average occupied blocks per requestor
-system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker     0.315295                       # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.occ_percent::total     0.315295                       # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker        12140                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.ReadReq_hits::total        12140                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker        12140                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::total        12140                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker        12140                       # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::total        12140                       # number of overall hits
-system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker         9925                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.ReadReq_misses::total         9925                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker         9925                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::total         9925                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker         9925                       # number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::total         9925                       # number of overall misses
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker    112013000                       # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::total    112013000                       # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker    112013000                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::total    112013000                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker    112013000                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::total    112013000                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker        22065                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.ReadReq_accesses::total        22065                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker        22065                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::total        22065                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker        22065                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::total        22065                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.449807                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.449807                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.449807                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::total     0.449807                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.449807                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::total     0.449807                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 11285.944584                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 11285.944584                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 11285.944584                       # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 11285.944584                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 11285.944584                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 11285.944584                       # average overall miss latency
+system.cpu.dtb_walker_cache.replacements         7529                       # number of replacements
+system.cpu.dtb_walker_cache.tagsinuse        5.053120                       # Cycle average of tags in use
+system.cpu.dtb_walker_cache.total_refs          13331                       # Total number of references to valid blocks.
+system.cpu.dtb_walker_cache.sampled_refs         7543                       # Sample count of references to valid blocks.
+system.cpu.dtb_walker_cache.avg_refs         1.767334                       # Average number of references to valid blocks.
+system.cpu.dtb_walker_cache.warmup_cycle 5161009068000                       # Cycle when the warmup percentage was hit.
+system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker     5.053120                       # Average occupied blocks per requestor
+system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker     0.315820                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.occ_percent::total     0.315820                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker        13332                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.ReadReq_hits::total        13332                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker        13332                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.demand_hits::total        13332                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker        13332                       # number of overall hits
+system.cpu.dtb_walker_cache.overall_hits::total        13332                       # number of overall hits
+system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker         8729                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.ReadReq_misses::total         8729                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker         8729                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.demand_misses::total         8729                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker         8729                       # number of overall misses
+system.cpu.dtb_walker_cache.overall_misses::total         8729                       # number of overall misses
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker    112265000                       # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::total    112265000                       # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker    112265000                       # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::total    112265000                       # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker    112265000                       # number of overall miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::total    112265000                       # number of overall miss cycles
+system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker        22061                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.ReadReq_accesses::total        22061                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker        22061                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.demand_accesses::total        22061                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker        22061                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::total        22061                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.395676                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.395676                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.395676                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::total     0.395676                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.395676                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::total     0.395676                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12861.152480                       # average ReadReq miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12861.152480                       # average ReadReq miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12861.152480                       # average overall miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12861.152480                       # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12861.152480                       # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12861.152480                       # average overall miss latency
 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -595,90 +595,90 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.dtb_walker_cache.writebacks::writebacks         2933                       # number of writebacks
-system.cpu.dtb_walker_cache.writebacks::total         2933                       # number of writebacks
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker         9925                       # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total         9925                       # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker         9925                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::total         9925                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker         9925                       # number of overall MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::total         9925                       # number of overall MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker     82238000                       # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total     82238000                       # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker     82238000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total     82238000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker     82238000                       # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total     82238000                       # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.449807                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.449807                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.449807                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.449807                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.449807                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.449807                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker  8285.944584                       # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total  8285.944584                       # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker  8285.944584                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total  8285.944584                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker  8285.944584                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total  8285.944584                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.writebacks::writebacks         2916                       # number of writebacks
+system.cpu.dtb_walker_cache.writebacks::total         2916                       # number of writebacks
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker         8729                       # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total         8729                       # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker         8729                       # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::total         8729                       # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker         8729                       # number of overall MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::total         8729                       # number of overall MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker     86078000                       # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total     86078000                       # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker     86078000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total     86078000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker     86078000                       # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total     86078000                       # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.395676                       # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.395676                       # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.395676                       # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.395676                       # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.395676                       # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.395676                       # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker  9861.152480                       # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total  9861.152480                       # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker  9861.152480                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total  9861.152480                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker  9861.152480                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total  9861.152480                       # average overall mshr miss latency
 system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                1621962                       # number of replacements
-system.cpu.dcache.tagsinuse                511.997374                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 20006252                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                1622474                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  12.330707                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle               44345000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data     511.997374                       # Average occupied blocks per requestor
+system.cpu.dcache.replacements                1620697                       # number of replacements
+system.cpu.dcache.tagsinuse                511.997463                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 20024819                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                1621209                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  12.351781                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle               45838000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data     511.997463                       # Average occupied blocks per requestor
 system.cpu.dcache.occ_percent::cpu.data      0.999995                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_percent::total         0.999995                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data     11972224                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        11972224                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      8031812                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        8031812                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      20004036                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         20004036                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     20004036                       # number of overall hits
-system.cpu.dcache.overall_hits::total        20004036                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1309841                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1309841                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       314876                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       314876                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      1624717                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1624717                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1624717                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1624717                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  19532720500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  19532720500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   9225744000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   9225744000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  28758464500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  28758464500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  28758464500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  28758464500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     13282065                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     13282065                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      8346688                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      8346688                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     21628753                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     21628753                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     21628753                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     21628753                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.098617                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.098617                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037725                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.037725                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.075118                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.075118                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.075118                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.075118                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14912.283628                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14912.283628                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29299.610005                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 29299.610005                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 17700.599243                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 17700.599243                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 17700.599243                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 17700.599243                       # average overall miss latency
+system.cpu.dcache.ReadReq_hits::cpu.data     11989145                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        11989145                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      8033493                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        8033493                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      20022638                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         20022638                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     20022638                       # number of overall hits
+system.cpu.dcache.overall_hits::total        20022638                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1308549                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1308549                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       314872                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       314872                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      1623421                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1623421                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1623421                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1623421                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  19872658500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  19872658500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   9327760500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   9327760500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  29200419000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  29200419000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  29200419000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  29200419000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     13297694                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     13297694                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      8348365                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      8348365                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     21646059                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     21646059                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     21646059                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     21646059                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.098404                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.098404                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037717                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.037717                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.074998                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.074998                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.074998                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.074998                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15186.789719                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 15186.789719                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29623.975774                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 29623.975774                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 17986.966412                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 17986.966412                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 17986.966412                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 17986.966412                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -687,46 +687,46 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      1538945                       # number of writebacks
-system.cpu.dcache.writebacks::total           1538945                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1309841                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1309841                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       314876                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       314876                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1624717                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1624717                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1624717                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1624717                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  15603157000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  15603157000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8281105000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   8281105000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  23884262000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  23884262000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  23884262000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  23884262000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  75925327500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  75925327500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   1379632500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   1379632500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  77304960000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  77304960000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.098617                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.098617                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.037725                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.037725                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.075118                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.075118                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.075118                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.075118                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11912.252709                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11912.252709                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26299.575071                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26299.575071                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14700.567545                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 14700.567545                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14700.567545                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 14700.567545                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks      1537686                       # number of writebacks
+system.cpu.dcache.writebacks::total           1537686                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1308549                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1308549                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       314872                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       314872                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1623421                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1623421                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1623421                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1623421                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  15946961002                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  15946961002                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8383141001                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   8383141001                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  24330102003                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  24330102003                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  24330102003                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  24330102003                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  75924400500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  75924400500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   1366040500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   1366040500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  77290441000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  77290441000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.098404                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.098404                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.037717                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.037717                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.074998                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.074998                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.074998                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.074998                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12186.751128                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12186.751128                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26623.964662                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26623.964662                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14986.933151                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 14986.933151                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14986.933151                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 14986.933151                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini
index 5cc0911e9..e1fc4e09c 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini
@@ -181,7 +181,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
@@ -213,7 +213,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout
index b9f1a2caf..da63093c1 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun  4 2012 11:50:11
-gem5 started Jun  4 2012 14:15:31
+gem5 compiled Jul  2 2012 08:30:56
+gem5 started Jul  2 2012 09:08:18
 gem5 executing on zizzer
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello world!
-Exiting @ tick 21234500 because target called exit()
+Exiting @ tick 21985500 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt
index 6887d118d..b38d65b68 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000021                       # Number of seconds simulated
-sim_ticks                                    21234500                       # Number of ticks simulated
-final_tick                                   21234500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000022                       # Number of seconds simulated
+sim_ticks                                    21985500                       # Number of ticks simulated
+final_tick                                   21985500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  73768                       # Simulator instruction rate (inst/s)
-host_op_rate                                    73752                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              244499363                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 214444                       # Number of bytes of host memory used
-host_seconds                                     0.09                       # Real time elapsed on the host
+host_inst_rate                                  65949                       # Simulator instruction rate (inst/s)
+host_op_rate                                    65938                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              226330541                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 218192                       # Number of bytes of host memory used
+host_seconds                                     0.10                       # Real time elapsed on the host
 sim_insts                                        6404                       # Number of instructions simulated
 sim_ops                                          6404                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             19264                       # Number of bytes read from this memory
@@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total           19264                       # Nu
 system.physmem.num_reads::cpu.inst                301                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                168                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   469                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            907202901                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            506345805                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1413548706                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       907202901                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          907202901                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           907202901                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           506345805                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1413548706                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            876213868                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            489049601                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1365263469                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       876213868                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          876213868                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           876213868                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           489049601                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1365263469                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -35,14 +35,14 @@ system.cpu.dtb.read_hits                         1186                       # DT
 system.cpu.dtb.read_misses                          7                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
 system.cpu.dtb.read_accesses                     1193                       # DTB read accesses
-system.cpu.dtb.write_hits                         898                       # DTB write hits
+system.cpu.dtb.write_hits                         900                       # DTB write hits
 system.cpu.dtb.write_misses                         3                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                     901                       # DTB write accesses
-system.cpu.dtb.data_hits                         2084                       # DTB hits
+system.cpu.dtb.write_accesses                     903                       # DTB write accesses
+system.cpu.dtb.data_hits                         2086                       # DTB hits
 system.cpu.dtb.data_misses                         10                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                     2094                       # DTB accesses
+system.cpu.dtb.data_accesses                     2096                       # DTB accesses
 system.cpu.itb.fetch_hits                         908                       # ITB hits
 system.cpu.itb.fetch_misses                        17                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
@@ -60,26 +60,26 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   17                       # Number of system calls
-system.cpu.numCycles                            42470                       # number of cpu cycles simulated
+system.cpu.numCycles                            43972                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.branch_predictor.lookups              1608                       # Number of BP lookups
-system.cpu.branch_predictor.condPredicted         1127                       # Number of conditional branches predicted
+system.cpu.branch_predictor.lookups              1607                       # Number of BP lookups
+system.cpu.branch_predictor.condPredicted         1126                       # Number of conditional branches predicted
 system.cpu.branch_predictor.condIncorrect          712                       # Number of conditional branches incorrect
-system.cpu.branch_predictor.BTBLookups           1187                       # Number of BTB lookups
+system.cpu.branch_predictor.BTBLookups           1186                       # Number of BTB lookups
 system.cpu.branch_predictor.BTBHits               314                       # Number of BTB hits
 system.cpu.branch_predictor.usedRAS               126                       # Number of times the RAS was used to get a target.
 system.cpu.branch_predictor.RASInCorrect            0                       # Number of incorrect RAS predictions.
-system.cpu.branch_predictor.BTBHitPct       26.453243                       # BTB Hit Percentage
+system.cpu.branch_predictor.BTBHitPct       26.475548                       # BTB Hit Percentage
 system.cpu.branch_predictor.predictedTaken          464                       # Number of Branches Predicted As Taken (True).
-system.cpu.branch_predictor.predictedNotTaken         1144                       # Number of Branches Predicted As Not Taken (False).
-system.cpu.regfile_manager.intRegFileReads         5213                       # Number of Reads from Int. Register File
+system.cpu.branch_predictor.predictedNotTaken         1143                       # Number of Branches Predicted As Not Taken (False).
+system.cpu.regfile_manager.intRegFileReads         5212                       # Number of Reads from Int. Register File
 system.cpu.regfile_manager.intRegFileWrites         4580                       # Number of Writes to Int. Register File
-system.cpu.regfile_manager.intRegFileAccesses         9793                       # Total Accesses (Read+Write) to the Int. Register File
+system.cpu.regfile_manager.intRegFileAccesses         9792                       # Total Accesses (Read+Write) to the Int. Register File
 system.cpu.regfile_manager.floatRegFileReads            8                       # Number of Reads from FP Register File
 system.cpu.regfile_manager.floatRegFileWrites            2                       # Number of Writes to FP Register File
 system.cpu.regfile_manager.floatRegFileAccesses           10                       # Total Accesses (Read+Write) to the FP Register File
-system.cpu.regfile_manager.regForwards           2970                       # Number of Registers Read Through Forwarding Logic
+system.cpu.regfile_manager.regForwards           2971                       # Number of Registers Read Through Forwarding Logic
 system.cpu.agen_unit.agens                       2183                       # Number of Address Generations
 system.cpu.execution_unit.predictedTakenIncorrect          284                       # Number of Branches Incorrectly Predicted As Taken.
 system.cpu.execution_unit.predictedNotTakenIncorrect          367                       # Number of Branches Incorrectly Predicted As Not Taken).
@@ -90,12 +90,12 @@ system.cpu.execution_unit.executions             4474                       # Nu
 system.cpu.mult_div_unit.multiplies                 1                       # Number of Multipy Operations Executed
 system.cpu.mult_div_unit.divides                    0                       # Number of Divide Operations Executed
 system.cpu.contextSwitches                          1                       # Number of context switches
-system.cpu.threadCycles                         11434                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles                         12078                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
 system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled                             443                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           35079                       # Number of cycles cpu's stages were not processed
-system.cpu.runCycles                             7391                       # Number of cycles cpu stages are processed.
-system.cpu.activity                         17.402873                       # Percentage of cycles cpu is active
+system.cpu.timesIdled                             536                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           36557                       # Number of cycles cpu's stages were not processed
+system.cpu.runCycles                             7415                       # Number of cycles cpu stages are processed.
+system.cpu.activity                         16.863004                       # Percentage of cycles cpu is active
 system.cpu.comLoads                              1185                       # Number of Load instructions committed
 system.cpu.comStores                              865                       # Number of Store instructions committed
 system.cpu.comBranches                           1051                       # Number of Branches instructions committed
@@ -107,72 +107,72 @@ system.cpu.committedInsts                        6404                       # Nu
 system.cpu.committedOps                          6404                       # Number of Ops committed (Per-Thread)
 system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
 system.cpu.committedInsts_total                  6404                       # Number of Instructions committed (Total)
-system.cpu.cpi                               6.631793                       # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi                               6.866334                       # CPI: Cycles Per Instruction (Per-Thread)
 system.cpu.smt_cpi                                nan                       # CPI: Total SMT-CPI
-system.cpu.cpi_total                         6.631793                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.150789                       # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.cpi_total                         6.866334                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.145638                       # IPC: Instructions Per Cycle (Per-Thread)
 system.cpu.smt_ipc                                nan                       # IPC: Total SMT-IPC
-system.cpu.ipc_total                         0.150789                       # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles                    37550                       # Number of cycles 0 instructions are processed.
-system.cpu.stage0.runCycles                      4920                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization               11.584648                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles                    38585                       # Number of cycles 0 instructions are processed.
-system.cpu.stage1.runCycles                      3885                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization                9.147634                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles                    38290                       # Number of cycles 0 instructions are processed.
-system.cpu.stage2.runCycles                      4180                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization                9.842242                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles                    41130                       # Number of cycles 0 instructions are processed.
-system.cpu.stage3.runCycles                      1340                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization                3.155168                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles                    38002                       # Number of cycles 0 instructions are processed.
-system.cpu.stage4.runCycles                      4468                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization               10.520367                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.ipc_total                         0.145638                       # IPC: Total IPC of All Threads
+system.cpu.stage0.idleCycles                    39051                       # Number of cycles 0 instructions are processed.
+system.cpu.stage0.runCycles                      4921                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.utilization               11.191213                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles                    40084                       # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles                      3888                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization                8.841990                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles                    39791                       # Number of cycles 0 instructions are processed.
+system.cpu.stage2.runCycles                      4181                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage2.utilization                9.508323                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles                    42630                       # Number of cycles 0 instructions are processed.
+system.cpu.stage3.runCycles                      1342                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage3.utilization                3.051942                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles                    39502                       # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles                      4470                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization               10.165560                       # Percentage of cycles stage was utilized (processing insts).
 system.cpu.icache.replacements                      0                       # number of replacements
-system.cpu.icache.tagsinuse                138.955928                       # Cycle average of tags in use
-system.cpu.icache.total_refs                      558                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                138.644500                       # Cycle average of tags in use
+system.cpu.icache.total_refs                      557                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    301                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                   1.853821                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs                   1.850498                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     138.955928                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.067850                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.067850                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst          558                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total             558                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst           558                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total              558                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst          558                       # number of overall hits
-system.cpu.icache.overall_hits::total             558                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          350                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           350                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          350                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            350                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          350                       # number of overall misses
-system.cpu.icache.overall_misses::total           350                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     19343500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     19343500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     19343500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     19343500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     19343500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     19343500                       # number of overall miss cycles
+system.cpu.icache.occ_blocks::cpu.inst     138.644500                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.067698                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.067698                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst          557                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total             557                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst           557                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total              557                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst          557                       # number of overall hits
+system.cpu.icache.overall_hits::total             557                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          351                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           351                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          351                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            351                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          351                       # number of overall misses
+system.cpu.icache.overall_misses::total           351                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     19781500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     19781500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     19781500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     19781500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     19781500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     19781500                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst          908                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total          908                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst          908                       # number of demand (read+write) accesses
 system.cpu.icache.demand_accesses::total          908                       # number of demand (read+write) accesses
 system.cpu.icache.overall_accesses::cpu.inst          908                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::total          908                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.385463                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.385463                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.385463                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.385463                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.385463                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.385463                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55267.142857                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 55267.142857                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 55267.142857                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 55267.142857                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 55267.142857                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 55267.142857                       # average overall miss latency
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.386564                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.386564                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.386564                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.386564                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.386564                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.386564                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56357.549858                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 56357.549858                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 56357.549858                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 56357.549858                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 56357.549858                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 56357.549858                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -181,70 +181,70 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst           48                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total           48                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst           48                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total           48                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst           48                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total           48                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst           49                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total           49                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst           49                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total           49                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst           49                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total           49                       # number of overall MSHR hits
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          302                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total          302                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst          302                       # number of demand (read+write) MSHR misses
 system.cpu.icache.demand_mshr_misses::total          302                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          302                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          302                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     16051500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     16051500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     16051500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     16051500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     16051500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     16051500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     16493500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     16493500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     16493500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     16493500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     16493500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     16493500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.332599                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.332599                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.332599                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.332599                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.332599                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.332599                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53150.662252                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53150.662252                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53150.662252                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 53150.662252                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53150.662252                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 53150.662252                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54614.238411                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54614.238411                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54614.238411                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 54614.238411                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54614.238411                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 54614.238411                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.tagsinuse                102.711534                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                     1703                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse                102.468585                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                     1702                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                    168                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  10.136905                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                  10.130952                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data     102.711534                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.025076                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.025076                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::cpu.data     102.468585                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.025017                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.025017                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data         1088                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total            1088                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data          615                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total            615                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          1703                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             1703                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         1703                       # number of overall hits
-system.cpu.dcache.overall_hits::total            1703                       # number of overall hits
+system.cpu.dcache.WriteReq_hits::cpu.data          614                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total            614                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data          1702                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             1702                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         1702                       # number of overall hits
+system.cpu.dcache.overall_hits::total            1702                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data           97                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total            97                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data          250                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total          250                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          347                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            347                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          347                       # number of overall misses
-system.cpu.dcache.overall_misses::total           347                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      5507500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      5507500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     13555000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     13555000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     19062500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     19062500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     19062500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     19062500                       # number of overall miss cycles
+system.cpu.dcache.WriteReq_misses::cpu.data          251                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total          251                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data          348                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            348                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          348                       # number of overall misses
+system.cpu.dcache.overall_misses::total           348                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      5918000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      5918000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     15290000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     15290000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     21208000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     21208000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     21208000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     21208000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data         1185                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total         1185                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          865                       # number of WriteReq accesses(hits+misses)
@@ -255,36 +255,36 @@ system.cpu.dcache.overall_accesses::cpu.data         2050
 system.cpu.dcache.overall_accesses::total         2050                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.081857                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.081857                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.289017                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.289017                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.169268                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.169268                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.169268                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.169268                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56778.350515                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 56778.350515                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        54220                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total        54220                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 54935.158501                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 54935.158501                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 54935.158501                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 54935.158501                       # average overall miss latency
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.290173                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.290173                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.169756                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.169756                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.169756                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.169756                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61010.309278                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 61010.309278                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60916.334661                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 60916.334661                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 60942.528736                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 60942.528736                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 60942.528736                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 60942.528736                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets      1656000                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets      1689000                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets              36                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets              37                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets        46000                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 45648.648649                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data            2                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total            2                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data          177                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total          177                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          179                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          179                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          179                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          179                       # number of overall MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data          178                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total          178                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          180                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          180                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          180                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          180                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data           95                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total           95                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data           73                       # number of WriteReq MSHR misses
@@ -293,14 +293,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          168
 system.cpu.dcache.demand_mshr_misses::total          168                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          168                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          168                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      5113000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      5113000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      3909500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      3909500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      9022500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      9022500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      9022500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      9022500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      5509500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      5509500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      4096500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      4096500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      9606000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      9606000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      9606000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      9606000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.080169                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.080169                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.084393                       # mshr miss rate for WriteReq accesses
@@ -309,26 +309,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.081951
 system.cpu.dcache.demand_mshr_miss_rate::total     0.081951                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.081951                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.081951                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53821.052632                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53821.052632                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53554.794521                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53554.794521                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53705.357143                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 53705.357143                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53705.357143                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 53705.357143                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57994.736842                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57994.736842                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56116.438356                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56116.438356                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57178.571429                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 57178.571429                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57178.571429                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 57178.571429                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse               195.300582                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               194.857279                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       1                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                   395                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.002532                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst    139.031748                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data     56.268833                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst     0.004243                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.001717                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.005960                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst    138.715070                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     56.142209                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.004233                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.001713                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.005947                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst            1                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              1                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            1                       # number of demand (read+write) hits
@@ -346,17 +346,17 @@ system.cpu.l2cache.demand_misses::total           469                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          301                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          168                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          469                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     15708000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      4994000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     20702000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      3821500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      3821500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     15708000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data      8815500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     24523500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     15708000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data      8815500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     24523500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     16152000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      5390000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     21542000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      4007500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      4007500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     16152000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      9397500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     25549500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     16152000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      9397500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     25549500                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst          302                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data           95                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total          397                       # number of ReadReq accesses(hits+misses)
@@ -379,17 +379,17 @@ system.cpu.l2cache.demand_miss_rate::total     0.997872                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996689                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.997872                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52186.046512                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52568.421053                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 52277.777778                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52349.315068                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52349.315068                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52186.046512                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52473.214286                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52288.912580                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52186.046512                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52473.214286                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52288.912580                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53661.129568                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56736.842105                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 54398.989899                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54897.260274                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54897.260274                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53661.129568                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55937.500000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 54476.545842                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53661.129568                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55937.500000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 54476.545842                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -409,17 +409,17 @@ system.cpu.l2cache.demand_mshr_misses::total          469
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          301                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          168                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          469                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     12038500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      3838000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     15876500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      2942500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2942500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     12038500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      6780500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     18819000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     12038500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      6780500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     18819000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     12487000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      4239000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     16726000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3129500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      3129500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     12487000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      7368500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     19855500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     12487000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      7368500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     19855500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.996689                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.997481                       # mshr miss rate for ReadReq accesses
@@ -431,17 +431,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.997872
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996689                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.997872                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39995.016611                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40400                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40092.171717                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40308.219178                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40308.219178                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39995.016611                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40360.119048                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40125.799574                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39995.016611                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40360.119048                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40125.799574                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41485.049834                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44621.052632                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42237.373737                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42869.863014                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42869.863014                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41485.049834                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43860.119048                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42335.820896                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41485.049834                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43860.119048                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42335.820896                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
index 280f44c05..fb11f0585 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
@@ -479,7 +479,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
@@ -511,7 +511,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout
index da5dd186c..809102793 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:05:18
-gem5 started Jun 28 2012 22:09:21
+gem5 compiled Jul  2 2012 08:30:56
+gem5 started Jul  2 2012 09:08:18
 gem5 executing on zizzer
 command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello world!
-Exiting @ tick 12146500 because target called exit()
+Exiting @ tick 12811000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
index 40a9fef11..37f1f46b0 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
@@ -1,52 +1,52 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000012                       # Number of seconds simulated
-sim_ticks                                    12146500                       # Number of ticks simulated
-final_tick                                   12146500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000013                       # Number of seconds simulated
+sim_ticks                                    12811000                       # Number of ticks simulated
+final_tick                                   12811000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 109785                       # Simulator instruction rate (inst/s)
-host_op_rate                                   109750                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              208686624                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 218220                       # Number of bytes of host memory used
-host_seconds                                     0.06                       # Real time elapsed on the host
+host_inst_rate                                  61639                       # Simulator instruction rate (inst/s)
+host_op_rate                                    61622                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              123585600                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 219212                       # Number of bytes of host memory used
+host_seconds                                     0.10                       # Real time elapsed on the host
 sim_insts                                        6386                       # Number of instructions simulated
 sim_ops                                          6386                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst             19968                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data             11264                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                31232                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        19968                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           19968                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                312                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data                176                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                   488                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst           1643930350                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            927345326                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              2571275676                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      1643930350                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         1643930350                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          1643930350                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           927345326                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             2571275676                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst             20096                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data             11200                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                31296                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        20096                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           20096                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                314                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                175                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                   489                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst           1568651940                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            874248693                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              2442900632                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      1568651940                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         1568651940                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          1568651940                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           874248693                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             2442900632                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                         1978                       # DTB read hits
-system.cpu.dtb.read_misses                         49                       # DTB read misses
+system.cpu.dtb.read_hits                         1966                       # DTB read hits
+system.cpu.dtb.read_misses                         45                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                     2027                       # DTB read accesses
+system.cpu.dtb.read_accesses                     2011                       # DTB read accesses
 system.cpu.dtb.write_hits                        1059                       # DTB write hits
-system.cpu.dtb.write_misses                        31                       # DTB write misses
+system.cpu.dtb.write_misses                        28                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                    1090                       # DTB write accesses
-system.cpu.dtb.data_hits                         3037                       # DTB hits
-system.cpu.dtb.data_misses                         80                       # DTB misses
+system.cpu.dtb.write_accesses                    1087                       # DTB write accesses
+system.cpu.dtb.data_hits                         3025                       # DTB hits
+system.cpu.dtb.data_misses                         73                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                     3117                       # DTB accesses
-system.cpu.itb.fetch_hits                        2279                       # ITB hits
-system.cpu.itb.fetch_misses                        30                       # ITB misses
+system.cpu.dtb.data_accesses                     3098                       # DTB accesses
+system.cpu.itb.fetch_hits                        2254                       # ITB hits
+system.cpu.itb.fetch_misses                        39                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                    2309                       # ITB accesses
+system.cpu.itb.fetch_accesses                    2293                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -60,246 +60,246 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   17                       # Number of system calls
-system.cpu.numCycles                            24294                       # number of cpu cycles simulated
+system.cpu.numCycles                            25623                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                     2808                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted               1620                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect                530                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups                  2127                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                      736                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                     2750                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted               1591                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect                527                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups                  2077                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                      748                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                      421                       # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect                  67                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles               7536                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          16063                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        2808                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches               1157                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          2867                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                    1787                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles                    912                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                   23                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles           639                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                      2279                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   349                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              13192                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.217632                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.600569                       # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS                      402                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect                  69                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles               8523                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          15693                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        2750                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches               1150                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                          2817                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                    1761                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles                    996                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                   25                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles           745                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                      2254                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   361                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples              14299                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.097489                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.491166                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                    10325     78.27%     78.27% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                      292      2.21%     80.48% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      224      1.70%     82.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      225      1.71%     83.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      268      2.03%     85.92% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      190      1.44%     87.36% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      268      2.03%     89.39% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      182      1.38%     90.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     1218      9.23%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                    11482     80.30%     80.30% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                      287      2.01%     82.31% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      235      1.64%     83.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      221      1.55%     85.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      257      1.80%     87.29% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      195      1.36%     88.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      267      1.87%     90.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      172      1.20%     91.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                     1183      8.27%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                13192                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.115584                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.661192                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                     8379                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                   934                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      2684                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                    63                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                   1132                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved                  256                       # Number of times decode resolved a branch
+system.cpu.fetch.rateDist::total                14299                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.107325                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.612458                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                     9448                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                  1035                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      2627                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                    79                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                   1110                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved                  255                       # Number of times decode resolved a branch
 system.cpu.decode.BranchMispred                    87                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts                  14824                       # Number of instructions handled by decode
+system.cpu.decode.DecodedInsts                  14531                       # Number of instructions handled by decode
 system.cpu.decode.SquashedInsts                   236                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                   1132                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                     8584                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                     335                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles            357                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      2519                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                   265                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  14111                       # Number of instructions processed by rename
-system.cpu.rename.IQFullEvents                      6                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents                   206                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands               10590                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 17651                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            17634                       # Number of integer rename lookups
+system.cpu.rename.SquashCycles                   1110                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                     9647                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                     356                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles            379                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                      2494                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                   313                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                  13871                       # Number of instructions processed by rename
+system.cpu.rename.IQFullEvents                      7                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents                   268                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands               10378                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 17349                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            17332                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups                17                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps                  4583                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                     6007                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                 33                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts             27                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                       768                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 2619                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                1317                       # Number of stores inserted to the mem dependence unit.
+system.cpu.rename.UndoneMaps                     5795                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                 32                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts             26                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                       762                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                 2605                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                1307                       # Number of stores inserted to the mem dependence unit.
 system.cpu.memDep0.conflictingLoads                 5                       # Number of conflicting loads.
 system.cpu.memDep0.conflictingStores                0                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                      12558                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                  31                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                     10419                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued                44                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined            5861                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined         3437                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             14                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         13192                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.789797                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.411802                       # Number of insts issued each cycle
+system.cpu.iq.iqInstsAdded                      12446                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                  30                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                     10341                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued                37                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined            5740                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined         3350                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             13                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples         14299                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.723197                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.354818                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0                8893     67.41%     67.41% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                1482     11.23%     78.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                1143      8.66%     87.31% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 751      5.69%     93.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 453      3.43%     96.44% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 282      2.14%     98.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 149      1.13%     99.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                  30      0.23%     99.93% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8                   9      0.07%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0                9905     69.27%     69.27% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                1622     11.34%     80.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                1176      8.22%     88.84% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 704      4.92%     93.76% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 444      3.11%     96.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 263      1.84%     98.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 141      0.99%     99.69% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                  34      0.24%     99.93% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                  10      0.07%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           13192                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           14299                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                       8      7.41%      7.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      7.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      7.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      7.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      7.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      7.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      7.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      7.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      7.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      7.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      7.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      7.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      7.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      7.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      7.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      7.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      7.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      7.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      7.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      7.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      7.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      7.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      7.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      7.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      7.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      7.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      7.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      7.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      7.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                     64     59.26%     66.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                    36     33.33%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                       8      7.27%      7.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      7.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      7.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      7.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      7.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      7.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      7.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      7.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      7.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      7.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      7.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      7.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      7.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      7.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      7.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      7.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      7.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      7.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      7.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      7.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      7.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      7.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      7.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      7.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      7.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      7.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      7.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      7.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      7.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                     65     59.09%     66.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    37     33.64%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 2      0.02%      0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                  7046     67.63%     67.65% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    1      0.01%     67.66% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.66% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     67.67% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.67% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.67% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.67% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.67% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.67% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.67% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.67% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.67% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.67% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.67% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.67% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.67% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.67% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.67% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.67% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.67% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.67% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.67% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.67% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.67% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.67% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.67% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.67% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.67% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.67% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 2237     21.47%     89.14% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                1131     10.86%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                  7000     67.69%     67.71% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    1      0.01%     67.72% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.72% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     67.74% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.74% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.74% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.74% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.74% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.74% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.74% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.74% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.74% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.74% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.74% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.74% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.74% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.74% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.74% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.74% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.74% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.74% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.74% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.74% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.74% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.74% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.74% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.74% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.74% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.74% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 2210     21.37%     89.11% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1126     10.89%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                  10419                       # Type of FU issued
-system.cpu.iq.rate                           0.428871                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                         108                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.010366                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              34161                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             18458                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses         9433                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total                  10341                       # Type of FU issued
+system.cpu.iq.rate                           0.403583                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                         110                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.010637                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              35107                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             18223                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses         9409                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                  21                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                 10                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           10                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                  10514                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                  10438                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                      11                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads               65                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads               70                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads         1434                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses            2                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.squashedLoads         1420                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses            4                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread0.memOrderViolation           19                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          452                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores          442                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            1                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                   1132                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                      41                       # Number of cycles IEW is blocking
+system.cpu.iew.iewSquashCycles                   1110                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                      39                       # Number of cycles IEW is blocking
 system.cpu.iew.iewUnblockCycles                     1                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               12672                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts               177                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  2619                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                 1317                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                 31                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispatchedInsts               12564                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts               188                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts                  2605                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                 1307                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                 30                       # Number of dispatched non-speculative instructions
 system.cpu.iew.iewIQFullEvents                      0                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewLSQFullEvents                     0                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.memOrderViolationEvents             19                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect            137                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect          393                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                  530                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                  9845                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                  2040                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts               574                       # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedTakenIncorrect            139                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect          385                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts                  524                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                  9796                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                  2022                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts               545                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                            83                       # number of nop insts executed
-system.cpu.iew.exec_refs                         3133                       # number of memory reference insts executed
+system.cpu.iew.exec_nop                            88                       # number of nop insts executed
+system.cpu.iew.exec_refs                         3112                       # number of memory reference insts executed
 system.cpu.iew.exec_branches                     1595                       # Number of branches executed
-system.cpu.iew.exec_stores                       1093                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.405244                       # Inst execution rate
-system.cpu.iew.wb_sent                           9591                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                          9443                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                      4951                       # num instructions producing a value
-system.cpu.iew.wb_consumers                      6720                       # num instructions consuming a value
+system.cpu.iew.exec_stores                       1090                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.382313                       # Inst execution rate
+system.cpu.iew.wb_sent                           9558                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                          9419                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                      4945                       # num instructions producing a value
+system.cpu.iew.wb_consumers                      6634                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.388697                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.736756                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.367599                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.745402                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts           6403                       # The number of committed instructions
 system.cpu.commit.commitCommittedOps             6403                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts            6261                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts            6160                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              17                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts               447                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        12060                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.530929                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.361741                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts               444                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples        13189                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.485480                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.291478                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0         9314     77.23%     77.23% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1         1447     12.00%     89.23% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          498      4.13%     93.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          252      2.09%     95.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          164      1.36%     96.81% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5           93      0.77%     97.58% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6          106      0.88%     98.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           41      0.34%     98.80% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8          145      1.20%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0        10357     78.53%     78.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         1540     11.68%     90.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          523      3.97%     94.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          223      1.69%     95.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          163      1.24%     97.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          109      0.83%     97.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6          106      0.80%     98.73% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           29      0.22%     98.95% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8          139      1.05%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        12060                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        13189                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts                 6403                       # Number of instructions committed
 system.cpu.commit.committedOps                   6403                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -310,70 +310,70 @@ system.cpu.commit.branches                       1051                       # Nu
 system.cpu.commit.fp_insts                         10                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                      6321                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                  127                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events                   145                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events                   139                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                        24228                       # The number of ROB reads
-system.cpu.rob.rob_writes                       26471                       # The number of ROB writes
-system.cpu.timesIdled                             224                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           11102                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                        25262                       # The number of ROB reads
+system.cpu.rob.rob_writes                       26244                       # The number of ROB writes
+system.cpu.timesIdled                             278                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           11324                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        6386                       # Number of Instructions Simulated
 system.cpu.committedOps                          6386                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total                  6386                       # Number of Instructions Simulated
-system.cpu.cpi                               3.804259                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         3.804259                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.262863                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.262863                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    12506                       # number of integer regfile reads
-system.cpu.int_regfile_writes                    7104                       # number of integer regfile writes
+system.cpu.cpi                               4.012371                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         4.012371                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.249229                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.249229                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                    12434                       # number of integer regfile reads
+system.cpu.int_regfile_writes                    7077                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                         8                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                        2                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                       1                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
 system.cpu.icache.replacements                      0                       # number of replacements
-system.cpu.icache.tagsinuse                161.646618                       # Cycle average of tags in use
-system.cpu.icache.total_refs                     1829                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                    313                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                   5.843450                       # Average number of references to valid blocks.
+system.cpu.icache.tagsinuse                159.968477                       # Cycle average of tags in use
+system.cpu.icache.total_refs                     1800                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    315                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                   5.714286                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     161.646618                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.078929                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.078929                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst         1829                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            1829                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          1829                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             1829                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         1829                       # number of overall hits
-system.cpu.icache.overall_hits::total            1829                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          450                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           450                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          450                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            450                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          450                       # number of overall misses
-system.cpu.icache.overall_misses::total           450                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     15742000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     15742000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     15742000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     15742000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     15742000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     15742000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         2279                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         2279                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         2279                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         2279                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         2279                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         2279                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.197455                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.197455                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.197455                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.197455                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.197455                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.197455                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34982.222222                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 34982.222222                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 34982.222222                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 34982.222222                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 34982.222222                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 34982.222222                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     159.968477                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.078110                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.078110                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst         1800                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            1800                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          1800                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             1800                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         1800                       # number of overall hits
+system.cpu.icache.overall_hits::total            1800                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          454                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           454                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          454                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            454                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          454                       # number of overall misses
+system.cpu.icache.overall_misses::total           454                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     16294000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     16294000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     16294000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     16294000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     16294000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     16294000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         2254                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         2254                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         2254                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         2254                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         2254                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         2254                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.201420                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.201420                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.201420                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.201420                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.201420                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.201420                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35889.867841                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 35889.867841                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 35889.867841                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 35889.867841                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 35889.867841                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 35889.867841                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -382,94 +382,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          137                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          137                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          137                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          137                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          137                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          137                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          313                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          313                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          313                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          313                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          313                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          313                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     11060000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     11060000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     11060000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     11060000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     11060000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     11060000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.137341                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.137341                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.137341                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.137341                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.137341                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.137341                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35335.463259                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35335.463259                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35335.463259                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 35335.463259                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35335.463259                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 35335.463259                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          139                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          139                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          139                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          139                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          139                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          139                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          315                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          315                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          315                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          315                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          315                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          315                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     11617000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     11617000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     11617000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     11617000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     11617000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     11617000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.139752                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.139752                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.139752                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.139752                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.139752                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.139752                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36879.365079                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36879.365079                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36879.365079                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 36879.365079                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36879.365079                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 36879.365079                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.tagsinuse                109.846299                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                     2275                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                    176                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  12.926136                       # Average number of references to valid blocks.
+system.cpu.dcache.tagsinuse                107.786985                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                     2240                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                    174                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  12.873563                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data     109.846299                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.026818                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.026818                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data         1766                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1766                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data          509                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total            509                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          2275                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             2275                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         2275                       # number of overall hits
-system.cpu.dcache.overall_hits::total            2275                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          146                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           146                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data          356                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total          356                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          502                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            502                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          502                       # number of overall misses
-system.cpu.dcache.overall_misses::total           502                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      5337000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      5337000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     12518000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     12518000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     17855000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     17855000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     17855000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     17855000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         1912                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         1912                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.occ_blocks::cpu.data     107.786985                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.026315                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.026315                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data         1734                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1734                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data          506                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total            506                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data          2240                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             2240                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         2240                       # number of overall hits
+system.cpu.dcache.overall_hits::total            2240                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          161                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           161                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data          359                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total          359                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data          520                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            520                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          520                       # number of overall misses
+system.cpu.dcache.overall_misses::total           520                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      6422000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      6422000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     15048500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     15048500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     21470500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     21470500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     21470500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     21470500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         1895                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1895                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          865                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total          865                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         2777                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2777                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         2777                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2777                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.076360                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.076360                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.411561                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.411561                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.180771                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.180771                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.180771                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.180771                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36554.794521                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 36554.794521                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35162.921348                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 35162.921348                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 35567.729084                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 35567.729084                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 35567.729084                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 35567.729084                       # average overall miss latency
+system.cpu.dcache.demand_accesses::cpu.data         2760                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2760                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2760                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2760                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.084960                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.084960                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.415029                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.415029                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.188406                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.188406                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.188406                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.188406                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39888.198758                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 39888.198758                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41917.827298                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 41917.827298                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 41289.423077                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 41289.423077                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 41289.423077                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 41289.423077                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -478,119 +478,119 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data           42                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           42                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data          284                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total          284                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          326                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          326                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          326                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          326                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data          104                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          104                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data           72                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total           72                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data          176                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total          176                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data          176                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total          176                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      3764000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      3764000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      2575000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      2575000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      6339000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      6339000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      6339000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      6339000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.054393                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.054393                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.083237                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.083237                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.063378                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.063378                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.063378                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.063378                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36192.307692                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 36192.307692                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35763.888889                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35763.888889                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36017.045455                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 36017.045455                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36017.045455                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 36017.045455                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           59                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           59                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data          286                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total          286                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          345                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          345                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          345                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          345                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          102                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          102                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data           73                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total           73                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data          175                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total          175                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data          175                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total          175                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4236500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      4236500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      2874500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      2874500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      7111000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      7111000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7111000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      7111000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.053826                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.053826                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.084393                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.084393                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.063406                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.063406                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.063406                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.063406                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 41534.313725                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 41534.313725                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39376.712329                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39376.712329                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 40634.285714                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 40634.285714                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 40634.285714                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 40634.285714                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse               224.380125                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               220.452556                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       1                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                   416                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  0.002404                       # Average number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                   415                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.002410                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst    161.620273                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data     62.759852                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst     0.004932                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.001915                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.006848                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst    159.940532                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     60.512024                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.004881                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.001847                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.006728                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst            1                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              1                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            1                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::total               1                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst            1                       # number of overall hits
 system.cpu.l2cache.overall_hits::total              1                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          312                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data          104                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.inst          314                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data          102                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::total          416                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data           72                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total           72                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          312                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data          176                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total           488                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          312                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data          176                       # number of overall misses
-system.cpu.l2cache.overall_misses::total          488                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     10703000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      3603500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     14306500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      2489000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      2489000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     10703000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data      6092500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     16795500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     10703000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data      6092500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     16795500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          313                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data          104                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_misses::cpu.data           73                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total           73                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          314                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data          175                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total           489                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          314                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data          175                       # number of overall misses
+system.cpu.l2cache.overall_misses::total          489                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     11286500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      4103500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     15390000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      2793500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      2793500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     11286500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      6897000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     18183500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     11286500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      6897000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     18183500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          315                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data          102                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total          417                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data           72                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total           72                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          313                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data          176                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total          489                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          313                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data          176                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total          489                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.996805                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_accesses::cpu.data           73                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total           73                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          315                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data          175                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total          490                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          315                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data          175                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total          490                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.996825                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::total     0.997602                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.996805                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.996825                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.997955                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996805                       # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::total     0.997959                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996825                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.997955                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34304.487179                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34649.038462                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 34390.625000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34569.444444                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34569.444444                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34304.487179                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34616.477273                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 34417.008197                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34304.487179                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34616.477273                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 34417.008197                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total     0.997959                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35944.267516                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 40230.392157                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 36995.192308                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 38267.123288                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 38267.123288                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35944.267516                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 39411.428571                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 37185.071575                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35944.267516                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 39411.428571                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 37185.071575                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -599,50 +599,50 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          312                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          104                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          314                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          102                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::total          416                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           72                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total           72                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          312                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data          176                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total          488                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          312                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data          176                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total          488                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst      9702500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      3275000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     12977500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      2264500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2264500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst      9702500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5539500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     15242000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst      9702500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5539500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     15242000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.996805                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           73                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total           73                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          314                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data          175                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total          489                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          314                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data          175                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total          489                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     10285500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      3793000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     14078500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      2567500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2567500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     10285500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      6360500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     16646000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     10285500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      6360500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     16646000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.996825                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.997602                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.996805                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.996825                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.997955                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996805                       # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.997959                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996825                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.997955                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31097.756410                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31490.384615                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31195.913462                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31451.388889                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31451.388889                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31097.756410                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31474.431818                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31233.606557                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31097.756410                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31474.431818                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31233.606557                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.997959                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32756.369427                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37186.274510                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33842.548077                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35171.232877                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35171.232877                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32756.369427                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36345.714286                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34040.899796                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32756.369427                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36345.714286                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34040.899796                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
index b0aed7d88..4b13e207f 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
@@ -148,7 +148,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
@@ -180,7 +180,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout
index 00df1b420..776a435c2 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun  4 2012 11:50:11
-gem5 started Jun  4 2012 13:52:31
+gem5 compiled Jul  2 2012 08:30:56
+gem5 started Jul  2 2012 09:08:22
 gem5 executing on zizzer
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello world!
-Exiting @ tick 33007000 because target called exit()
+Exiting @ tick 34425000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt
index 0370e845f..a9d405edb 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000033                       # Number of seconds simulated
-sim_ticks                                    33007000                       # Number of ticks simulated
-final_tick                                   33007000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000034                       # Number of seconds simulated
+sim_ticks                                    34425000                       # Number of ticks simulated
+final_tick                                   34425000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 524144                       # Simulator instruction rate (inst/s)
-host_op_rate                                   523337                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2693393609                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 214140                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
+host_inst_rate                                   6722                       # Simulator instruction rate (inst/s)
+host_op_rate                                     6722                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               36133024                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 217168                       # Number of bytes of host memory used
+host_seconds                                     0.95                       # Real time elapsed on the host
 sim_insts                                        6404                       # Number of instructions simulated
 sim_ops                                          6404                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             17792                       # Number of bytes read from this memory
@@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total           17792                       # Nu
 system.physmem.num_reads::cpu.inst                278                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                168                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   446                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            539037174                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            325749084                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               864786257                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       539037174                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          539037174                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           539037174                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           325749084                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              864786257                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            516833696                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            312331155                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               829164851                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       516833696                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          516833696                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           516833696                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           312331155                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              829164851                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -60,7 +60,7 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   17                       # Number of system calls
-system.cpu.numCycles                            66014                       # number of cpu cycles simulated
+system.cpu.numCycles                            68850                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        6404                       # Number of instructions committed
@@ -79,18 +79,18 @@ system.cpu.num_mem_refs                          2060                       # nu
 system.cpu.num_load_insts                        1192                       # Number of load instructions
 system.cpu.num_store_insts                        868                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                      66014                       # Number of busy cycles
+system.cpu.num_busy_cycles                      68850                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                      0                       # number of replacements
-system.cpu.icache.tagsinuse                127.883393                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                128.155444                       # Cycle average of tags in use
 system.cpu.icache.total_refs                     6136                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    279                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                  21.992832                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     127.883393                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.062443                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.062443                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst     128.155444                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.062576                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.062576                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst         6136                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total            6136                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst          6136                       # number of demand (read+write) hits
@@ -161,14 +161,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52849.462366
 system.cpu.icache.overall_avg_mshr_miss_latency::total 52849.462366                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.tagsinuse                103.680615                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse                103.856385                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                     1882                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                    168                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                  11.202381                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data     103.680615                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.025313                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.025313                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::cpu.data     103.856385                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.025356                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.025356                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data         1090                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total            1090                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          792                       # number of WriteReq hits
@@ -259,16 +259,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        53000
 system.cpu.dcache.overall_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse               184.342479                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               184.699061                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       1                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                   373                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.002681                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst    127.900723                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data     56.441756                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst     0.003903                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.001722                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.005626                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst    128.168283                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     56.530778                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.003911                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.001725                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.005637                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst            1                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              1                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            1                       # number of demand (read+write) hits
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
index 3b6b2b818..0de3d5fa0 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
@@ -479,7 +479,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
@@ -511,7 +511,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout
index 2586fc610..07442c5d8 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:05:18
-gem5 started Jun 28 2012 22:09:32
+gem5 compiled Jul  2 2012 08:30:56
+gem5 started Jul  2 2012 09:08:29
 gem5 executing on zizzer
 command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello world!
-Exiting @ tick 6934000 because target called exit()
+Exiting @ tick 7252000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
index 729742f8d..572203942 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000007                       # Number of seconds simulated
-sim_ticks                                     6934000                       # Number of ticks simulated
-final_tick                                    6934000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                     7252000                       # Number of ticks simulated
+final_tick                                    7252000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  29510                       # Simulator instruction rate (inst/s)
-host_op_rate                                    29504                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               85688409                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 217944                       # Number of bytes of host memory used
-host_seconds                                     0.08                       # Real time elapsed on the host
+host_inst_rate                                  57662                       # Simulator instruction rate (inst/s)
+host_op_rate                                    57638                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              175044086                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 217908                       # Number of bytes of host memory used
+host_seconds                                     0.04                       # Real time elapsed on the host
 sim_insts                                        2387                       # Number of instructions simulated
 sim_ops                                          2387                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             12032                       # Number of bytes read from this memory
@@ -19,34 +19,34 @@ system.physmem.bytes_inst_read::total           12032                       # Nu
 system.physmem.num_reads::cpu.inst                188                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                 85                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   273                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst           1735217768                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            784539948                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              2519757716                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      1735217768                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         1735217768                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          1735217768                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           784539948                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             2519757716                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst           1659128516                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            750137893                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              2409266409                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      1659128516                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         1659128516                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          1659128516                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           750137893                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             2409266409                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                          704                       # DTB read hits
-system.cpu.dtb.read_misses                         36                       # DTB read misses
+system.cpu.dtb.read_hits                          712                       # DTB read hits
+system.cpu.dtb.read_misses                         13                       # DTB read misses
 system.cpu.dtb.read_acv                             1                       # DTB read access violations
-system.cpu.dtb.read_accesses                      740                       # DTB read accesses
-system.cpu.dtb.write_hits                         367                       # DTB write hits
-system.cpu.dtb.write_misses                        22                       # DTB write misses
+system.cpu.dtb.read_accesses                      725                       # DTB read accesses
+system.cpu.dtb.write_hits                         368                       # DTB write hits
+system.cpu.dtb.write_misses                        15                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                     389                       # DTB write accesses
-system.cpu.dtb.data_hits                         1071                       # DTB hits
-system.cpu.dtb.data_misses                         58                       # DTB misses
+system.cpu.dtb.write_accesses                     383                       # DTB write accesses
+system.cpu.dtb.data_hits                         1080                       # DTB hits
+system.cpu.dtb.data_misses                         28                       # DTB misses
 system.cpu.dtb.data_acv                             1                       # DTB access violations
-system.cpu.dtb.data_accesses                     1129                       # DTB accesses
-system.cpu.itb.fetch_hits                         999                       # ITB hits
+system.cpu.dtb.data_accesses                     1108                       # DTB accesses
+system.cpu.itb.fetch_hits                        1014                       # ITB hits
 system.cpu.itb.fetch_misses                        30                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                    1029                       # ITB accesses
+system.cpu.itb.fetch_accesses                    1044                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -60,246 +60,246 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                    4                       # Number of system calls
-system.cpu.numCycles                            13869                       # number of cpu cycles simulated
+system.cpu.numCycles                            14505                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                     1119                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted                563                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect                252                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups                   783                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                      216                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                     1131                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted                573                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect                253                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups                   782                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                      218                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                      210                       # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect                  34                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles               3820                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                           6858                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        1119                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches                426                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          1175                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                     850                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles                    242                       # Number of cycles fetch has spent blocked
+system.cpu.BPredUnit.usedRAS                      211                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect                  37                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles               4349                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                           6900                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        1131                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches                429                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                          1183                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                     857                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles                    264                       # Number of cycles fetch has spent blocked
 system.cpu.fetch.MiscStallCycles                   17                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles           783                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                       999                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   170                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples               6611                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.037362                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.461313                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.PendingTrapStallCycles           948                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                      1014                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   172                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples               7341                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.939926                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.361375                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                     5436     82.23%     82.23% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                       51      0.77%     83.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      129      1.95%     84.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                       97      1.47%     86.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      136      2.06%     88.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                       62      0.94%     89.41% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                       66      1.00%     90.41% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                       64      0.97%     91.38% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                      570      8.62%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                     6158     83.89%     83.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                       50      0.68%     84.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      129      1.76%     86.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      101      1.38%     87.70% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      139      1.89%     89.59% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                       62      0.84%     90.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                       66      0.90%     91.34% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                       61      0.83%     92.17% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                      575      7.83%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                 6611                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.080684                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.494484                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                     4718                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                   256                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      1133                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                    10                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                    494                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved                  166                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                    83                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts                   6102                       # Number of instructions handled by decode
+system.cpu.fetch.rateDist::total                 7341                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.077973                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.475698                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                     5395                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                   291                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      1141                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                    13                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                    501                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved                  167                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                    81                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts                   6151                       # Number of instructions handled by decode
 system.cpu.decode.SquashedInsts                   293                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                    494                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                     4814                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                      67                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles            147                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      1046                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                    43                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                   5849                       # Number of instructions processed by rename
-system.cpu.rename.IQFullEvents                     16                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents                    16                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands                4252                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                  6619                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups             6607                       # Number of integer rename lookups
+system.cpu.rename.SquashCycles                    501                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                     5491                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                      66                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles            174                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                      1058                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                    51                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                   5908                       # Number of instructions processed by rename
+system.cpu.rename.IQFullEvents                     21                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents                    20                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands                4280                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                  6676                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups             6664                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups                12                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps                  1768                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                     2484                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps                     2512                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts                  8                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts              6                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                       137                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                  945                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                 472                       # Number of stores inserted to the mem dependence unit.
+system.cpu.rename.skidInsts                       145                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                  960                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                 476                       # Number of stores inserted to the mem dependence unit.
 system.cpu.memDep0.conflictingLoads                 3                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores                3                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                       4975                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.memDep0.conflictingStores                4                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                       5051                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqNonSpecInstsAdded                   6                       # Number of non-speculative instructions added to the IQ
 system.cpu.iq.iqInstsIssued                      4026                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued                68                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined            2372                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined         1428                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedInstsIssued                79                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined            2503                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined         1510                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved              2                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples          6611                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.608985                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.321430                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples          7341                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.548427                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.241979                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0                4990     75.48%     75.48% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                 583      8.82%     84.30% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                 382      5.78%     90.08% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 267      4.04%     94.12% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 192      2.90%     97.02% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 114      1.72%     98.74% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                  53      0.80%     99.55% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                  18      0.27%     99.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8                  12      0.18%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0                5680     77.37%     77.37% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                 617      8.40%     85.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                 387      5.27%     91.05% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 273      3.72%     94.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 198      2.70%     97.47% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 114      1.55%     99.02% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                  56      0.76%     99.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                  10      0.14%     99.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                   6      0.08%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total            6611                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total            7341                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                       4      9.09%      9.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      9.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      9.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      9.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      9.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      9.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      9.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      9.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      9.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      9.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      9.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      9.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      9.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      9.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      9.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      9.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      9.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      9.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      9.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      9.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      9.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      9.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      9.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      9.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      9.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      9.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      9.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      9.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      9.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                     17     38.64%     47.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                    23     52.27%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                       2      4.88%      4.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      4.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      4.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      4.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      4.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      4.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      4.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      4.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      4.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      4.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      4.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      4.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      4.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      4.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      4.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      4.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      4.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      4.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      4.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      4.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      4.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      4.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      4.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      4.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      4.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      4.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      4.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      4.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      4.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                     17     41.46%     46.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    22     53.66%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                  2853     70.86%     70.86% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    1      0.02%     70.89% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     70.89% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     70.89% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     70.89% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     70.89% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     70.89% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     70.89% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     70.89% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     70.89% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     70.89% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     70.89% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     70.89% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     70.89% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     70.89% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     70.89% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     70.89% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     70.89% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     70.89% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     70.89% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     70.89% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     70.89% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     70.89% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     70.89% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     70.89% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     70.89% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     70.89% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     70.89% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     70.89% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                  775     19.25%     90.14% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                 397      9.86%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                  2876     71.44%     71.44% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    1      0.02%     71.46% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     71.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     71.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     71.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     71.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     71.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     71.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     71.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     71.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     71.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     71.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     71.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     71.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     71.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     71.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     71.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     71.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     71.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     71.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     71.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     71.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     71.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     71.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     71.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     71.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     71.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     71.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     71.46% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                  761     18.90%     90.36% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                 388      9.64%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::total                   4026                       # Type of FU issued
-system.cpu.iq.rate                           0.290288                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                          44                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.010929                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              14762                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes              7351                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses         3682                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.rate                           0.277559                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                          41                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.010184                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              15500                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes              7558                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses         3688                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                  13                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                  6                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses            6                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                   4063                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                   4060                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                       7                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads               31                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads               33                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads          530                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads          545                       # Number of loads squashed
 system.cpu.iew.lsq.thread0.ignoredResponses            0                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread0.memOrderViolation            5                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          178                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores          182                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                    494                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                      53                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                     6                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts                5319                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts                96                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                   945                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                  472                       # Number of dispatched store instructions
+system.cpu.iew.iewSquashCycles                    501                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                      55                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                     5                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts                5407                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts                98                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts                   960                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                  476                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts                  6                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                      6                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIQFullEvents                      4                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewLSQFullEvents                     0                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.memOrderViolationEvents              5                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect             54                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect          153                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect             57                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect          150                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.branchMispredicts                  207                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                  3873                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                   741                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts               153                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts                  3874                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                   726                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts               152                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                           338                       # number of nop insts executed
-system.cpu.iew.exec_refs                         1130                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                      650                       # Number of branches executed
-system.cpu.iew.exec_stores                        389                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.279256                       # Inst execution rate
-system.cpu.iew.wb_sent                           3778                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                          3688                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                      1732                       # num instructions producing a value
-system.cpu.iew.wb_consumers                      2249                       # num instructions consuming a value
+system.cpu.iew.exec_nop                           350                       # number of nop insts executed
+system.cpu.iew.exec_refs                         1109                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                      649                       # Number of branches executed
+system.cpu.iew.exec_stores                        383                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.267080                       # Inst execution rate
+system.cpu.iew.wb_sent                           3756                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                          3694                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                      1740                       # num instructions producing a value
+system.cpu.iew.wb_consumers                      2202                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.265917                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.770120                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.254671                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.790191                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts           2576                       # The number of committed instructions
 system.cpu.commit.commitCommittedOps             2576                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts            2738                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts            2822                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls               4                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts               172                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples         6117                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.421121                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.275697                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts               174                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples         6840                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.376608                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.225423                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0         5226     85.43%     85.43% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1          218      3.56%     89.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          319      5.21%     94.21% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          117      1.91%     96.13% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4           69      1.13%     97.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5           56      0.92%     98.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6           32      0.52%     98.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           19      0.31%     99.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8           61      1.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0         5956     87.08%     87.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1          217      3.17%     90.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          318      4.65%     94.90% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          115      1.68%     96.58% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4           67      0.98%     97.56% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5           47      0.69%     98.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6           32      0.47%     98.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           21      0.31%     99.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8           67      0.98%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total         6117                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total         6840                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts                 2576                       # Number of instructions committed
 system.cpu.commit.committedOps                   2576                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -310,69 +310,69 @@ system.cpu.commit.branches                        396                       # Nu
 system.cpu.commit.fp_insts                          6                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                      2367                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                   71                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events                    61                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events                    67                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                        11123                       # The number of ROB reads
-system.cpu.rob.rob_writes                       11131                       # The number of ROB writes
-system.cpu.timesIdled                             138                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                            7258                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                        11924                       # The number of ROB reads
+system.cpu.rob.rob_writes                       11305                       # The number of ROB writes
+system.cpu.timesIdled                             172                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                            7164                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        2387                       # Number of Instructions Simulated
 system.cpu.committedOps                          2387                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total                  2387                       # Number of Instructions Simulated
-system.cpu.cpi                               5.810222                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         5.810222                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.172110                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.172110                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                     4695                       # number of integer regfile reads
-system.cpu.int_regfile_writes                    2856                       # number of integer regfile writes
+system.cpu.cpi                               6.076665                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         6.076665                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.164564                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.164564                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                     4677                       # number of integer regfile reads
+system.cpu.int_regfile_writes                    2861                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                         6                       # number of floating regfile reads
 system.cpu.misc_regfile_reads                       1                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
 system.cpu.icache.replacements                      0                       # number of replacements
-system.cpu.icache.tagsinuse                 93.248355                       # Cycle average of tags in use
-system.cpu.icache.total_refs                      752                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                 94.201337                       # Cycle average of tags in use
+system.cpu.icache.total_refs                      769                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    188                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                          4                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs                   4.090426                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst      93.248355                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.045531                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.045531                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst          752                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total             752                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst           752                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total              752                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst          752                       # number of overall hits
-system.cpu.icache.overall_hits::total             752                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          247                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           247                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          247                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            247                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          247                       # number of overall misses
-system.cpu.icache.overall_misses::total           247                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst      8946000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total      8946000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst      8946000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total      8946000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst      8946000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total      8946000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst          999                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total          999                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst          999                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total          999                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst          999                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total          999                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.247247                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.247247                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.247247                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.247247                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.247247                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.247247                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36218.623482                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 36218.623482                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 36218.623482                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 36218.623482                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 36218.623482                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 36218.623482                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst      94.201337                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.045997                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.045997                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst          769                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total             769                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst           769                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total              769                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst          769                       # number of overall hits
+system.cpu.icache.overall_hits::total             769                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          245                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           245                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          245                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            245                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          245                       # number of overall misses
+system.cpu.icache.overall_misses::total           245                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst      9112500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total      9112500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst      9112500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total      9112500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst      9112500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total      9112500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         1014                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         1014                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         1014                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         1014                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         1014                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         1014                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.241617                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.241617                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.241617                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.241617                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.241617                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.241617                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37193.877551                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 37193.877551                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 37193.877551                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 37193.877551                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 37193.877551                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 37193.877551                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -381,94 +381,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst           59                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total           59                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst           59                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total           59                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst           59                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total           59                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst           57                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total           57                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst           57                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total           57                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst           57                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total           57                       # number of overall MSHR hits
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          188                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total          188                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst          188                       # number of demand (read+write) MSHR misses
 system.cpu.icache.demand_mshr_misses::total          188                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          188                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          188                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst      6660500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total      6660500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst      6660500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total      6660500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst      6660500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total      6660500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.188188                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.188188                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.188188                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.188188                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.188188                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.188188                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35428.191489                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35428.191489                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35428.191489                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 35428.191489                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35428.191489                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 35428.191489                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst      6932500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total      6932500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst      6932500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total      6932500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst      6932500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total      6932500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.185404                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.185404                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.185404                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.185404                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.185404                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.185404                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst        36875                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total        36875                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst        36875                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total        36875                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst        36875                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total        36875                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.tagsinuse                 45.780075                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                      785                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse                 45.851495                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                      774                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                     85                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                   9.235294                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                   9.105882                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data      45.780075                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.011177                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.011177                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data          563                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total             563                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data          222                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total            222                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data           785                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total              785                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data          785                       # number of overall hits
-system.cpu.dcache.overall_hits::total             785                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          110                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           110                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data           72                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total           72                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          182                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            182                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          182                       # number of overall misses
-system.cpu.dcache.overall_misses::total           182                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      3679000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      3679000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data      2813500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      2813500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data      6492500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total      6492500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data      6492500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total      6492500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data          673                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total          673                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.occ_blocks::cpu.data      45.851495                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.011194                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.011194                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data          561                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total             561                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data          213                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total            213                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data           774                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total              774                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data          774                       # number of overall hits
+system.cpu.dcache.overall_hits::total             774                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          118                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           118                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data           81                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total           81                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data          199                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            199                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          199                       # number of overall misses
+system.cpu.dcache.overall_misses::total           199                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      4328500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      4328500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      3561500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      3561500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data      7890000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total      7890000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data      7890000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total      7890000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data          679                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total          679                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          294                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total          294                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data          967                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total          967                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data          967                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total          967                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.163447                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.163447                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.244898                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.244898                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.188211                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.188211                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.188211                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.188211                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33445.454545                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 33445.454545                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39076.388889                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 39076.388889                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 35673.076923                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 35673.076923                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 35673.076923                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 35673.076923                       # average overall miss latency
+system.cpu.dcache.demand_accesses::cpu.data          973                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total          973                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data          973                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total          973                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.173785                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.173785                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.275510                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.275510                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.204522                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.204522                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.204522                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.204522                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36682.203390                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 36682.203390                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43969.135802                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 43969.135802                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 39648.241206                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 39648.241206                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 39648.241206                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 39648.241206                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -477,14 +477,14 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data           49                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           49                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data           48                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total           48                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data           97                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total           97                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data           97                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total           97                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           57                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           57                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data           57                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total           57                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          114                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          114                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          114                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          114                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data           61                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total           61                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data           24                       # number of WriteReq MSHR misses
@@ -493,42 +493,42 @@ system.cpu.dcache.demand_mshr_misses::cpu.data           85
 system.cpu.dcache.demand_mshr_misses::total           85                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data           85                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total           85                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      2166000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      2166000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data       871000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total       871000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      3037000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      3037000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      3037000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      3037000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.090639                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.090639                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      2511500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      2511500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data       981000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total       981000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      3492500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      3492500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      3492500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      3492500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.089838                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.089838                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.081633                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.081633                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.087901                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.087901                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.087901                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.087901                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35508.196721                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35508.196721                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36291.666667                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36291.666667                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35729.411765                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 35729.411765                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35729.411765                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 35729.411765                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.087359                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.087359                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.087359                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.087359                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 41172.131148                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 41172.131148                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        40875                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        40875                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 41088.235294                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 41088.235294                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 41088.235294                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 41088.235294                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse               122.119430                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               123.109780                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       0                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                   249                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                         0                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst     93.334885                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data     28.784545                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst     0.002848                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.000878                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.003727                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst     94.284624                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     28.825156                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.002877                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.000880                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.003757                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_misses::cpu.inst          188                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.data           61                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::total          249                       # number of ReadReq misses
@@ -540,17 +540,17 @@ system.cpu.l2cache.demand_misses::total           273                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          188                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data           85                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          273                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst      6449000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      2098500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total      8547500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data       830000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total       830000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst      6449000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data      2928500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total      9377500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst      6449000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data      2928500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total      9377500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst      6740500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      2447000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total      9187500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data       950000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total       950000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst      6740500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      3397000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     10137500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst      6740500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      3397000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     10137500                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst          188                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data           61                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total          249                       # number of ReadReq accesses(hits+misses)
@@ -573,17 +573,17 @@ system.cpu.l2cache.demand_miss_rate::total            1                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total            1                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34303.191489                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34401.639344                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 34327.309237                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34583.333333                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34583.333333                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34303.191489                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34452.941176                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 34349.816850                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34303.191489                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34452.941176                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 34349.816850                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35853.723404                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 40114.754098                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 36897.590361                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39583.333333                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39583.333333                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35853.723404                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 39964.705882                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 37133.699634                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35853.723404                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 39964.705882                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 37133.699634                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -603,17 +603,17 @@ system.cpu.l2cache.demand_mshr_misses::total          273
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          188                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data           85                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          273                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst      5849000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      1904500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total      7753500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data       755000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total       755000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst      5849000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      2659500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total      8508500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst      5849000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      2659500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total      8508500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst      6136500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      2258000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total      8394500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data       876000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total       876000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst      6136500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      3134000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total      9270500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst      6136500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      3134000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total      9270500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -625,17 +625,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total            1
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31111.702128                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31221.311475                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31138.554217                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31458.333333                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31458.333333                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31111.702128                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31288.235294                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31166.666667                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31111.702128                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31288.235294                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31166.666667                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32640.957447                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37016.393443                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33712.851406                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        36500                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        36500                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32640.957447                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36870.588235                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33957.875458                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32640.957447                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36870.588235                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33957.875458                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini
index 3d54d7382..b94afa836 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini
@@ -148,7 +148,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
@@ -180,7 +180,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout
index 803a08b4e..95893429b 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun  4 2012 11:50:11
-gem5 started Jun  4 2012 14:39:41
+gem5 compiled Jul  2 2012 08:30:56
+gem5 started Jul  2 2012 09:08:33
 gem5 executing on zizzer
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello world!
-Exiting @ tick 16769000 because target called exit()
+Exiting @ tick 17541000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt
index fab613981..aabb78aae 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,13 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000017                       # Number of seconds simulated
-sim_ticks                                    16769000                       # Number of ticks simulated
-final_tick                                   16769000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000018                       # Number of seconds simulated
+sim_ticks                                    17541000                       # Number of ticks simulated
+final_tick                                   17541000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 308591                       # Simulator instruction rate (inst/s)
-host_op_rate                                   307918                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1999557615                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 213304                       # Number of bytes of host memory used
+host_inst_rate                                 207586                       # Simulator instruction rate (inst/s)
+host_op_rate                                   207300                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1409208031                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 216876                       # Number of bytes of host memory used
 host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
@@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total           10432                       # Nu
 system.physmem.num_reads::cpu.inst                163                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                 82                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   245                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            622100304                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            312958435                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               935058739                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       622100304                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          622100304                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           622100304                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           312958435                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              935058739                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            594720940                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            299184767                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               893905707                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       594720940                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          594720940                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           594720940                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           299184767                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              893905707                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -60,7 +60,7 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                    4                       # Number of system calls
-system.cpu.numCycles                            33538                       # number of cpu cycles simulated
+system.cpu.numCycles                            35082                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        2577                       # Number of instructions committed
@@ -79,18 +79,18 @@ system.cpu.num_mem_refs                           717                       # nu
 system.cpu.num_load_insts                         419                       # Number of load instructions
 system.cpu.num_store_insts                        298                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                      33538                       # Number of busy cycles
+system.cpu.num_busy_cycles                      35082                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                      0                       # number of replacements
-system.cpu.icache.tagsinuse                 80.003762                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                 80.027768                       # Cycle average of tags in use
 system.cpu.icache.total_refs                     2423                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    163                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                  14.865031                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst      80.003762                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.039064                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.039064                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst      80.027768                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.039076                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.039076                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst         2423                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total            2423                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst          2423                       # number of demand (read+write) hits
@@ -161,14 +161,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst        53000
 system.cpu.icache.overall_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.tagsinuse                 47.418751                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse                 47.439715                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                      627                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                     82                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                   7.646341                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data      47.418751                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.011577                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.011577                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::cpu.data      47.439715                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.011582                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.011582                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data          360                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total             360                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          267                       # number of WriteReq hits
@@ -259,16 +259,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        53000
 system.cpu.dcache.overall_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse               107.101205                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               107.121835                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       0                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                   218                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                         0                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst     80.120406                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data     26.980800                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst     0.002445                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst     80.139278                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     26.982557                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.002446                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.data     0.000823                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.003268                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.003269                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_misses::cpu.inst          163                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.data           55                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::total          218                       # number of ReadReq misses
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini
index d0f59b4b6..f2874fc12 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini
@@ -556,7 +556,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port
 
@@ -588,7 +588,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout
index c374c028c..3b3dd4083 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout
@@ -1,11 +1,11 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:10:14
-gem5 started Jun 29 2012 00:34:53
+gem5 compiled Jul  2 2012 09:08:16
+gem5 started Jul  2 2012 15:18:47
 gem5 executing on zizzer
 command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing-checker -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing-checker
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
-Exiting @ tick 10305000 because target called exit()
+Exiting @ tick 10843000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
index 9b64fc302..e9752a794 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
@@ -1,32 +1,32 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000010                       # Number of seconds simulated
-sim_ticks                                    10305000                       # Number of ticks simulated
-final_tick                                   10305000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000011                       # Number of seconds simulated
+sim_ticks                                    10843000                       # Number of ticks simulated
+final_tick                                   10843000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  40668                       # Simulator instruction rate (inst/s)
-host_op_rate                                    50741                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               91257316                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 232684                       # Number of bytes of host memory used
-host_seconds                                     0.11                       # Real time elapsed on the host
+host_inst_rate                                  27388                       # Simulator instruction rate (inst/s)
+host_op_rate                                    34173                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               64670790                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 232736                       # Number of bytes of host memory used
+host_seconds                                     0.17                       # Real time elapsed on the host
 sim_insts                                        4591                       # Number of instructions simulated
 sim_ops                                          5729                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst             17664                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst             17600                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data              7872                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                25536                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        17664                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           17664                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                276                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total                25472                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        17600                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           17600                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                275                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                123                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                   399                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst           1714119360                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            763901019                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              2478020378                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      1714119360                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         1714119360                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          1714119360                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           763901019                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             2478020378                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_reads::total                   398                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst           1623167020                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            725998340                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              2349165360                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      1623167020                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         1623167020                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          1623167020                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           725998340                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             2349165360                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.checker.dtb.inst_hits                    0                       # ITB inst hits
 system.cpu.checker.dtb.inst_misses                  0                       # ITB inst misses
 system.cpu.checker.dtb.read_hits                    0                       # DTB read hits
@@ -115,245 +115,245 @@ system.cpu.itb.inst_accesses                        0                       # IT
 system.cpu.itb.hits                                 0                       # DTB hits
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.numCycles                            20611                       # number of cpu cycles simulated
+system.cpu.numCycles                            21687                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                     2522                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted               1857                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect                445                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups                  1967                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                      669                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                     2517                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted               1836                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect                456                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups                  1920                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                      676                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                      255                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.usedRAS                      253                       # Number of times the RAS was used to get a target.
 system.cpu.BPredUnit.RASInCorrect                  57                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles               6205                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          12809                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        2522                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches                924                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          2802                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                    1712                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles                   1810                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.icacheStallCycles               7080                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          12862                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        2517                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches                929                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                          2805                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                    1740                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles                   2260                       # Number of cycles fetch has spent blocked
 system.cpu.fetch.MiscStallCycles                    1                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.CacheLines                      1996                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   298                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              11993                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.366631                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.761460                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines                      1997                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   304                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples              13334                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.230988                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.652427                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                     9191     76.64%     76.64% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                      251      2.09%     78.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      179      1.49%     80.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      222      1.85%     82.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      215      1.79%     83.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      290      2.42%     86.28% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      118      0.98%     87.27% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      119      0.99%     88.26% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     1408     11.74%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                    10529     78.96%     78.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                      255      1.91%     80.88% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      171      1.28%     82.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      221      1.66%     83.82% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      220      1.65%     85.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      289      2.17%     87.63% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      122      0.91%     88.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      119      0.89%     89.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                     1408     10.56%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                11993                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.122362                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.621464                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                     6357                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                  1977                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      2573                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                    70                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                   1016                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved                  444                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                   163                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts                  14344                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                   551                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                   1016                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                     6632                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                     279                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           1507                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      2368                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                   191                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  13444                       # Number of instructions processed by rename
-system.cpu.rename.IQFullEvents                     12                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents                   160                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands               13077                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 61779                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            60371                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups              1408                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total                13334                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.116060                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.593074                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                     7240                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                  2427                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      2551                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                    88                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                   1028                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved                  446                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                   164                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts                  14296                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                   558                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                   1028                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                     7514                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                     500                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           1638                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                      2347                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                   307                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                  13390                       # Number of instructions processed by rename
+system.cpu.rename.IQFullEvents                     19                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents                   246                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands               13047                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 61618                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            60098                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups              1520                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps                  5673                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                     7404                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                 45                       # count of serializing insts renamed
+system.cpu.rename.UndoneMaps                     7374                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                 46                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts             42                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                       627                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 2891                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                1788                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads                40                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores               23                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                      11732                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                  51                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                      9186                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued               117                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined            5655                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined        16152                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             14                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         11993                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.765947                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.466891                       # Number of insts issued each cycle
+system.cpu.rename.skidInsts                       753                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                 2834                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                1819                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads                45                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores               25                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                      11727                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                  53                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                      9087                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued               132                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined            5777                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined        16432                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             16                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples         13334                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.681491                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.365437                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0                8390     69.96%     69.96% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                1302     10.86%     80.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                 789      6.58%     87.39% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 542      4.52%     91.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 463      3.86%     95.77% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 295      2.46%     98.23% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 149      1.24%     99.47% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                  45      0.38%     99.85% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8                  18      0.15%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0                9565     71.73%     71.73% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                1503     11.27%     83.01% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                 815      6.11%     89.12% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 548      4.11%     93.23% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 447      3.35%     96.58% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 275      2.06%     98.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 130      0.97%     99.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                  41      0.31%     99.93% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                  10      0.07%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           11993                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           13334                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                       3      1.38%      1.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      1.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      1.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      1.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      1.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      1.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      1.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      1.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      1.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      1.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      1.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      1.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      1.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      1.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      1.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      1.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      1.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      1.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      1.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      1.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      1.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      1.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      1.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      1.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      1.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      1.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      1.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      1.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      1.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                    150     69.12%     70.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                    64     29.49%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                       6      2.86%      2.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      2.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      2.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      2.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      2.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      2.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      2.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      2.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      2.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      2.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      2.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      2.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      2.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      2.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      2.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      2.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      2.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      2.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      2.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      2.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      2.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      2.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      2.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      2.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      2.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      2.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      2.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      2.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      2.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                    142     67.62%     70.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    62     29.52%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                  5505     59.93%     59.93% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    7      0.08%     60.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     60.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     60.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     60.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     60.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     60.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     60.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     60.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     60.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     60.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     60.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     60.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     60.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     60.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     60.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     60.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     60.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     60.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     60.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     60.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     60.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     60.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     60.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     60.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.03%     60.04% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     60.04% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     60.04% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     60.04% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 2406     26.19%     86.23% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                1265     13.77%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                  5478     60.28%     60.28% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    8      0.09%     60.37% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     60.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     60.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     60.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     60.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     60.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     60.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     60.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     60.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     60.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     60.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     60.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     60.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     60.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     60.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     60.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     60.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     60.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     60.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     60.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     60.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     60.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     60.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     60.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.03%     60.40% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     60.40% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     60.40% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     60.40% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 2349     25.85%     86.26% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1249     13.74%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                   9186                       # Type of FU issued
-system.cpu.iq.rate                           0.445684                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                         217                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.023623                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              30663                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             17408                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses         8220                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total                   9087                       # Type of FU issued
+system.cpu.iq.rate                           0.419007                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                         210                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.023110                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              31814                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             17497                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses         8174                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                  36                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                 46                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_writes                 76                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                   9383                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                   9277                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                      20                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads               64                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads               57                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads         1691                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses            0                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.squashedLoads         1634                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread0.memOrderViolation           19                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          850                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores          881                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                   1016                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                     175                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                    21                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               11783                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts               140                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  2891                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                 1788                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                 39                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                     13                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                     0                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles                   1028                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                     203                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                    24                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts               11780                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts               137                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts                  2834                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                 1819                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                 41                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                     14                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                     1                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.memOrderViolationEvents             19                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect             88                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect          319                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                  407                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                  8719                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                  2169                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts               467                       # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedTakenIncorrect             89                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect          334                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts                  423                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                  8660                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                  2140                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts               427                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                         3377                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                     1400                       # Number of branches executed
-system.cpu.iew.exec_stores                       1208                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.423027                       # Inst execution rate
-system.cpu.iew.wb_sent                           8403                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                          8236                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                      3901                       # num instructions producing a value
-system.cpu.iew.wb_consumers                      7899                       # num instructions consuming a value
+system.cpu.iew.exec_refs                         3344                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                     1407                       # Number of branches executed
+system.cpu.iew.exec_stores                       1204                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.399318                       # Inst execution rate
+system.cpu.iew.wb_sent                           8336                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                          8190                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                      3858                       # num instructions producing a value
+system.cpu.iew.wb_consumers                      7806                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.399592                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.493860                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.377646                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.494235                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts           4591                       # The number of committed instructions
 system.cpu.commit.commitCommittedOps             5729                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts            6053                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts            6051                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              37                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts               355                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        10978                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.521862                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.331986                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts               369                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples        12307                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.465507                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.263835                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0         8629     78.60%     78.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1         1108     10.09%     88.70% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          430      3.92%     92.61% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          264      2.40%     95.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          184      1.68%     96.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5          173      1.58%     98.27% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6           56      0.51%     98.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           40      0.36%     99.14% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8           94      0.86%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0         9888     80.34%     80.34% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         1205      9.79%     90.14% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          432      3.51%     93.65% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          264      2.15%     95.79% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          159      1.29%     97.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          164      1.33%     98.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6           55      0.45%     98.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           38      0.31%     99.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8          102      0.83%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        10978                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        12307                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts                 4591                       # Number of instructions committed
 system.cpu.commit.committedOps                   5729                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -364,69 +364,69 @@ system.cpu.commit.branches                        944                       # Nu
 system.cpu.commit.fp_insts                         16                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                      4976                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                   82                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events                    94                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events                   102                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                        22509                       # The number of ROB reads
-system.cpu.rob.rob_writes                       24591                       # The number of ROB writes
-system.cpu.timesIdled                             178                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                            8618                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                        23828                       # The number of ROB reads
+system.cpu.rob.rob_writes                       24602                       # The number of ROB writes
+system.cpu.timesIdled                             202                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                            8353                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        4591                       # Number of Instructions Simulated
 system.cpu.committedOps                          5729                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total                  4591                       # Number of Instructions Simulated
-system.cpu.cpi                               4.489436                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         4.489436                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.222745                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.222745                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    40006                       # number of integer regfile reads
-system.cpu.int_regfile_writes                    8113                       # number of integer regfile writes
+system.cpu.cpi                               4.723807                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         4.723807                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.211694                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.211694                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                    39657                       # number of integer regfile reads
+system.cpu.int_regfile_writes                    8076                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
-system.cpu.misc_regfile_reads                   15846                       # number of misc regfile reads
+system.cpu.misc_regfile_reads                   15863                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                     24                       # number of misc regfile writes
 system.cpu.icache.replacements                      5                       # number of replacements
-system.cpu.icache.tagsinuse                150.103653                       # Cycle average of tags in use
-system.cpu.icache.total_refs                     1637                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                149.186170                       # Cycle average of tags in use
+system.cpu.icache.total_refs                     1630                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    296                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                   5.530405                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs                   5.506757                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     150.103653                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.073293                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.073293                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst         1637                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            1637                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          1637                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             1637                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         1637                       # number of overall hits
-system.cpu.icache.overall_hits::total            1637                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          359                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           359                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          359                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            359                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          359                       # number of overall misses
-system.cpu.icache.overall_misses::total           359                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     12452500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     12452500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     12452500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     12452500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     12452500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     12452500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         1996                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         1996                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         1996                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         1996                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         1996                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         1996                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.179860                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.179860                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.179860                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.179860                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.179860                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.179860                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34686.629526                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 34686.629526                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 34686.629526                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 34686.629526                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 34686.629526                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 34686.629526                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     149.186170                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.072845                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.072845                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst         1630                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            1630                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          1630                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             1630                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         1630                       # number of overall hits
+system.cpu.icache.overall_hits::total            1630                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          367                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           367                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          367                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            367                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          367                       # number of overall misses
+system.cpu.icache.overall_misses::total           367                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     13154000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     13154000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     13154000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     13154000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     13154000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     13154000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         1997                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         1997                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         1997                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         1997                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         1997                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         1997                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.183776                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.183776                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.183776                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.183776                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.183776                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.183776                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35841.961853                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 35841.961853                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 35841.961853                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 35841.961853                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 35841.961853                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 35841.961853                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -435,110 +435,110 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst           63                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total           63                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst           63                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total           63                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst           63                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total           63                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst           71                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total           71                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst           71                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total           71                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst           71                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total           71                       # number of overall MSHR hits
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          296                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total          296                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst          296                       # number of demand (read+write) MSHR misses
 system.cpu.icache.demand_mshr_misses::total          296                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          296                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          296                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst      9831500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total      9831500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst      9831500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total      9831500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst      9831500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total      9831500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.148297                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.148297                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.148297                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.148297                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.148297                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.148297                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33214.527027                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 33214.527027                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33214.527027                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 33214.527027                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33214.527027                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 33214.527027                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     10405500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     10405500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     10405500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     10405500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     10405500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     10405500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.148222                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.148222                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.148222                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.148222                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.148222                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.148222                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35153.716216                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35153.716216                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35153.716216                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 35153.716216                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35153.716216                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 35153.716216                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.tagsinuse                 87.680549                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                     2445                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse                 86.628845                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                     2404                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                    149                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  16.409396                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                  16.134228                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data      87.680549                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.021406                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.021406                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data         1816                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1816                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data          609                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total            609                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data            9                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total            9                       # number of LoadLockedReq hits
+system.cpu.dcache.occ_blocks::cpu.data      86.628845                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.021150                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.021150                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data         1780                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1780                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data          602                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total            602                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data           11                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total           11                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data           11                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total           11                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data          2425                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             2425                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         2425                       # number of overall hits
-system.cpu.dcache.overall_hits::total            2425                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          173                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           173                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data          304                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total          304                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data          2382                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             2382                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         2382                       # number of overall hits
+system.cpu.dcache.overall_hits::total            2382                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          190                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           190                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data          311                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total          311                       # number of WriteReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            2                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            2                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data          477                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            477                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          477                       # number of overall misses
-system.cpu.dcache.overall_misses::total           477                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      5540500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      5540500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     10913500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     10913500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data          501                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            501                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          501                       # number of overall misses
+system.cpu.dcache.overall_misses::total           501                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      6900500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      6900500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     12710500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     12710500                       # number of WriteReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        76500                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::total        76500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     16454000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     16454000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     16454000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     16454000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         1989                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         1989                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data     19611000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     19611000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     19611000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     19611000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         1970                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1970                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          913                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total          913                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data           11                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total           11                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data           13                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total           13                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data           11                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total           11                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         2902                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2902                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         2902                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2902                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.086978                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.086978                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.332968                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.332968                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.181818                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.181818                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.164369                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.164369                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.164369                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.164369                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32026.011561                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 32026.011561                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35899.671053                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 35899.671053                       # average WriteReq miss latency
+system.cpu.dcache.demand_accesses::cpu.data         2883                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2883                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2883                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2883                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.096447                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.096447                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.340635                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.340635                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.153846                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.153846                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.173777                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.173777                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.173777                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.173777                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36318.421053                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 36318.421053                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40869.774920                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 40869.774920                       # average WriteReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        38250                       # average LoadLockedReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        38250                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 34494.758910                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 34494.758910                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 34494.758910                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 34494.758910                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 39143.712575                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 39143.712575                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 39143.712575                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 39143.712575                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -547,16 +547,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data           66                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           66                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data          262                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total          262                       # number of WriteReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           83                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           83                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data          269                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total          269                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            2                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total            2                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          328                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          328                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          328                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          328                       # number of overall MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          352                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          352                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          352                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          352                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data          107                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total          107                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data           42                       # number of WriteReq MSHR misses
@@ -565,73 +565,73 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          149
 system.cpu.dcache.demand_mshr_misses::total          149                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          149                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          149                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      3133500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      3133500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      1505500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      1505500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      4639000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      4639000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      4639000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      4639000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.053796                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.053796                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      3667500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      3667500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      1713000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      1713000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      5380500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      5380500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      5380500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      5380500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.054315                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.054315                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.046002                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.046002                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.051344                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.051344                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.051344                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.051344                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29285.046729                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29285.046729                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35845.238095                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35845.238095                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31134.228188                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 31134.228188                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31134.228188                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 31134.228188                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.051682                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.051682                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.051682                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.051682                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34275.700935                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34275.700935                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40785.714286                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40785.714286                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36110.738255                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 36110.738255                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36110.738255                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 36110.738255                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse               188.762510                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                      42                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                   357                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  0.117647                       # Average number of references to valid blocks.
+system.cpu.l2cache.tagsinuse               186.552400                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                      41                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                   356                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.115169                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst    142.243584                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data     46.518926                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst     0.004341                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.001420                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.005761                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst           20                       # number of ReadReq hits
+system.cpu.l2cache.occ_blocks::cpu.inst    140.494709                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     46.057690                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.004288                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.001406                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.005693                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst           19                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data           22                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total             42                       # number of ReadReq hits
-system.cpu.l2cache.demand_hits::cpu.inst           20                       # number of demand (read+write) hits
+system.cpu.l2cache.ReadReq_hits::total             41                       # number of ReadReq hits
+system.cpu.l2cache.demand_hits::cpu.inst           19                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.data           22                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total              42                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst           20                       # number of overall hits
+system.cpu.l2cache.demand_hits::total              41                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst           19                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.data           22                       # number of overall hits
-system.cpu.l2cache.overall_hits::total             42                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          276                       # number of ReadReq misses
+system.cpu.l2cache.overall_hits::total             41                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          277                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.data           85                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total          361                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total          362                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data           42                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total           42                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          276                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst          277                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.data          127                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total           403                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          276                       # number of overall misses
+system.cpu.l2cache.demand_misses::total           404                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          277                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          127                       # number of overall misses
-system.cpu.l2cache.overall_misses::total          403                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst      9473000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      2933000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     12406000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      1449000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      1449000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst      9473000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data      4382000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     13855000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst      9473000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data      4382000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     13855000                       # number of overall miss cycles
+system.cpu.l2cache.overall_misses::total          404                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst      9973000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      3362000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     13335000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      1665500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      1665500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst      9973000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      5027500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     15000500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst      9973000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      5027500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     15000500                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst          296                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data          107                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total          403                       # number of ReadReq accesses(hits+misses)
@@ -643,28 +643,28 @@ system.cpu.l2cache.demand_accesses::total          445                       # n
 system.cpu.l2cache.overall_accesses::cpu.inst          296                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data          149                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total          445                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.932432                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.935811                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.794393                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.895782                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.898263                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.932432                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.935811                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.852349                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.905618                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.932432                       # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::total     0.907865                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.935811                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.852349                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.905618                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34322.463768                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34505.882353                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 34365.650970                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        34500                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total        34500                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34322.463768                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34503.937008                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 34379.652605                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34322.463768                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34503.937008                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 34379.652605                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total     0.907865                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36003.610108                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 39552.941176                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 36837.016575                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39654.761905                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39654.761905                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36003.610108                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 39586.614173                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 37129.950495                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36003.610108                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 39586.614173                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 37129.950495                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -673,56 +673,59 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            2                       # number of ReadReq MSHR hits
 system.cpu.l2cache.ReadReq_mshr_hits::cpu.data            4                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total            4                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total            6                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst            2                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.data            4                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total            4                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total            6                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst            2                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.data            4                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total            4                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          276                       # number of ReadReq MSHR misses
+system.cpu.l2cache.overall_mshr_hits::total            6                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          275                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           81                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total          357                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total          356                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           42                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total           42                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          276                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          275                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data          123                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total          399                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          276                       # number of overall MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total          398                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          275                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          123                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total          399                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst      8590000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      2552500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     11142500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      1317000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      1317000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst      8590000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      3869500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     12459500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst      8590000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      3869500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     12459500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.932432                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.overall_mshr_misses::total          398                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst      9090000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      2983000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     12073000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      1532500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      1532500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst      9090000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      4515500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     13605500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst      9090000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      4515500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     13605500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.929054                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.757009                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.885856                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.883375                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.932432                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.929054                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.825503                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.896629                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.932432                       # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.894382                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.929054                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.825503                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.896629                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31123.188406                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31512.345679                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31211.484594                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31357.142857                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31357.142857                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31123.188406                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31459.349593                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31226.817043                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31123.188406                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31459.349593                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31226.817043                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.894382                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33054.545455                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 36827.160494                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33912.921348                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36488.095238                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36488.095238                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33054.545455                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36711.382114                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34184.673367                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33054.545455                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36711.382114                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34184.673367                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
index 693c71c0c..9e38ceef5 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
@@ -497,7 +497,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
@@ -529,7 +529,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout
index 8b9162b5e..b7b5be837 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout
@@ -1,11 +1,11 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:10:14
-gem5 started Jun 29 2012 00:34:42
+gem5 compiled Jul  2 2012 09:08:16
+gem5 started Jul  2 2012 15:18:36
 gem5 executing on zizzer
 command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
-Exiting @ tick 10305000 because target called exit()
+Exiting @ tick 10843000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
index e182dd250..260f325f8 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
@@ -1,32 +1,32 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000010                       # Number of seconds simulated
-sim_ticks                                    10305000                       # Number of ticks simulated
-final_tick                                   10305000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000011                       # Number of seconds simulated
+sim_ticks                                    10843000                       # Number of ticks simulated
+final_tick                                   10843000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  29768                       # Simulator instruction rate (inst/s)
-host_op_rate                                    37142                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               66801597                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 232684                       # Number of bytes of host memory used
-host_seconds                                     0.15                       # Real time elapsed on the host
+host_inst_rate                                  17631                       # Simulator instruction rate (inst/s)
+host_op_rate                                    22000                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               41635778                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 232604                       # Number of bytes of host memory used
+host_seconds                                     0.26                       # Real time elapsed on the host
 sim_insts                                        4591                       # Number of instructions simulated
 sim_ops                                          5729                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst             17664                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst             17600                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data              7872                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                25536                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        17664                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           17664                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                276                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total                25472                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        17600                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           17600                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                275                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                123                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                   399                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst           1714119360                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            763901019                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              2478020378                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      1714119360                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         1714119360                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          1714119360                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           763901019                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             2478020378                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_reads::total                   398                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst           1623167020                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            725998340                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              2349165360                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      1623167020                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         1623167020                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          1623167020                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           725998340                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             2349165360                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -70,245 +70,245 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                   13                       # Number of system calls
-system.cpu.numCycles                            20611                       # number of cpu cycles simulated
+system.cpu.numCycles                            21687                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                     2522                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted               1857                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect                445                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups                  1967                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                      669                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                     2517                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted               1836                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect                456                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups                  1920                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                      676                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                      255                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.usedRAS                      253                       # Number of times the RAS was used to get a target.
 system.cpu.BPredUnit.RASInCorrect                  57                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles               6205                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          12809                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        2522                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches                924                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          2802                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                    1712                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles                   1810                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.icacheStallCycles               7080                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          12862                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        2517                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches                929                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                          2805                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                    1740                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles                   2260                       # Number of cycles fetch has spent blocked
 system.cpu.fetch.MiscStallCycles                    1                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.CacheLines                      1996                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   298                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              11993                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.366631                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.761460                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines                      1997                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   304                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples              13334                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.230988                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.652427                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                     9191     76.64%     76.64% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                      251      2.09%     78.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      179      1.49%     80.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      222      1.85%     82.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      215      1.79%     83.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      290      2.42%     86.28% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      118      0.98%     87.27% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      119      0.99%     88.26% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     1408     11.74%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                    10529     78.96%     78.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                      255      1.91%     80.88% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      171      1.28%     82.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      221      1.66%     83.82% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      220      1.65%     85.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      289      2.17%     87.63% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      122      0.91%     88.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      119      0.89%     89.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                     1408     10.56%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                11993                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.122362                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.621464                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                     6357                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                  1977                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      2573                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                    70                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                   1016                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved                  444                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                   163                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts                  14344                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                   551                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                   1016                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                     6632                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                     279                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           1507                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      2368                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                   191                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  13444                       # Number of instructions processed by rename
-system.cpu.rename.IQFullEvents                     12                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents                   160                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands               13077                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 61779                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            60371                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups              1408                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total                13334                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.116060                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.593074                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                     7240                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                  2427                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      2551                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                    88                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                   1028                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved                  446                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                   164                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts                  14296                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                   558                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                   1028                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                     7514                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                     500                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           1638                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                      2347                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                   307                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                  13390                       # Number of instructions processed by rename
+system.cpu.rename.IQFullEvents                     19                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents                   246                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands               13047                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 61618                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            60098                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups              1520                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps                  5673                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                     7404                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                 45                       # count of serializing insts renamed
+system.cpu.rename.UndoneMaps                     7374                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                 46                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts             42                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                       627                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 2891                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                1788                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads                40                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores               23                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                      11732                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                  51                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                      9186                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued               117                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined            5655                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined        16152                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             14                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         11993                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.765947                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.466891                       # Number of insts issued each cycle
+system.cpu.rename.skidInsts                       753                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                 2834                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                1819                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads                45                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores               25                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                      11727                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                  53                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                      9087                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued               132                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined            5777                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined        16432                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             16                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples         13334                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.681491                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.365437                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0                8390     69.96%     69.96% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                1302     10.86%     80.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                 789      6.58%     87.39% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 542      4.52%     91.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 463      3.86%     95.77% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 295      2.46%     98.23% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 149      1.24%     99.47% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                  45      0.38%     99.85% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8                  18      0.15%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0                9565     71.73%     71.73% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                1503     11.27%     83.01% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                 815      6.11%     89.12% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 548      4.11%     93.23% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 447      3.35%     96.58% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 275      2.06%     98.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 130      0.97%     99.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                  41      0.31%     99.93% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                  10      0.07%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           11993                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           13334                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                       3      1.38%      1.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      1.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      1.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      1.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      1.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      1.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      1.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      1.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      1.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      1.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      1.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      1.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      1.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      1.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      1.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      1.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      1.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      1.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      1.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      1.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      1.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      1.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      1.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      1.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      1.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      1.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      1.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      1.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      1.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                    150     69.12%     70.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                    64     29.49%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                       6      2.86%      2.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      2.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      2.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      2.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      2.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      2.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      2.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      2.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      2.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      2.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      2.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      2.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      2.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      2.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      2.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      2.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      2.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      2.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      2.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      2.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      2.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      2.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      2.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      2.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      2.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      2.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      2.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      2.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      2.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                    142     67.62%     70.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    62     29.52%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                  5505     59.93%     59.93% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    7      0.08%     60.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     60.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     60.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     60.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     60.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     60.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     60.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     60.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     60.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     60.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     60.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     60.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     60.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     60.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     60.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     60.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     60.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     60.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     60.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     60.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     60.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     60.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     60.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     60.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.03%     60.04% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     60.04% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     60.04% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     60.04% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 2406     26.19%     86.23% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                1265     13.77%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                  5478     60.28%     60.28% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    8      0.09%     60.37% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     60.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     60.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     60.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     60.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     60.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     60.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     60.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     60.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     60.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     60.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     60.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     60.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     60.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     60.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     60.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     60.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     60.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     60.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     60.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     60.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     60.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     60.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     60.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.03%     60.40% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     60.40% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     60.40% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     60.40% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 2349     25.85%     86.26% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1249     13.74%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                   9186                       # Type of FU issued
-system.cpu.iq.rate                           0.445684                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                         217                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.023623                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              30663                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             17408                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses         8220                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total                   9087                       # Type of FU issued
+system.cpu.iq.rate                           0.419007                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                         210                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.023110                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              31814                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             17497                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses         8174                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                  36                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                 46                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_writes                 76                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                   9383                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                   9277                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                      20                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads               64                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads               57                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads         1691                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses            0                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.squashedLoads         1634                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread0.memOrderViolation           19                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          850                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores          881                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                   1016                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                     175                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                    21                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               11783                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts               140                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  2891                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                 1788                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                 39                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                     13                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                     0                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles                   1028                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                     203                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                    24                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts               11780                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts               137                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts                  2834                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                 1819                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                 41                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                     14                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                     1                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.memOrderViolationEvents             19                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect             88                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect          319                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                  407                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                  8719                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                  2169                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts               467                       # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedTakenIncorrect             89                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect          334                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts                  423                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                  8660                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                  2140                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts               427                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                         3377                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                     1400                       # Number of branches executed
-system.cpu.iew.exec_stores                       1208                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.423027                       # Inst execution rate
-system.cpu.iew.wb_sent                           8403                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                          8236                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                      3901                       # num instructions producing a value
-system.cpu.iew.wb_consumers                      7899                       # num instructions consuming a value
+system.cpu.iew.exec_refs                         3344                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                     1407                       # Number of branches executed
+system.cpu.iew.exec_stores                       1204                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.399318                       # Inst execution rate
+system.cpu.iew.wb_sent                           8336                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                          8190                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                      3858                       # num instructions producing a value
+system.cpu.iew.wb_consumers                      7806                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.399592                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.493860                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.377646                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.494235                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts           4591                       # The number of committed instructions
 system.cpu.commit.commitCommittedOps             5729                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts            6053                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts            6051                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              37                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts               355                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        10978                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.521862                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.331986                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts               369                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples        12307                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.465507                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.263835                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0         8629     78.60%     78.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1         1108     10.09%     88.70% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          430      3.92%     92.61% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          264      2.40%     95.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          184      1.68%     96.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5          173      1.58%     98.27% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6           56      0.51%     98.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           40      0.36%     99.14% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8           94      0.86%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0         9888     80.34%     80.34% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         1205      9.79%     90.14% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          432      3.51%     93.65% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          264      2.15%     95.79% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          159      1.29%     97.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          164      1.33%     98.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6           55      0.45%     98.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           38      0.31%     99.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8          102      0.83%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        10978                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        12307                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts                 4591                       # Number of instructions committed
 system.cpu.commit.committedOps                   5729                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -319,69 +319,69 @@ system.cpu.commit.branches                        944                       # Nu
 system.cpu.commit.fp_insts                         16                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                      4976                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                   82                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events                    94                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events                   102                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                        22509                       # The number of ROB reads
-system.cpu.rob.rob_writes                       24591                       # The number of ROB writes
-system.cpu.timesIdled                             178                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                            8618                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                        23828                       # The number of ROB reads
+system.cpu.rob.rob_writes                       24602                       # The number of ROB writes
+system.cpu.timesIdled                             202                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                            8353                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        4591                       # Number of Instructions Simulated
 system.cpu.committedOps                          5729                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total                  4591                       # Number of Instructions Simulated
-system.cpu.cpi                               4.489436                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         4.489436                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.222745                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.222745                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    40006                       # number of integer regfile reads
-system.cpu.int_regfile_writes                    8113                       # number of integer regfile writes
+system.cpu.cpi                               4.723807                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         4.723807                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.211694                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.211694                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                    39657                       # number of integer regfile reads
+system.cpu.int_regfile_writes                    8076                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
-system.cpu.misc_regfile_reads                   15846                       # number of misc regfile reads
+system.cpu.misc_regfile_reads                   15863                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                     24                       # number of misc regfile writes
 system.cpu.icache.replacements                      5                       # number of replacements
-system.cpu.icache.tagsinuse                150.103653                       # Cycle average of tags in use
-system.cpu.icache.total_refs                     1637                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                149.186170                       # Cycle average of tags in use
+system.cpu.icache.total_refs                     1630                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    296                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                   5.530405                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs                   5.506757                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     150.103653                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.073293                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.073293                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst         1637                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            1637                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          1637                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             1637                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         1637                       # number of overall hits
-system.cpu.icache.overall_hits::total            1637                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          359                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           359                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          359                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            359                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          359                       # number of overall misses
-system.cpu.icache.overall_misses::total           359                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     12452500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     12452500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     12452500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     12452500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     12452500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     12452500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         1996                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         1996                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         1996                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         1996                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         1996                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         1996                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.179860                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.179860                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.179860                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.179860                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.179860                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.179860                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34686.629526                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 34686.629526                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 34686.629526                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 34686.629526                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 34686.629526                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 34686.629526                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     149.186170                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.072845                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.072845                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst         1630                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            1630                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          1630                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             1630                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         1630                       # number of overall hits
+system.cpu.icache.overall_hits::total            1630                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          367                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           367                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          367                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            367                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          367                       # number of overall misses
+system.cpu.icache.overall_misses::total           367                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     13154000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     13154000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     13154000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     13154000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     13154000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     13154000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         1997                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         1997                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         1997                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         1997                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         1997                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         1997                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.183776                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.183776                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.183776                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.183776                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.183776                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.183776                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35841.961853                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 35841.961853                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 35841.961853                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 35841.961853                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 35841.961853                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 35841.961853                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -390,110 +390,110 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst           63                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total           63                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst           63                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total           63                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst           63                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total           63                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst           71                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total           71                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst           71                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total           71                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst           71                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total           71                       # number of overall MSHR hits
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          296                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total          296                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst          296                       # number of demand (read+write) MSHR misses
 system.cpu.icache.demand_mshr_misses::total          296                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          296                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          296                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst      9831500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total      9831500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst      9831500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total      9831500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst      9831500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total      9831500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.148297                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.148297                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.148297                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.148297                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.148297                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.148297                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33214.527027                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 33214.527027                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33214.527027                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 33214.527027                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33214.527027                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 33214.527027                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     10405500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     10405500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     10405500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     10405500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     10405500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     10405500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.148222                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.148222                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.148222                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.148222                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.148222                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.148222                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35153.716216                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35153.716216                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35153.716216                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 35153.716216                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35153.716216                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 35153.716216                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.tagsinuse                 87.680549                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                     2445                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse                 86.628845                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                     2404                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                    149                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  16.409396                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                  16.134228                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data      87.680549                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.021406                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.021406                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data         1816                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1816                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data          609                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total            609                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data            9                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total            9                       # number of LoadLockedReq hits
+system.cpu.dcache.occ_blocks::cpu.data      86.628845                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.021150                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.021150                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data         1780                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1780                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data          602                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total            602                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data           11                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total           11                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data           11                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total           11                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data          2425                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             2425                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         2425                       # number of overall hits
-system.cpu.dcache.overall_hits::total            2425                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          173                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           173                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data          304                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total          304                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data          2382                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             2382                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         2382                       # number of overall hits
+system.cpu.dcache.overall_hits::total            2382                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          190                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           190                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data          311                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total          311                       # number of WriteReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            2                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            2                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data          477                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            477                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          477                       # number of overall misses
-system.cpu.dcache.overall_misses::total           477                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      5540500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      5540500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     10913500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     10913500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data          501                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            501                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          501                       # number of overall misses
+system.cpu.dcache.overall_misses::total           501                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      6900500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      6900500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     12710500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     12710500                       # number of WriteReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        76500                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::total        76500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     16454000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     16454000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     16454000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     16454000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         1989                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         1989                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data     19611000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     19611000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     19611000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     19611000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         1970                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1970                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          913                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total          913                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data           11                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total           11                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data           13                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total           13                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data           11                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total           11                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         2902                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2902                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         2902                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2902                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.086978                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.086978                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.332968                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.332968                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.181818                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.181818                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.164369                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.164369                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.164369                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.164369                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32026.011561                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 32026.011561                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35899.671053                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 35899.671053                       # average WriteReq miss latency
+system.cpu.dcache.demand_accesses::cpu.data         2883                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2883                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2883                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2883                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.096447                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.096447                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.340635                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.340635                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.153846                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.153846                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.173777                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.173777                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.173777                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.173777                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36318.421053                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 36318.421053                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40869.774920                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 40869.774920                       # average WriteReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        38250                       # average LoadLockedReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        38250                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 34494.758910                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 34494.758910                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 34494.758910                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 34494.758910                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 39143.712575                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 39143.712575                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 39143.712575                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 39143.712575                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -502,16 +502,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data           66                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           66                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data          262                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total          262                       # number of WriteReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           83                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           83                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data          269                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total          269                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            2                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total            2                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          328                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          328                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          328                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          328                       # number of overall MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          352                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          352                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          352                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          352                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data          107                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total          107                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data           42                       # number of WriteReq MSHR misses
@@ -520,73 +520,73 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          149
 system.cpu.dcache.demand_mshr_misses::total          149                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          149                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          149                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      3133500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      3133500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      1505500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      1505500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      4639000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      4639000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      4639000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      4639000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.053796                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.053796                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      3667500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      3667500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      1713000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      1713000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      5380500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      5380500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      5380500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      5380500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.054315                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.054315                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.046002                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.046002                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.051344                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.051344                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.051344                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.051344                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29285.046729                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29285.046729                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35845.238095                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35845.238095                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31134.228188                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 31134.228188                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31134.228188                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 31134.228188                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.051682                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.051682                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.051682                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.051682                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34275.700935                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34275.700935                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40785.714286                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40785.714286                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36110.738255                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 36110.738255                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36110.738255                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 36110.738255                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse               188.762510                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                      42                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                   357                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  0.117647                       # Average number of references to valid blocks.
+system.cpu.l2cache.tagsinuse               186.552400                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                      41                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                   356                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.115169                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst    142.243584                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data     46.518926                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst     0.004341                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.001420                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.005761                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst           20                       # number of ReadReq hits
+system.cpu.l2cache.occ_blocks::cpu.inst    140.494709                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     46.057690                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.004288                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.001406                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.005693                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst           19                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data           22                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total             42                       # number of ReadReq hits
-system.cpu.l2cache.demand_hits::cpu.inst           20                       # number of demand (read+write) hits
+system.cpu.l2cache.ReadReq_hits::total             41                       # number of ReadReq hits
+system.cpu.l2cache.demand_hits::cpu.inst           19                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.data           22                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total              42                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst           20                       # number of overall hits
+system.cpu.l2cache.demand_hits::total              41                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst           19                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.data           22                       # number of overall hits
-system.cpu.l2cache.overall_hits::total             42                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          276                       # number of ReadReq misses
+system.cpu.l2cache.overall_hits::total             41                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          277                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.data           85                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total          361                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total          362                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data           42                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total           42                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          276                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst          277                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.data          127                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total           403                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          276                       # number of overall misses
+system.cpu.l2cache.demand_misses::total           404                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          277                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          127                       # number of overall misses
-system.cpu.l2cache.overall_misses::total          403                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst      9473000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      2933000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     12406000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      1449000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      1449000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst      9473000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data      4382000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     13855000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst      9473000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data      4382000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     13855000                       # number of overall miss cycles
+system.cpu.l2cache.overall_misses::total          404                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst      9973000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      3362000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     13335000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      1665500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      1665500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst      9973000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      5027500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     15000500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst      9973000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      5027500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     15000500                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst          296                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data          107                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total          403                       # number of ReadReq accesses(hits+misses)
@@ -598,28 +598,28 @@ system.cpu.l2cache.demand_accesses::total          445                       # n
 system.cpu.l2cache.overall_accesses::cpu.inst          296                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data          149                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total          445                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.932432                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.935811                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.794393                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.895782                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.898263                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.932432                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.935811                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.852349                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.905618                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.932432                       # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::total     0.907865                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.935811                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.852349                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.905618                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34322.463768                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34505.882353                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 34365.650970                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        34500                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total        34500                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34322.463768                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34503.937008                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 34379.652605                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34322.463768                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34503.937008                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 34379.652605                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total     0.907865                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36003.610108                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 39552.941176                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 36837.016575                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39654.761905                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39654.761905                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36003.610108                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 39586.614173                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 37129.950495                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36003.610108                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 39586.614173                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 37129.950495                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -628,56 +628,59 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            2                       # number of ReadReq MSHR hits
 system.cpu.l2cache.ReadReq_mshr_hits::cpu.data            4                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total            4                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total            6                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst            2                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.data            4                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total            4                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total            6                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst            2                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.data            4                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total            4                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          276                       # number of ReadReq MSHR misses
+system.cpu.l2cache.overall_mshr_hits::total            6                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          275                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           81                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total          357                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total          356                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           42                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total           42                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          276                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          275                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data          123                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total          399                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          276                       # number of overall MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total          398                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          275                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          123                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total          399                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst      8590000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      2552500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     11142500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      1317000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      1317000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst      8590000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      3869500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     12459500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst      8590000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      3869500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     12459500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.932432                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.overall_mshr_misses::total          398                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst      9090000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      2983000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     12073000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      1532500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      1532500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst      9090000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      4515500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     13605500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst      9090000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      4515500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     13605500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.929054                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.757009                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.885856                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.883375                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.932432                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.929054                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.825503                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.896629                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.932432                       # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.894382                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.929054                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.825503                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.896629                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31123.188406                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31512.345679                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31211.484594                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31357.142857                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31357.142857                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31123.188406                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31459.349593                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31226.817043                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31123.188406                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31459.349593                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31226.817043                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.894382                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33054.545455                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 36827.160494                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33912.921348                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36488.095238                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36488.095238                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33054.545455                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36711.382114                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34184.673367                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33054.545455                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36711.382114                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34184.673367                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini
index 89402c0d8..e19a07626 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini
@@ -166,7 +166,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
@@ -198,7 +198,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout
index d4a066c4f..16fea9a8f 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout
@@ -1,11 +1,11 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:10:14
-gem5 started Jun 29 2012 00:35:26
+gem5 compiled Jul  2 2012 09:08:16
+gem5 started Jul  2 2012 15:19:21
 gem5 executing on zizzer
 command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
-Exiting @ tick 26351000 because target called exit()
+Exiting @ tick 27316000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
index bac15b503..0ed449cb9 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
@@ -1,13 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000026                       # Number of seconds simulated
-sim_ticks                                    26351000                       # Number of ticks simulated
-final_tick                                   26351000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000027                       # Number of seconds simulated
+sim_ticks                                    27316000                       # Number of ticks simulated
+final_tick                                   27316000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  50718                       # Simulator instruction rate (inst/s)
-host_op_rate                                    63005                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              292657577                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 231660                       # Number of bytes of host memory used
+host_inst_rate                                  53670                       # Simulator instruction rate (inst/s)
+host_op_rate                                    66671                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              321019881                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 231588                       # Number of bytes of host memory used
 host_seconds                                     0.09                       # Real time elapsed on the host
 sim_insts                                        4565                       # Number of instructions simulated
 sim_ops                                          5672                       # Number of ops (including micro ops) simulated
@@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total           14400                       # Nu
 system.physmem.num_reads::cpu.inst                225                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                125                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   350                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            546468825                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            303593792                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               850062616                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       546468825                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          546468825                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           546468825                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           303593792                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              850062616                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            527163567                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            292868648                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               820032216                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       527163567                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          527163567                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           527163567                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           292868648                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              820032216                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -70,7 +70,7 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                   13                       # Number of system calls
-system.cpu.numCycles                            52702                       # number of cpu cycles simulated
+system.cpu.numCycles                            54632                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        4565                       # Number of instructions committed
@@ -89,18 +89,18 @@ system.cpu.num_mem_refs                          2138                       # nu
 system.cpu.num_load_insts                        1200                       # Number of load instructions
 system.cpu.num_store_insts                        938                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                      52702                       # Number of busy cycles
+system.cpu.num_busy_cycles                      54632                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                      1                       # number of replacements
-system.cpu.icache.tagsinuse                114.562374                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                114.832264                       # Cycle average of tags in use
 system.cpu.icache.total_refs                     4364                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    241                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                  18.107884                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     114.562374                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.055939                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.055939                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst     114.832264                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.056070                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.056070                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst         4364                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total            4364                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst          4364                       # number of demand (read+write) hits
@@ -171,14 +171,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50211.618257
 system.cpu.icache.overall_avg_mshr_miss_latency::total 50211.618257                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.tagsinuse                 82.961484                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse                 83.122861                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                     1940                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                    141                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                  13.758865                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data      82.961484                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.020254                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.020254                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::cpu.data      83.122861                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.020294                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.020294                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data         1048                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total            1048                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          870                       # number of WriteReq hits
@@ -277,16 +277,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 48234.042553                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse               154.001524                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               154.336658                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                      32                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                   307                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.104235                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst    105.840466                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data     48.161058                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst     0.003230                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.001470                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.004700                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst    106.089659                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     48.246999                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.003238                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.001472                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.004710                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst           16                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data           16                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total             32                       # number of ReadReq hits
diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini
index ee123d638..3f1b44728 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini
@@ -181,7 +181,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
@@ -213,7 +213,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout
index 40197f717..3e33cecf6 100755
--- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout
+++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun  4 2012 11:58:11
-gem5 started Jun  4 2012 14:43:16
+gem5 compiled Jul  2 2012 08:47:33
+gem5 started Jul  2 2012 11:28:42
 gem5 executing on zizzer
-command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing
+command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello World!
-Exiting @ tick 19775000 because target called exit()
+Exiting @ tick 20520000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt
index 705e8dbde..615d61bce 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000020                       # Number of seconds simulated
-sim_ticks                                    19775000                       # Number of ticks simulated
-final_tick                                   19775000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000021                       # Number of seconds simulated
+sim_ticks                                    20520000                       # Number of ticks simulated
+final_tick                                   20520000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  79967                       # Simulator instruction rate (inst/s)
-host_op_rate                                    79947                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              271245925                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 215348                       # Number of bytes of host memory used
-host_seconds                                     0.07                       # Real time elapsed on the host
+host_inst_rate                                  67788                       # Simulator instruction rate (inst/s)
+host_op_rate                                    67774                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              238625492                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 219036                       # Number of bytes of host memory used
+host_seconds                                     0.09                       # Real time elapsed on the host
 sim_insts                                        5827                       # Number of instructions simulated
 sim_ops                                          5827                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             20288                       # Number of bytes read from this memory
@@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total           20288                       # Nu
 system.physmem.num_reads::cpu.inst                317                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                138                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   455                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst           1025941846                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            446624526                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1472566372                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      1025941846                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         1025941846                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          1025941846                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           446624526                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1472566372                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            988693957                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            430409357                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1419103314                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       988693957                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          988693957                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           988693957                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           430409357                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1419103314                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
 system.cpu.dtb.read_accesses                        0                       # DTB read accesses
@@ -46,27 +46,27 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                    8                       # Number of system calls
-system.cpu.numCycles                            39551                       # number of cpu cycles simulated
+system.cpu.numCycles                            41041                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.branch_predictor.lookups              1152                       # Number of BP lookups
-system.cpu.branch_predictor.condPredicted          851                       # Number of conditional branches predicted
+system.cpu.branch_predictor.lookups              1151                       # Number of BP lookups
+system.cpu.branch_predictor.condPredicted          850                       # Number of conditional branches predicted
 system.cpu.branch_predictor.condIncorrect          605                       # Number of conditional branches incorrect
-system.cpu.branch_predictor.BTBLookups            867                       # Number of BTB lookups
-system.cpu.branch_predictor.BTBHits               309                       # Number of BTB hits
+system.cpu.branch_predictor.BTBLookups            866                       # Number of BTB lookups
+system.cpu.branch_predictor.BTBHits               310                       # Number of BTB hits
 system.cpu.branch_predictor.usedRAS                86                       # Number of times the RAS was used to get a target.
 system.cpu.branch_predictor.RASInCorrect           32                       # Number of incorrect RAS predictions.
-system.cpu.branch_predictor.BTBHitPct       35.640138                       # BTB Hit Percentage
-system.cpu.branch_predictor.predictedTaken          402                       # Number of Branches Predicted As Taken (True).
-system.cpu.branch_predictor.predictedNotTaken          750                       # Number of Branches Predicted As Not Taken (False).
-system.cpu.regfile_manager.intRegFileReads         5104                       # Number of Reads from Int. Register File
+system.cpu.branch_predictor.BTBHitPct       35.796767                       # BTB Hit Percentage
+system.cpu.branch_predictor.predictedTaken          403                       # Number of Branches Predicted As Taken (True).
+system.cpu.branch_predictor.predictedNotTaken          748                       # Number of Branches Predicted As Not Taken (False).
+system.cpu.regfile_manager.intRegFileReads         5102                       # Number of Reads from Int. Register File
 system.cpu.regfile_manager.intRegFileWrites         3408                       # Number of Writes to Int. Register File
-system.cpu.regfile_manager.intRegFileAccesses         8512                       # Total Accesses (Read+Write) to the Int. Register File
+system.cpu.regfile_manager.intRegFileAccesses         8510                       # Total Accesses (Read+Write) to the Int. Register File
 system.cpu.regfile_manager.floatRegFileReads            3                       # Number of Reads from FP Register File
 system.cpu.regfile_manager.floatRegFileWrites            1                       # Number of Writes to FP Register File
 system.cpu.regfile_manager.floatRegFileAccesses            4                       # Total Accesses (Read+Write) to the FP Register File
-system.cpu.regfile_manager.regForwards           1330                       # Number of Registers Read Through Forwarding Logic
-system.cpu.agen_unit.agens                       2238                       # Number of Address Generations
+system.cpu.regfile_manager.regForwards           1331                       # Number of Registers Read Through Forwarding Logic
+system.cpu.agen_unit.agens                       2237                       # Number of Address Generations
 system.cpu.execution_unit.predictedTakenIncorrect          262                       # Number of Branches Incorrectly Predicted As Taken.
 system.cpu.execution_unit.predictedNotTakenIncorrect          334                       # Number of Branches Incorrectly Predicted As Not Taken).
 system.cpu.execution_unit.mispredicted            596                       # Number of Branches Incorrectly Predicted
@@ -76,12 +76,12 @@ system.cpu.execution_unit.executions             3155                       # Nu
 system.cpu.mult_div_unit.multiplies                 3                       # Number of Multipy Operations Executed
 system.cpu.mult_div_unit.divides                    1                       # Number of Divide Operations Executed
 system.cpu.contextSwitches                          1                       # Number of context switches
-system.cpu.threadCycles                          9142                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles                          9765                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
 system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled                             404                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           34183                       # Number of cycles cpu's stages were not processed
-system.cpu.runCycles                             5368                       # Number of cycles cpu stages are processed.
-system.cpu.activity                         13.572350                       # Percentage of cycles cpu is active
+system.cpu.timesIdled                             505                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           35643                       # Number of cycles cpu's stages were not processed
+system.cpu.runCycles                             5398                       # Number of cycles cpu stages are processed.
+system.cpu.activity                         13.152701                       # Percentage of cycles cpu is active
 system.cpu.comLoads                              1164                       # Number of Load instructions committed
 system.cpu.comStores                              925                       # Number of Store instructions committed
 system.cpu.comBranches                            916                       # Number of Branches instructions committed
@@ -93,72 +93,72 @@ system.cpu.committedInsts                        5827                       # Nu
 system.cpu.committedOps                          5827                       # Number of Ops committed (Per-Thread)
 system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
 system.cpu.committedInsts_total                  5827                       # Number of Instructions committed (Total)
-system.cpu.cpi                               6.787541                       # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi                               7.043247                       # CPI: Cycles Per Instruction (Per-Thread)
 system.cpu.smt_cpi                                nan                       # CPI: Total SMT-CPI
-system.cpu.cpi_total                         6.787541                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.147329                       # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.cpi_total                         7.043247                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.141980                       # IPC: Instructions Per Cycle (Per-Thread)
 system.cpu.smt_ipc                                nan                       # IPC: Total SMT-IPC
-system.cpu.ipc_total                         0.147329                       # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles                    35911                       # Number of cycles 0 instructions are processed.
-system.cpu.stage0.runCycles                      3640                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization                9.203307                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles                    36722                       # Number of cycles 0 instructions are processed.
+system.cpu.ipc_total                         0.141980                       # IPC: Total IPC of All Threads
+system.cpu.stage0.idleCycles                    37403                       # Number of cycles 0 instructions are processed.
+system.cpu.stage0.runCycles                      3638                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.utilization                8.864306                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles                    38212                       # Number of cycles 0 instructions are processed.
 system.cpu.stage1.runCycles                      2829                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization                7.152790                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles                    36760                       # Number of cycles 0 instructions are processed.
-system.cpu.stage2.runCycles                      2791                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization                7.056712                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles                    38308                       # Number of cycles 0 instructions are processed.
+system.cpu.stage1.utilization                6.893107                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles                    38251                       # Number of cycles 0 instructions are processed.
+system.cpu.stage2.runCycles                      2790                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage2.utilization                6.798080                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles                    39798                       # Number of cycles 0 instructions are processed.
 system.cpu.stage3.runCycles                      1243                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization                3.142778                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles                    36647                       # Number of cycles 0 instructions are processed.
-system.cpu.stage4.runCycles                      2904                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization                7.342419                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.utilization                3.028679                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles                    38136                       # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles                      2905                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization                7.078288                       # Percentage of cycles stage was utilized (processing insts).
 system.cpu.icache.replacements                     13                       # number of replacements
-system.cpu.icache.tagsinuse                148.175887                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                147.235290                       # Cycle average of tags in use
 system.cpu.icache.total_refs                      411                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    319                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                   1.288401                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     148.175887                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.072352                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.072352                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst     147.235290                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.071892                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.071892                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst          411                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total             411                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst           411                       # number of demand (read+write) hits
 system.cpu.icache.demand_hits::total              411                       # number of demand (read+write) hits
 system.cpu.icache.overall_hits::cpu.inst          411                       # number of overall hits
 system.cpu.icache.overall_hits::total             411                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          343                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           343                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          343                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            343                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          343                       # number of overall misses
-system.cpu.icache.overall_misses::total           343                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     19128500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     19128500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     19128500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     19128500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     19128500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     19128500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst          754                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total          754                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst          754                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total          754                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst          754                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total          754                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.454907                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.454907                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.454907                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.454907                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.454907                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.454907                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55768.221574                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 55768.221574                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 55768.221574                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 55768.221574                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 55768.221574                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 55768.221574                       # average overall miss latency
+system.cpu.icache.ReadReq_misses::cpu.inst          344                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           344                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          344                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            344                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          344                       # number of overall misses
+system.cpu.icache.overall_misses::total           344                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     19612500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     19612500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     19612500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     19612500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     19612500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     19612500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst          755                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total          755                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst          755                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total          755                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst          755                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total          755                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.455629                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.455629                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.455629                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.455629                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.455629                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.455629                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 57013.081395                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 57013.081395                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 57013.081395                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 57013.081395                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 57013.081395                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 57013.081395                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets        29000                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -167,70 +167,70 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets        29000                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst           24                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total           24                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst           24                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total           24                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst           24                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total           24                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst           25                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total           25                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst           25                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total           25                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst           25                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total           25                       # number of overall MSHR hits
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          319                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total          319                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst          319                       # number of demand (read+write) MSHR misses
 system.cpu.icache.demand_mshr_misses::total          319                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          319                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          319                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     16951500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     16951500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     16951500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     16951500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     16951500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     16951500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.423077                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.423077                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.423077                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.423077                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.423077                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.423077                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53139.498433                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53139.498433                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53139.498433                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 53139.498433                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53139.498433                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 53139.498433                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     17428000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     17428000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     17428000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     17428000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     17428000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     17428000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.422517                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.422517                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.422517                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.422517                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.422517                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.422517                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54633.228840                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54633.228840                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54633.228840                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 54633.228840                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54633.228840                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 54633.228840                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.tagsinuse                 89.746602                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                     1838                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse                 89.278998                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                     1835                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                    138                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  13.318841                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                  13.297101                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data      89.746602                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.021911                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.021911                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data         1075                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1075                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data          763                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total            763                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          1838                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             1838                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         1838                       # number of overall hits
-system.cpu.dcache.overall_hits::total            1838                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data           89                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total            89                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data          162                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total          162                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          251                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            251                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          251                       # number of overall misses
-system.cpu.dcache.overall_misses::total           251                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      5072500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      5072500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data      8910500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      8910500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     13983000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     13983000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     13983000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     13983000                       # number of overall miss cycles
+system.cpu.dcache.occ_blocks::cpu.data      89.278998                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.021797                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.021797                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data         1073                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1073                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data          762                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total            762                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data          1835                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             1835                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         1835                       # number of overall hits
+system.cpu.dcache.overall_hits::total            1835                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data           91                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total            91                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data          163                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total          163                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data          254                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            254                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          254                       # number of overall misses
+system.cpu.dcache.overall_misses::total           254                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      5537000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      5537000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     10150000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     10150000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     15687000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     15687000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     15687000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     15687000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data         1164                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total         1164                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          925                       # number of WriteReq accesses(hits+misses)
@@ -239,38 +239,38 @@ system.cpu.dcache.demand_accesses::cpu.data         2089                       #
 system.cpu.dcache.demand_accesses::total         2089                       # number of demand (read+write) accesses
 system.cpu.dcache.overall_accesses::cpu.data         2089                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total         2089                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.076460                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.076460                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.175135                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.175135                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.120153                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.120153                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.120153                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.120153                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56994.382022                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 56994.382022                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55003.086420                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 55003.086420                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 55709.163347                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 55709.163347                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 55709.163347                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 55709.163347                       # average overall miss latency
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.078179                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.078179                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.176216                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.176216                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.121589                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.121589                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.121589                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.121589                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60846.153846                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 60846.153846                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62269.938650                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 62269.938650                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 61759.842520                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 61759.842520                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 61759.842520                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 61759.842520                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets      1153500                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets      1194500                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets              23                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 50152.173913                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 51934.782609                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data            2                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total            2                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data          111                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total          111                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          113                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          113                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          113                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          113                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data            4                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total            4                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data          112                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total          112                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          116                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          116                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          116                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          116                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data           87                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total           87                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data           51                       # number of WriteReq MSHR misses
@@ -279,14 +279,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          138
 system.cpu.dcache.demand_mshr_misses::total          138                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          138                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          138                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4702500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      4702500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      2745500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      2745500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      7448000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      7448000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7448000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      7448000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      5138000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      5138000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      2913500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      2913500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      8051500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      8051500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      8051500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      8051500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.074742                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.074742                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.055135                       # mshr miss rate for WriteReq accesses
@@ -295,26 +295,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.066060
 system.cpu.dcache.demand_mshr_miss_rate::total     0.066060                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.066060                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.066060                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54051.724138                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54051.724138                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53833.333333                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53833.333333                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53971.014493                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 53971.014493                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53971.014493                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 53971.014493                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59057.471264                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59057.471264                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 57127.450980                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 57127.450980                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58344.202899                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 58344.202899                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58344.202899                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 58344.202899                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse               205.517886                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               204.292602                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       2                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                   404                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.004950                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst    149.817885                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data     55.700002                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst     0.004572                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.001700                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.006272                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst    148.846889                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     55.445713                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.004542                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.001692                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.006235                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              2                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
@@ -332,17 +332,17 @@ system.cpu.l2cache.demand_misses::total           455                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          317                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          138                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          455                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     16585000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      4585000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     21170000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      2682000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      2682000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     16585000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data      7267000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     23852000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     16585000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data      7267000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     23852000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     17060000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      5021500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     22081500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      2843500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      2843500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     17060000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      7865000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     24925000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     17060000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      7865000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     24925000                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst          319                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data           87                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total          406                       # number of ReadReq accesses(hits+misses)
@@ -365,17 +365,17 @@ system.cpu.l2cache.demand_miss_rate::total     0.995624                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.993730                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.995624                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52318.611987                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52701.149425                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 52400.990099                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52588.235294                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52588.235294                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52318.611987                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52659.420290                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52421.978022                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52318.611987                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52659.420290                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52421.978022                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53817.034700                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57718.390805                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 54657.178218                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55754.901961                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55754.901961                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53817.034700                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56992.753623                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 54780.219780                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53817.034700                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56992.753623                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 54780.219780                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -395,17 +395,17 @@ system.cpu.l2cache.demand_mshr_misses::total          455
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          317                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          138                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          455                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     12717500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      3529500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     16247000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      2058000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2058000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     12717500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5587500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     18305000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     12717500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5587500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     18305000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     13201000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      3966500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     17167500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      2221000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2221000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     13201000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      6187500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     19388500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     13201000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      6187500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     19388500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.993730                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.995074                       # mshr miss rate for ReadReq accesses
@@ -417,17 +417,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.995624
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.993730                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.995624                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40118.296530                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40568.965517                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40215.346535                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40352.941176                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40352.941176                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40118.296530                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40489.130435                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40230.769231                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40118.296530                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40489.130435                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40230.769231                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41643.533123                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45591.954023                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42493.811881                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43549.019608                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43549.019608                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41643.533123                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44836.956522                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42612.087912                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41643.533123                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44836.956522                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42612.087912                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini
index a70bd3d3a..f6f1675ea 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini
@@ -479,7 +479,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
@@ -511,7 +511,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout
index d99f33506..d96fc7f5c 100755
--- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:05:18
-gem5 started Jun 28 2012 22:52:53
+gem5 compiled Jul  2 2012 08:47:33
+gem5 started Jul  2 2012 11:28:53
 gem5 executing on zizzer
 command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello World!
-Exiting @ tick 12478500 because target called exit()
+Exiting @ tick 13016500 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
index 7981b4fdb..4a3a21e6c 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
@@ -1,32 +1,32 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000012                       # Number of seconds simulated
-sim_ticks                                    12478500                       # Number of ticks simulated
-final_tick                                   12478500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000013                       # Number of seconds simulated
+sim_ticks                                    13016500                       # Number of ticks simulated
+final_tick                                   13016500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  84509                       # Simulator instruction rate (inst/s)
-host_op_rate                                    84485                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              203899861                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 220092                       # Number of bytes of host memory used
-host_seconds                                     0.06                       # Real time elapsed on the host
+host_inst_rate                                  54505                       # Simulator instruction rate (inst/s)
+host_op_rate                                    54495                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              137205108                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 220060                       # Number of bytes of host memory used
+host_seconds                                     0.10                       # Real time elapsed on the host
 sim_insts                                        5169                       # Number of instructions simulated
 sim_ops                                          5169                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst             21632                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data              9152                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst             21760                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              9024                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                30784                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        21632                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           21632                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                338                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data                143                       # Number of read requests responded to by this memory
+system.physmem.bytes_inst_read::cpu.inst        21760                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           21760                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                340                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                141                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   481                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst           1733541692                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            733421485                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              2466963177                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      1733541692                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         1733541692                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          1733541692                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           733421485                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             2466963177                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst           1671724350                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            693273922                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              2364998271                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      1671724350                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         1671724350                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          1671724350                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           693273922                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             2364998271                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
 system.cpu.dtb.read_accesses                        0                       # DTB read accesses
@@ -46,245 +46,245 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                    8                       # Number of system calls
-system.cpu.numCycles                            24958                       # number of cpu cycles simulated
+system.cpu.numCycles                            26034                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                     2172                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted               1452                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect                447                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups                  1660                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                      457                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                     2148                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted               1448                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect                450                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups                  1662                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                      462                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                      278                       # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect                  71                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles               8142                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          13207                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        2172                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches                735                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          3199                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                    1325                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles                    670                       # Number of cycles fetch has spent blocked
+system.cpu.BPredUnit.usedRAS                      263                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect                  67                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles               8866                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          13061                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        2148                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches                725                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                          3176                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                    1340                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles                    826                       # Number of cycles fetch has spent blocked
 system.cpu.fetch.MiscStallCycles                    1                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingTrapStallCycles           143                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                      1938                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   262                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              13025                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.013973                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.329859                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines                      1948                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   270                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples              13893                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.940114                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.257377                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                     9826     75.44%     75.44% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                     1298      9.97%     85.40% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      113      0.87%     86.27% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      139      1.07%     87.34% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      293      2.25%     89.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      102      0.78%     90.37% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      157      1.21%     91.58% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      134      1.03%     92.61% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                      963      7.39%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                    10717     77.14%     77.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                     1298      9.34%     86.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      110      0.79%     87.27% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      134      0.96%     88.24% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      300      2.16%     90.40% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      103      0.74%     91.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      148      1.07%     92.20% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      126      0.91%     93.11% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                      957      6.89%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                13025                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.087026                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.529169                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                     8327                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                   818                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      3014                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                    41                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                    825                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved                  136                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                    46                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts                  12256                       # Number of instructions handled by decode
+system.cpu.fetch.rateDist::total                13893                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.082507                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.501690                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                     9037                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                   974                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      2996                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                    51                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                    835                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved                  145                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                    47                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts                  12168                       # Number of instructions handled by decode
 system.cpu.decode.SquashedInsts                   188                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                    825                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                     8509                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                     222                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles            499                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      2873                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                    97                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  11712                       # Number of instructions processed by rename
-system.cpu.rename.LSQFullEvents                    88                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands                7146                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 13901                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            13897                       # Number of integer rename lookups
+system.cpu.rename.SquashCycles                    835                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                     9227                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                     288                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles            540                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                      2860                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                   143                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                  11638                       # Number of instructions processed by rename
+system.cpu.rename.LSQFullEvents                   129                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands                7046                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 13805                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            13801                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups                 4                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps                  3410                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                     3736                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                 18                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts             11                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                       266                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 2476                       # Number of loads inserted to the mem dependence unit.
+system.cpu.rename.UndoneMaps                     3636                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                 16                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts             10                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                       308                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                 2447                       # Number of loads inserted to the mem dependence unit.
 system.cpu.memDep0.insertedStores                1180                       # Number of stores inserted to the mem dependence unit.
 system.cpu.memDep0.conflictingLoads                 1                       # Number of conflicting loads.
 system.cpu.memDep0.conflictingStores                1                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                       9032                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                  13                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                      8121                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued                52                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined            3346                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined         2009                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved              3                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         13025                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.623493                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.295831                       # Number of insts issued each cycle
+system.cpu.iq.iqInstsAdded                       9050                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                  12                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                      8137                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued                46                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined            3435                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined         1984                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved              2                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples         13893                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.585691                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.249798                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0                9566     73.44%     73.44% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                1360     10.44%     83.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                 840      6.45%     90.33% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 535      4.11%     94.44% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 357      2.74%     97.18% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 221      1.70%     98.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                  96      0.74%     99.62% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                  33      0.25%     99.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8                  17      0.13%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0               10352     74.51%     74.51% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                1446     10.41%     84.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                 850      6.12%     91.04% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 537      3.87%     94.90% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 350      2.52%     97.42% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 226      1.63%     99.05% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                  89      0.64%     99.69% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                  28      0.20%     99.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                  15      0.11%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           13025                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           13893                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                       4      2.63%      2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      2.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                     96     63.16%     65.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                       3      1.97%      1.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      1.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      1.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      1.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      1.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      1.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      1.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      1.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      1.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      1.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      1.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      1.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      1.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      1.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      1.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      1.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      1.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      1.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      1.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      1.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      1.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      1.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      1.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      1.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      1.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      1.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      1.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      1.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      1.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                     97     63.82%     65.79% # attempts to use FU when none available
 system.cpu.iq.fu_full::MemWrite                    52     34.21%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                  4783     58.90%     58.90% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    4      0.05%     58.95% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     2      0.02%     58.97% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     59.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     59.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     59.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     59.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     59.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     59.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     59.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     59.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     59.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     59.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     59.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     59.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     59.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     59.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     59.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     59.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     59.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     59.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     59.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     59.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     59.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     59.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     59.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     59.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     59.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     59.00% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 2243     27.62%     86.61% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                1087     13.39%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                  4825     59.30%     59.30% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    5      0.06%     59.36% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     2      0.02%     59.38% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     59.41% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     59.41% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     59.41% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     59.41% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     59.41% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     59.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     59.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     59.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     59.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     59.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     59.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     59.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     59.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     59.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     59.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     59.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     59.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     59.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     59.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     59.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     59.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     59.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     59.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     59.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     59.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     59.41% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 2212     27.18%     86.59% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1091     13.41%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                   8121                       # Type of FU issued
-system.cpu.iq.rate                           0.325387                       # Inst issue rate
+system.cpu.iq.FU_type_0::total                   8137                       # Type of FU issued
+system.cpu.iq.rate                           0.312553                       # Inst issue rate
 system.cpu.iq.fu_busy_cnt                         152                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.018717                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              29467                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             12396                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses         7292                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fu_busy_rate                   0.018680                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              30361                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             12504                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses         7339                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                   4                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                  2                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses            2                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                   8271                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                   8287                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                       2                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads               61                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads               60                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads         1312                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses            4                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation            7                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedLoads         1283                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses            5                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation            9                       # Number of memory ordering violations
 system.cpu.iew.lsq.thread0.squashedStores          255                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                    825                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                     149                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                    10                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               10514                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts               112                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  2476                       # Number of dispatched load instructions
+system.cpu.iew.iewSquashCycles                    835                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                     148                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                    16                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts               10551                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts                78                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts                  2447                       # Number of dispatched load instructions
 system.cpu.iew.iewDispStoreInsts                 1180                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                 13                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispNonSpecInsts                 12                       # Number of dispatched non-speculative instructions
 system.cpu.iew.iewIQFullEvents                      2                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewLSQFullEvents                     1                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents              7                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect            107                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect          373                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                  480                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                  7766                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                  2126                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts               355                       # Number of squashed instructions skipped in execute
+system.cpu.iew.memOrderViolationEvents              9                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect            101                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect          378                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts                  479                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                  7784                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                  2096                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts               353                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                          1469                       # number of nop insts executed
-system.cpu.iew.exec_refs                         3191                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                     1304                       # Number of branches executed
-system.cpu.iew.exec_stores                       1065                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.311163                       # Inst execution rate
-system.cpu.iew.wb_sent                           7392                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                          7294                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                      2836                       # num instructions producing a value
-system.cpu.iew.wb_consumers                      4075                       # num instructions consuming a value
+system.cpu.iew.exec_nop                          1489                       # number of nop insts executed
+system.cpu.iew.exec_refs                         3163                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                     1325                       # Number of branches executed
+system.cpu.iew.exec_stores                       1067                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.298994                       # Inst execution rate
+system.cpu.iew.wb_sent                           7431                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                          7341                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                      2840                       # num instructions producing a value
+system.cpu.iew.wb_consumers                      4066                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.292251                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.695951                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.281977                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.698475                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts           5826                       # The number of committed instructions
 system.cpu.commit.commitCommittedOps             5826                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts            4683                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts            4721                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              10                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts               402                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        12200                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.477541                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.256570                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts               404                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples        13058                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.446163                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.225344                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0         9781     80.17%     80.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1         1000      8.20%     88.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          629      5.16%     93.52% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          333      2.73%     96.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          158      1.30%     97.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5           93      0.76%     98.31% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6           67      0.55%     98.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           42      0.34%     99.20% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8           97      0.80%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0        10619     81.32%     81.32% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         1036      7.93%     89.26% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          643      4.92%     94.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          305      2.34%     96.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          154      1.18%     97.69% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5           84      0.64%     98.34% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6           72      0.55%     98.89% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           39      0.30%     99.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8          106      0.81%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        12200                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        13058                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts                 5826                       # Number of instructions committed
 system.cpu.commit.committedOps                   5826                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -295,69 +295,69 @@ system.cpu.commit.branches                        916                       # Nu
 system.cpu.commit.fp_insts                          2                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                      5124                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                   87                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events                    97                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events                   106                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                        22599                       # The number of ROB reads
-system.cpu.rob.rob_writes                       21853                       # The number of ROB writes
-system.cpu.timesIdled                             249                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           11933                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                        23486                       # The number of ROB reads
+system.cpu.rob.rob_writes                       21936                       # The number of ROB writes
+system.cpu.timesIdled                             270                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           12141                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        5169                       # Number of Instructions Simulated
 system.cpu.committedOps                          5169                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total                  5169                       # Number of Instructions Simulated
-system.cpu.cpi                               4.828400                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         4.828400                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.207108                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.207108                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    10560                       # number of integer regfile reads
-system.cpu.int_regfile_writes                    5130                       # number of integer regfile writes
+system.cpu.cpi                               5.036564                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         5.036564                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.198548                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.198548                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                    10600                       # number of integer regfile reads
+system.cpu.int_regfile_writes                    5152                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                         3                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                        1                       # number of floating regfile writes
-system.cpu.misc_regfile_reads                     150                       # number of misc regfile reads
+system.cpu.misc_regfile_reads                     155                       # number of misc regfile reads
 system.cpu.icache.replacements                     17                       # number of replacements
-system.cpu.icache.tagsinuse                163.784522                       # Cycle average of tags in use
-system.cpu.icache.total_refs                     1503                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                    341                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                   4.407625                       # Average number of references to valid blocks.
+system.cpu.icache.tagsinuse                163.172601                       # Cycle average of tags in use
+system.cpu.icache.total_refs                     1511                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    343                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                   4.405248                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     163.784522                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.079973                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.079973                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst         1503                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            1503                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          1503                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             1503                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         1503                       # number of overall hits
-system.cpu.icache.overall_hits::total            1503                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          435                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           435                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          435                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            435                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          435                       # number of overall misses
-system.cpu.icache.overall_misses::total           435                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     15599500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     15599500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     15599500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     15599500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     15599500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     15599500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         1938                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         1938                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         1938                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         1938                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         1938                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         1938                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.224458                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.224458                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.224458                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.224458                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.224458                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.224458                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35860.919540                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 35860.919540                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 35860.919540                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 35860.919540                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 35860.919540                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 35860.919540                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     163.172601                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.079674                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.079674                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst         1511                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            1511                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          1511                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             1511                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         1511                       # number of overall hits
+system.cpu.icache.overall_hits::total            1511                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          437                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           437                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          437                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            437                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          437                       # number of overall misses
+system.cpu.icache.overall_misses::total           437                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     15987000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     15987000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     15987000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     15987000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     15987000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     15987000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         1948                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         1948                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         1948                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         1948                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         1948                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         1948                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.224333                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.224333                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.224333                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.224333                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.224333                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.224333                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36583.524027                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 36583.524027                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 36583.524027                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 36583.524027                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 36583.524027                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 36583.524027                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -372,88 +372,88 @@ system.cpu.icache.demand_mshr_hits::cpu.inst           94
 system.cpu.icache.demand_mshr_hits::total           94                       # number of demand (read+write) MSHR hits
 system.cpu.icache.overall_mshr_hits::cpu.inst           94                       # number of overall MSHR hits
 system.cpu.icache.overall_mshr_hits::total           94                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          341                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          341                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          341                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          341                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          341                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          341                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     11963500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     11963500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     11963500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     11963500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     11963500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     11963500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.175955                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.175955                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.175955                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.175955                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.175955                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.175955                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35083.577713                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35083.577713                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35083.577713                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 35083.577713                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35083.577713                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 35083.577713                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          343                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          343                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          343                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          343                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          343                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          343                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     12452000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     12452000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     12452000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     12452000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     12452000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     12452000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.176078                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.176078                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.176078                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.176078                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.176078                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.176078                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36303.206997                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36303.206997                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36303.206997                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 36303.206997                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36303.206997                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 36303.206997                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.tagsinuse                 92.268506                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                     2489                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                    143                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  17.405594                       # Average number of references to valid blocks.
+system.cpu.dcache.tagsinuse                 91.140441                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                     2441                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                    141                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  17.312057                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data      92.268506                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.022526                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.022526                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data         1903                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1903                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data          586                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total            586                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          2489                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             2489                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         2489                       # number of overall hits
-system.cpu.dcache.overall_hits::total            2489                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          133                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           133                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data          339                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total          339                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          472                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            472                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          472                       # number of overall misses
-system.cpu.dcache.overall_misses::total           472                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      4784500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      4784500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     11421000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     11421000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     16205500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     16205500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     16205500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     16205500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         2036                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         2036                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.occ_blocks::cpu.data      91.140441                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.022251                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.022251                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data         1863                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1863                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data          578                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total            578                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data          2441                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             2441                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         2441                       # number of overall hits
+system.cpu.dcache.overall_hits::total            2441                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          148                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           148                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data          347                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total          347                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data          495                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            495                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          495                       # number of overall misses
+system.cpu.dcache.overall_misses::total           495                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      5658500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      5658500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     13040000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     13040000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     18698500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     18698500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     18698500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     18698500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         2011                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         2011                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          925                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total          925                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         2961                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2961                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         2961                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2961                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.065324                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.065324                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.366486                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.366486                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.159406                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.159406                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.159406                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.159406                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35973.684211                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 35973.684211                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33690.265487                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 33690.265487                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 34333.686441                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 34333.686441                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 34333.686441                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 34333.686441                       # average overall miss latency
+system.cpu.dcache.demand_accesses::cpu.data         2936                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2936                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2936                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2936                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.073595                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.073595                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.375135                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.375135                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.168597                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.168597                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.168597                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.168597                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38233.108108                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 38233.108108                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37579.250720                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 37579.250720                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 37774.747475                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 37774.747475                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 37774.747475                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 37774.747475                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -462,119 +462,119 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data           41                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           41                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data          288                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total          288                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          329                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          329                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          329                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          329                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data           92                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total           92                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           58                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           58                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data          296                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total          296                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          354                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          354                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          354                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          354                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data           90                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total           90                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data           51                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total           51                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data          143                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total          143                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data          143                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total          143                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      3306000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      3306000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      1845000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      1845000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      5151000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      5151000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      5151000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      5151000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.045187                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.045187                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_misses::cpu.data          141                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total          141                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data          141                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total          141                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      3847000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      3847000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      2081000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      2081000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      5928000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      5928000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      5928000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      5928000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.044754                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.044754                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.055135                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.055135                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.048294                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.048294                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.048294                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.048294                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35934.782609                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35934.782609                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36176.470588                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36176.470588                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36020.979021                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 36020.979021                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36020.979021                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 36020.979021                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.048025                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.048025                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.048025                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.048025                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 42744.444444                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 42744.444444                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40803.921569                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40803.921569                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 42042.553191                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 42042.553191                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 42042.553191                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 42042.553191                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse               224.190745                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               222.725864                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       3                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                   430                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.006977                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst    165.976213                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data     58.214532                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst     0.005065                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.001777                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.006842                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst    165.335127                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     57.390737                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.005046                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.001751                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.006797                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst            3                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              3                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            3                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::total               3                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst            3                       # number of overall hits
 system.cpu.l2cache.overall_hits::total              3                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          338                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data           92                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.inst          340                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data           90                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::total          430                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data           51                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total           51                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          338                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data          143                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst          340                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data          141                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::total           481                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          338                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data          143                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.inst          340                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data          141                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          481                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     11593500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      3178500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     14772000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      1768500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      1768500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     11593500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data      4947000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     16540500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     11593500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data      4947000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     16540500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          341                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data           92                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     12086500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      3738500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     15825000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      1998000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      1998000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     12086500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      5736500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     17823000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     12086500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      5736500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     17823000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          343                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data           90                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total          433                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data           51                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total           51                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          341                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data          143                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst          343                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data          141                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::total          484                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          341                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data          143                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          343                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data          141                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total          484                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.991202                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.991254                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::total     0.993072                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.991202                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.991254                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::total     0.993802                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.991202                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.991254                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.993802                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34300.295858                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34548.913043                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 34353.488372                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34676.470588                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34676.470588                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34300.295858                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34594.405594                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 34387.733888                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34300.295858                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34594.405594                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 34387.733888                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35548.529412                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 41538.888889                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 36802.325581                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39176.470588                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39176.470588                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35548.529412                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 40684.397163                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 37054.054054                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35548.529412                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 40684.397163                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 37054.054054                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -583,50 +583,50 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          338                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           92                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          340                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           90                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::total          430                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           51                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total           51                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          338                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data          143                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          340                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data          141                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::total          481                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          338                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data          143                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          340                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data          141                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          481                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     10498500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      2890500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     13389000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      1604000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      1604000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     10498500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      4494500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     14993000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     10498500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      4494500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     14993000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.991202                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     10999000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      3463000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     14462000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      1839500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      1839500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     10999000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5302500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     16301500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     10999000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5302500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     16301500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.991254                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.993072                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.991202                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.991254                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.993802                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.991202                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.991254                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.993802                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31060.650888                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31418.478261                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31137.209302                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31450.980392                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31450.980392                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31060.650888                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31430.069930                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31170.478170                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31060.650888                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31430.069930                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31170.478170                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        32350                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 38477.777778                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33632.558140                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36068.627451                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36068.627451                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        32350                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37606.382979                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33890.852391                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        32350                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37606.382979                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33890.852391                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini
index f7cc4efef..1e54677ab 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini
@@ -148,7 +148,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
@@ -180,7 +180,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout
index ac53df969..3ee3fb923 100755
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun  4 2012 11:58:11
-gem5 started Jun  4 2012 14:43:48
+gem5 compiled Jul  2 2012 08:47:33
+gem5 started Jul  2 2012 11:29:16
 gem5 executing on zizzer
-command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing
+command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello World!
-Exiting @ tick 32088000 because target called exit()
+Exiting @ tick 33413000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt
index 8f49928a9..eb8915cb4 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000032                       # Number of seconds simulated
-sim_ticks                                    32088000                       # Number of ticks simulated
-final_tick                                   32088000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000033                       # Number of seconds simulated
+sim_ticks                                    33413000                       # Number of ticks simulated
+final_tick                                   33413000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 540307                       # Simulator instruction rate (inst/s)
-host_op_rate                                   539410                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2965678153                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 215020                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
+host_inst_rate                                 168189                       # Simulator instruction rate (inst/s)
+host_op_rate                                   168105                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              963489284                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 219036                       # Number of bytes of host memory used
+host_seconds                                     0.03                       # Real time elapsed on the host
 sim_insts                                        5827                       # Number of instructions simulated
 sim_ops                                          5827                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             19264                       # Number of bytes read from this memory
@@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total           19264                       # Nu
 system.physmem.num_reads::cpu.inst                301                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                138                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   439                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            600349040                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            275243082                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               875592122                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       600349040                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          600349040                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           600349040                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           275243082                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              875592122                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            576542064                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            264328255                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               840870320                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       576542064                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          576542064                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           576542064                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           264328255                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              840870320                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
 system.cpu.dtb.read_accesses                        0                       # DTB read accesses
@@ -46,7 +46,7 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                    8                       # Number of system calls
-system.cpu.numCycles                            64176                       # number of cpu cycles simulated
+system.cpu.numCycles                            66826                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        5827                       # Number of instructions committed
@@ -65,18 +65,18 @@ system.cpu.num_mem_refs                          2090                       # nu
 system.cpu.num_load_insts                        1164                       # Number of load instructions
 system.cpu.num_store_insts                        926                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                      64176                       # Number of busy cycles
+system.cpu.num_busy_cycles                      66826                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                     13                       # number of replacements
-system.cpu.icache.tagsinuse                132.493866                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                133.092783                       # Cycle average of tags in use
 system.cpu.icache.total_refs                     5526                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    303                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                  18.237624                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     132.493866                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.064694                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.064694                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst     133.092783                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.064987                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.064987                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst         5526                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total            5526                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst          5526                       # number of demand (read+write) hits
@@ -147,14 +147,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52722.772277
 system.cpu.icache.overall_avg_mshr_miss_latency::total 52722.772277                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.tagsinuse                 87.458397                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse                 87.717237                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                     1951                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                    138                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                  14.137681                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data      87.458397                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.021352                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.021352                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::cpu.data      87.717237                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.021415                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.021415                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data         1077                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total            1077                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          874                       # number of WriteReq hits
@@ -245,16 +245,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        53000
 system.cpu.dcache.overall_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse               188.045319                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               188.818071                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       2                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                   388                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.005155                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst    133.837577                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data     54.207742                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst     0.004084                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.001654                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.005739                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst    134.446837                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     54.371234                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.004103                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.001659                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.005762                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              2                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini
index 928f0469f..fe01ee3c1 100644
--- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini
@@ -480,7 +480,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
@@ -512,7 +512,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout
index 584102e9c..4c16f50ba 100755
--- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout
@@ -1,11 +1,11 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:05:18
-gem5 started Jun 28 2012 22:53:15
+gem5 compiled Jul  2 2012 08:50:36
+gem5 started Jul  2 2012 11:29:39
 gem5 executing on zizzer
 command line: build/POWER/gem5.fast -d build/POWER/tests/fast/quick/se/00.hello/power/linux/o3-timing -re tests/run.py build/POWER/tests/fast/quick/se/00.hello/power/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
-Exiting @ tick 11179000 because target called exit()
+Exiting @ tick 11812000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
index f8f7991bd..0b8cd16ea 100644
--- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
@@ -1,32 +1,32 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000011                       # Number of seconds simulated
-sim_ticks                                    11179000                       # Number of ticks simulated
-final_tick                                   11179000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000012                       # Number of seconds simulated
+sim_ticks                                    11812000                       # Number of ticks simulated
+final_tick                                   11812000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  61972                       # Simulator instruction rate (inst/s)
-host_op_rate                                    61960                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              119400246                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 216052                       # Number of bytes of host memory used
-host_seconds                                     0.09                       # Real time elapsed on the host
+host_inst_rate                                  59914                       # Simulator instruction rate (inst/s)
+host_op_rate                                    59903                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              121974515                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 216016                       # Number of bytes of host memory used
+host_seconds                                     0.10                       # Real time elapsed on the host
 sim_insts                                        5800                       # Number of instructions simulated
 sim_ops                                          5800                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst             22400                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data              6464                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                28864                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        22400                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           22400                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                350                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data                101                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                   451                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst           2003757044                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            578227033                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              2581984077                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      2003757044                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         2003757044                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          2003757044                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           578227033                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             2581984077                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst             22528                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              6400                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                28928                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        22528                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           22528                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                352                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                100                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                   452                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst           1907213004                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            541821876                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              2449034880                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      1907213004                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         1907213004                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          1907213004                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           541821876                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             2449034880                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
 system.cpu.dtb.read_accesses                        0                       # DTB read accesses
@@ -46,245 +46,245 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                    9                       # Number of system calls
-system.cpu.numCycles                            22359                       # number of cpu cycles simulated
+system.cpu.numCycles                            23625                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                     2487                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted               2038                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect                457                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups                  2063                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                      631                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                     2490                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted               2041                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect                460                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups                  2061                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                      629                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                      157                       # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect                  28                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles               6834                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          14542                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        2487                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches                788                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          2415                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                    1412                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles                    813                       # Number of cycles fetch has spent blocked
+system.cpu.BPredUnit.usedRAS                      162                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect                  30                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles               7441                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          14561                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        2490                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches                791                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                          2421                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                    1432                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles                    932                       # Number of cycles fetch has spent blocked
 system.cpu.fetch.MiscStallCycles                    1                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.CacheLines                      1887                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   310                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              11013                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.320439                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.737355                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines                      1897                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   321                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples              11761                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.238075                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.668941                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                     8598     78.07%     78.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                      170      1.54%     79.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      167      1.52%     81.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      144      1.31%     82.44% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      198      1.80%     84.24% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      151      1.37%     85.61% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      257      2.33%     87.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      107      0.97%     88.91% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     1221     11.09%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                     9340     79.42%     79.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                      172      1.46%     80.88% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      167      1.42%     82.30% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      146      1.24%     83.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      197      1.68%     85.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      155      1.32%     86.53% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      255      2.17%     88.70% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      108      0.92%     89.62% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                     1221     10.38%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                11013                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.111230                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.650387                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                     7023                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                   884                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      2239                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                    74                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                    793                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved                  359                       # Number of times decode resolved a branch
+system.cpu.fetch.rateDist::total                11761                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.105397                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.616339                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                     7565                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                  1069                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      2256                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                    64                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                    807                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved                  361                       # Number of times decode resolved a branch
 system.cpu.decode.BranchMispred                   160                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts                  12898                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                   445                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                    793                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                     7240                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                     304                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles            345                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      2086                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                   245                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  12206                       # Number of instructions processed by rename
-system.cpu.rename.IQFullEvents                      3                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents                   201                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands               10543                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 19911                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            19856                       # Number of integer rename lookups
+system.cpu.decode.DecodedInsts                  12930                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                   452                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                    807                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                     7781                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                     440                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles            384                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                      2100                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                   249                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                  12283                       # Number of instructions processed by rename
+system.cpu.rename.IQFullEvents                     13                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents                   203                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands               10602                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 20025                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            19970                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups                55                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps                  5007                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                     5536                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                 25                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts             25                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                       518                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 2072                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                1895                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads                60                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores               30                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                      10882                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                  61                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                      9264                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued               154                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined            4859                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined         4160                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             45                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         11013                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.841188                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.574613                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                     5595                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                 26                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts             26                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                       552                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                 2098                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                1917                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads                63                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores               31                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                      11001                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                  65                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                      9282                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued               167                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined            4968                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined         4343                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             49                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples         11761                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.789219                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.523023                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0                7627     69.25%     69.25% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                1067      9.69%     78.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                 747      6.78%     85.73% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 527      4.79%     90.51% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 479      4.35%     94.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 323      2.93%     97.79% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 151      1.37%     99.16% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                  51      0.46%     99.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8                  41      0.37%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0                8303     70.60%     70.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                1127      9.58%     80.18% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                 767      6.52%     86.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 536      4.56%     91.26% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 478      4.06%     95.32% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 324      2.75%     98.08% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 139      1.18%     99.26% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                  49      0.42%     99.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                  38      0.32%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           11013                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           11761                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                       6      3.35%      3.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      3.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      3.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      3.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      3.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      3.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      3.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      3.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      3.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      3.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      3.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      3.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      3.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      3.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      3.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      3.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      3.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      3.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      3.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      3.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      3.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      3.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      3.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      3.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      3.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      3.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      3.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      3.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      3.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                     80     44.69%     48.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                    93     51.96%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                       5      2.87%      2.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      2.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      2.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      2.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      2.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      2.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      2.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      2.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      2.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      2.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      2.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      2.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      2.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      2.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      2.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      2.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      2.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      2.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      2.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      2.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      2.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      2.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      2.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      2.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      2.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      2.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      2.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      2.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      2.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                     78     44.83%     47.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    91     52.30%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                  5707     61.60%     61.60% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    0      0.00%     61.60% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     61.60% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     61.63% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     61.63% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     61.63% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     61.63% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     61.63% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     61.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     61.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     61.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     61.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     61.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     61.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     61.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     61.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     61.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     61.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     61.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     61.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     61.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     61.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     61.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     61.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     61.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     61.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     61.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     61.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     61.63% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 1853     20.00%     81.63% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                1702     18.37%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                  5709     61.51%     61.51% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    0      0.00%     61.51% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     61.51% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     61.53% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     61.53% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     61.53% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     61.53% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     61.53% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     61.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     61.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     61.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     61.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     61.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     61.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     61.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     61.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     61.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     61.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     61.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     61.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     61.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     61.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     61.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     61.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     61.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     61.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     61.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     61.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     61.53% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 1861     20.05%     81.58% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1710     18.42%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                   9264                       # Type of FU issued
-system.cpu.iq.rate                           0.414330                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                         179                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.019322                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              29812                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             15773                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses         8347                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total                   9282                       # Type of FU issued
+system.cpu.iq.rate                           0.392889                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                         174                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.018746                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              30604                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             16005                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses         8374                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                  62                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                 36                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           27                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                   9409                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                   9422                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                      34                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads               65                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads               70                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads         1110                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads         1136                       # Number of loads squashed
 system.cpu.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread0.memOrderViolation            7                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          849                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores          871                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            1                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                    793                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                     112                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                    15                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               10943                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts               107                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  2072                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                 1895                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                 51                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewSquashCycles                    807                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                     227                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                    22                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts               11066                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts               108                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts                  2098                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                 1917                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                 54                       # Number of dispatched non-speculative instructions
 system.cpu.iew.iewIQFullEvents                      9                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                     2                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                     3                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.memOrderViolationEvents              7                       # Number of memory order violations
 system.cpu.iew.predictedTakenIncorrect             78                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect          311                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                  389                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                  8757                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                  1710                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts               507                       # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedNotTakenIncorrect          309                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts                  387                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                  8779                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                  1716                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts               503                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                         3276                       # number of memory reference insts executed
+system.cpu.iew.exec_refs                         3289                       # number of memory reference insts executed
 system.cpu.iew.exec_branches                     1382                       # Number of branches executed
-system.cpu.iew.exec_stores                       1566                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.391654                       # Inst execution rate
-system.cpu.iew.wb_sent                           8550                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                          8374                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                      4334                       # num instructions producing a value
-system.cpu.iew.wb_consumers                      6981                       # num instructions consuming a value
+system.cpu.iew.exec_stores                       1573                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.371598                       # Inst execution rate
+system.cpu.iew.wb_sent                           8575                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                          8401                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                      4358                       # num instructions producing a value
+system.cpu.iew.wb_consumers                      6997                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.374525                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.620828                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.355598                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.622838                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts           5800                       # The number of committed instructions
 system.cpu.commit.commitCommittedOps             5800                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts            5152                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts            5275                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              16                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts               300                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        10220                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.567515                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.347907                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts               301                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples        10954                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.529487                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.308345                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0         7783     76.15%     76.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1         1041     10.19%     86.34% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          649      6.35%     92.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          256      2.50%     95.20% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          188      1.84%     97.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5          108      1.06%     98.09% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6           57      0.56%     98.65% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           45      0.44%     99.09% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8           93      0.91%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0         8509     77.68%     77.68% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         1052      9.60%     87.28% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          645      5.89%     93.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          263      2.40%     95.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          183      1.67%     97.24% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          104      0.95%     98.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6           63      0.58%     98.77% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           41      0.37%     99.14% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8           94      0.86%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        10220                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        10954                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts                 5800                       # Number of instructions committed
 system.cpu.commit.committedOps                   5800                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -295,68 +295,68 @@ system.cpu.commit.branches                       1038                       # Nu
 system.cpu.commit.fp_insts                         22                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                      5706                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                  103                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events                    93                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events                    94                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                        21079                       # The number of ROB reads
-system.cpu.rob.rob_writes                       22698                       # The number of ROB writes
-system.cpu.timesIdled                             215                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           11346                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                        21935                       # The number of ROB reads
+system.cpu.rob.rob_writes                       22958                       # The number of ROB writes
+system.cpu.timesIdled                             232                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           11864                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        5800                       # Number of Instructions Simulated
 system.cpu.committedOps                          5800                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total                  5800                       # Number of Instructions Simulated
-system.cpu.cpi                               3.855000                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         3.855000                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.259403                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.259403                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    13891                       # number of integer regfile reads
-system.cpu.int_regfile_writes                    7248                       # number of integer regfile writes
+system.cpu.cpi                               4.073276                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         4.073276                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.245503                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.245503                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                    13900                       # number of integer regfile reads
+system.cpu.int_regfile_writes                    7266                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        25                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                        2                       # number of floating regfile writes
 system.cpu.icache.replacements                      0                       # number of replacements
-system.cpu.icache.tagsinuse                172.424294                       # Cycle average of tags in use
-system.cpu.icache.total_refs                     1455                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                    355                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                   4.098592                       # Average number of references to valid blocks.
+system.cpu.icache.tagsinuse                172.776641                       # Cycle average of tags in use
+system.cpu.icache.total_refs                     1462                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    357                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                   4.095238                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     172.424294                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.084192                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.084192                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst         1455                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            1455                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          1455                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             1455                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         1455                       # number of overall hits
-system.cpu.icache.overall_hits::total            1455                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          432                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           432                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          432                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            432                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          432                       # number of overall misses
-system.cpu.icache.overall_misses::total           432                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     15599000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     15599000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     15599000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     15599000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     15599000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     15599000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         1887                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         1887                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         1887                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         1887                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         1887                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         1887                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.228935                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.228935                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.228935                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.228935                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.228935                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.228935                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36108.796296                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 36108.796296                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 36108.796296                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 36108.796296                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 36108.796296                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 36108.796296                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     172.776641                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.084364                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.084364                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst         1462                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            1462                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          1462                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             1462                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         1462                       # number of overall hits
+system.cpu.icache.overall_hits::total            1462                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          435                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           435                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          435                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            435                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          435                       # number of overall misses
+system.cpu.icache.overall_misses::total           435                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     16386000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     16386000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     16386000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     16386000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     16386000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     16386000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         1897                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         1897                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         1897                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         1897                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         1897                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         1897                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.229309                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.229309                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.229309                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.229309                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.229309                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.229309                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37668.965517                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 37668.965517                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 37668.965517                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 37668.965517                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 37668.965517                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 37668.965517                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -365,70 +365,70 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst           77                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total           77                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst           77                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total           77                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst           77                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total           77                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          355                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          355                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          355                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          355                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          355                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          355                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     12417500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     12417500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     12417500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     12417500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     12417500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     12417500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.188129                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.188129                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.188129                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.188129                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.188129                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.188129                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34978.873239                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34978.873239                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34978.873239                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 34978.873239                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34978.873239                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 34978.873239                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst           78                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total           78                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst           78                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total           78                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst           78                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total           78                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          357                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          357                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          357                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          357                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          357                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          357                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     13154500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     13154500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     13154500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     13154500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     13154500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     13154500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.188192                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.188192                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.188192                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.188192                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.188192                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.188192                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36847.338936                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36847.338936                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36847.338936                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 36847.338936                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36847.338936                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 36847.338936                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.tagsinuse                 63.023619                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                     2216                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                    101                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  21.940594                       # Average number of references to valid blocks.
+system.cpu.dcache.tagsinuse                 63.298936                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                     2197                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                    100                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  21.970000                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data      63.023619                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.015387                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.015387                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data         1486                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1486                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data          730                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total            730                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          2216                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             2216                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         2216                       # number of overall hits
-system.cpu.dcache.overall_hits::total            2216                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data           86                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total            86                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data          316                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total          316                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          402                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            402                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          402                       # number of overall misses
-system.cpu.dcache.overall_misses::total           402                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      3106000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      3106000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     10571500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     10571500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     13677500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     13677500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     13677500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     13677500                       # number of overall miss cycles
+system.cpu.dcache.occ_blocks::cpu.data      63.298936                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.015454                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.015454                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data         1480                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1480                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data          717                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total            717                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data          2197                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             2197                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         2197                       # number of overall hits
+system.cpu.dcache.overall_hits::total            2197                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data           92                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total            92                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data          329                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total          329                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data          421                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            421                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          421                       # number of overall misses
+system.cpu.dcache.overall_misses::total           421                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      3732500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      3732500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     12822500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     12822500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     16555000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     16555000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     16555000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     16555000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data         1572                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total         1572                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data         1046                       # number of WriteReq accesses(hits+misses)
@@ -437,22 +437,22 @@ system.cpu.dcache.demand_accesses::cpu.data         2618                       #
 system.cpu.dcache.demand_accesses::total         2618                       # number of demand (read+write) accesses
 system.cpu.dcache.overall_accesses::cpu.data         2618                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total         2618                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.054707                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.054707                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.302103                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.302103                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.153552                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.153552                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.153552                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.153552                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36116.279070                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 36116.279070                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33454.113924                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 33454.113924                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 34023.631841                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 34023.631841                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 34023.631841                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 34023.631841                       # average overall miss latency
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.058524                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.058524                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.314532                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.314532                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.160810                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.160810                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.160810                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.160810                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40570.652174                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 40570.652174                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38974.164134                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 38974.164134                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 39323.040380                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 39323.040380                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 39323.040380                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 39323.040380                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -461,119 +461,119 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data           33                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           33                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data          268                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total          268                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          301                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          301                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          301                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          301                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           39                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           39                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data          282                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total          282                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          321                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          321                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          321                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          321                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data           53                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total           53                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data           48                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total           48                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data          101                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total          101                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data          101                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total          101                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      1890500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      1890500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      1748500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      1748500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      3639000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      3639000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      3639000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      3639000                       # number of overall MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data           47                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total           47                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data          100                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total          100                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data          100                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total          100                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      2119000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      2119000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      2085000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      2085000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      4204000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      4204000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      4204000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      4204000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.033715                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.033715                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.045889                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.045889                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.038579                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.038579                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.038579                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.038579                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35669.811321                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35669.811321                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36427.083333                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36427.083333                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36029.702970                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 36029.702970                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36029.702970                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 36029.702970                       # average overall mshr miss latency
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.044933                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.044933                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.038197                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.038197                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.038197                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.038197                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39981.132075                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39981.132075                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44361.702128                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44361.702128                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        42040                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total        42040                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        42040                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total        42040                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse               202.260551                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               203.410235                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       5                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                   403                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  0.012407                       # Average number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                   405                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.012346                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst    171.544564                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data     30.715987                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst     0.005235                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.000937                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.006173                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst    171.891736                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     31.518500                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.005246                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.000962                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.006208                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst            5                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              5                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            5                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::total               5                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst            5                       # number of overall hits
 system.cpu.l2cache.overall_hits::total              5                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          350                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.inst          352                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.data           53                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total          403                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data           48                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total           48                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          350                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data          101                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total           451                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          350                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data          101                       # number of overall misses
-system.cpu.l2cache.overall_misses::total          451                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     12033000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      1829000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     13862000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      1674500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      1674500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     12033000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data      3503500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     15536500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     12033000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data      3503500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     15536500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          355                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_misses::total          405                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data           47                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total           47                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          352                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data          100                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total           452                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          352                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data          100                       # number of overall misses
+system.cpu.l2cache.overall_misses::total          452                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     12780500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      2060500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     14841000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      2028000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      2028000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     12780500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      4088500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     16869000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     12780500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      4088500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     16869000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          357                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data           53                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total          408                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data           48                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total           48                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          355                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data          101                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total          456                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          355                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data          101                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total          456                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.985915                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_accesses::total          410                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data           47                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total           47                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          357                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data          100                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total          457                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          357                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data          100                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total          457                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.985994                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.987745                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.987805                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.985915                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.985994                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.989035                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.985915                       # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::total     0.989059                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.985994                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.989035                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        34380                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34509.433962                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 34397.022333                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34885.416667                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34885.416667                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        34380                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34688.118812                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 34449.002217                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        34380                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34688.118812                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 34449.002217                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total     0.989059                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36308.238636                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 38877.358491                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 36644.444444                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 43148.936170                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 43148.936170                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36308.238636                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data        40885                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 37320.796460                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36308.238636                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data        40885                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 37320.796460                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -582,50 +582,50 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          350                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          352                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           53                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total          403                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           48                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total           48                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          350                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data          101                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total          451                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          350                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data          101                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total          451                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     10908500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      1662000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     12570500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      1521500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      1521500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     10908500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      3183500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     14092000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     10908500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      3183500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     14092000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.985915                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses::total          405                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           47                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total           47                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          352                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data          100                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total          452                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          352                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data          100                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total          452                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     11653500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      1896000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     13549500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      1881500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      1881500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     11653500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      3777500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     15431000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     11653500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      3777500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     15431000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.985994                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.987745                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.987805                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.985915                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.985994                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.989035                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.985915                       # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.989059                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.985994                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.989035                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31167.142857                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31358.490566                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31192.307692                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31697.916667                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31697.916667                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31167.142857                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31519.801980                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31246.119734                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31167.142857                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31519.801980                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31246.119734                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.989059                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33106.534091                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 35773.584906                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33455.555556                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40031.914894                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40031.914894                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33106.534091                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        37775                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34139.380531                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33106.534091                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        37775                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34139.380531                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini
index d62e06b17..dd53d4220 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini
@@ -181,7 +181,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
@@ -213,7 +213,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout
index 76c88733e..a234b881d 100755
--- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout
+++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun  4 2012 12:01:47
-gem5 started Jun  4 2012 14:44:31
+gem5 compiled Jul  2 2012 08:54:18
+gem5 started Jul  2 2012 11:30:03
 gem5 executing on zizzer
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
-Hello World!Exiting @ tick 18196500 because target called exit()
+Hello World!Exiting @ tick 18885500 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt
index b45b5b881..fa8b51b5a 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000018                       # Number of seconds simulated
-sim_ticks                                    18196500                       # Number of ticks simulated
-final_tick                                   18196500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000019                       # Number of seconds simulated
+sim_ticks                                    18885500                       # Number of ticks simulated
+final_tick                                   18885500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  58781                       # Simulator instruction rate (inst/s)
-host_op_rate                                    58769                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              200221364                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 221628                       # Number of bytes of host memory used
-host_seconds                                     0.09                       # Real time elapsed on the host
+host_inst_rate                                  37135                       # Simulator instruction rate (inst/s)
+host_op_rate                                    37131                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              131302803                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 220012                       # Number of bytes of host memory used
+host_seconds                                     0.14                       # Real time elapsed on the host
 sim_insts                                        5340                       # Number of instructions simulated
 sim_ops                                          5340                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             18496                       # Number of bytes read from this memory
@@ -19,28 +19,28 @@ system.physmem.bytes_inst_read::total           18496                       # Nu
 system.physmem.num_reads::cpu.inst                289                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                134                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   423                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst           1016459209                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            471299426                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1487758635                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      1016459209                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         1016459209                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          1016459209                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           471299426                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1487758635                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            979375712                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            454105001                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1433480713                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       979375712                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          979375712                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           979375712                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           454105001                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1433480713                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
-system.cpu.numCycles                            36394                       # number of cpu cycles simulated
+system.cpu.numCycles                            37772                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.branch_predictor.lookups              1617                       # Number of BP lookups
+system.cpu.branch_predictor.lookups              1615                       # Number of BP lookups
 system.cpu.branch_predictor.condPredicted         1022                       # Number of conditional branches predicted
 system.cpu.branch_predictor.condIncorrect          899                       # Number of conditional branches incorrect
-system.cpu.branch_predictor.BTBLookups           1172                       # Number of BTB lookups
+system.cpu.branch_predictor.BTBLookups           1170                       # Number of BTB lookups
 system.cpu.branch_predictor.BTBHits               435                       # Number of BTB hits
 system.cpu.branch_predictor.usedRAS                67                       # Number of times the RAS was used to get a target.
 system.cpu.branch_predictor.RASInCorrect            4                       # Number of incorrect RAS predictions.
-system.cpu.branch_predictor.BTBHitPct       37.116041                       # BTB Hit Percentage
+system.cpu.branch_predictor.BTBHitPct       37.179487                       # BTB Hit Percentage
 system.cpu.branch_predictor.predictedTaken          502                       # Number of Branches Predicted As Taken (True).
-system.cpu.branch_predictor.predictedNotTaken         1115                       # Number of Branches Predicted As Not Taken (False).
+system.cpu.branch_predictor.predictedNotTaken         1113                       # Number of Branches Predicted As Not Taken (False).
 system.cpu.regfile_manager.intRegFileReads         5634                       # Number of Reads from Int. Register File
 system.cpu.regfile_manager.intRegFileWrites         4000                       # Number of Writes to Int. Register File
 system.cpu.regfile_manager.intRegFileAccesses         9634                       # Total Accesses (Read+Write) to the Int. Register File
@@ -58,12 +58,12 @@ system.cpu.execution_unit.executions             3979                       # Nu
 system.cpu.mult_div_unit.multiplies                 0                       # Number of Multipy Operations Executed
 system.cpu.mult_div_unit.divides                    0                       # Number of Divide Operations Executed
 system.cpu.contextSwitches                          1                       # Number of context switches
-system.cpu.threadCycles                          9708                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles                         10178                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
 system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled                             421                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           30167                       # Number of cycles cpu's stages were not processed
-system.cpu.runCycles                             6227                       # Number of cycles cpu stages are processed.
-system.cpu.activity                         17.109963                       # Percentage of cycles cpu is active
+system.cpu.timesIdled                             501                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           31527                       # Number of cycles cpu's stages were not processed
+system.cpu.runCycles                             6245                       # Number of cycles cpu stages are processed.
+system.cpu.activity                         16.533411                       # Percentage of cycles cpu is active
 system.cpu.comLoads                               716                       # Number of Load instructions committed
 system.cpu.comStores                              673                       # Number of Store instructions committed
 system.cpu.comBranches                           1116                       # Number of Branches instructions committed
@@ -75,72 +75,72 @@ system.cpu.committedInsts                        5340                       # Nu
 system.cpu.committedOps                          5340                       # Number of Ops committed (Per-Thread)
 system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
 system.cpu.committedInsts_total                  5340                       # Number of Instructions committed (Total)
-system.cpu.cpi                               6.815356                       # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi                               7.073408                       # CPI: Cycles Per Instruction (Per-Thread)
 system.cpu.smt_cpi                                nan                       # CPI: Total SMT-CPI
-system.cpu.cpi_total                         6.815356                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.146727                       # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.cpi_total                         7.073408                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.141375                       # IPC: Instructions Per Cycle (Per-Thread)
 system.cpu.smt_ipc                                nan                       # IPC: Total SMT-IPC
-system.cpu.ipc_total                         0.146727                       # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles                    31821                       # Number of cycles 0 instructions are processed.
-system.cpu.stage0.runCycles                      4573                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization               12.565258                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles                    33191                       # Number of cycles 0 instructions are processed.
-system.cpu.stage1.runCycles                      3203                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization                8.800901                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles                    33344                       # Number of cycles 0 instructions are processed.
+system.cpu.ipc_total                         0.141375                       # IPC: Total IPC of All Threads
+system.cpu.stage0.idleCycles                    33203                       # Number of cycles 0 instructions are processed.
+system.cpu.stage0.runCycles                      4569                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.utilization               12.096262                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles                    34575                       # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles                      3197                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization                8.463942                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles                    34722                       # Number of cycles 0 instructions are processed.
 system.cpu.stage2.runCycles                      3050                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization                8.380502                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles                    35411                       # Number of cycles 0 instructions are processed.
+system.cpu.stage2.utilization                8.074764                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles                    36789                       # Number of cycles 0 instructions are processed.
 system.cpu.stage3.runCycles                       983                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization                2.700995                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles                    33220                       # Number of cycles 0 instructions are processed.
-system.cpu.stage4.runCycles                      3174                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization                8.721218                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.utilization                2.602457                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles                    34600                       # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles                      3172                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization                8.397755                       # Percentage of cycles stage was utilized (processing insts).
 system.cpu.icache.replacements                      0                       # number of replacements
-system.cpu.icache.tagsinuse                136.672418                       # Cycle average of tags in use
-system.cpu.icache.total_refs                      827                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                136.494329                       # Cycle average of tags in use
+system.cpu.icache.total_refs                      825                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    291                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                   2.841924                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs                   2.835052                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     136.672418                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.066735                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.066735                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst          827                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total             827                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst           827                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total              827                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst          827                       # number of overall hits
-system.cpu.icache.overall_hits::total             827                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          347                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           347                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          347                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            347                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          347                       # number of overall misses
-system.cpu.icache.overall_misses::total           347                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     19107000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     19107000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     19107000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     19107000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     19107000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     19107000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         1174                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         1174                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         1174                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         1174                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         1174                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         1174                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.295571                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.295571                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.295571                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.295571                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.295571                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.295571                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55063.400576                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 55063.400576                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 55063.400576                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 55063.400576                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 55063.400576                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 55063.400576                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     136.494329                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.066648                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.066648                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst          825                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total             825                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst           825                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total              825                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst          825                       # number of overall hits
+system.cpu.icache.overall_hits::total             825                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          350                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           350                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          350                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            350                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          350                       # number of overall misses
+system.cpu.icache.overall_misses::total           350                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     19647000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     19647000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     19647000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     19647000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     19647000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     19647000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         1175                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         1175                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         1175                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         1175                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         1175                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         1175                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.297872                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.297872                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.297872                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.297872                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.297872                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.297872                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56134.285714                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 56134.285714                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 56134.285714                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 56134.285714                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 56134.285714                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 56134.285714                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets       106000                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -149,70 +149,70 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets 35333.333333                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst           56                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total           56                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst           56                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total           56                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst           56                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total           56                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst           59                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total           59                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst           59                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total           59                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst           59                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total           59                       # number of overall MSHR hits
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          291                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total          291                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst          291                       # number of demand (read+write) MSHR misses
 system.cpu.icache.demand_mshr_misses::total          291                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          291                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          291                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     15468000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     15468000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     15468000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     15468000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     15468000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     15468000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.247871                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.247871                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.247871                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.247871                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.247871                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.247871                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53154.639175                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53154.639175                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53154.639175                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 53154.639175                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53154.639175                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 53154.639175                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     15992500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     15992500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     15992500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     15992500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     15992500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     15992500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.247660                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.247660                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.247660                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.247660                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.247660                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.247660                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54957.044674                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54957.044674                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54957.044674                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 54957.044674                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54957.044674                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 54957.044674                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.tagsinuse                 82.864730                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                     1049                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse                 82.670041                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                     1046                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                    135                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                   7.770370                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                   7.748148                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data      82.864730                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.020231                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.020231                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data          657                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total             657                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data          392                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total            392                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          1049                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             1049                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         1049                       # number of overall hits
-system.cpu.dcache.overall_hits::total            1049                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data           59                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total            59                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data          281                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total          281                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          340                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            340                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          340                       # number of overall misses
-system.cpu.dcache.overall_misses::total           340                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      3291500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      3291500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     15458000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     15458000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     18749500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     18749500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     18749500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     18749500                       # number of overall miss cycles
+system.cpu.dcache.occ_blocks::cpu.data      82.670041                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.020183                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.020183                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data          655                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total             655                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data          391                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total            391                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data          1046                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             1046                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         1046                       # number of overall hits
+system.cpu.dcache.overall_hits::total            1046                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data           61                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total            61                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data          282                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total          282                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data          343                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            343                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          343                       # number of overall misses
+system.cpu.dcache.overall_misses::total           343                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      3569500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      3569500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     17306500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     17306500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     20876000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     20876000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     20876000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     20876000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data          716                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total          716                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          673                       # number of WriteReq accesses(hits+misses)
@@ -221,38 +221,38 @@ system.cpu.dcache.demand_accesses::cpu.data         1389                       #
 system.cpu.dcache.demand_accesses::total         1389                       # number of demand (read+write) accesses
 system.cpu.dcache.overall_accesses::cpu.data         1389                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total         1389                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.082402                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.082402                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.417533                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.417533                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.244780                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.244780                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.244780                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.244780                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55788.135593                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 55788.135593                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55010.676157                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 55010.676157                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 55145.588235                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 55145.588235                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 55145.588235                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 55145.588235                       # average overall miss latency
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.085196                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.085196                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.419019                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.419019                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.246940                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.246940                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.246940                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.246940                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58516.393443                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 58516.393443                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61370.567376                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 61370.567376                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 60862.973761                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 60862.973761                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 60862.973761                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 60862.973761                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets      2259500                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets      2306500                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets              45                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 50211.111111                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 51255.555556                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data            5                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total            5                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data          200                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total          200                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          205                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          205                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          205                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          205                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data            7                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total            7                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data          201                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total          201                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          208                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          208                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          208                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          208                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data           54                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total           54                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data           81                       # number of WriteReq MSHR misses
@@ -261,14 +261,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          135
 system.cpu.dcache.demand_mshr_misses::total          135                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          135                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          135                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      2866000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      2866000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      4327500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      4327500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      7193500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      7193500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7193500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      7193500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      3065000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      3065000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      4526000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      4526000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      7591000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      7591000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7591000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      7591000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.075419                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.075419                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.120357                       # mshr miss rate for WriteReq accesses
@@ -277,26 +277,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.097192
 system.cpu.dcache.demand_mshr_miss_rate::total     0.097192                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.097192                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.097192                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53074.074074                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53074.074074                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53425.925926                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53425.925926                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53285.185185                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 53285.185185                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53285.185185                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 53285.185185                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 56759.259259                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 56759.259259                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 55876.543210                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 55876.543210                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56229.629630                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 56229.629630                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56229.629630                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 56229.629630                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse               162.299655                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               162.084916                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       3                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                   342                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.008772                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst    136.188396                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data     26.111259                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst     0.004156                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.000797                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.004953                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst    136.002391                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     26.082525                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.004150                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.000796                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.004946                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data            1                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              3                       # number of ReadReq hits
@@ -317,17 +317,17 @@ system.cpu.l2cache.demand_misses::total           423                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          289                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          134                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          423                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     15131000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      2786500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     17917500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      4230500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      4230500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     15131000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data      7017000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     22148000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     15131000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data      7017000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     22148000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     15656000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      2985500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     18641500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      4434500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      4434500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     15656000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      7420000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     23076000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     15656000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      7420000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     23076000                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst          291                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data           54                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total          345                       # number of ReadReq accesses(hits+misses)
@@ -350,17 +350,17 @@ system.cpu.l2cache.demand_miss_rate::total     0.992958                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.993127                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.992593                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.992958                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52356.401384                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52575.471698                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 52390.350877                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52228.395062                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52228.395062                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52356.401384                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52365.671642                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52359.338061                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52356.401384                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52365.671642                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52359.338061                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54173.010381                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56330.188679                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 54507.309942                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54746.913580                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54746.913580                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54173.010381                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55373.134328                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 54553.191489                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54173.010381                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55373.134328                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 54553.191489                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -380,17 +380,17 @@ system.cpu.l2cache.demand_mshr_misses::total          423
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          289                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          134                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          423                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     11603500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      2143500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     13747000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3255500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      3255500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     11603500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5399000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     17002500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     11603500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5399000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     17002500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     12139500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      2343500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     14483000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3454500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      3454500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     12139500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5798000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     17937500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     12139500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5798000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     17937500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.993127                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.981481                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.991304                       # mshr miss rate for ReadReq accesses
@@ -402,17 +402,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.992958
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.993127                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.992593                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.992958                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40150.519031                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40443.396226                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40195.906433                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40191.358025                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40191.358025                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40150.519031                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40291.044776                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40195.035461                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40150.519031                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40291.044776                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40195.035461                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42005.190311                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44216.981132                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42347.953216                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42648.148148                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42648.148148                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42005.190311                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43268.656716                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42405.437352                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42005.190311                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43268.656716                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42405.437352                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini
index 232d3350e..53f402a63 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini
@@ -148,7 +148,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
@@ -180,7 +180,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout
index e4af58bc7..81bff15c4 100755
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun  4 2012 12:01:47
-gem5 started Jun  4 2012 14:44:42
+gem5 compiled Jul  2 2012 08:54:18
+gem5 started Jul  2 2012 11:30:26
 gem5 executing on zizzer
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
-Hello World!Exiting @ tick 28206000 because target called exit()
+Hello World!Exiting @ tick 29541000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
index 3580b75db..d0e2c9d97 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000028                       # Number of seconds simulated
-sim_ticks                                    28206000                       # Number of ticks simulated
-final_tick                                   28206000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000030                       # Number of seconds simulated
+sim_ticks                                    29541000                       # Number of ticks simulated
+final_tick                                   29541000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 427855                       # Simulator instruction rate (inst/s)
-host_op_rate                                   427237                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2253599179                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 221156                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
+host_inst_rate                                  73924                       # Simulator instruction rate (inst/s)
+host_op_rate                                    73907                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              408761366                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 220016                       # Number of bytes of host memory used
+host_seconds                                     0.07                       # Real time elapsed on the host
 sim_insts                                        5340                       # Number of instructions simulated
 sim_ops                                          5340                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             16320                       # Number of bytes read from this memory
@@ -19,16 +19,16 @@ system.physmem.bytes_inst_read::total           16320                       # Nu
 system.physmem.num_reads::cpu.inst                255                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                134                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   389                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            578600298                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            304048784                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               882649082                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       578600298                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          578600298                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           578600298                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           304048784                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              882649082                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            552452524                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            290308385                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               842760909                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       552452524                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          552452524                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           552452524                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           290308385                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              842760909                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
-system.cpu.numCycles                            56412                       # number of cpu cycles simulated
+system.cpu.numCycles                            59082                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        5340                       # Number of instructions committed
@@ -47,18 +47,18 @@ system.cpu.num_mem_refs                          1402                       # nu
 system.cpu.num_load_insts                         724                       # Number of load instructions
 system.cpu.num_store_insts                        678                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                      56412                       # Number of busy cycles
+system.cpu.num_busy_cycles                      59082                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                      0                       # number of replacements
-system.cpu.icache.tagsinuse                116.975932                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                117.079183                       # Cycle average of tags in use
 system.cpu.icache.total_refs                     5127                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    257                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                  19.949416                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     116.975932                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.057117                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.057117                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst     117.079183                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.057168                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.057168                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst         5127                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total            5127                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst          5127                       # number of demand (read+write) hits
@@ -129,14 +129,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52673.151751
 system.cpu.icache.overall_avg_mshr_miss_latency::total 52673.151751                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.tagsinuse                 82.065697                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse                 82.107175                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                     1254                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                    135                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                   9.288889                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data      82.065697                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.020036                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.020036                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::cpu.data      82.107175                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.020046                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.020046                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data          662                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total             662                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          592                       # number of WriteReq hits
@@ -227,16 +227,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52688.888889
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 52688.888889                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse               142.102892                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               142.223187                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       3                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                   308                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.009740                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst    116.450335                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data     25.652557                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst     0.003554                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.000783                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.004337                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst    116.548564                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     25.674623                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.003557                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.000784                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.004340                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data            1                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              3                       # number of ReadReq hits
diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
index f4e4acba8..73bd70079 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
@@ -500,7 +500,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
@@ -532,7 +532,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
 slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
 
diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout
index 19d634444..3bef840f7 100755
--- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout
@@ -1,11 +1,11 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun  4 2012 13:44:28
-gem5 started Jun  4 2012 15:03:58
+gem5 compiled Jul  2 2012 08:58:39
+gem5 started Jul  2 2012 12:38:36
 gem5 executing on zizzer
-command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing
+command line: build/X86/gem5.fast -d build/X86/tests/fast/quick/se/00.hello/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/quick/se/00.hello/x86/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
-Exiting @ tick 12198000 because target called exit()
+Exiting @ tick 12803000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
index b16a10afa..d0e4f2a16 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
@@ -1,272 +1,272 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000012                       # Number of seconds simulated
-sim_ticks                                    12198000                       # Number of ticks simulated
-final_tick                                   12198000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000013                       # Number of seconds simulated
+sim_ticks                                    12803000                       # Number of ticks simulated
+final_tick                                   12803000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  39950                       # Simulator instruction rate (inst/s)
-host_op_rate                                    72345                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               89952499                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 224288                       # Number of bytes of host memory used
-host_seconds                                     0.14                       # Real time elapsed on the host
+host_inst_rate                                  24032                       # Simulator instruction rate (inst/s)
+host_op_rate                                    43521                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               56800152                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 227452                       # Number of bytes of host memory used
+host_seconds                                     0.23                       # Real time elapsed on the host
 sim_insts                                        5416                       # Number of instructions simulated
 sim_ops                                          9809                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst             19328                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data              9536                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                28864                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        19328                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           19328                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                302                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data                149                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                   451                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst           1584522053                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            781767503                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              2366289556                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      1584522053                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         1584522053                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          1584522053                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           781767503                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             2366289556                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst             19264                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              9280                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                28544                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        19264                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           19264                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                301                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                145                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                   446                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst           1504647348                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            724830118                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              2229477466                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      1504647348                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         1504647348                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          1504647348                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           724830118                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             2229477466                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
-system.cpu.numCycles                            24397                       # number of cpu cycles simulated
+system.cpu.numCycles                            25607                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                     3206                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted               3206                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect                560                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups                  2627                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                      792                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                     3125                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted               3125                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect                558                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups                  2605                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                      830                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
 system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles               7375                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          15410                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        3206                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches                792                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          4170                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                    2487                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles                   3163                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                   16                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles            98                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                      1951                       # Number of cache lines fetched
+system.cpu.fetch.icacheStallCycles               8034                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          14981                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        3125                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches                830                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                          4070                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                    2483                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles                   3408                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                   41                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles           244                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                      1957                       # Number of cache lines fetched
 system.cpu.fetch.IcacheSquashes                   281                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              16727                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.635918                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.075272                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples              17679                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.502687                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.975668                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                    12659     75.68%     75.68% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                      177      1.06%     76.74% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      166      0.99%     77.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      214      1.28%     79.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      171      1.02%     80.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      175      1.05%     81.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      250      1.49%     82.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      166      0.99%     83.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     2749     16.43%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                    13710     77.55%     77.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                      177      1.00%     78.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      164      0.93%     79.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      211      1.19%     80.67% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      170      0.96%     81.63% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      182      1.03%     82.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      260      1.47%     84.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      162      0.92%     85.05% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                     2643     14.95%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                16727                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.131410                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.631635                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                     7836                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                  3109                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      3749                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                   128                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                   1905                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts                  26025                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles                   1905                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                     8180                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                    1960                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles            442                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      3522                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                   718                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  24463                       # Number of instructions processed by rename
+system.cpu.fetch.rateDist::total                17679                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.122037                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.585035                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                     8588                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                  3390                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      3692                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                   127                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                   1882                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts                  25327                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles                   1882                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                     8910                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                    2031                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles            505                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                      3461                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                   890                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                  23802                       # Number of instructions processed by rename
 system.cpu.rename.ROBFullEvents                     3                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                     50                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents                   591                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.IQFullEvents                     47                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents                   747                       # Number of times rename has blocked due to LSQ full
 system.cpu.rename.FullRegisterEvents                1                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands               35223                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 70488                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            70472                       # Number of integer rename lookups
+system.cpu.rename.RenamedOperands               34224                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 68607                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            68591                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups                16                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps                 14707                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                    20516                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                 33                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts             33                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                      1918                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 2376                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                1791                       # Number of stores inserted to the mem dependence unit.
+system.cpu.rename.UndoneMaps                    19517                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                 35                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts             35                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                      1875                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                 2306                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                1775                       # Number of stores inserted to the mem dependence unit.
 system.cpu.memDep0.conflictingLoads                11                       # Number of conflicting loads.
 system.cpu.memDep0.conflictingStores                4                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                      21692                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                  38                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                     17854                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued                82                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined           11255                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined        20549                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             25                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         16727                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.067376                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.893384                       # Number of insts issued each cycle
+system.cpu.iq.iqInstsAdded                      21232                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                  40                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                     17582                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued                92                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined           10865                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined        19620                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             27                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples         17679                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.994513                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.826049                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0               11276     67.41%     67.41% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                1383      8.27%     75.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                1035      6.19%     81.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 667      3.99%     85.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 692      4.14%     89.99% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 723      4.32%     94.31% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 673      4.02%     98.34% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                 245      1.46%     99.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8                  33      0.20%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0               12114     68.52%     68.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                1582      8.95%     77.47% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                1012      5.72%     83.19% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 689      3.90%     87.09% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 696      3.94%     91.03% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 692      3.91%     94.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 627      3.55%     98.49% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                 233      1.32%     99.81% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                  34      0.19%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           16727                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           17679                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                     140     73.30%     73.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     73.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     73.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     73.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     73.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     73.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     73.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     73.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     73.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     73.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     73.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     73.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     73.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     73.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     73.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     73.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     73.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     73.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     73.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     73.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     73.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     73.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     73.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     73.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     73.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     73.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     73.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     73.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     73.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                     30     15.71%     89.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                    21     10.99%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                     133     73.08%     73.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     73.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     73.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     73.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     73.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     73.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     73.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     73.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     73.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     73.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     73.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     73.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     73.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     73.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     73.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     73.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     73.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     73.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     73.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     73.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     73.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     73.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     73.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     73.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     73.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     73.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     73.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     73.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     73.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                     29     15.93%     89.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    20     10.99%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 4      0.02%      0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                 14397     80.64%     80.66% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    0      0.00%     80.66% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     80.66% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     80.66% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     80.66% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     80.66% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     80.66% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     80.66% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     80.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     80.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     80.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     80.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     80.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     80.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     80.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     80.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     80.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     80.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     80.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     80.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     80.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     80.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     80.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     80.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     80.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     80.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     80.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     80.66% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     80.66% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 1982     11.10%     91.76% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                1471      8.24%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                 14185     80.68%     80.70% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    0      0.00%     80.70% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     80.70% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     80.70% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     80.70% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     80.70% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     80.70% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     80.70% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     80.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     80.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     80.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     80.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     80.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     80.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     80.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     80.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     80.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     80.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     80.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     80.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     80.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     80.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     80.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     80.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     80.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     80.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     80.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     80.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     80.70% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 1924     10.94%     91.64% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1469      8.36%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                  17854                       # Type of FU issued
-system.cpu.iq.rate                           0.731811                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                         191                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.010698                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              52700                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             32991                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses        16402                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total                  17582                       # Type of FU issued
+system.cpu.iq.rate                           0.686609                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                         182                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.010351                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              53109                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             32144                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses        16183                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                   8                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                  4                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses            4                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                  18037                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                  17756                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                       4                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads              151                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads              148                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads         1320                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses           20                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.squashedLoads         1250                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses           14                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread0.memOrderViolation           11                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          857                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores          841                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                   1905                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                    1329                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                    39                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               21730                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts                24                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  2376                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                 1791                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                 34                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                     10                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles                   1882                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                    1425                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                    33                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts               21272                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts                46                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts                  2306                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                 1775                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                 36                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                      4                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewLSQFullEvents                     0                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.memOrderViolationEvents             11                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect             59                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect          631                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                  690                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                 16824                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                  1844                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts              1030                       # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedTakenIncorrect             65                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect          640                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts                  705                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                 16602                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                  1794                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts               980                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                         3203                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                     1645                       # Number of branches executed
-system.cpu.iew.exec_stores                       1359                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.689593                       # Inst execution rate
-system.cpu.iew.wb_sent                          16593                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                         16406                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                     10679                       # num instructions producing a value
-system.cpu.iew.wb_consumers                     24448                       # num instructions consuming a value
+system.cpu.iew.exec_refs                         3144                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                     1642                       # Number of branches executed
+system.cpu.iew.exec_stores                       1350                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.648338                       # Inst execution rate
+system.cpu.iew.wb_sent                          16384                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                         16187                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                     10480                       # num instructions producing a value
+system.cpu.iew.wb_consumers                     24095                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.672460                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.436805                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.632132                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.434945                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts           5416                       # The number of committed instructions
 system.cpu.commit.commitCommittedOps             9809                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts           11920                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts           11462                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              13                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts               571                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        14822                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.661787                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.507902                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts               589                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples        15797                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.620941                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.463366                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0        11181     75.44%     75.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1         1365      9.21%     84.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          653      4.41%     89.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          730      4.93%     93.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          365      2.46%     96.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5          129      0.87%     97.31% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6          139      0.94%     98.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           71      0.48%     98.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8          189      1.28%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0        12065     76.38%     76.38% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         1534      9.71%     86.09% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          576      3.65%     89.73% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          731      4.63%     94.36% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          367      2.32%     96.68% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          129      0.82%     97.50% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6          134      0.85%     98.35% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           75      0.47%     98.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8          186      1.18%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        14822                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        15797                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts                 5416                       # Number of instructions committed
 system.cpu.commit.committedOps                   9809                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -277,68 +277,68 @@ system.cpu.commit.branches                       1214                       # Nu
 system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                      9714                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                    0                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events                   189                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events                   186                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                        36362                       # The number of ROB reads
-system.cpu.rob.rob_writes                       45397                       # The number of ROB writes
-system.cpu.timesIdled                             150                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                            7670                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                        36882                       # The number of ROB reads
+system.cpu.rob.rob_writes                       44457                       # The number of ROB writes
+system.cpu.timesIdled                             153                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                            7928                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        5416                       # Number of Instructions Simulated
 system.cpu.committedOps                          9809                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total                  5416                       # Number of Instructions Simulated
-system.cpu.cpi                               4.504616                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         4.504616                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.221995                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.221995                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    35460                       # number of integer regfile reads
-system.cpu.int_regfile_writes                   22063                       # number of integer regfile writes
+system.cpu.cpi                               4.728028                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         4.728028                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.211505                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.211505                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                    35136                       # number of integer regfile reads
+system.cpu.int_regfile_writes                   21832                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                         4                       # number of floating regfile reads
-system.cpu.misc_regfile_reads                    7402                       # number of misc regfile reads
+system.cpu.misc_regfile_reads                    7303                       # number of misc regfile reads
 system.cpu.icache.replacements                      0                       # number of replacements
-system.cpu.icache.tagsinuse                145.636183                       # Cycle average of tags in use
-system.cpu.icache.total_refs                     1561                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                    304                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                   5.134868                       # Average number of references to valid blocks.
+system.cpu.icache.tagsinuse                144.987593                       # Cycle average of tags in use
+system.cpu.icache.total_refs                     1569                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    302                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                   5.195364                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     145.636183                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.071111                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.071111                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst         1561                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            1561                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          1561                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             1561                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         1561                       # number of overall hits
-system.cpu.icache.overall_hits::total            1561                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          390                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           390                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          390                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            390                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          390                       # number of overall misses
-system.cpu.icache.overall_misses::total           390                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     13866500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     13866500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     13866500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     13866500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     13866500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     13866500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         1951                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         1951                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         1951                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         1951                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         1951                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         1951                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.199897                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.199897                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.199897                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.199897                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.199897                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.199897                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35555.128205                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 35555.128205                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 35555.128205                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 35555.128205                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 35555.128205                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 35555.128205                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     144.987593                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.070795                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.070795                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst         1569                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            1569                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          1569                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             1569                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         1569                       # number of overall hits
+system.cpu.icache.overall_hits::total            1569                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          388                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           388                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          388                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            388                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          388                       # number of overall misses
+system.cpu.icache.overall_misses::total           388                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     14367500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     14367500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     14367500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     14367500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     14367500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     14367500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         1957                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         1957                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         1957                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         1957                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         1957                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         1957                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.198263                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.198263                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.198263                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.198263                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.198263                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.198263                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37029.639175                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 37029.639175                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 37029.639175                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 37029.639175                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 37029.639175                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 37029.639175                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -353,88 +353,88 @@ system.cpu.icache.demand_mshr_hits::cpu.inst           86
 system.cpu.icache.demand_mshr_hits::total           86                       # number of demand (read+write) MSHR hits
 system.cpu.icache.overall_mshr_hits::cpu.inst           86                       # number of overall MSHR hits
 system.cpu.icache.overall_mshr_hits::total           86                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          304                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          304                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          304                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          304                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          304                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          304                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     10687000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     10687000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     10687000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     10687000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     10687000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     10687000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.155818                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.155818                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.155818                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.155818                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.155818                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.155818                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35154.605263                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35154.605263                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35154.605263                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 35154.605263                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35154.605263                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 35154.605263                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          302                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          302                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          302                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          302                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          302                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          302                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     11138000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     11138000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     11138000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     11138000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     11138000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     11138000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.154318                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.154318                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.154318                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.154318                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.154318                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.154318                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36880.794702                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36880.794702                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36880.794702                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 36880.794702                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36880.794702                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 36880.794702                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.tagsinuse                 84.751522                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                     2365                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                    148                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  15.979730                       # Average number of references to valid blocks.
+system.cpu.dcache.tagsinuse                 83.196834                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                     2330                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                    144                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  16.180556                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data      84.751522                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.020691                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.020691                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data         1507                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1507                       # number of ReadReq hits
+system.cpu.dcache.occ_blocks::cpu.data      83.196834                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.020312                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.020312                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data         1472                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1472                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          858                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total            858                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          2365                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             2365                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         2365                       # number of overall hits
-system.cpu.dcache.overall_hits::total            2365                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          115                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           115                       # number of ReadReq misses
+system.cpu.dcache.demand_hits::cpu.data          2330                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             2330                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         2330                       # number of overall hits
+system.cpu.dcache.overall_hits::total            2330                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          112                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           112                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data           76                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_misses::total           76                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          191                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            191                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          191                       # number of overall misses
-system.cpu.dcache.overall_misses::total           191                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      4030500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      4030500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data      2917500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      2917500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data      6948000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total      6948000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data      6948000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total      6948000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         1622                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         1622                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data          188                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            188                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          188                       # number of overall misses
+system.cpu.dcache.overall_misses::total           188                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      4401500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      4401500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      3078500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      3078500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data      7480000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total      7480000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data      7480000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total      7480000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         1584                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1584                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          934                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total          934                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         2556                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2556                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         2556                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2556                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.070900                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.070900                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data         2518                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2518                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2518                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2518                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.070707                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.070707                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.081370                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.081370                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.074726                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.074726                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.074726                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.074726                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35047.826087                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 35047.826087                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38388.157895                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 38388.157895                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 36376.963351                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 36376.963351                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 36376.963351                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 36376.963351                       # average overall miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.074662                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.074662                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.074662                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.074662                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39299.107143                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 39299.107143                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40506.578947                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 40506.578947                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 39787.234043                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 39787.234043                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 39787.234043                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 39787.234043                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -443,117 +443,117 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data           42                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           42                       # number of ReadReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data           42                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total           42                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data           42                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total           42                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data           73                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total           73                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           43                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           43                       # number of ReadReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data           43                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total           43                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data           43                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total           43                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data           69                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total           69                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data           76                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total           76                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data          149                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total          149                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data          149                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total          149                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      2574000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      2574000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      2689500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      2689500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      5263500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      5263500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      5263500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      5263500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.045006                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.045006                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_misses::cpu.data          145                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total          145                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data          145                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total          145                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      2699500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      2699500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      2850500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      2850500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      5550000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      5550000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      5550000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      5550000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.043561                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.043561                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.081370                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.081370                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.058294                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.058294                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.058294                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.058294                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35260.273973                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35260.273973                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35388.157895                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35388.157895                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35325.503356                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 35325.503356                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35325.503356                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 35325.503356                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.057585                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.057585                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.057585                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.057585                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39123.188406                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39123.188406                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37506.578947                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37506.578947                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38275.862069                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 38275.862069                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38275.862069                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 38275.862069                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse               179.622577                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                       2                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                   374                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  0.005348                       # Average number of references to valid blocks.
+system.cpu.l2cache.tagsinuse               177.887385                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                       1                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                   369                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.002710                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst    145.234150                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data     34.388427                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst     0.004432                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.001049                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.005482                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total              2                       # number of ReadReq hits
-system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total               2                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst            2                       # number of overall hits
-system.cpu.l2cache.overall_hits::total              2                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          302                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data           73                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total          375                       # number of ReadReq misses
+system.cpu.l2cache.occ_blocks::cpu.inst    144.949907                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     32.937478                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.004424                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.001005                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.005429                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst            1                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total              1                       # number of ReadReq hits
+system.cpu.l2cache.demand_hits::cpu.inst            1                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total               1                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst            1                       # number of overall hits
+system.cpu.l2cache.overall_hits::total              1                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          301                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data           69                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total          370                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data           76                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total           76                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          302                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data          149                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total           451                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          302                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data          149                       # number of overall misses
-system.cpu.l2cache.overall_misses::total          451                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     10368000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      2486500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     12854500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      2603000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      2603000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     10368000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data      5089500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     15457500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     10368000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data      5089500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     15457500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          304                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data           73                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total          377                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.demand_misses::cpu.inst          301                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data          145                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total           446                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          301                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data          145                       # number of overall misses
+system.cpu.l2cache.overall_misses::total          446                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     10831500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      2627000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     13458500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      2772000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      2772000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     10831500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      5399000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     16230500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     10831500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      5399000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     16230500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          302                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data           69                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total          371                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data           76                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total           76                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          304                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data          149                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total          453                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          304                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data          149                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total          453                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.993421                       # miss rate for ReadReq accesses
+system.cpu.l2cache.demand_accesses::cpu.inst          302                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data          145                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total          447                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          302                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data          145                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total          447                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.996689                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.994695                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.997305                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.993421                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.996689                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.995585                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.993421                       # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::total     0.997763                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996689                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.995585                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34331.125828                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34061.643836                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 34278.666667                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        34250                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total        34250                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34331.125828                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34157.718121                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 34273.835920                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34331.125828                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34157.718121                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 34273.835920                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total     0.997763                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35985.049834                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 38072.463768                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 36374.324324                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 36473.684211                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 36473.684211                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35985.049834                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 37234.482759                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 36391.255605                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35985.049834                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 37234.482759                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 36391.255605                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -562,50 +562,50 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          302                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           73                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total          375                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          301                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           69                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total          370                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           76                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total           76                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          302                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data          149                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total          451                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          302                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data          149                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total          451                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst      9394000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      2263500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     11657500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      2369500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2369500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst      9394000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      4633000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     14027000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst      9394000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      4633000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     14027000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.993421                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          301                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data          145                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total          446                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          301                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data          145                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total          446                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst      9877000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      2416500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     12293500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      2541500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2541500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst      9877000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      4958000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     14835000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst      9877000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      4958000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     14835000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.996689                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.994695                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.997305                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.993421                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.996689                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.995585                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.993421                       # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.997763                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996689                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.995585                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31105.960265                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31006.849315                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31086.666667                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31177.631579                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31177.631579                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31105.960265                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31093.959732                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31101.995565                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31105.960265                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31093.959732                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31101.995565                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.997763                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32813.953488                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 35021.739130                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33225.675676                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33440.789474                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33440.789474                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32813.953488                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34193.103448                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33262.331839                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32813.953488                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34193.103448                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33262.331839                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
index 3ced8b832..75df56c4d 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
@@ -169,7 +169,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
@@ -201,7 +201,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
 slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
 
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout
index 62a044b81..c1b9925b1 100755
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout
@@ -1,11 +1,11 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun  4 2012 13:44:28
-gem5 started Jun  4 2012 15:04:19
+gem5 compiled Jul  2 2012 08:58:39
+gem5 started Jul  2 2012 12:38:59
 gem5 executing on zizzer
-command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing
+command line: build/X86/gem5.fast -d build/X86/tests/fast/quick/se/00.hello/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/quick/se/00.hello/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
-Exiting @ tick 28768000 because target called exit()
+Exiting @ tick 29726000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
index 1e89d36d4..4b1ad61d2 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000029                       # Number of seconds simulated
-sim_ticks                                    28768000                       # Number of ticks simulated
-final_tick                                   28768000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000030                       # Number of seconds simulated
+sim_ticks                                    29726000                       # Number of ticks simulated
+final_tick                                   29726000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 318234                       # Simulator instruction rate (inst/s)
-host_op_rate                                   575684                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1686451163                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 223048                       # Number of bytes of host memory used
-host_seconds                                     0.02                       # Real time elapsed on the host
+host_inst_rate                                 107097                       # Simulator instruction rate (inst/s)
+host_op_rate                                   193883                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              587308683                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 226300                       # Number of bytes of host memory used
+host_seconds                                     0.05                       # Real time elapsed on the host
 sim_insts                                        5417                       # Number of instructions simulated
 sim_ops                                          9810                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             14528                       # Number of bytes read from this memory
@@ -19,16 +19,16 @@ system.physmem.bytes_inst_read::total           14528                       # Nu
 system.physmem.num_reads::cpu.inst                227                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                134                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   361                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            505005562                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            298109010                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               803114572                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       505005562                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          505005562                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           505005562                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           298109010                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              803114572                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            488730404                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            288501648                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               777232053                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       488730404                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          488730404                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           488730404                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           288501648                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              777232053                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
-system.cpu.numCycles                            57536                       # number of cpu cycles simulated
+system.cpu.numCycles                            59452                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        5417                       # Number of instructions committed
@@ -47,18 +47,18 @@ system.cpu.num_mem_refs                          1990                       # nu
 system.cpu.num_load_insts                        1056                       # Number of load instructions
 system.cpu.num_store_insts                        934                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                      57536                       # Number of busy cycles
+system.cpu.num_busy_cycles                      59452                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                      0                       # number of replacements
-system.cpu.icache.tagsinuse                105.363985                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                105.590396                       # Cycle average of tags in use
 system.cpu.icache.total_refs                     6683                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    228                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                  29.311404                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     105.363985                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.051447                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.051447                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst     105.590396                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.051558                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.051558                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst         6683                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total            6683                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst          6683                       # number of demand (read+write) hits
@@ -129,14 +129,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52815.789474
 system.cpu.icache.overall_avg_mshr_miss_latency::total 52815.789474                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.tagsinuse                 80.668870                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse                 80.767478                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                     1856                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                    134                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                  13.850746                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data      80.668870                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.019695                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.019695                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::cpu.data      80.767478                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.019719                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.019719                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data         1001                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total            1001                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          855                       # number of WriteReq hits
@@ -227,16 +227,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        53000
 system.cpu.dcache.overall_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse               133.809342                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               134.079161                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       1                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                   282                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.003546                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst    105.370729                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data     28.438613                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst     0.003216                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.000868                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.004084                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst    105.593760                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     28.485401                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.003222                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.000869                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.004092                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst            1                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              1                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            1                       # number of demand (read+write) hits
diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
index 01d2e4278..856b4f64d 100644
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
@@ -479,7 +479,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
@@ -530,7 +530,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
index 8da405b24..94c9ff95a 100755
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
+++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:05:18
-gem5 started Jun 28 2012 22:09:52
+gem5 compiled Jul  2 2012 08:30:56
+gem5 started Jul  2 2012 09:08:40
 gem5 executing on zizzer
 command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/01.hello-2T-smt/alpha/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
@@ -11,4 +11,4 @@ info: Increasing stack size by one page.
 info: Increasing stack size by one page.
 Hello world!
 Hello world!
-Exiting @ tick 13801000 because target called exit()
+Exiting @ tick 15041500 because target called exit()
diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
index 3bebb79ad..a5109fa39 100644
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
+++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
@@ -1,52 +1,52 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000014                       # Number of seconds simulated
-sim_ticks                                    13801000                       # Number of ticks simulated
-final_tick                                   13801000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000015                       # Number of seconds simulated
+sim_ticks                                    15041500                       # Number of ticks simulated
+final_tick                                   15041500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  32086                       # Simulator instruction rate (inst/s)
-host_op_rate                                    32085                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               34665771                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 218816                       # Number of bytes of host memory used
-host_seconds                                     0.40                       # Real time elapsed on the host
+host_inst_rate                                 102152                       # Simulator instruction rate (inst/s)
+host_op_rate                                   102138                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              120262580                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 219804                       # Number of bytes of host memory used
+host_seconds                                     0.13                       # Real time elapsed on the host
 sim_insts                                       12773                       # Number of instructions simulated
 sim_ops                                         12773                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst             40000                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data             22720                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                62720                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        40000                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           40000                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                625                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data                355                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                   980                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst           2898340700                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data           1646257518                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              4544598218                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      2898340700                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         2898340700                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          2898340700                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data          1646257518                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             4544598218                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst             39936                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data             22400                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                62336                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        39936                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           39936                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                624                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                350                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                   974                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst           2655054350                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data           1489213177                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              4144267527                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      2655054350                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         2655054350                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          2655054350                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data          1489213177                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             4144267527                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                         4109                       # DTB read hits
-system.cpu.dtb.read_misses                         91                       # DTB read misses
+system.cpu.dtb.read_hits                         4063                       # DTB read hits
+system.cpu.dtb.read_misses                         99                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                     4200                       # DTB read accesses
-system.cpu.dtb.write_hits                        2070                       # DTB write hits
-system.cpu.dtb.write_misses                        61                       # DTB write misses
+system.cpu.dtb.read_accesses                     4162                       # DTB read accesses
+system.cpu.dtb.write_hits                        2079                       # DTB write hits
+system.cpu.dtb.write_misses                        66                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                    2131                       # DTB write accesses
-system.cpu.dtb.data_hits                         6179                       # DTB hits
-system.cpu.dtb.data_misses                        152                       # DTB misses
+system.cpu.dtb.write_accesses                    2145                       # DTB write accesses
+system.cpu.dtb.data_hits                         6142                       # DTB hits
+system.cpu.dtb.data_misses                        165                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                     6331                       # DTB accesses
-system.cpu.itb.fetch_hits                        5033                       # ITB hits
-system.cpu.itb.fetch_misses                        52                       # ITB misses
+system.cpu.dtb.data_accesses                     6307                       # DTB accesses
+system.cpu.itb.fetch_hits                        4998                       # ITB hits
+system.cpu.itb.fetch_misses                        64                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                    5085                       # ITB accesses
+system.cpu.itb.fetch_accesses                    5062                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -61,360 +61,361 @@ system.cpu.itb.data_acv                             0                       # DT
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload0.num_syscalls                  17                       # Number of system calls
 system.cpu.workload1.num_syscalls                  17                       # Number of system calls
-system.cpu.numCycles                            27603                       # number of cpu cycles simulated
+system.cpu.numCycles                            30084                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                     6273                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted               3546                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect               1676                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups                  4641                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                      749                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                     6210                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted               3535                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect               1700                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups                  4700                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                      759                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                      905                       # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect                 178                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles               1498                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          35104                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        6273                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches               1654                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          5870                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                    1752                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                   45                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.CacheLines                      5033                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   742                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              21582                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.626541                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.950246                       # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS                      825                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect                 175                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles               1535                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          34626                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        6210                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches               1584                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                          5789                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                    1776                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                   48                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.CacheLines                      4998                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   745                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples              24259                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.427347                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.816880                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                    15712     72.80%     72.80% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                      465      2.15%     74.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      353      1.64%     76.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      445      2.06%     78.65% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      412      1.91%     80.56% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      367      1.70%     82.26% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      466      2.16%     84.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      577      2.67%     87.10% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     2785     12.90%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                    18470     76.14%     76.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                      464      1.91%     78.05% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      348      1.43%     79.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      447      1.84%     81.33% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      403      1.66%     82.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      343      1.41%     84.40% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      469      1.93%     86.33% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      536      2.21%     88.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                     2779     11.46%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                21582                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.227258                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.271746                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                    29958                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                  5047                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      5024                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                   472                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                   2407                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved                  618                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                   398                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts                  30693                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                   650                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                   2407                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                    30628                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                    2400                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles            805                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      4751                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                  1917                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  28414                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                     8                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.LSQFullEvents                  1949                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands               21384                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 35492                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            35458                       # Number of integer rename lookups
+system.cpu.fetch.rateDist::total                24259                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.206422                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.150977                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                    34703                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                  5701                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      4994                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                   517                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                   2387                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved                  655                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                   440                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts                  30483                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                   727                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                   2387                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                    35405                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                    2859                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles            908                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                      4714                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                  2029                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                  28166                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                    11                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                      1                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents                  2057                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands               21169                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 35183                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            35149                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups                34                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps                  9166                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                    12218                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                 55                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts             43                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                      5512                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 2647                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                1284                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads                 3                       # Number of conflicting loads.
+system.cpu.rename.UndoneMaps                    12003                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                 54                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts             42                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                      5549                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                 2568                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                1287                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads                11                       # Number of conflicting loads.
 system.cpu.memDep0.conflictingStores                0                       # Number of conflicting stores.
-system.cpu.memDep1.insertedLoads                 2635                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep1.insertedStores                1309                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep1.conflictingLoads                14                       # Number of conflicting loads.
+system.cpu.memDep1.insertedLoads                 2598                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep1.insertedStores                1301                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep1.conflictingLoads                17                       # Number of conflicting loads.
 system.cpu.memDep1.conflictingStores                0                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                      25261                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                  50                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                     21461                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued               117                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined           11327                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined         6314                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             16                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         21582                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.994393                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.507504                       # Number of insts issued each cycle
+system.cpu.iq.iqInstsAdded                      25020                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                  51                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                     21261                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued               104                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined           11085                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined         6273                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             17                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples         24259                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.876417                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.449361                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0               12693     58.81%     58.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                3009     13.94%     72.76% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                2444     11.32%     84.08% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                1529      7.08%     91.16% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                1011      4.68%     95.85% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 561      2.60%     98.45% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 239      1.11%     99.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                  74      0.34%     99.90% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8                  22      0.10%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0               15324     63.17%     63.17% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                3188     13.14%     76.31% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                2404      9.91%     86.22% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                1484      6.12%     92.34% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 963      3.97%     96.31% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 553      2.28%     98.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 233      0.96%     99.55% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                  82      0.34%     99.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                  28      0.12%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           21582                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           24259                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                       7      3.76%      3.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      3.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      3.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      3.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      3.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      3.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      3.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      3.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      3.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      3.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      3.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      3.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      3.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      3.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      3.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      3.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      3.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      3.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      3.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      3.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      3.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      3.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      3.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      3.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      3.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      3.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      3.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      3.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      3.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                    115     61.83%     65.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                    64     34.41%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                       5      2.69%      2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                    116     62.37%     65.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    65     34.95%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 2      0.02%      0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                  7347     68.12%     68.13% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    1      0.01%     68.14% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     68.14% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     68.16% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     68.16% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     68.16% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     68.16% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     68.16% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     68.16% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     68.16% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     68.16% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     68.16% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     68.16% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     68.16% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     68.16% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     68.16% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     68.16% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     68.16% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     68.16% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     68.16% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     68.16% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     68.16% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     68.16% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     68.16% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     68.16% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     68.16% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     68.16% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.16% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     68.16% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 2315     21.46%     89.63% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                1119     10.37%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                  7259     68.24%     68.26% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    1      0.01%     68.27% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     68.27% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     68.29% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     68.29% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     68.29% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     68.29% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     68.29% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     68.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     68.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     68.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     68.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     68.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     68.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     68.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     68.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     68.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     68.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     68.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     68.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     68.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     68.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     68.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     68.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     68.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     68.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     68.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     68.29% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 2247     21.12%     89.41% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1126     10.59%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                  10786                       # Type of FU issued
+system.cpu.iq.FU_type_0::total                  10637                       # Type of FU issued
 system.cpu.iq.FU_type_1::No_OpClass                 2      0.02%      0.02% # Type of FU issued
-system.cpu.iq.FU_type_1::IntAlu                  7235     67.78%     67.79% # Type of FU issued
-system.cpu.iq.FU_type_1::IntMult                    1      0.01%     67.80% # Type of FU issued
-system.cpu.iq.FU_type_1::IntDiv                     0      0.00%     67.80% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatAdd                   2      0.02%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatCmp                   0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatCvt                   0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatMult                  0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatDiv                   0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatSqrt                  0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdAdd                    0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdAddAcc                 0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdAlu                    0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdCmp                    0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdCvt                    0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdMisc                   0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdMult                   0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdMultAcc                0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdShift                  0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdShiftAcc               0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdSqrt                   0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatAdd               0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatAlu               0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatCmp               0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatCvt               0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatDiv               0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatMisc              0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatMult              0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatMultAcc            0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatSqrt              0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_1::MemRead                 2307     21.61%     89.43% # Type of FU issued
-system.cpu.iq.FU_type_1::MemWrite                1128     10.57%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_1::IntAlu                  7177     67.55%     67.57% # Type of FU issued
+system.cpu.iq.FU_type_1::IntMult                    1      0.01%     67.58% # Type of FU issued
+system.cpu.iq.FU_type_1::IntDiv                     0      0.00%     67.58% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatAdd                   2      0.02%     67.60% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatCmp                   0      0.00%     67.60% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatCvt                   0      0.00%     67.60% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatMult                  0      0.00%     67.60% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatDiv                   0      0.00%     67.60% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatSqrt                  0      0.00%     67.60% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdAdd                    0      0.00%     67.60% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdAddAcc                 0      0.00%     67.60% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdAlu                    0      0.00%     67.60% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdCmp                    0      0.00%     67.60% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdCvt                    0      0.00%     67.60% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdMisc                   0      0.00%     67.60% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdMult                   0      0.00%     67.60% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdMultAcc                0      0.00%     67.60% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdShift                  0      0.00%     67.60% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdShiftAcc               0      0.00%     67.60% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdSqrt                   0      0.00%     67.60% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatAdd               0      0.00%     67.60% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatAlu               0      0.00%     67.60% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatCmp               0      0.00%     67.60% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatCvt               0      0.00%     67.60% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatDiv               0      0.00%     67.60% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatMisc              0      0.00%     67.60% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatMult              0      0.00%     67.60% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatMultAcc            0      0.00%     67.60% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatSqrt              0      0.00%     67.60% # Type of FU issued
+system.cpu.iq.FU_type_1::MemRead                 2282     21.48%     89.08% # Type of FU issued
+system.cpu.iq.FU_type_1::MemWrite                1160     10.92%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_1::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_1::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_1::total                  10675                       # Type of FU issued
+system.cpu.iq.FU_type_1::total                  10624                       # Type of FU issued
 system.cpu.iq.FU_type::No_OpClass                   4      0.02%      0.02% # Type of FU issued
-system.cpu.iq.FU_type::IntAlu                   14582     67.95%     67.97% # Type of FU issued
-system.cpu.iq.FU_type::IntMult                      2      0.01%     67.97% # Type of FU issued
-system.cpu.iq.FU_type::IntDiv                       0      0.00%     67.97% # Type of FU issued
-system.cpu.iq.FU_type::FloatAdd                     4      0.02%     67.99% # Type of FU issued
-system.cpu.iq.FU_type::FloatCmp                     0      0.00%     67.99% # Type of FU issued
-system.cpu.iq.FU_type::FloatCvt                     0      0.00%     67.99% # Type of FU issued
-system.cpu.iq.FU_type::FloatMult                    0      0.00%     67.99% # Type of FU issued
-system.cpu.iq.FU_type::FloatDiv                     0      0.00%     67.99% # Type of FU issued
-system.cpu.iq.FU_type::FloatSqrt                    0      0.00%     67.99% # Type of FU issued
-system.cpu.iq.FU_type::SimdAdd                      0      0.00%     67.99% # Type of FU issued
-system.cpu.iq.FU_type::SimdAddAcc                   0      0.00%     67.99% # Type of FU issued
-system.cpu.iq.FU_type::SimdAlu                      0      0.00%     67.99% # Type of FU issued
-system.cpu.iq.FU_type::SimdCmp                      0      0.00%     67.99% # Type of FU issued
-system.cpu.iq.FU_type::SimdCvt                      0      0.00%     67.99% # Type of FU issued
-system.cpu.iq.FU_type::SimdMisc                     0      0.00%     67.99% # Type of FU issued
-system.cpu.iq.FU_type::SimdMult                     0      0.00%     67.99% # Type of FU issued
-system.cpu.iq.FU_type::SimdMultAcc                  0      0.00%     67.99% # Type of FU issued
-system.cpu.iq.FU_type::SimdShift                    0      0.00%     67.99% # Type of FU issued
-system.cpu.iq.FU_type::SimdShiftAcc                 0      0.00%     67.99% # Type of FU issued
-system.cpu.iq.FU_type::SimdSqrt                     0      0.00%     67.99% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatAdd                 0      0.00%     67.99% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatAlu                 0      0.00%     67.99% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatCmp                 0      0.00%     67.99% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatCvt                 0      0.00%     67.99% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatDiv                 0      0.00%     67.99% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatMisc                0      0.00%     67.99% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatMult                0      0.00%     67.99% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatMultAcc             0      0.00%     67.99% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatSqrt                0      0.00%     67.99% # Type of FU issued
-system.cpu.iq.FU_type::MemRead                   4622     21.54%     89.53% # Type of FU issued
-system.cpu.iq.FU_type::MemWrite                  2247     10.47%    100.00% # Type of FU issued
+system.cpu.iq.FU_type::IntAlu                   14436     67.90%     67.92% # Type of FU issued
+system.cpu.iq.FU_type::IntMult                      2      0.01%     67.93% # Type of FU issued
+system.cpu.iq.FU_type::IntDiv                       0      0.00%     67.93% # Type of FU issued
+system.cpu.iq.FU_type::FloatAdd                     4      0.02%     67.95% # Type of FU issued
+system.cpu.iq.FU_type::FloatCmp                     0      0.00%     67.95% # Type of FU issued
+system.cpu.iq.FU_type::FloatCvt                     0      0.00%     67.95% # Type of FU issued
+system.cpu.iq.FU_type::FloatMult                    0      0.00%     67.95% # Type of FU issued
+system.cpu.iq.FU_type::FloatDiv                     0      0.00%     67.95% # Type of FU issued
+system.cpu.iq.FU_type::FloatSqrt                    0      0.00%     67.95% # Type of FU issued
+system.cpu.iq.FU_type::SimdAdd                      0      0.00%     67.95% # Type of FU issued
+system.cpu.iq.FU_type::SimdAddAcc                   0      0.00%     67.95% # Type of FU issued
+system.cpu.iq.FU_type::SimdAlu                      0      0.00%     67.95% # Type of FU issued
+system.cpu.iq.FU_type::SimdCmp                      0      0.00%     67.95% # Type of FU issued
+system.cpu.iq.FU_type::SimdCvt                      0      0.00%     67.95% # Type of FU issued
+system.cpu.iq.FU_type::SimdMisc                     0      0.00%     67.95% # Type of FU issued
+system.cpu.iq.FU_type::SimdMult                     0      0.00%     67.95% # Type of FU issued
+system.cpu.iq.FU_type::SimdMultAcc                  0      0.00%     67.95% # Type of FU issued
+system.cpu.iq.FU_type::SimdShift                    0      0.00%     67.95% # Type of FU issued
+system.cpu.iq.FU_type::SimdShiftAcc                 0      0.00%     67.95% # Type of FU issued
+system.cpu.iq.FU_type::SimdSqrt                     0      0.00%     67.95% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatAdd                 0      0.00%     67.95% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatAlu                 0      0.00%     67.95% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatCmp                 0      0.00%     67.95% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatCvt                 0      0.00%     67.95% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatDiv                 0      0.00%     67.95% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatMisc                0      0.00%     67.95% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatMult                0      0.00%     67.95% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatMultAcc             0      0.00%     67.95% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatSqrt                0      0.00%     67.95% # Type of FU issued
+system.cpu.iq.FU_type::MemRead                   4529     21.30%     89.25% # Type of FU issued
+system.cpu.iq.FU_type::MemWrite                  2286     10.75%    100.00% # Type of FU issued
 system.cpu.iq.FU_type::IprAccess                    0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type::InstPrefetch                 0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type::total                    21461                       # Type of FU issued
-system.cpu.iq.rate                           0.777488                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt::0                       93                       # FU busy when requested
-system.cpu.iq.fu_busy_cnt::1                       93                       # FU busy when requested
+system.cpu.iq.FU_type::total                    21261                       # Type of FU issued
+system.cpu.iq.rate                           0.706721                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt::0                       86                       # FU busy when requested
+system.cpu.iq.fu_busy_cnt::1                      100                       # FU busy when requested
 system.cpu.iq.fu_busy_cnt::total                  186                       # FU busy when requested
-system.cpu.iq.fu_busy_rate::0                0.004333                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.fu_busy_rate::1                0.004333                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.fu_busy_rate::total            0.008667                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              64765                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             36642                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses        19216                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fu_busy_rate::0                0.004045                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_busy_rate::1                0.004703                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_busy_rate::total            0.008748                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              67029                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             36163                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses        19051                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                  42                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                 20                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           20                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                  21621                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                  21421                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                      22                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads               55                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads               47                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads         1462                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses            4                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation           16                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          419                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads         1383                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation           14                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores          422                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            1                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread1.forwLoads               61                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread1.forwLoads               65                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread1.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread1.squashedLoads         1450                       # Number of loads squashed
-system.cpu.iew.lsq.thread1.ignoredResponses            1                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread1.memOrderViolation           17                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread1.squashedStores          444                       # Number of stores squashed
+system.cpu.iew.lsq.thread1.squashedLoads         1413                       # Number of loads squashed
+system.cpu.iew.lsq.thread1.ignoredResponses            2                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread1.memOrderViolation           16                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread1.squashedStores          436                       # Number of stores squashed
 system.cpu.iew.lsq.thread1.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread1.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread1.rescheduledLoads            1                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread1.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                   2407                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                     503                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                    41                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               25446                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts               693                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  5282                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                 2593                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                 50                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                     33                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                     2                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents             33                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect            259                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect         1247                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                 1506                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                 20047                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts::0               2108                       # Number of load instructions executed
-system.cpu.iew.iewExecLoadInsts::1               2105                       # Number of load instructions executed
-system.cpu.iew.iewExecLoadInsts::total           4213                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts              1414                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                   2387                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                     608                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                    48                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts               25214                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts               623                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts                  5166                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                 2588                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                 51                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                     40                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                     1                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents             30                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect            252                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect         1229                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts                 1481                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                 19905                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts::0               2053                       # Number of load instructions executed
+system.cpu.iew.iewExecLoadInsts::1               2121                       # Number of load instructions executed
+system.cpu.iew.iewExecLoadInsts::total           4174                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts              1356                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp::0                          0                       # number of swp insts executed
 system.cpu.iew.exec_swp::1                          0                       # number of swp insts executed
 system.cpu.iew.exec_swp::total                      0                       # number of swp insts executed
-system.cpu.iew.exec_nop::0                         69                       # number of nop insts executed
-system.cpu.iew.exec_nop::1                         66                       # number of nop insts executed
-system.cpu.iew.exec_nop::total                    135                       # number of nop insts executed
-system.cpu.iew.exec_refs::0                      3190                       # number of memory reference insts executed
-system.cpu.iew.exec_refs::1                      3171                       # number of memory reference insts executed
-system.cpu.iew.exec_refs::total                  6361                       # number of memory reference insts executed
-system.cpu.iew.exec_branches::0                  1643                       # Number of branches executed
-system.cpu.iew.exec_branches::1                  1639                       # Number of branches executed
-system.cpu.iew.exec_branches::total              3282                       # Number of branches executed
-system.cpu.iew.exec_stores::0                    1082                       # Number of stores executed
-system.cpu.iew.exec_stores::1                    1066                       # Number of stores executed
-system.cpu.iew.exec_stores::total                2148                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.726262                       # Inst execution rate
-system.cpu.iew.wb_sent::0                        9814                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_sent::1                        9693                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_sent::total                   19507                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count::0                       9690                       # cumulative count of insts written-back
-system.cpu.iew.wb_count::1                       9546                       # cumulative count of insts written-back
-system.cpu.iew.wb_count::total                  19236                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers::0                   5036                       # num instructions producing a value
-system.cpu.iew.wb_producers::1                   4985                       # num instructions producing a value
-system.cpu.iew.wb_producers::total              10021                       # num instructions producing a value
-system.cpu.iew.wb_consumers::0                   6558                       # num instructions consuming a value
-system.cpu.iew.wb_consumers::1                   6494                       # num instructions consuming a value
-system.cpu.iew.wb_consumers::total              13052                       # num instructions consuming a value
+system.cpu.iew.exec_nop::0                         70                       # number of nop insts executed
+system.cpu.iew.exec_nop::1                         73                       # number of nop insts executed
+system.cpu.iew.exec_nop::total                    143                       # number of nop insts executed
+system.cpu.iew.exec_refs::0                      3144                       # number of memory reference insts executed
+system.cpu.iew.exec_refs::1                      3199                       # number of memory reference insts executed
+system.cpu.iew.exec_refs::total                  6343                       # number of memory reference insts executed
+system.cpu.iew.exec_branches::0                  1633                       # Number of branches executed
+system.cpu.iew.exec_branches::1                  1644                       # Number of branches executed
+system.cpu.iew.exec_branches::total              3277                       # Number of branches executed
+system.cpu.iew.exec_stores::0                    1091                       # Number of stores executed
+system.cpu.iew.exec_stores::1                    1078                       # Number of stores executed
+system.cpu.iew.exec_stores::total                2169                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.661647                       # Inst execution rate
+system.cpu.iew.wb_sent::0                        9696                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_sent::1                        9663                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_sent::total                   19359                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count::0                       9565                       # cumulative count of insts written-back
+system.cpu.iew.wb_count::1                       9506                       # cumulative count of insts written-back
+system.cpu.iew.wb_count::total                  19071                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers::0                   4909                       # num instructions producing a value
+system.cpu.iew.wb_producers::1                   4894                       # num instructions producing a value
+system.cpu.iew.wb_producers::total               9803                       # num instructions producing a value
+system.cpu.iew.wb_consumers::0                   6387                       # num instructions consuming a value
+system.cpu.iew.wb_consumers::1                   6353                       # num instructions consuming a value
+system.cpu.iew.wb_consumers::total              12740                       # num instructions consuming a value
 system.cpu.iew.wb_penalized::0                      0                       # number of instrctions required to write to 'other' IQ
 system.cpu.iew.wb_penalized::1                      0                       # number of instrctions required to write to 'other' IQ
 system.cpu.iew.wb_penalized::total                  0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate::0                    0.351049                       # insts written-back per cycle
-system.cpu.iew.wb_rate::1                    0.345832                       # insts written-back per cycle
-system.cpu.iew.wb_rate::total                0.696881                       # insts written-back per cycle
-system.cpu.iew.wb_fanout::0                  0.767917                       # average fanout of values written-back
-system.cpu.iew.wb_fanout::1                  0.767632                       # average fanout of values written-back
-system.cpu.iew.wb_fanout::total              0.767775                       # average fanout of values written-back
+system.cpu.iew.wb_rate::0                    0.317943                       # insts written-back per cycle
+system.cpu.iew.wb_rate::1                    0.315982                       # insts written-back per cycle
+system.cpu.iew.wb_rate::total                0.633925                       # insts written-back per cycle
+system.cpu.iew.wb_fanout::0                  0.768592                       # average fanout of values written-back
+system.cpu.iew.wb_fanout::1                  0.770345                       # average fanout of values written-back
+system.cpu.iew.wb_fanout::total              0.769466                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate::0                 0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.iew.wb_penalized_rate::1                 0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.iew.wb_penalized_rate::total             0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts          12807                       # The number of committed instructions
 system.cpu.commit.commitCommittedOps            12807                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts           12581                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts           12383                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              34                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts              1295                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        21524                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.595010                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.388263                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts              1285                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples        24193                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.529368                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.313270                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0        15949     74.10%     74.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1         2814     13.07%     87.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2         1173      5.45%     92.62% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          493      2.29%     94.91% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          336      1.56%     96.47% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5          260      1.21%     97.68% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6          183      0.85%     98.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7          102      0.47%     99.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8          214      0.99%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0        18560     76.72%     76.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         2866     11.85%     88.56% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2         1184      4.89%     93.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          489      2.02%     95.48% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          363      1.50%     96.98% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          239      0.99%     97.97% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6          192      0.79%     98.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           93      0.38%     99.14% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8          207      0.86%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        21524                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        24193                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts::0              6403                       # Number of instructions committed
 system.cpu.commit.committedInsts::1              6404                       # Number of instructions committed
 system.cpu.commit.committedInsts::total         12807                       # Number of instructions committed
@@ -445,27 +446,27 @@ system.cpu.commit.int_insts::total              12642                       # Nu
 system.cpu.commit.function_calls::0               127                       # Number of function calls committed.
 system.cpu.commit.function_calls::1               127                       # Number of function calls committed.
 system.cpu.commit.function_calls::total           254                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events                   214                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events                   207                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited::0                     0                       # number of insts not committed due to BW limits
 system.cpu.commit.bw_limited::1                     0                       # number of insts not committed due to BW limits
 system.cpu.commit.bw_limited::total                 0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                       111695                       # The number of ROB reads
-system.cpu.rob.rob_writes                       53212                       # The number of ROB writes
-system.cpu.timesIdled                             218                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                            6021                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                       116646                       # The number of ROB reads
+system.cpu.rob.rob_writes                       52783                       # The number of ROB writes
+system.cpu.timesIdled                             298                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                            5825                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts::0                     6386                       # Number of Instructions Simulated
 system.cpu.committedInsts::1                     6387                       # Number of Instructions Simulated
 system.cpu.committedOps::0                       6386                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedOps::1                       6387                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total                 12773                       # Number of Instructions Simulated
-system.cpu.cpi::0                            4.322424                       # CPI: Cycles Per Instruction
-system.cpu.cpi::1                            4.321747                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         2.161043                       # CPI: Total CPI of All Threads
-system.cpu.ipc::0                            0.231352                       # IPC: Instructions Per Cycle
-system.cpu.ipc::1                            0.231388                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.462740                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    25345                       # number of integer regfile reads
-system.cpu.int_regfile_writes                   14554                       # number of integer regfile writes
+system.cpu.cpi::0                            4.710930                       # CPI: Cycles Per Instruction
+system.cpu.cpi::1                            4.710193                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         2.355281                       # CPI: Total CPI of All Threads
+system.cpu.ipc::0                            0.212272                       # IPC: Instructions Per Cycle
+system.cpu.ipc::1                            0.212306                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.424578                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                    25165                       # number of integer regfile reads
+system.cpu.int_regfile_writes                   14392                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                        4                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                       2                       # number of misc regfile reads
@@ -473,50 +474,50 @@ system.cpu.misc_regfile_writes                      2                       # nu
 system.cpu.icache.replacements::0                   6                       # number of replacements
 system.cpu.icache.replacements::1                   0                       # number of replacements
 system.cpu.icache.replacements::total               6                       # number of replacements
-system.cpu.icache.tagsinuse                321.631643                       # Cycle average of tags in use
-system.cpu.icache.total_refs                     4144                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                    627                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                   6.609250                       # Average number of references to valid blocks.
+system.cpu.icache.tagsinuse                315.592215                       # Cycle average of tags in use
+system.cpu.icache.total_refs                     4122                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    626                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                   6.584665                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     321.631643                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.157047                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.157047                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst         4144                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            4144                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          4144                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             4144                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         4144                       # number of overall hits
-system.cpu.icache.overall_hits::total            4144                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          889                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           889                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          889                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            889                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          889                       # number of overall misses
-system.cpu.icache.overall_misses::total           889                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     31471500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     31471500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     31471500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     31471500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     31471500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     31471500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         5033                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         5033                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         5033                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         5033                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         5033                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         5033                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.176634                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.176634                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.176634                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.176634                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.176634                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.176634                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35401.012373                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 35401.012373                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 35401.012373                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 35401.012373                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 35401.012373                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 35401.012373                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     315.592215                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.154098                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.154098                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst         4122                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            4122                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          4122                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             4122                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         4122                       # number of overall hits
+system.cpu.icache.overall_hits::total            4122                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          876                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           876                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          876                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            876                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          876                       # number of overall misses
+system.cpu.icache.overall_misses::total           876                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     34427000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     34427000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     34427000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     34427000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     34427000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     34427000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         4998                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         4998                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         4998                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         4998                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         4998                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         4998                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.175270                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.175270                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.175270                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.175270                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.175270                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.175270                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39300.228311                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 39300.228311                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 39300.228311                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 39300.228311                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 39300.228311                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 39300.228311                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -525,96 +526,96 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          262                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          262                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          262                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          262                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          262                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          262                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          627                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          627                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          627                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          627                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          627                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          627                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     22341500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     22341500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     22341500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     22341500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     22341500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     22341500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.124578                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.124578                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.124578                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.124578                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.124578                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.124578                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35632.376396                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35632.376396                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35632.376396                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 35632.376396                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35632.376396                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 35632.376396                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          250                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          250                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          250                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          250                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          250                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          250                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          626                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          626                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          626                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          626                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          626                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          626                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     25017500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     25017500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     25017500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     25017500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     25017500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     25017500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.125250                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.125250                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.125250                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.125250                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.125250                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.125250                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39964.057508                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39964.057508                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39964.057508                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 39964.057508                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39964.057508                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 39964.057508                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements::0                   0                       # number of replacements
 system.cpu.dcache.replacements::1                   0                       # number of replacements
 system.cpu.dcache.replacements::total               0                       # number of replacements
-system.cpu.dcache.tagsinuse                221.639601                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                     4700                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                    355                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  13.239437                       # Average number of references to valid blocks.
+system.cpu.dcache.tagsinuse                216.324578                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                     4646                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                    350                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  13.274286                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data     221.639601                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.054111                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.054111                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data         3679                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            3679                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data         1021                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total           1021                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          4700                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             4700                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         4700                       # number of overall hits
-system.cpu.dcache.overall_hits::total            4700                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          312                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           312                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data          709                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total          709                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data         1021                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           1021                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         1021                       # number of overall misses
-system.cpu.dcache.overall_misses::total          1021                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     11353000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     11353000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     22399000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     22399000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     33752000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     33752000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     33752000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     33752000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         3991                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         3991                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.occ_blocks::cpu.data     216.324578                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.052814                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.052814                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data         3634                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            3634                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data         1012                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total           1012                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data          4646                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             4646                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         4646                       # number of overall hits
+system.cpu.dcache.overall_hits::total            4646                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          315                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           315                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data          718                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total          718                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data         1033                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           1033                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         1033                       # number of overall misses
+system.cpu.dcache.overall_misses::total          1033                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     14081500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     14081500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     28681000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     28681000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     42762500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     42762500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     42762500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     42762500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         3949                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         3949                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data         1730                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total         1730                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         5721                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         5721                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         5721                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         5721                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.078176                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.078176                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.409827                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.409827                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.178465                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.178465                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.178465                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.178465                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36387.820513                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 36387.820513                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31592.383639                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 31592.383639                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 33057.786484                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 33057.786484                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 33057.786484                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 33057.786484                       # average overall miss latency
+system.cpu.dcache.demand_accesses::cpu.data         5679                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         5679                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         5679                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         5679                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.079767                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.079767                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.415029                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.415029                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.181898                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.181898                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.181898                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.181898                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 44703.174603                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 44703.174603                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39945.682451                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 39945.682451                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 41396.418199                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 41396.418199                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 41396.418199                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 41396.418199                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -623,173 +624,173 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          102                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          102                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data          564                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total          564                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          666                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          666                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          666                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          666                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data          210                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          210                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data          145                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total          145                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data          355                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total          355                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data          355                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total          355                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      7724000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      7724000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      5248500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      5248500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     12972500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     12972500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     12972500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     12972500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.052618                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.052618                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.083815                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.083815                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.062052                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.062052                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.062052                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.062052                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36780.952381                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 36780.952381                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36196.551724                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36196.551724                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36542.253521                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 36542.253521                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36542.253521                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 36542.253521                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          111                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          111                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data          572                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total          572                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          683                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          683                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          683                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          683                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          204                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          204                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data          146                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total          146                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data          350                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total          350                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data          350                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total          350                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      9596500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      9596500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      6268000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      6268000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     15864500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     15864500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     15864500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     15864500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.051659                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.051659                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.084393                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.084393                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.061631                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.061631                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.061631                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.061631                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47041.666667                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47041.666667                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42931.506849                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42931.506849                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45327.142857                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 45327.142857                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45327.142857                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 45327.142857                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements::0                  0                       # number of replacements
 system.cpu.l2cache.replacements::1                  0                       # number of replacements
 system.cpu.l2cache.replacements::total              0                       # number of replacements
-system.cpu.l2cache.tagsinuse               447.061292                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               437.003550                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       2                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                   835                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  0.002395                       # Average number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                   828                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.002415                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst    321.947671                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data    125.113621                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst     0.009825                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.003818                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.013643                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst    315.880086                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    121.123464                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.009640                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.003696                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.013336                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              2                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::total               2                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst            2                       # number of overall hits
 system.cpu.l2cache.overall_hits::total              2                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          625                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data          210                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total          835                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data          145                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total          145                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          625                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data          355                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total           980                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          625                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data          355                       # number of overall misses
-system.cpu.l2cache.overall_misses::total          980                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     21523000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      7330000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     28853000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      5026500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      5026500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     21523000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     12356500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     33879500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     21523000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     12356500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     33879500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          627                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data          210                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total          837                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data          145                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total          145                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          627                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data          355                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total          982                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          627                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data          355                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total          982                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.996810                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses::cpu.inst          624                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data          204                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total          828                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data          146                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total          146                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          624                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data          350                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total           974                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          624                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data          350                       # number of overall misses
+system.cpu.l2cache.overall_misses::total          974                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     24336000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      9337500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     33673500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      6106000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      6106000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     24336000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     15443500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     39779500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     24336000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     15443500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     39779500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          626                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data          204                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total          830                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data          146                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total          146                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          626                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data          350                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total          976                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          626                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data          350                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total          976                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.996805                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.997611                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.997590                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.996810                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.996805                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.997963                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996810                       # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::total     0.997951                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996805                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.997963                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34436.800000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34904.761905                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 34554.491018                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34665.517241                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34665.517241                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34436.800000                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34807.042254                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 34570.918367                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34436.800000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34807.042254                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 34570.918367                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs        21000                       # number of cycles access was blocked
+system.cpu.l2cache.overall_miss_rate::total     0.997951                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        39000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 45772.058824                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 40668.478261                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 41821.917808                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 41821.917808                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        39000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 44124.285714                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 40841.375770                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        39000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 44124.285714                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 40841.375770                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs        37500                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs                4                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                9                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs         5250                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs  4166.666667                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          625                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          210                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total          835                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          145                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total          145                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          625                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data          355                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total          980                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          625                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data          355                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total          980                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     19555500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      6675000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     26230500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      4577500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      4577500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     19555500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     11252500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     30808000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     19555500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     11252500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     30808000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.996810                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          624                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          204                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total          828                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          146                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total          146                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          624                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data          350                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total          974                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          624                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data          350                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total          974                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     22375000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      8716000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     31091000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      5649500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      5649500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     22375000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     14365500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     36740500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     22375000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     14365500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     36740500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.996805                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.997611                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.997590                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.996810                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.996805                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.997963                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996810                       # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.997951                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996805                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.997963                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31288.800000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31785.714286                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31413.772455                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31568.965517                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31568.965517                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31288.800000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31697.183099                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31436.734694                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31288.800000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31697.183099                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31436.734694                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.997951                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35857.371795                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42725.490196                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37549.516908                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38695.205479                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38695.205479                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35857.371795                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41044.285714                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 37721.252567                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35857.371795                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41044.285714                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37721.252567                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini
index b15f5671c..09d24317c 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini
@@ -181,7 +181,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
@@ -213,7 +213,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout
index 30eeb514f..6fbf990e1 100755
--- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun  4 2012 12:01:47
-gem5 started Jun  4 2012 14:44:53
+gem5 compiled Jul  2 2012 08:54:18
+gem5 started Jul  2 2012 11:30:48
 gem5 executing on zizzer
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/inorder-timing
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Begining test of difficult SPARC instructions...
@@ -18,4 +18,4 @@ LDTX:		Passed
 LDTW:		Passed
 STTW:		Passed
 Done
-Exiting @ tick 25007500 because target called exit()
+Exiting @ tick 25615500 because target called exit()
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt
index 73324a4d5..c2589ee2d 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000025                       # Number of seconds simulated
-sim_ticks                                    25007500                       # Number of ticks simulated
-final_tick                                   25007500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000026                       # Number of seconds simulated
+sim_ticks                                    25615500                       # Number of ticks simulated
+final_tick                                   25615500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  72389                       # Simulator instruction rate (inst/s)
-host_op_rate                                    72383                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              119272701                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 221376                       # Number of bytes of host memory used
-host_seconds                                     0.21                       # Real time elapsed on the host
+host_inst_rate                                  51797                       # Simulator instruction rate (inst/s)
+host_op_rate                                    51795                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               87424707                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 219936                       # Number of bytes of host memory used
+host_seconds                                     0.29                       # Real time elapsed on the host
 sim_insts                                       15175                       # Number of instructions simulated
 sim_ops                                         15175                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             19072                       # Number of bytes read from this memory
@@ -19,36 +19,36 @@ system.physmem.bytes_inst_read::total           19072                       # Nu
 system.physmem.num_reads::cpu.inst                298                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                138                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   436                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            762651205                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            353174048                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1115825252                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       762651205                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          762651205                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           762651205                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           353174048                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1115825252                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            744549199                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            344791240                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1089340438                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       744549199                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          744549199                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           744549199                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           344791240                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1089340438                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   18                       # Number of system calls
-system.cpu.numCycles                            50016                       # number of cpu cycles simulated
+system.cpu.numCycles                            51232                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.branch_predictor.lookups              5015                       # Number of BP lookups
+system.cpu.branch_predictor.lookups              5014                       # Number of BP lookups
 system.cpu.branch_predictor.condPredicted         3353                       # Number of conditional branches predicted
 system.cpu.branch_predictor.condIncorrect         2379                       # Number of conditional branches incorrect
-system.cpu.branch_predictor.BTBLookups           3332                       # Number of BTB lookups
+system.cpu.branch_predictor.BTBLookups           3331                       # Number of BTB lookups
 system.cpu.branch_predictor.BTBHits              2040                       # Number of BTB hits
 system.cpu.branch_predictor.usedRAS               174                       # Number of times the RAS was used to get a target.
 system.cpu.branch_predictor.RASInCorrect            5                       # Number of incorrect RAS predictions.
-system.cpu.branch_predictor.BTBHitPct       61.224490                       # BTB Hit Percentage
+system.cpu.branch_predictor.BTBHitPct       61.242870                       # BTB Hit Percentage
 system.cpu.branch_predictor.predictedTaken         2214                       # Number of Branches Predicted As Taken (True).
-system.cpu.branch_predictor.predictedNotTaken         2801                       # Number of Branches Predicted As Not Taken (False).
+system.cpu.branch_predictor.predictedNotTaken         2800                       # Number of Branches Predicted As Not Taken (False).
 system.cpu.regfile_manager.intRegFileReads        14401                       # Number of Reads from Int. Register File
 system.cpu.regfile_manager.intRegFileWrites        11111                       # Number of Writes to Int. Register File
 system.cpu.regfile_manager.intRegFileAccesses        25512                       # Total Accesses (Read+Write) to the Int. Register File
 system.cpu.regfile_manager.floatRegFileReads            0                       # Number of Reads from FP Register File
 system.cpu.regfile_manager.floatRegFileWrites            0                       # Number of Writes to FP Register File
 system.cpu.regfile_manager.floatRegFileAccesses            0                       # Total Accesses (Read+Write) to the FP Register File
-system.cpu.regfile_manager.regForwards           4993                       # Number of Registers Read Through Forwarding Logic
-system.cpu.agen_unit.agens                       3952                       # Number of Address Generations
+system.cpu.regfile_manager.regForwards           4991                       # Number of Registers Read Through Forwarding Logic
+system.cpu.agen_unit.agens                       3950                       # Number of Address Generations
 system.cpu.execution_unit.predictedTakenIncorrect         1316                       # Number of Branches Incorrectly Predicted As Taken.
 system.cpu.execution_unit.predictedNotTakenIncorrect         1000                       # Number of Branches Incorrectly Predicted As Not Taken).
 system.cpu.execution_unit.mispredicted           2316                       # Number of Branches Incorrectly Predicted
@@ -58,12 +58,12 @@ system.cpu.execution_unit.executions            11084                       # Nu
 system.cpu.mult_div_unit.multiplies                 0                       # Number of Multipy Operations Executed
 system.cpu.mult_div_unit.divides                    0                       # Number of Divide Operations Executed
 system.cpu.contextSwitches                          1                       # Number of context switches
-system.cpu.threadCycles                         21887                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles                         22262                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
 system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled                             453                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           32683                       # Number of cycles cpu's stages were not processed
-system.cpu.runCycles                            17333                       # Number of cycles cpu stages are processed.
-system.cpu.activity                         34.654910                       # Percentage of cycles cpu is active
+system.cpu.timesIdled                             525                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           33883                       # Number of cycles cpu's stages were not processed
+system.cpu.runCycles                            17349                       # Number of cycles cpu stages are processed.
+system.cpu.activity                         33.863601                       # Percentage of cycles cpu is active
 system.cpu.comLoads                              2226                       # Number of Load instructions committed
 system.cpu.comStores                             1448                       # Number of Store instructions committed
 system.cpu.comBranches                           3359                       # Number of Branches instructions committed
@@ -75,72 +75,72 @@ system.cpu.committedInsts                       15175                       # Nu
 system.cpu.committedOps                         15175                       # Number of Ops committed (Per-Thread)
 system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
 system.cpu.committedInsts_total                 15175                       # Number of Instructions committed (Total)
-system.cpu.cpi                               3.295947                       # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi                               3.376079                       # CPI: Cycles Per Instruction (Per-Thread)
 system.cpu.smt_cpi                                nan                       # CPI: Total SMT-CPI
-system.cpu.cpi_total                         3.295947                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.303403                       # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.cpi_total                         3.376079                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.296202                       # IPC: Instructions Per Cycle (Per-Thread)
 system.cpu.smt_ipc                                nan                       # IPC: Total SMT-IPC
-system.cpu.ipc_total                         0.303403                       # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles                    36923                       # Number of cycles 0 instructions are processed.
+system.cpu.ipc_total                         0.296202                       # IPC: Total IPC of All Threads
+system.cpu.stage0.idleCycles                    38139                       # Number of cycles 0 instructions are processed.
 system.cpu.stage0.runCycles                     13093                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization               26.177623                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles                    40814                       # Number of cycles 0 instructions are processed.
-system.cpu.stage1.runCycles                      9202                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization               18.398113                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles                    41191                       # Number of cycles 0 instructions are processed.
-system.cpu.stage2.runCycles                      8825                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization               17.644354                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles                    47132                       # Number of cycles 0 instructions are processed.
-system.cpu.stage3.runCycles                      2884                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization                5.766155                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles                    40690                       # Number of cycles 0 instructions are processed.
-system.cpu.stage4.runCycles                      9326                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization               18.646033                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage0.utilization               25.556293                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles                    42033                       # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles                      9199                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization               17.955575                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles                    42406                       # Number of cycles 0 instructions are processed.
+system.cpu.stage2.runCycles                      8826                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage2.utilization               17.227514                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles                    48347                       # Number of cycles 0 instructions are processed.
+system.cpu.stage3.runCycles                      2885                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage3.utilization                5.631246                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles                    41905                       # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles                      9327                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization               18.205418                       # Percentage of cycles stage was utilized (processing insts).
 system.cpu.icache.replacements                      0                       # number of replacements
-system.cpu.icache.tagsinuse                165.557258                       # Cycle average of tags in use
-system.cpu.icache.total_refs                     2602                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                164.555255                       # Cycle average of tags in use
+system.cpu.icache.total_refs                     2600                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    299                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                   8.702341                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs                   8.695652                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     165.557258                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.080839                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.080839                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst         2602                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            2602                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          2602                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             2602                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         2602                       # number of overall hits
-system.cpu.icache.overall_hits::total            2602                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          368                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           368                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          368                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            368                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          368                       # number of overall misses
-system.cpu.icache.overall_misses::total           368                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     20203500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     20203500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     20203500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     20203500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     20203500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     20203500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         2970                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         2970                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         2970                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         2970                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         2970                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         2970                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.123906                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.123906                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.123906                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.123906                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.123906                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.123906                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54900.815217                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 54900.815217                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 54900.815217                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 54900.815217                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 54900.815217                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 54900.815217                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     164.555255                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.080349                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.080349                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst         2600                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            2600                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          2600                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             2600                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         2600                       # number of overall hits
+system.cpu.icache.overall_hits::total            2600                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          371                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           371                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          371                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            371                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          371                       # number of overall misses
+system.cpu.icache.overall_misses::total           371                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     20687000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     20687000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     20687000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     20687000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     20687000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     20687000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         2971                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         2971                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         2971                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         2971                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         2971                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         2971                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.124874                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.124874                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.124874                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.124874                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.124874                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.124874                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55760.107817                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 55760.107817                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 55760.107817                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 55760.107817                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 55760.107817                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 55760.107817                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets        65500                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -149,72 +149,72 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets        32750                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst           67                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total           67                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst           67                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total           67                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst           67                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total           67                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst           70                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total           70                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst           70                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total           70                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst           70                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total           70                       # number of overall MSHR hits
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          301                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total          301                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst          301                       # number of demand (read+write) MSHR misses
 system.cpu.icache.demand_mshr_misses::total          301                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          301                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          301                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     15872000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     15872000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     15872000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     15872000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     15872000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     15872000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.101347                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.101347                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.101347                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.101347                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.101347                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.101347                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52730.897010                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52730.897010                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52730.897010                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 52730.897010                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52730.897010                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 52730.897010                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     16327000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     16327000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     16327000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     16327000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     16327000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     16327000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.101313                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.101313                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.101313                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.101313                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.101313                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.101313                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54242.524917                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54242.524917                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54242.524917                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 54242.524917                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54242.524917                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 54242.524917                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.tagsinuse                 97.041769                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                     3316                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse                 96.551113                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                     3315                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                    138                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  24.028986                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                  24.021739                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data      97.041769                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.023692                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.023692                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::cpu.data      96.551113                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.023572                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.023572                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data         2168                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total            2168                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data         1142                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total           1142                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data         1141                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total           1141                       # number of WriteReq hits
 system.cpu.dcache.SwapReq_hits::cpu.data            6                       # number of SwapReq hits
 system.cpu.dcache.SwapReq_hits::total               6                       # number of SwapReq hits
-system.cpu.dcache.demand_hits::cpu.data          3310                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             3310                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         3310                       # number of overall hits
-system.cpu.dcache.overall_hits::total            3310                       # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data          3309                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             3309                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         3309                       # number of overall hits
+system.cpu.dcache.overall_hits::total            3309                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data           58                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total            58                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data          300                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total          300                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          358                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            358                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          358                       # number of overall misses
-system.cpu.dcache.overall_misses::total           358                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      3281500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      3281500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     16397000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     16397000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     19678500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     19678500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     19678500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     19678500                       # number of overall miss cycles
+system.cpu.dcache.WriteReq_misses::cpu.data          301                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total          301                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data          359                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            359                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          359                       # number of overall misses
+system.cpu.dcache.overall_misses::total           359                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      3488000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      3488000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     18458000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     18458000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     21946000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     21946000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     21946000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     21946000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data         2226                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total         2226                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data         1442                       # number of WriteReq accesses(hits+misses)
@@ -227,36 +227,36 @@ system.cpu.dcache.overall_accesses::cpu.data         3668
 system.cpu.dcache.overall_accesses::total         3668                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.026056                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.026056                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.208044                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.208044                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.097601                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.097601                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.097601                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.097601                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56577.586207                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 56577.586207                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54656.666667                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 54656.666667                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 54967.877095                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 54967.877095                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 54967.877095                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 54967.877095                       # average overall miss latency
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.208738                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.208738                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.097874                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.097874                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.097874                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.097874                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60137.931034                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 60137.931034                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61322.259136                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 61322.259136                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 61130.919220                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 61130.919220                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 61130.919220                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 61130.919220                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets      2208000                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets      2258500                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets              44                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets              45                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 50181.818182                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 50188.888889                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data            5                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total            5                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data          215                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total          215                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          220                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          220                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          220                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          220                       # number of overall MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data          216                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total          216                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          221                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          221                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          221                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          221                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data           53                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total           53                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data           85                       # number of WriteReq MSHR misses
@@ -265,14 +265,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          138
 system.cpu.dcache.demand_mshr_misses::total          138                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          138                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          138                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      2837000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      2837000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      4545000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      4545000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      7382000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      7382000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7382000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      7382000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      2987500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      2987500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      4730000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      4730000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      7717500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      7717500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7717500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      7717500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.023810                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.023810                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.058946                       # mshr miss rate for WriteReq accesses
@@ -281,26 +281,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.037623
 system.cpu.dcache.demand_mshr_miss_rate::total     0.037623                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.037623                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.037623                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53528.301887                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53528.301887                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53470.588235                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53470.588235                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53492.753623                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 53492.753623                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53492.753623                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 53492.753623                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 56367.924528                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 56367.924528                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 55647.058824                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 55647.058824                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 55923.913043                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 55923.913043                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 55923.913043                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 55923.913043                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse               196.205624                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               195.062761                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       2                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                   350                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.005714                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst    164.948941                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data     31.256684                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst     0.005034                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.000954                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.005988                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst    163.946873                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     31.115888                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.005003                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.000950                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.005953                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              2                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
@@ -318,17 +318,17 @@ system.cpu.l2cache.demand_misses::total           437                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          299                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          138                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          437                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     15533000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      2776500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     18309500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      4442500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      4442500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     15533000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data      7219000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     22752000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     15533000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data      7219000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     22752000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     15990000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      2926500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     18916500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      4635000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      4635000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     15990000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      7561500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     23551500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     15990000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      7561500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     23551500                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst          301                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data           53                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total          354                       # number of ReadReq accesses(hits+misses)
@@ -351,17 +351,17 @@ system.cpu.l2cache.demand_miss_rate::total     0.995444                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.993355                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.995444                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51949.832776                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52386.792453                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 52015.625000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52264.705882                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52264.705882                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51949.832776                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52311.594203                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52064.073227                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51949.832776                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52311.594203                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52064.073227                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53478.260870                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55216.981132                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 53740.056818                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54529.411765                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54529.411765                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53478.260870                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54793.478261                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 53893.592677                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53478.260870                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54793.478261                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 53893.592677                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -381,17 +381,17 @@ system.cpu.l2cache.demand_mshr_misses::total          437
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          299                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          138                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          437                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     11916000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      2132500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     14048500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3416000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      3416000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     11916000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5548500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     17464500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     11916000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5548500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     17464500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     12379500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      2285000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     14664500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3604000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      3604000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     12379500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5889000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     18268500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     12379500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5889000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     18268500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.993355                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.994350                       # mshr miss rate for ReadReq accesses
@@ -403,17 +403,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.995444
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.993355                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.995444                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39852.842809                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40235.849057                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39910.511364                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40188.235294                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40188.235294                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39852.842809                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40206.521739                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39964.530892                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39852.842809                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40206.521739                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39964.530892                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41403.010033                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43113.207547                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41660.511364                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        42400                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        42400                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41403.010033                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42673.913043                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41804.347826                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41403.010033                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42673.913043                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41804.347826                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini
index e306accf8..f6619bb03 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini
@@ -479,7 +479,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
@@ -511,7 +511,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout
index c81e9ca95..47b15000f 100755
--- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:06:58
-gem5 started Jun 28 2012 22:53:48
+gem5 compiled Jul  2 2012 08:54:18
+gem5 started Jul  2 2012 11:30:59
 gem5 executing on zizzer
 command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
@@ -18,4 +18,4 @@ LDTX:		Passed
 LDTW:		Passed
 STTW:		Passed
 Done
-Exiting @ tick 19806500 because target called exit()
+Exiting @ tick 20274500 because target called exit()
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
index 52156950f..49a67051b 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
@@ -1,269 +1,269 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000020                       # Number of seconds simulated
-sim_ticks                                    19806500                       # Number of ticks simulated
-final_tick                                   19806500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    20274500                       # Number of ticks simulated
+final_tick                                   20274500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  96556                       # Simulator instruction rate (inst/s)
-host_op_rate                                    96545                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              132327745                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 221008                       # Number of bytes of host memory used
-host_seconds                                     0.15                       # Real time elapsed on the host
+host_inst_rate                                  55162                       # Simulator instruction rate (inst/s)
+host_op_rate                                    55159                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               77392529                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 220968                       # Number of bytes of host memory used
+host_seconds                                     0.26                       # Real time elapsed on the host
 sim_insts                                       14449                       # Number of instructions simulated
 sim_ops                                         14449                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst             21632                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst             21568                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data              9344                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                30976                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        21632                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           21632                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                338                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total                30912                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        21568                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           21568                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                337                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                146                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                   484                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst           1092166713                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            471764320                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1563931033                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      1092166713                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         1092166713                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          1092166713                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           471764320                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1563931033                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_reads::total                   483                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst           1063799354                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            460874498                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1524673851                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      1063799354                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         1063799354                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          1063799354                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           460874498                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1524673851                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   18                       # Number of system calls
-system.cpu.numCycles                            39614                       # number of cpu cycles simulated
+system.cpu.numCycles                            40550                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                     6890                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted               4576                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect               1121                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups                  5201                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                     2595                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                     6892                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted               4586                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect               1120                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups                  5125                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                     2600                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                      459                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.usedRAS                      458                       # Number of times the RAS was used to get a target.
 system.cpu.BPredUnit.RASInCorrect                 168                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles              11869                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          32300                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        6890                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches               3054                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          9560                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                    3188                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles                   6935                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.icacheStallCycles              12259                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          32259                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        6892                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches               3058                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                          9557                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                    3181                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles                   7365                       # Number of cycles fetch has spent blocked
 system.cpu.fetch.MiscStallCycles                    4                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles           726                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                      5516                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   469                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              31065                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.039755                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.210803                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.PendingTrapStallCycles           767                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                      5500                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   472                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples              31917                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.010715                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.185460                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                    21505     69.23%     69.23% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                     4746     15.28%     84.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      494      1.59%     86.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      444      1.43%     87.52% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      682      2.20%     89.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      763      2.46%     92.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      240      0.77%     92.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      277      0.89%     93.84% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     1914      6.16%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                    22360     70.06%     70.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                     4750     14.88%     84.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      493      1.54%     86.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      436      1.37%     87.85% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      686      2.15%     90.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      773      2.42%     92.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      235      0.74%     93.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      276      0.86%     94.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                     1908      5.98%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                31065                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.173928                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.815368                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                    12513                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                  7669                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      8722                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                   190                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                   1971                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts                  30088                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles                   1971                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                    13189                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                     248                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           6922                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      8283                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                   452                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  27408                       # Number of instructions processed by rename
-system.cpu.rename.IQFullEvents                      5                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents                   125                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands               24445                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 50953                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            50953                       # Number of integer rename lookups
+system.cpu.fetch.rateDist::total                31917                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.169963                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.795536                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                    12903                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                  8133                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      8719                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                   197                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                   1965                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts                  30080                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles                   1965                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                    13582                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                     285                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           7298                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                      8277                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                   510                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                  27385                       # Number of instructions processed by rename
+system.cpu.rename.IQFullEvents                     11                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents                   172                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands               24421                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 50913                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            50913                       # Number of integer rename lookups
 system.cpu.rename.CommittedMaps                 13832                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                    10613                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                705                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            708                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                      2841                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 3647                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                2469                       # Number of stores inserted to the mem dependence unit.
+system.cpu.rename.UndoneMaps                    10589                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                704                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            706                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                      2903                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                 3640                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                2472                       # Number of stores inserted to the mem dependence unit.
 system.cpu.memDep0.conflictingLoads                 4                       # Number of conflicting loads.
 system.cpu.memDep0.conflictingStores                0                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                      23180                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                 670                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                     21761                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued               105                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined            8457                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined         5919                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            195                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         31065                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.700499                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.316624                       # Number of insts issued each cycle
+system.cpu.iq.iqInstsAdded                      23148                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                 669                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                     21730                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued               108                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined            8364                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined         5915                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            194                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples         31917                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.680828                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.297413                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0               21619     69.59%     69.59% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                3603     11.60%     81.19% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                2384      7.67%     88.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                1730      5.57%     94.43% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 898      2.89%     97.32% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 488      1.57%     98.90% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 252      0.81%     99.71% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                  72      0.23%     99.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8                  19      0.06%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0               22417     70.24%     70.24% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                3682     11.54%     81.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                2373      7.43%     89.21% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                1722      5.40%     94.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 904      2.83%     97.43% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 493      1.54%     98.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 244      0.76%     99.74% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                  65      0.20%     99.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                  17      0.05%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           31065                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           31917                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                      54     29.19%     29.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     29.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     29.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     29.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     29.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     29.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     29.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     29.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     29.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     29.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     29.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     29.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     29.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     29.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     29.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     29.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     29.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     29.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     29.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     29.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     29.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     29.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     29.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     29.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     29.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     29.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     29.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     29.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     29.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                     26     14.05%     43.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                   105     56.76%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                      46     26.59%     26.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     26.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     26.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     26.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     26.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     26.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     26.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     26.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     26.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     26.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     26.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     26.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     26.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     26.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     26.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     26.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     26.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     26.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     26.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     26.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     26.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     26.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     26.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     26.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     26.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     26.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     26.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     26.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     26.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                     24     13.87%     40.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                   103     59.54%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                 16056     73.78%     73.78% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    0      0.00%     73.78% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     73.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     73.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     73.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     73.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     73.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     73.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     73.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     73.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     73.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     73.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     73.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     73.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     73.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     73.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     73.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     73.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     73.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     73.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     73.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     73.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     73.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     73.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     73.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     73.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     73.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     73.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     73.78% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 3441     15.81%     89.60% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                2264     10.40%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                 16031     73.77%     73.77% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    0      0.00%     73.77% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     73.77% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     73.77% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     73.77% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     73.77% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     73.77% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     73.77% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     73.77% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     73.77% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     73.77% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     73.77% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     73.77% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     73.77% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     73.77% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     73.77% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     73.77% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     73.77% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     73.77% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     73.77% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     73.77% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     73.77% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     73.77% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     73.77% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     73.77% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     73.77% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     73.77% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     73.77% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     73.77% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 3433     15.80%     89.57% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                2266     10.43%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                  21761                       # Type of FU issued
-system.cpu.iq.rate                           0.549326                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                         185                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.008501                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              74877                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             32333                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses        19979                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total                  21730                       # Type of FU issued
+system.cpu.iq.rate                           0.535882                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                         173                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.007961                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              75658                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             32207                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses        19957                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                   0                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                  0                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                  21946                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                  21903                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                       0                       # Number of floating point alu accesses
 system.cpu.iew.lsq.thread0.forwLoads               26                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads         1421                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads         1414                       # Number of loads squashed
 system.cpu.iew.lsq.thread0.ignoredResponses            2                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread0.memOrderViolation           27                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores         1021                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores         1024                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            1                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                   1971                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                     144                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                    11                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               25018                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts               406                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  3647                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                 2469                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                670                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                      3                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles                   1965                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                      99                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                     5                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts               24982                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts               417                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts                  3640                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                 2472                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                669                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                      2                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewLSQFullEvents                     0                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.memOrderViolationEvents             27                       # Number of memory order violations
 system.cpu.iew.predictedTakenIncorrect            291                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect          962                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                 1253                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                 20571                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                  3278                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts              1190                       # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedNotTakenIncorrect          958                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts                 1249                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                 20553                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                  3273                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts              1177                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                          1168                       # number of nop insts executed
-system.cpu.iew.exec_refs                         5421                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                     4301                       # Number of branches executed
-system.cpu.iew.exec_stores                       2143                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.519286                       # Inst execution rate
-system.cpu.iew.wb_sent                          20246                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                         19979                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                      9281                       # num instructions producing a value
-system.cpu.iew.wb_consumers                     11411                       # num instructions consuming a value
+system.cpu.iew.exec_nop                          1165                       # number of nop insts executed
+system.cpu.iew.exec_refs                         5419                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                     4294                       # Number of branches executed
+system.cpu.iew.exec_stores                       2146                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.506856                       # Inst execution rate
+system.cpu.iew.wb_sent                          20221                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                         19957                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                      9257                       # num instructions producing a value
+system.cpu.iew.wb_consumers                     11359                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.504342                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.813338                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.492158                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.814948                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts          15175                       # The number of committed instructions
 system.cpu.commit.commitCommittedOps            15175                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts            9761                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts            9725                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             475                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts              1121                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        29111                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.521281                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.203804                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts              1120                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples        29969                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.506357                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.189037                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0        21721     74.61%     74.61% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1         4069     13.98%     88.59% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2         1444      4.96%     93.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          793      2.72%     96.28% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          337      1.16%     97.43% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5          258      0.89%     98.32% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6          320      1.10%     99.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           71      0.24%     99.66% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8           98      0.34%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0        22543     75.22%     75.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         4136     13.80%     89.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2         1421      4.74%     93.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          789      2.63%     96.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          331      1.10%     97.50% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          259      0.86%     98.36% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6          318      1.06%     99.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           73      0.24%     99.67% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8           99      0.33%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        29111                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        29969                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts                15175                       # Number of instructions committed
 system.cpu.commit.committedOps                  15175                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -274,68 +274,68 @@ system.cpu.commit.branches                       3359                       # Nu
 system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                     12186                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                  187                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events                    98                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events                    99                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                        53126                       # The number of ROB reads
-system.cpu.rob.rob_writes                       51851                       # The number of ROB writes
-system.cpu.timesIdled                             186                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                            8549                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                        53947                       # The number of ROB reads
+system.cpu.rob.rob_writes                       51773                       # The number of ROB writes
+system.cpu.timesIdled                             196                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                            8633                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                       14449                       # Number of Instructions Simulated
 system.cpu.committedOps                         14449                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total                 14449                       # Number of Instructions Simulated
-system.cpu.cpi                               2.741643                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         2.741643                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.364745                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.364745                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    32757                       # number of integer regfile reads
-system.cpu.int_regfile_writes                   18209                       # number of integer regfile writes
-system.cpu.misc_regfile_reads                    7073                       # number of misc regfile reads
+system.cpu.cpi                               2.806423                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         2.806423                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.356326                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.356326                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                    32739                       # number of integer regfile reads
+system.cpu.int_regfile_writes                   18191                       # number of integer regfile writes
+system.cpu.misc_regfile_reads                    7070                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                    569                       # number of misc regfile writes
 system.cpu.icache.replacements                      0                       # number of replacements
-system.cpu.icache.tagsinuse                201.055469                       # Cycle average of tags in use
-system.cpu.icache.total_refs                     5034                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                    340                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                  14.805882                       # Average number of references to valid blocks.
+system.cpu.icache.tagsinuse                199.218311                       # Cycle average of tags in use
+system.cpu.icache.total_refs                     5020                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    339                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                  14.808260                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     201.055469                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.098172                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.098172                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst         5034                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            5034                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          5034                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             5034                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         5034                       # number of overall hits
-system.cpu.icache.overall_hits::total            5034                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          482                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           482                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          482                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            482                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          482                       # number of overall misses
-system.cpu.icache.overall_misses::total           482                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     16634500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     16634500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     16634500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     16634500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     16634500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     16634500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         5516                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         5516                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         5516                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         5516                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         5516                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         5516                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.087382                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.087382                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.087382                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.087382                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.087382                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.087382                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34511.410788                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 34511.410788                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 34511.410788                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 34511.410788                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 34511.410788                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 34511.410788                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     199.218311                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.097275                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.097275                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst         5020                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            5020                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          5020                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             5020                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         5020                       # number of overall hits
+system.cpu.icache.overall_hits::total            5020                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          480                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           480                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          480                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            480                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          480                       # number of overall misses
+system.cpu.icache.overall_misses::total           480                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     16877500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     16877500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     16877500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     16877500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     16877500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     16877500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         5500                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         5500                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         5500                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         5500                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         5500                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         5500                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.087273                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.087273                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.087273                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.087273                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.087273                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.087273                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35161.458333                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 35161.458333                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 35161.458333                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 35161.458333                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 35161.458333                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 35161.458333                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -344,98 +344,98 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          142                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          142                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          142                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          142                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          142                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          142                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          340                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          340                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          340                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          340                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          340                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          340                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     11937500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     11937500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     11937500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     11937500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     11937500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     11937500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.061639                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.061639                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.061639                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.061639                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.061639                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.061639                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35110.294118                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35110.294118                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35110.294118                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 35110.294118                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35110.294118                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 35110.294118                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          141                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          141                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          141                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          141                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          141                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          141                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          339                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          339                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          339                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          339                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          339                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          339                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     12213000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     12213000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     12213000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     12213000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     12213000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     12213000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.061636                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.061636                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.061636                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.061636                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.061636                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.061636                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36026.548673                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36026.548673                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36026.548673                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 36026.548673                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36026.548673                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 36026.548673                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.tagsinuse                103.574586                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                     4084                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse                102.764065                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                     4075                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                    146                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  27.972603                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                  27.910959                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data     103.574586                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.025287                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.025287                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data         3044                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            3044                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data         1034                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total           1034                       # number of WriteReq hits
+system.cpu.dcache.occ_blocks::cpu.data     102.764065                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.025089                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.025089                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data         3036                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            3036                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data         1033                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total           1033                       # number of WriteReq hits
 system.cpu.dcache.SwapReq_hits::cpu.data            6                       # number of SwapReq hits
 system.cpu.dcache.SwapReq_hits::total               6                       # number of SwapReq hits
-system.cpu.dcache.demand_hits::cpu.data          4078                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             4078                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         4078                       # number of overall hits
-system.cpu.dcache.overall_hits::total            4078                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          116                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           116                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data          408                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total          408                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          524                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            524                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          524                       # number of overall misses
-system.cpu.dcache.overall_misses::total           524                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      4022000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      4022000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     14592500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     14592500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     18614500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     18614500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     18614500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     18614500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         3160                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         3160                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_hits::cpu.data          4069                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             4069                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         4069                       # number of overall hits
+system.cpu.dcache.overall_hits::total            4069                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          121                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           121                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data          409                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total          409                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data          530                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            530                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          530                       # number of overall misses
+system.cpu.dcache.overall_misses::total           530                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      4649500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      4649500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     17651000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     17651000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     22300500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     22300500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     22300500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     22300500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         3157                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         3157                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data         1442                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total         1442                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SwapReq_accesses::cpu.data            6                       # number of SwapReq accesses(hits+misses)
 system.cpu.dcache.SwapReq_accesses::total            6                       # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         4602                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         4602                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         4602                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         4602                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.036709                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.036709                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.282940                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.282940                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.113864                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.113864                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.113864                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.113864                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34672.413793                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 34672.413793                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35765.931373                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 35765.931373                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 35523.854962                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 35523.854962                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 35523.854962                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 35523.854962                       # average overall miss latency
+system.cpu.dcache.demand_accesses::cpu.data         4599                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         4599                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         4599                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         4599                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.038328                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.038328                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.283634                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.283634                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.115242                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.115242                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.115242                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.115242                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38425.619835                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 38425.619835                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43156.479218                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 43156.479218                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 42076.415094                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 42076.415094                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 42076.415094                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 42076.415094                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -444,14 +444,14 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data           53                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           53                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data          325                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total          325                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          378                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          378                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          378                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          378                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           58                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           58                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data          326                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total          326                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          384                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          384                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          384                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          384                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data           63                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total           63                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data           83                       # number of WriteReq MSHR misses
@@ -460,103 +460,103 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          146
 system.cpu.dcache.demand_mshr_misses::total          146                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          146                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          146                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      2243500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      2243500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      2978500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      2978500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      5222000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      5222000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      5222000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      5222000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.019937                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.019937                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      2518000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      2518000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      3293000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      3293000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      5811000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      5811000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      5811000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      5811000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.019956                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.019956                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.057559                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.057559                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.031725                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.031725                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.031725                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.031725                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35611.111111                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35611.111111                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35885.542169                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35885.542169                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35767.123288                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 35767.123288                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35767.123288                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 35767.123288                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.031746                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.031746                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.031746                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.031746                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39968.253968                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39968.253968                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39674.698795                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39674.698795                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 39801.369863                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 39801.369863                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 39801.369863                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 39801.369863                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse               236.586962                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               234.467813                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       2                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                   401                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  0.004988                       # Average number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                   400                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.005000                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst    200.308921                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data     36.278041                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst     0.006113                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.001107                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.007220                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst    198.479082                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     35.988731                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.006057                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.001098                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.007155                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              2                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::total               2                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst            2                       # number of overall hits
 system.cpu.l2cache.overall_hits::total              2                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          338                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.inst          337                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.data           63                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total          401                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total          400                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data           83                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total           83                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          338                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst          337                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.data          146                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total           484                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          338                       # number of overall misses
+system.cpu.l2cache.demand_misses::total           483                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          337                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          146                       # number of overall misses
-system.cpu.l2cache.overall_misses::total          484                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     11581500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      2169000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     13750500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      2869000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      2869000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     11581500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data      5038000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     16619500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     11581500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data      5038000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     16619500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          340                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.overall_misses::total          483                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     11867000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      2431500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     14298500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      3194500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      3194500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     11867000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      5626000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     17493000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     11867000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      5626000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     17493000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          339                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data           63                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total          403                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total          402                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data           83                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total           83                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          340                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst          339                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data          146                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total          486                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          340                       # number of overall (read+write) accesses
+system.cpu.l2cache.demand_accesses::total          485                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          339                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data          146                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total          486                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.994118                       # miss rate for ReadReq accesses
+system.cpu.l2cache.overall_accesses::total          485                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.994100                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.995037                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.995025                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.994118                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.994100                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.995885                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.994118                       # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::total     0.995876                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.994100                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.995885                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34264.792899                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34428.571429                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 34290.523691                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34566.265060                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34566.265060                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34264.792899                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34506.849315                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 34337.809917                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34264.792899                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34506.849315                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 34337.809917                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total     0.995876                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35213.649852                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 38595.238095                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 35746.250000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 38487.951807                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 38487.951807                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35213.649852                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 38534.246575                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 36217.391304                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35213.649852                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 38534.246575                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 36217.391304                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -565,50 +565,50 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          338                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          337                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           63                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total          401                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total          400                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           83                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total           83                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          338                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          337                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data          146                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total          484                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          338                       # number of overall MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total          483                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          337                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          146                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total          484                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     10495000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      1969500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     12464500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      2607500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2607500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     10495000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      4577000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     15072000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     10495000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      4577000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     15072000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.994118                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.overall_mshr_misses::total          483                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     10794500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      2238500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     13033000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      2937500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2937500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     10794500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5176000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     15970500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     10794500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5176000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     15970500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.994100                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.995037                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.995025                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.994118                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.994100                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.995885                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.994118                       # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.995876                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.994100                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.995885                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31050.295858                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31261.904762                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31083.541147                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31415.662651                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31415.662651                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31050.295858                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31349.315068                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31140.495868                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31050.295858                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31349.315068                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31140.495868                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.995876                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32031.157270                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 35531.746032                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32582.500000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35391.566265                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35391.566265                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32031.157270                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35452.054795                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33065.217391                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32031.157270                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35452.054795                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33065.217391                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini
index cfbf65944..10c1546b5 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini
@@ -148,7 +148,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 
@@ -180,7 +180,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0]
 slave=system.system_port system.cpu.l2cache.mem_side
 
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout
index 423d84a63..71ca2d641 100755
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun  4 2012 12:01:47
-gem5 started Jun  4 2012 14:45:13
+gem5 compiled Jul  2 2012 08:54:18
+gem5 started Jul  2 2012 11:31:22
 gem5 executing on zizzer
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Begining test of difficult SPARC instructions...
@@ -18,4 +18,4 @@ LDTX:		Passed
 LDTW:		Passed
 STTW:		Passed
 Done
-Exiting @ tick 41800000 because target called exit()
+Exiting @ tick 43120000 because target called exit()
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt
index f6532c6ee..54833842f 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000042                       # Number of seconds simulated
-sim_ticks                                    41800000                       # Number of ticks simulated
-final_tick                                   41800000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000043                       # Number of seconds simulated
+sim_ticks                                    43120000                       # Number of ticks simulated
+final_tick                                   43120000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 488993                       # Simulator instruction rate (inst/s)
-host_op_rate                                   488707                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1345414902                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 221064                       # Number of bytes of host memory used
-host_seconds                                     0.03                       # Real time elapsed on the host
+host_inst_rate                                 107758                       # Simulator instruction rate (inst/s)
+host_op_rate                                   107745                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              306125993                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 219936                       # Number of bytes of host memory used
+host_seconds                                     0.14                       # Real time elapsed on the host
 sim_insts                                       15175                       # Number of instructions simulated
 sim_ops                                         15175                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             17792                       # Number of bytes read from this memory
@@ -19,16 +19,16 @@ system.physmem.bytes_inst_read::total           17792                       # Nu
 system.physmem.num_reads::cpu.inst                278                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                138                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   416                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            425645933                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            211291866                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               636937799                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       425645933                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          425645933                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           425645933                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           211291866                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              636937799                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            412615955                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            204823748                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               617439703                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       412615955                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          412615955                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           412615955                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           204823748                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              617439703                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   18                       # Number of system calls
-system.cpu.numCycles                            83600                       # number of cpu cycles simulated
+system.cpu.numCycles                            86240                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                       15175                       # Number of instructions committed
@@ -47,18 +47,18 @@ system.cpu.num_mem_refs                          3684                       # nu
 system.cpu.num_load_insts                        2232                       # Number of load instructions
 system.cpu.num_store_insts                       1452                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                      83600                       # Number of busy cycles
+system.cpu.num_busy_cycles                      86240                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                      0                       # number of replacements
-system.cpu.icache.tagsinuse                153.436702                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                152.912665                       # Cycle average of tags in use
 system.cpu.icache.total_refs                    14941                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    280                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                  53.360714                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     153.436702                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.074920                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.074920                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst     152.912665                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.074664                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.074664                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst        14941                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total           14941                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst         14941                       # number of demand (read+write) hits
@@ -129,14 +129,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst        52700
 system.cpu.icache.overall_avg_mshr_miss_latency::total        52700                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.tagsinuse                 97.842991                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse                 97.642881                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                     3536                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                    138                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                  25.623188                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data      97.842991                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.023887                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.023887                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::cpu.data      97.642881                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.023839                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.023839                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data         2173                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total            2173                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data         1357                       # number of WriteReq hits
@@ -231,16 +231,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        53000
 system.cpu.dcache.overall_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse               184.236128                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               183.636297                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       2                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                   331                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.006042                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst    152.765242                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data     31.470886                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst     0.004662                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.000960                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.005622                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst    152.238639                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     31.397658                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.004646                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.000958                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.005604                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              2                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
index 08b3f6997..e18da5544 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
@@ -1773,7 +1773,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0]
 slave=system.l2c.mem_side system.system_port
 
@@ -1795,7 +1795,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.l2c.cpu_side
 slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
 
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
index b2cdd54e1..2447cd00c 100755
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:06:58
-gem5 started Jun 28 2012 22:54:10
+gem5 compiled Jul  2 2012 08:54:18
+gem5 started Jul  2 2012 11:31:33
 gem5 executing on zizzer
 command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
 Global frequency set at 1000000000000 ticks per second
@@ -17,66 +17,66 @@ Init done
 Iteration 1 completed
 [Iteration 2, Thread 3] Got lock
 [Iteration 2, Thread 3] Critical section done, previously next=0, now next=3
-[Iteration 2, Thread 1] Got lock
-[Iteration 2, Thread 1] Critical section done, previously next=3, now next=1
 [Iteration 2, Thread 2] Got lock
-[Iteration 2, Thread 2] Critical section done, previously next=1, now next=2
+[Iteration 2, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 2, Thread 1] Got lock
+[Iteration 2, Thread 1] Critical section done, previously next=2, now next=1
 Iteration 2 completed
-[Iteration 3, Thread 3] Got lock
-[Iteration 3, Thread 3] Critical section done, previously next=0, now next=3
 [Iteration 3, Thread 2] Got lock
-[Iteration 3, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 3, Thread 2] Critical section done, previously next=0, now next=2
 [Iteration 3, Thread 1] Got lock
 [Iteration 3, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 3, Thread 3] Got lock
+[Iteration 3, Thread 3] Critical section done, previously next=1, now next=3
 Iteration 3 completed
-[Iteration 4, Thread 3] Got lock
-[Iteration 4, Thread 3] Critical section done, previously next=0, now next=3
-[Iteration 4, Thread 1] Got lock
-[Iteration 4, Thread 1] Critical section done, previously next=3, now next=1
 [Iteration 4, Thread 2] Got lock
-[Iteration 4, Thread 2] Critical section done, previously next=1, now next=2
+[Iteration 4, Thread 2] Critical section done, previously next=0, now next=2
+[Iteration 4, Thread 1] Got lock
+[Iteration 4, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 4, Thread 3] Got lock
+[Iteration 4, Thread 3] Critical section done, previously next=1, now next=3
 Iteration 4 completed
-[Iteration 5, Thread 3] Got lock
-[Iteration 5, Thread 3] Critical section done, previously next=0, now next=3
 [Iteration 5, Thread 2] Got lock
-[Iteration 5, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 5, Thread 2] Critical section done, previously next=0, now next=2
+[Iteration 5, Thread 3] Got lock
+[Iteration 5, Thread 3] Critical section done, previously next=2, now next=3
 [Iteration 5, Thread 1] Got lock
-[Iteration 5, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 5, Thread 1] Critical section done, previously next=3, now next=1
 Iteration 5 completed
+[Iteration 6, Thread 3] Got lock
+[Iteration 6, Thread 3] Critical section done, previously next=0, now next=3
 [Iteration 6, Thread 2] Got lock
-[Iteration 6, Thread 2] Critical section done, previously next=0, now next=2
+[Iteration 6, Thread 2] Critical section done, previously next=3, now next=2
 [Iteration 6, Thread 1] Got lock
 [Iteration 6, Thread 1] Critical section done, previously next=2, now next=1
-[Iteration 6, Thread 3] Got lock
-[Iteration 6, Thread 3] Critical section done, previously next=1, now next=3
 Iteration 6 completed
-[Iteration 7, Thread 1] Got lock
-[Iteration 7, Thread 1] Critical section done, previously next=0, now next=1
-[Iteration 7, Thread 3] Got lock
-[Iteration 7, Thread 3] Critical section done, previously next=1, now next=3
 [Iteration 7, Thread 2] Got lock
-[Iteration 7, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 7, Thread 2] Critical section done, previously next=0, now next=2
+[Iteration 7, Thread 3] Got lock
+[Iteration 7, Thread 3] Critical section done, previously next=2, now next=3
+[Iteration 7, Thread 1] Got lock
+[Iteration 7, Thread 1] Critical section done, previously next=3, now next=1
 Iteration 7 completed
+[Iteration 8, Thread 1] Got lock
+[Iteration 8, Thread 1] Critical section done, previously next=0, now next=1
 [Iteration 8, Thread 2] Got lock
-[Iteration 8, Thread 2] Critical section done, previously next=0, now next=2
+[Iteration 8, Thread 2] Critical section done, previously next=1, now next=2
 [Iteration 8, Thread 3] Got lock
 [Iteration 8, Thread 3] Critical section done, previously next=2, now next=3
-[Iteration 8, Thread 1] Got lock
-[Iteration 8, Thread 1] Critical section done, previously next=3, now next=1
 Iteration 8 completed
-[Iteration 9, Thread 2] Got lock
-[Iteration 9, Thread 2] Critical section done, previously next=0, now next=2
-[Iteration 9, Thread 1] Got lock
-[Iteration 9, Thread 1] Critical section done, previously next=2, now next=1
 [Iteration 9, Thread 3] Got lock
-[Iteration 9, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 9, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 9, Thread 1] Got lock
+[Iteration 9, Thread 1] Critical section done, previously next=3, now next=1
+[Iteration 9, Thread 2] Got lock
+[Iteration 9, Thread 2] Critical section done, previously next=1, now next=2
 Iteration 9 completed
-[Iteration 10, Thread 3] Got lock
-[Iteration 10, Thread 3] Critical section done, previously next=0, now next=3
 [Iteration 10, Thread 2] Got lock
-[Iteration 10, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 10, Thread 2] Critical section done, previously next=0, now next=2
+[Iteration 10, Thread 3] Got lock
+[Iteration 10, Thread 3] Critical section done, previously next=2, now next=3
 [Iteration 10, Thread 1] Got lock
-[Iteration 10, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 10, Thread 1] Critical section done, previously next=3, now next=1
 Iteration 10 completed
 PASSED :-)
-Exiting @ tick 111594500 because target called exit()
+Exiting @ tick 113941500 because target called exit()
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
index ea1876230..08b3d0977 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
@@ -1,958 +1,958 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000112                       # Number of seconds simulated
-sim_ticks                                   111594500                       # Number of ticks simulated
-final_tick                                  111594500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000114                       # Number of seconds simulated
+sim_ticks                                   113941500                       # Number of ticks simulated
+final_tick                                  113941500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 200629                       # Simulator instruction rate (inst/s)
-host_op_rate                                   200629                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               20568067                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 235024                       # Number of bytes of host memory used
-host_seconds                                     5.43                       # Real time elapsed on the host
-sim_insts                                     1088531                       # Number of instructions simulated
-sim_ops                                       1088531                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu0.inst            23104                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data            10816                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst             5632                       # Number of bytes read from this memory
+host_inst_rate                                 130117                       # Simulator instruction rate (inst/s)
+host_op_rate                                   130117                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               13474596                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 234988                       # Number of bytes of host memory used
+host_seconds                                     8.46                       # Real time elapsed on the host
+sim_insts                                     1100269                       # Number of instructions simulated
+sim_ops                                       1100269                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu0.inst            23232                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data            10752                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst             5376                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.data             1280                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst              128                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst              320                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu2.data              832                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.inst              256                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.inst              384                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu3.data              832                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                42880                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst        23104                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst         5632                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst          128                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu3.inst          256                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           29120                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu0.inst               361                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data               169                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst                88                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total                43008                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst        23232                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst         5376                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst          320                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu3.inst          384                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           29312                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu0.inst               363                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data               168                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst                84                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.data                20                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst                 2                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst                 5                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu2.data                13                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.inst                 4                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.inst                 6                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu3.data                13                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                   670                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu0.inst           207035293                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            96922339                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst            50468437                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data            11470099                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst             1147010                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data             7455565                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst             2294020                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data             7455565                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               384248328                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst      207035293                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst       50468437                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst        1147010                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst        2294020                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          260944760                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst          207035293                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           96922339                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst           50468437                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data           11470099                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst            1147010                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data            7455565                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst            2294020                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data            7455565                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              384248328                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_reads::total                   672                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu0.inst           203894104                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data            94364213                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst            47182107                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data            11233835                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst             2808459                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data             7301993                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.inst             3370150                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.data             7301993                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               377456853                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst      203894104                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst       47182107                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst        2808459                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu3.inst        3370150                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          257254819                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst          203894104                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           94364213                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst           47182107                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data           11233835                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst            2808459                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data            7301993                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.inst            3370150                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.data            7301993                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              377456853                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu0.workload.num_syscalls                  89                       # Number of system calls
-system.cpu0.numCycles                          223190                       # number of cpu cycles simulated
+system.cpu0.numCycles                          227884                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.BPredUnit.lookups                   87370                       # Number of BP lookups
-system.cpu0.BPredUnit.condPredicted             85036                       # Number of conditional branches predicted
-system.cpu0.BPredUnit.condIncorrect              1313                       # Number of conditional branches incorrect
-system.cpu0.BPredUnit.BTBLookups                84895                       # Number of BTB lookups
-system.cpu0.BPredUnit.BTBHits                   82517                       # Number of BTB hits
+system.cpu0.BPredUnit.lookups                   88195                       # Number of BP lookups
+system.cpu0.BPredUnit.condPredicted             85894                       # Number of conditional branches predicted
+system.cpu0.BPredUnit.condIncorrect              1314                       # Number of conditional branches incorrect
+system.cpu0.BPredUnit.BTBLookups                85741                       # Number of BTB lookups
+system.cpu0.BPredUnit.BTBHits                   83416                       # Number of BTB hits
 system.cpu0.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.BPredUnit.usedRAS                     514                       # Number of times the RAS was used to get a target.
+system.cpu0.BPredUnit.usedRAS                     517                       # Number of times the RAS was used to get a target.
 system.cpu0.BPredUnit.RASInCorrect                132                       # Number of incorrect RAS predictions.
-system.cpu0.fetch.icacheStallCycles             17415                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                        518858                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                      87370                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches             83031                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                       170328                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles                   4037                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.BlockedCycles                 13330                       # Number of cycles fetch has spent blocked
+system.cpu0.fetch.icacheStallCycles             17885                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                        523742                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                      88195                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches             83933                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                       172058                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles                   4069                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.BlockedCycles                 15014                       # Number of cycles fetch has spent blocked
 system.cpu0.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles         1404                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.CacheLines                     6152                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes                  508                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.rateDist::samples            205057                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             2.530311                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            2.210840                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.PendingTrapStallCycles         1439                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.CacheLines                     6122                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes                  517                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.rateDist::samples            209007                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             2.505859                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            2.211450                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0                   34729     16.94%     16.94% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                   84380     41.15%     58.09% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                     595      0.29%     58.38% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                     973      0.47%     58.85% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4                     523      0.26%     59.11% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5                   80298     39.16%     98.26% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6                     656      0.32%     98.58% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7                     373      0.18%     98.77% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8                    2530      1.23%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0                   36949     17.68%     17.68% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                   85270     40.80%     58.48% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                     593      0.28%     58.76% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                    1005      0.48%     59.24% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4                     500      0.24%     59.48% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5                   81190     38.85%     98.33% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6                     659      0.32%     98.64% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7                     361      0.17%     98.81% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8                    2480      1.19%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total              205057                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.391460                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       2.324737                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles                   18107                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles                14779                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                   169274                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles                  322                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles                  2575                       # Number of cycles decode is squashing
-system.cpu0.decode.DecodedInsts                515764                       # Number of instructions handled by decode
-system.cpu0.rename.SquashCycles                  2575                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles                   18814                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles                   1415                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles         12654                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                   168925                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles                  674                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts                512400                       # Number of instructions processed by rename
-system.cpu0.rename.IQFullEvents                     5                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LSQFullEvents                  252                       # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.RenamedOperands             350257                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups              1022076                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups         1022076                       # Number of integer rename lookups
-system.cpu0.rename.CommittedMaps               336320                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                   13937                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts               921                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts           951                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                     4116                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads              164196                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores              82879                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads            80125                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores           79869                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                    428350                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded                958                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                   425359                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued              176                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined          11411                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined        10569                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved           399                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples       205057                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        2.074345                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.084750                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total              209007                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.387017                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       2.298283                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles                   18552                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles                16516                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                   170985                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles                  348                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles                  2606                       # Number of cycles decode is squashing
+system.cpu0.decode.DecodedInsts                520718                       # Number of instructions handled by decode
+system.cpu0.rename.SquashCycles                  2606                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles                   19281                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles                   2206                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles         13583                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                   170639                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles                  692                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts                517471                       # Number of instructions processed by rename
+system.cpu0.rename.IQFullEvents                     4                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LSQFullEvents                  300                       # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.RenamedOperands             353567                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups              1032190                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups         1032190                       # Number of integer rename lookups
+system.cpu0.rename.CommittedMaps               339600                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                   13967                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts               909                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts           933                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                     4082                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads              165924                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores              83735                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads            81055                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores           80764                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                    432543                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded                950                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                   429278                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued              221                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined          11501                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined        11387                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved           391                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples       209007                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        2.053893                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.097042                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0              33897     16.53%     16.53% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1               5266      2.57%     19.10% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2              81920     39.95%     59.05% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3              81274     39.63%     98.68% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4               1599      0.78%     99.46% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5                693      0.34%     99.80% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6                302      0.15%     99.95% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7                 90      0.04%     99.99% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8                 16      0.01%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0              36203     17.32%     17.32% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1               5360      2.56%     19.89% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2              82686     39.56%     59.45% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3              82056     39.26%     98.71% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4               1635      0.78%     99.49% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5                680      0.33%     99.81% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6                282      0.13%     99.95% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7                 94      0.04%     99.99% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8                 11      0.01%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total         205057                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total         209007                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                     54     22.69%     22.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                     0      0.00%     22.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                      0      0.00%     22.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     22.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     22.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     22.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%     22.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     22.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     22.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     22.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     22.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     22.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     22.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     22.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     22.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%     22.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     22.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%     22.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     22.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     22.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     22.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     22.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     22.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     22.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     22.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     22.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     22.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     22.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     22.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead                    72     30.25%     52.94% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite                  112     47.06%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                     43     16.23%     16.23% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                     0      0.00%     16.23% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                      0      0.00%     16.23% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     16.23% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     16.23% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     16.23% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%     16.23% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     16.23% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     16.23% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     16.23% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     16.23% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     16.23% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     16.23% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     16.23% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     16.23% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%     16.23% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     16.23% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%     16.23% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     16.23% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     16.23% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     16.23% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     16.23% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     16.23% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     16.23% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     16.23% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     16.23% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     16.23% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     16.23% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     16.23% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead                   110     41.51%     57.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite                  112     42.26%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu               179447     42.19%     42.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult                   0      0.00%     42.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     42.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     42.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     42.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     42.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     42.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     42.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     42.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     42.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     42.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     42.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     42.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     42.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     42.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     42.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     42.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     42.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     42.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     42.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     42.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     42.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     42.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     42.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     42.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     42.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     42.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     42.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     42.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead              163633     38.47%     80.66% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite              82279     19.34%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu               180966     42.16%     42.16% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult                   0      0.00%     42.16% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     42.16% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     42.16% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     42.16% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     42.16% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     42.16% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     42.16% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     42.16% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     42.16% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     42.16% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     42.16% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     42.16% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     42.16% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     42.16% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     42.16% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     42.16% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     42.16% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     42.16% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     42.16% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     42.16% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     42.16% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     42.16% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     42.16% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     42.16% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     42.16% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     42.16% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     42.16% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     42.16% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead              165240     38.49%     80.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite              83072     19.35%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total                425359                       # Type of FU issued
-system.cpu0.iq.rate                          1.905816                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                        238                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.000560                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads           1056189                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes           440777                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses       423418                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.FU_type_0::total                429278                       # Type of FU issued
+system.cpu0.iq.rate                          1.883757                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                        265                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.000617                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads           1068049                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes           445050                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses       427325                       # Number of integer instruction queue wakeup accesses
 system.cpu0.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
 system.cpu0.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
 system.cpu0.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses                425597                       # Number of integer alu accesses
+system.cpu0.iq.int_alu_accesses                429543                       # Number of integer alu accesses
 system.cpu0.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads           79599                       # Number of loads that had data forwarded from stores
+system.cpu0.iew.lsq.thread0.forwLoads           80408                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads         2452                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.squashedLoads         2540                       # Number of loads squashed
 system.cpu0.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation           58                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores         1501                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation           56                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores         1537                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu0.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked           16                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.cacheBlocked            8                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles                  2575                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles                   1020                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles                   41                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts             509980                       # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts              329                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts               164196                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts               82879                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts               846                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                    43                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewSquashCycles                  2606                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles                   1701                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles                   86                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts             515038                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts              368                       # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts               165924                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts               83735                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts               837                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                    90                       # Number of times the IQ has become full, causing a stall
 system.cpu0.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents            58                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect           368                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect         1157                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts                1525                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts               424238                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts               163317                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts             1121                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.memOrderViolationEvents            56                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect           370                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect         1149                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts                1519                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts               428170                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts               164921                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts             1108                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                        80672                       # number of nop insts executed
-system.cpu0.iew.exec_refs                      245449                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches                   84313                       # Number of branches executed
-system.cpu0.iew.exec_stores                     82132                       # Number of stores executed
-system.cpu0.iew.exec_rate                    1.900793                       # Inst execution rate
-system.cpu0.iew.wb_sent                        423777                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                       423418                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                   250898                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                   253433                       # num instructions consuming a value
+system.cpu0.iew.exec_nop                        81545                       # number of nop insts executed
+system.cpu0.iew.exec_refs                      247840                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches                   85100                       # Number of branches executed
+system.cpu0.iew.exec_stores                     82919                       # Number of stores executed
+system.cpu0.iew.exec_rate                    1.878895                       # Inst execution rate
+system.cpu0.iew.wb_sent                        427676                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                       427325                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                   253224                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                   255650                       # num instructions consuming a value
 system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate                      1.897119                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.989997                       # average fanout of values written-back
+system.cpu0.iew.wb_rate                      1.875186                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.990510                       # average fanout of values written-back
 system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitCommittedInsts        496825                       # The number of committed instructions
-system.cpu0.commit.commitCommittedOps          496825                       # The number of committed instructions
-system.cpu0.commit.commitSquashedInsts          13135                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitCommittedInsts        501745                       # The number of committed instructions
+system.cpu0.commit.commitCommittedOps          501745                       # The number of committed instructions
+system.cpu0.commit.commitSquashedInsts          13260                       # The number of squashed insts skipped by commit
 system.cpu0.commit.commitNonSpecStalls            559                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts             1313                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples       202499                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     2.453469                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     2.133222                       # Number of insts commited each cycle
+system.cpu0.commit.branchMispredicts             1314                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples       206418                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     2.430723                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     2.136815                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0        34446     17.01%     17.01% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1        84010     41.49%     58.50% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2         2422      1.20%     59.69% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3          711      0.35%     60.04% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4          562      0.28%     60.32% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5        79343     39.18%     99.50% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6          465      0.23%     99.73% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7          235      0.12%     99.85% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8          305      0.15%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0        36760     17.81%     17.81% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1        84779     41.07%     58.88% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2         2446      1.18%     60.07% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3          715      0.35%     60.41% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4          578      0.28%     60.69% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5        80055     38.78%     99.47% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6          554      0.27%     99.74% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7          230      0.11%     99.85% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8          301      0.15%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total       202499                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts              496825                       # Number of instructions committed
-system.cpu0.commit.committedOps                496825                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total       206418                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts              501745                       # Number of instructions committed
+system.cpu0.commit.committedOps                501745                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                        243122                       # Number of memory references committed
-system.cpu0.commit.loads                       161744                       # Number of loads committed
+system.cpu0.commit.refs                        245582                       # Number of memory references committed
+system.cpu0.commit.loads                       163384                       # Number of loads committed
 system.cpu0.commit.membars                         84                       # Number of memory barriers committed
-system.cpu0.commit.branches                     83266                       # Number of branches committed
+system.cpu0.commit.branches                     84086                       # Number of branches committed
 system.cpu0.commit.fp_insts                         0                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                   334650                       # Number of committed integer instructions.
+system.cpu0.commit.int_insts                   337930                       # Number of committed integer instructions.
 system.cpu0.commit.function_calls                 223                       # Number of function calls committed.
-system.cpu0.commit.bw_lim_events                  305                       # number cycles where commit BW limit reached
+system.cpu0.commit.bw_lim_events                  301                       # number cycles where commit BW limit reached
 system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads                      710993                       # The number of ROB reads
-system.cpu0.rob.rob_writes                    1022511                       # The number of ROB writes
-system.cpu0.timesIdled                            324                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                          18133                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.committedInsts                     416744                       # Number of Instructions Simulated
-system.cpu0.committedOps                       416744                       # Number of Ops (including micro ops) Simulated
-system.cpu0.committedInsts_total               416744                       # Number of Instructions Simulated
-system.cpu0.cpi                              0.535557                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        0.535557                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              1.867216                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        1.867216                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads                  758967                       # number of integer regfile reads
-system.cpu0.int_regfile_writes                 341941                       # number of integer regfile writes
+system.cpu0.rob.rob_reads                      719961                       # The number of ROB reads
+system.cpu0.rob.rob_writes                    1032633                       # The number of ROB writes
+system.cpu0.timesIdled                            343                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                          18877                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.committedInsts                     420844                       # Number of Instructions Simulated
+system.cpu0.committedOps                       420844                       # Number of Ops (including micro ops) Simulated
+system.cpu0.committedInsts_total               420844                       # Number of Instructions Simulated
+system.cpu0.cpi                              0.541493                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        0.541493                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              1.846747                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        1.846747                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads                  766075                       # number of integer regfile reads
+system.cpu0.int_regfile_writes                 345063                       # number of integer regfile writes
 system.cpu0.fp_regfile_reads                      192                       # number of floating regfile reads
-system.cpu0.misc_regfile_reads                 247293                       # number of misc regfile reads
+system.cpu0.misc_regfile_reads                 249668                       # number of misc regfile reads
 system.cpu0.misc_regfile_writes                   564                       # number of misc regfile writes
-system.cpu0.icache.replacements                   307                       # number of replacements
-system.cpu0.icache.tagsinuse               248.147409                       # Cycle average of tags in use
-system.cpu0.icache.total_refs                    5393                       # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs                   598                       # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs                  9.018395                       # Average number of references to valid blocks.
+system.cpu0.icache.replacements                   308                       # number of replacements
+system.cpu0.icache.tagsinuse               248.197747                       # Cycle average of tags in use
+system.cpu0.icache.total_refs                    5361                       # Total number of references to valid blocks.
+system.cpu0.icache.sampled_refs                   601                       # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs                  8.920133                       # Average number of references to valid blocks.
 system.cpu0.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst   248.147409                       # Average occupied blocks per requestor
-system.cpu0.icache.occ_percent::cpu0.inst     0.484663                       # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::total        0.484663                       # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst         5393                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total           5393                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst         5393                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total            5393                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst         5393                       # number of overall hits
-system.cpu0.icache.overall_hits::total           5393                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst          759                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total          759                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst          759                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total           759                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst          759                       # number of overall misses
-system.cpu0.icache.overall_misses::total          759                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst     28913000                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total     28913000                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst     28913000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total     28913000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst     28913000                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total     28913000                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst         6152                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total         6152                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst         6152                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total         6152                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst         6152                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total         6152                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.123375                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.123375                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.123375                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.123375                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.123375                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.123375                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38093.544137                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 38093.544137                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38093.544137                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 38093.544137                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38093.544137                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 38093.544137                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs        15500                       # number of cycles access was blocked
+system.cpu0.icache.occ_blocks::cpu0.inst   248.197747                       # Average occupied blocks per requestor
+system.cpu0.icache.occ_percent::cpu0.inst     0.484761                       # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::total        0.484761                       # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits::cpu0.inst         5361                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total           5361                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst         5361                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total            5361                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst         5361                       # number of overall hits
+system.cpu0.icache.overall_hits::total           5361                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst          761                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total          761                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst          761                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total           761                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst          761                       # number of overall misses
+system.cpu0.icache.overall_misses::total          761                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst     29540500                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total     29540500                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst     29540500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total     29540500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst     29540500                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total     29540500                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst         6122                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total         6122                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst         6122                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total         6122                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst         6122                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total         6122                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.124306                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.124306                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.124306                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.124306                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.124306                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.124306                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38818.002628                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 38818.002628                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38818.002628                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 38818.002628                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38818.002628                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 38818.002628                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs        13500                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                1                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs        15500                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs        13500                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst          160                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total          160                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst          160                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total          160                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst          160                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total          160                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst          599                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total          599                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst          599                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total          599                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst          599                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total          599                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst     21855500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total     21855500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst     21855500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total     21855500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst     21855500                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total     21855500                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.097367                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.097367                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.097367                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.097367                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.097367                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.097367                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36486.644407                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36486.644407                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36486.644407                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 36486.644407                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36486.644407                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 36486.644407                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst          159                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total          159                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst          159                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total          159                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst          159                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total          159                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst          602                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total          602                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst          602                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total          602                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst          602                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total          602                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst     22436000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total     22436000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst     22436000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total     22436000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst     22436000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total     22436000                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.098334                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.098334                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.098334                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.098334                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.098334                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.098334                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 37269.102990                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 37269.102990                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 37269.102990                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 37269.102990                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 37269.102990                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 37269.102990                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu0.dcache.replacements                     2                       # number of replacements
-system.cpu0.dcache.tagsinuse               144.541703                       # Cycle average of tags in use
-system.cpu0.dcache.total_refs                  163878                       # Total number of references to valid blocks.
-system.cpu0.dcache.sampled_refs                   171                       # Sample count of references to valid blocks.
-system.cpu0.dcache.avg_refs                958.350877                       # Average number of references to valid blocks.
+system.cpu0.dcache.tagsinuse               144.386808                       # Cycle average of tags in use
+system.cpu0.dcache.total_refs                  165433                       # Total number of references to valid blocks.
+system.cpu0.dcache.sampled_refs                   170                       # Sample count of references to valid blocks.
+system.cpu0.dcache.avg_refs                973.135294                       # Average number of references to valid blocks.
 system.cpu0.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::cpu0.data   144.541703                       # Average occupied blocks per requestor
-system.cpu0.dcache.occ_percent::cpu0.data     0.282308                       # Average percentage of cache occupancy
-system.cpu0.dcache.occ_percent::total        0.282308                       # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::cpu0.data        83150                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total          83150                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data        80790                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total         80790                       # number of WriteReq hits
-system.cpu0.dcache.SwapReq_hits::cpu0.data           21                       # number of SwapReq hits
-system.cpu0.dcache.SwapReq_hits::total             21                       # number of SwapReq hits
-system.cpu0.dcache.demand_hits::cpu0.data       163940                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total          163940                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data       163940                       # number of overall hits
-system.cpu0.dcache.overall_hits::total         163940                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data          500                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total          500                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data          546                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total          546                       # number of WriteReq misses
-system.cpu0.dcache.SwapReq_misses::cpu0.data           21                       # number of SwapReq misses
-system.cpu0.dcache.SwapReq_misses::total           21                       # number of SwapReq misses
-system.cpu0.dcache.demand_misses::cpu0.data         1046                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total          1046                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data         1046                       # number of overall misses
-system.cpu0.dcache.overall_misses::total         1046                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data     13780500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total     13780500                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data     24368986                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total     24368986                       # number of WriteReq miss cycles
-system.cpu0.dcache.SwapReq_miss_latency::cpu0.data       390500                       # number of SwapReq miss cycles
-system.cpu0.dcache.SwapReq_miss_latency::total       390500                       # number of SwapReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data     38149486                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total     38149486                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data     38149486                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total     38149486                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data        83650                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total        83650                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data        81336                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total        81336                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.occ_blocks::cpu0.data   144.386808                       # Average occupied blocks per requestor
+system.cpu0.dcache.occ_percent::cpu0.data     0.282005                       # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::total        0.282005                       # Average percentage of cache occupancy
+system.cpu0.dcache.ReadReq_hits::cpu0.data        83919                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total          83919                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data        81593                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total         81593                       # number of WriteReq hits
+system.cpu0.dcache.SwapReq_hits::cpu0.data           18                       # number of SwapReq hits
+system.cpu0.dcache.SwapReq_hits::total             18                       # number of SwapReq hits
+system.cpu0.dcache.demand_hits::cpu0.data       165512                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total          165512                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data       165512                       # number of overall hits
+system.cpu0.dcache.overall_hits::total         165512                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data          525                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total          525                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data          563                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total          563                       # number of WriteReq misses
+system.cpu0.dcache.SwapReq_misses::cpu0.data           24                       # number of SwapReq misses
+system.cpu0.dcache.SwapReq_misses::total           24                       # number of SwapReq misses
+system.cpu0.dcache.demand_misses::cpu0.data         1088                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total          1088                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data         1088                       # number of overall misses
+system.cpu0.dcache.overall_misses::total         1088                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data     16325500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total     16325500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data     28838494                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total     28838494                       # number of WriteReq miss cycles
+system.cpu0.dcache.SwapReq_miss_latency::cpu0.data       480000                       # number of SwapReq miss cycles
+system.cpu0.dcache.SwapReq_miss_latency::total       480000                       # number of SwapReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data     45163994                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total     45163994                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data     45163994                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total     45163994                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data        84444                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total        84444                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data        82156                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total        82156                       # number of WriteReq accesses(hits+misses)
 system.cpu0.dcache.SwapReq_accesses::cpu0.data           42                       # number of SwapReq accesses(hits+misses)
 system.cpu0.dcache.SwapReq_accesses::total           42                       # number of SwapReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data       164986                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total       164986                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data       164986                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total       164986                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.005977                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.005977                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.006713                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.006713                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SwapReq_miss_rate::cpu0.data     0.500000                       # miss rate for SwapReq accesses
-system.cpu0.dcache.SwapReq_miss_rate::total     0.500000                       # miss rate for SwapReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.006340                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.006340                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.006340                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.006340                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data        27561                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total        27561                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44631.842491                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 44631.842491                       # average WriteReq miss latency
-system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 18595.238095                       # average SwapReq miss latency
-system.cpu0.dcache.SwapReq_avg_miss_latency::total 18595.238095                       # average SwapReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36471.783939                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 36471.783939                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36471.783939                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 36471.783939                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs       194000                       # number of cycles access was blocked
+system.cpu0.dcache.demand_accesses::cpu0.data       166600                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total       166600                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data       166600                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total       166600                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.006217                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.006217                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.006853                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.006853                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SwapReq_miss_rate::cpu0.data     0.571429                       # miss rate for SwapReq accesses
+system.cpu0.dcache.SwapReq_miss_rate::total     0.571429                       # miss rate for SwapReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.006531                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.006531                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.006531                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.006531                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31096.190476                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 31096.190476                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 51222.902309                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 51222.902309                       # average WriteReq miss latency
+system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data        20000                       # average SwapReq miss latency
+system.cpu0.dcache.SwapReq_avg_miss_latency::total        20000                       # average SwapReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 41511.023897                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 41511.023897                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 41511.023897                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 41511.023897                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs       119500                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs               19                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs               18                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10210.526316                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs  6638.888889                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.dcache.writebacks::writebacks            1                       # number of writebacks
 system.cpu0.dcache.writebacks::total                1                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data          320                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total          320                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data          371                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total          371                       # number of WriteReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data          691                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total          691                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data          691                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total          691                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data          345                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total          345                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data          392                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total          392                       # number of WriteReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data          737                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total          737                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data          737                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total          737                       # number of overall MSHR hits
 system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data          180                       # number of ReadReq MSHR misses
 system.cpu0.dcache.ReadReq_mshr_misses::total          180                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data          175                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total          175                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data           21                       # number of SwapReq MSHR misses
-system.cpu0.dcache.SwapReq_mshr_misses::total           21                       # number of SwapReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data          355                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total          355                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data          355                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total          355                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data      4933000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total      4933000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data      6275500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total      6275500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data       327500                       # number of SwapReq MSHR miss cycles
-system.cpu0.dcache.SwapReq_mshr_miss_latency::total       327500                       # number of SwapReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data     11208500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total     11208500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data     11208500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total     11208500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.002152                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.002152                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.002152                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.002152                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data     0.500000                       # mshr miss rate for SwapReq accesses
-system.cpu0.dcache.SwapReq_mshr_miss_rate::total     0.500000                       # mshr miss rate for SwapReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.002152                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.002152                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.002152                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.002152                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27405.555556                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 27405.555556                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data        35860                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total        35860                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 15595.238095                       # average SwapReq mshr miss latency
-system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 15595.238095                       # average SwapReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31573.239437                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31573.239437                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31573.239437                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31573.239437                       # average overall mshr miss latency
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data          171                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total          171                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data           24                       # number of SwapReq MSHR misses
+system.cpu0.dcache.SwapReq_mshr_misses::total           24                       # number of SwapReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data          351                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total          351                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data          351                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total          351                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data      5693511                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total      5693511                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data      6731000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total      6731000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data       405000                       # number of SwapReq MSHR miss cycles
+system.cpu0.dcache.SwapReq_mshr_miss_latency::total       405000                       # number of SwapReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data     12424511                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total     12424511                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data     12424511                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total     12424511                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.002132                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.002132                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.002081                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.002081                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data     0.571429                       # mshr miss rate for SwapReq accesses
+system.cpu0.dcache.SwapReq_mshr_miss_rate::total     0.571429                       # mshr miss rate for SwapReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.002107                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.002107                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.002107                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.002107                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 31630.616667                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 31630.616667                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39362.573099                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39362.573099                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data        16875                       # average SwapReq mshr miss latency
+system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total        16875                       # average SwapReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35397.467236                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35397.467236                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35397.467236                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35397.467236                       # average overall mshr miss latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.numCycles                          187839                       # number of cpu cycles simulated
+system.cpu1.numCycles                          191339                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.BPredUnit.lookups                   50940                       # Number of BP lookups
-system.cpu1.BPredUnit.condPredicted             47890                       # Number of conditional branches predicted
-system.cpu1.BPredUnit.condIncorrect              1510                       # Number of conditional branches incorrect
-system.cpu1.BPredUnit.BTBLookups                44289                       # Number of BTB lookups
-system.cpu1.BPredUnit.BTBHits                   43310                       # Number of BTB hits
+system.cpu1.BPredUnit.lookups                   49631                       # Number of BP lookups
+system.cpu1.BPredUnit.condPredicted             46572                       # Number of conditional branches predicted
+system.cpu1.BPredUnit.condIncorrect              1528                       # Number of conditional branches incorrect
+system.cpu1.BPredUnit.BTBLookups                42950                       # Number of BTB lookups
+system.cpu1.BPredUnit.BTBHits                   41997                       # Number of BTB hits
 system.cpu1.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.BPredUnit.usedRAS                     829                       # Number of times the RAS was used to get a target.
+system.cpu1.BPredUnit.usedRAS                     805                       # Number of times the RAS was used to get a target.
 system.cpu1.BPredUnit.RASInCorrect                232                       # Number of incorrect RAS predictions.
-system.cpu1.fetch.icacheStallCycles             31688                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                        280910                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                      50940                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches             44139                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                       100869                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles                   4392                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.BlockedCycles                 39081                       # Number of cycles fetch has spent blocked
+system.cpu1.fetch.icacheStallCycles             33375                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                        271825                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                      49631                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches             42802                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                        98758                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles                   4453                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.BlockedCycles                 42292                       # Number of cycles fetch has spent blocked
 system.cpu1.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.NoActiveThreadStallCycles         6575                       # Number of stall cycles due to no active thread to fetch from
-system.cpu1.fetch.PendingTrapStallCycles         1045                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.CacheLines                    22757                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes                  318                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.rateDist::samples            182067                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             1.542894                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            2.098462                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.NoActiveThreadStallCycles         6725                       # Number of stall cycles due to no active thread to fetch from
+system.cpu1.fetch.PendingTrapStallCycles         1070                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.CacheLines                    23889                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes                  317                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.rateDist::samples            185079                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             1.468697                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            2.066601                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0                   81198     44.60%     44.60% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                   51887     28.50%     73.10% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                    7438      4.09%     77.18% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                    3280      1.80%     78.98% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4                     684      0.38%     79.36% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5                   31924     17.53%     96.89% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6                    1209      0.66%     97.56% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7                     879      0.48%     98.04% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8                    3568      1.96%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0                   86321     46.64%     46.64% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                   51121     27.62%     74.26% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                    7925      4.28%     78.54% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                    3336      1.80%     80.35% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4                     734      0.40%     80.74% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5                   30013     16.22%     96.96% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6                    1151      0.62%     97.58% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7                     885      0.48%     98.06% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8                    3593      1.94%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total              182067                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.271190                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       1.495483                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                   38413                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles                34373                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                    93637                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles                 6265                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles                  2804                       # Number of cycles decode is squashing
-system.cpu1.decode.DecodedInsts                276803                       # Number of instructions handled by decode
-system.cpu1.rename.SquashCycles                  2804                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles                   39183                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles                  19194                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles         14318                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                    87661                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles                12332                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts                274424                       # Number of instructions processed by rename
-system.cpu1.rename.IQFullEvents                    18                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LSQFullEvents                   52                       # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.RenamedOperands             191179                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups               520245                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups          520245                       # Number of integer rename lookups
-system.cpu1.rename.CommittedMaps               175779                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                   15400                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts              1221                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts          1348                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                    15085                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads               76182                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores              35431                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads            36807                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores           30214                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                    225638                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded               7711                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                   228522                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued               80                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined          12774                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined        11561                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved           762                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples       182067                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        1.255153                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.306407                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total              185079                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.259388                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       1.420646                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                   40472                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles                37211                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                    91012                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles                 6805                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles                  2854                       # Number of cycles decode is squashing
+system.cpu1.decode.DecodedInsts                267804                       # Number of instructions handled by decode
+system.cpu1.rename.SquashCycles                  2854                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles                   41302                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles                  21637                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles         14674                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                    84497                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles                13390                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts                265308                       # Number of instructions processed by rename
+system.cpu1.rename.IQFullEvents                    16                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LSQFullEvents                   60                       # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.RenamedOperands             184298                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups               499771                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups          499771                       # Number of integer rename lookups
+system.cpu1.rename.CommittedMaps               168579                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                   15719                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts              1236                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts          1367                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                    16177                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads               72909                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores              33507                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads            35450                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores           28267                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                    217311                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded               8226                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                   220400                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued              173                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined          13138                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined        12222                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved           799                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples       185079                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        1.190843                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.296813                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0              78861     43.31%     43.31% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1              26436     14.52%     57.83% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2              35607     19.56%     77.39% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3              36159     19.86%     97.25% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4               3279      1.80%     99.05% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5               1252      0.69%     99.74% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6                353      0.19%     99.93% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7                 59      0.03%     99.97% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0              84217     45.50%     45.50% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1              27917     15.08%     60.59% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2              33688     18.20%     78.79% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3              34243     18.50%     97.29% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4               3324      1.80%     99.09% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5               1232      0.67%     99.75% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6                345      0.19%     99.94% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7                 52      0.03%     99.97% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::8                 61      0.03%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total         182067                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total         185079                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                     20      6.62%      6.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                     0      0.00%      6.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                      0      0.00%      6.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      6.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      6.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      6.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%      6.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      6.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      6.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      6.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      6.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      6.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      6.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      6.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      6.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%      6.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      6.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%      6.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      6.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      6.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      6.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      6.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      6.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      6.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      6.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      6.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      6.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      6.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      6.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead                    72     23.84%     30.46% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite                  210     69.54%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                     21      6.60%      6.60% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                     0      0.00%      6.60% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                      0      0.00%      6.60% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      6.60% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      6.60% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      6.60% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%      6.60% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      6.60% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      6.60% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      6.60% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      6.60% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      6.60% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      6.60% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      6.60% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      6.60% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%      6.60% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      6.60% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%      6.60% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      6.60% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      6.60% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      6.60% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      6.60% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      6.60% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      6.60% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      6.60% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      6.60% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      6.60% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      6.60% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      6.60% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead                    87     27.36%     33.96% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite                  210     66.04%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu               112122     49.06%     49.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult                   0      0.00%     49.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     49.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     49.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     49.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     49.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     49.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     49.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     49.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     49.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     49.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     49.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     49.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     49.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     49.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     49.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     49.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     49.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     49.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     49.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     49.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     49.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     49.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     49.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     49.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     49.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     49.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     49.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     49.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead               81642     35.73%     84.79% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite              34758     15.21%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu               108844     49.38%     49.38% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult                   0      0.00%     49.38% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     49.38% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     49.38% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     49.38% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     49.38% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     49.38% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     49.38% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     49.38% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     49.38% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     49.38% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     49.38% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     49.38% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     49.38% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     49.38% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     49.38% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     49.38% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     49.38% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     49.38% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     49.38% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     49.38% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     49.38% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     49.38% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     49.38% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     49.38% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     49.38% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     49.38% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     49.38% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     49.38% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead               78735     35.72%     85.11% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite              32821     14.89%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total                228522                       # Type of FU issued
-system.cpu1.iq.rate                          1.216584                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                        302                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.001322                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads            639493                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes           246163                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses       226488                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.FU_type_0::total                220400                       # Type of FU issued
+system.cpu1.iq.rate                          1.151882                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                        318                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.001443                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads            626370                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes           238714                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses       218326                       # Number of integer instruction queue wakeup accesses
 system.cpu1.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
 system.cpu1.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
 system.cpu1.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses                228824                       # Number of integer alu accesses
+system.cpu1.iq.int_alu_accesses                220718                       # Number of integer alu accesses
 system.cpu1.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads           30049                       # Number of loads that had data forwarded from stores
+system.cpu1.iew.lsq.thread0.forwLoads           28122                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads         2733                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses            6                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation           40                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores         1566                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads         2824                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses            8                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation           39                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores         1558                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu1.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
 system.cpu1.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles                  2804                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles                   1582                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles                   60                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts             271136                       # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts              377                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts                76182                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts               35431                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts              1144                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                    55                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewSquashCycles                  2854                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles                   2376                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles                   88                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts             261974                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts              434                       # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts                72909                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts               33507                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts              1131                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                    89                       # Number of times the IQ has become full, causing a stall
 system.cpu1.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents            40                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect           494                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect         1182                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts                1676                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts               227186                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts                75112                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts             1336                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.memOrderViolationEvents            39                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect           510                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect         1187                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts                1697                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts               219051                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts                71704                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts             1349                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                        37787                       # number of nop insts executed
-system.cpu1.iew.exec_refs                      109780                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches                   47145                       # Number of branches executed
-system.cpu1.iew.exec_stores                     34668                       # Number of stores executed
-system.cpu1.iew.exec_rate                    1.209472                       # Inst execution rate
-system.cpu1.iew.wb_sent                        226789                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                       226488                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                   126631                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                   131515                       # num instructions consuming a value
+system.cpu1.iew.exec_nop                        36437                       # number of nop insts executed
+system.cpu1.iew.exec_refs                      104435                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches                   45735                       # Number of branches executed
+system.cpu1.iew.exec_stores                     32731                       # Number of stores executed
+system.cpu1.iew.exec_rate                    1.144832                       # Inst execution rate
+system.cpu1.iew.wb_sent                        218612                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                       218326                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                   121254                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                   126110                       # num instructions consuming a value
 system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate                      1.205756                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.962864                       # average fanout of values written-back
+system.cpu1.iew.wb_rate                      1.141043                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.961494                       # average fanout of values written-back
 system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitCommittedInsts        256347                       # The number of committed instructions
-system.cpu1.commit.commitCommittedOps          256347                       # The number of committed instructions
-system.cpu1.commit.commitSquashedInsts          14788                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls           6949                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts             1510                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples       172689                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     1.484443                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.966336                       # Number of insts commited each cycle
+system.cpu1.commit.commitCommittedInsts        246738                       # The number of committed instructions
+system.cpu1.commit.commitCommittedOps          246738                       # The number of committed instructions
+system.cpu1.commit.commitSquashedInsts          15223                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls           7427                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts             1528                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples       175501                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     1.405907                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.932846                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0        79222     45.88%     45.88% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1        45065     26.10%     71.97% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2         6173      3.57%     75.55% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3         7849      4.55%     80.09% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4         1517      0.88%     80.97% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5        30495     17.66%     98.63% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6          550      0.32%     98.95% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7          998      0.58%     99.53% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8          820      0.47%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0        84843     48.34%     48.34% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1        43671     24.88%     73.23% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2         6232      3.55%     76.78% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3         8331      4.75%     81.52% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4         1551      0.88%     82.41% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5        28453     16.21%     98.62% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6          613      0.35%     98.97% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7          993      0.57%     99.54% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8          814      0.46%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total       172689                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts              256347                       # Number of instructions committed
-system.cpu1.commit.committedOps                256347                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total       175501                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts              246738                       # Number of instructions committed
+system.cpu1.commit.committedOps                246738                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                        107314                       # Number of memory references committed
-system.cpu1.commit.loads                        73449                       # Number of loads committed
-system.cpu1.commit.membars                       6235                       # Number of memory barriers committed
-system.cpu1.commit.branches                     46061                       # Number of branches committed
+system.cpu1.commit.refs                        102034                       # Number of memory references committed
+system.cpu1.commit.loads                        70085                       # Number of loads committed
+system.cpu1.commit.membars                       6711                       # Number of memory barriers committed
+system.cpu1.commit.branches                     44619                       # Number of branches committed
 system.cpu1.commit.fp_insts                         0                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                   175498                       # Number of committed integer instructions.
+system.cpu1.commit.int_insts                   168775                       # Number of committed integer instructions.
 system.cpu1.commit.function_calls                 322                       # Number of function calls committed.
-system.cpu1.commit.bw_lim_events                  820                       # number cycles where commit BW limit reached
+system.cpu1.commit.bw_lim_events                  814                       # number cycles where commit BW limit reached
 system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads                      442417                       # The number of ROB reads
-system.cpu1.rob.rob_writes                     545088                       # The number of ROB writes
-system.cpu1.timesIdled                            232                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                           5772                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                       35349                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                     213261                       # Number of Instructions Simulated
-system.cpu1.committedOps                       213261                       # Number of Ops (including micro ops) Simulated
-system.cpu1.committedInsts_total               213261                       # Number of Instructions Simulated
-system.cpu1.cpi                              0.880794                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        0.880794                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              1.135339                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        1.135339                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads                  389025                       # number of integer regfile reads
-system.cpu1.int_regfile_writes                 181950                       # number of integer regfile writes
+system.cpu1.rob.rob_reads                      436061                       # The number of ROB reads
+system.cpu1.rob.rob_writes                     526790                       # The number of ROB writes
+system.cpu1.timesIdled                            250                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                           6260                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                       36543                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                     204620                       # Number of Instructions Simulated
+system.cpu1.committedOps                       204620                       # Number of Ops (including micro ops) Simulated
+system.cpu1.committedInsts_total               204620                       # Number of Instructions Simulated
+system.cpu1.cpi                              0.935094                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        0.935094                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              1.069411                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        1.069411                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads                  373202                       # number of integer regfile reads
+system.cpu1.int_regfile_writes                 174771                       # number of integer regfile writes
 system.cpu1.fp_regfile_writes                      64                       # number of floating regfile writes
-system.cpu1.misc_regfile_reads                 111436                       # number of misc regfile reads
+system.cpu1.misc_regfile_reads                 106146                       # number of misc regfile reads
 system.cpu1.misc_regfile_writes                   646                       # number of misc regfile writes
-system.cpu1.icache.replacements                   321                       # number of replacements
-system.cpu1.icache.tagsinuse                92.166456                       # Cycle average of tags in use
-system.cpu1.icache.total_refs                   22247                       # Total number of references to valid blocks.
+system.cpu1.icache.replacements                   322                       # number of replacements
+system.cpu1.icache.tagsinuse                90.902674                       # Cycle average of tags in use
+system.cpu1.icache.total_refs                   23372                       # Total number of references to valid blocks.
 system.cpu1.icache.sampled_refs                   436                       # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs                 51.025229                       # Average number of references to valid blocks.
+system.cpu1.icache.avg_refs                 53.605505                       # Average number of references to valid blocks.
 system.cpu1.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::cpu1.inst    92.166456                       # Average occupied blocks per requestor
-system.cpu1.icache.occ_percent::cpu1.inst     0.180013                       # Average percentage of cache occupancy
-system.cpu1.icache.occ_percent::total        0.180013                       # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst        22247                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total          22247                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst        22247                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total           22247                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst        22247                       # number of overall hits
-system.cpu1.icache.overall_hits::total          22247                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst          510                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total          510                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst          510                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total           510                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst          510                       # number of overall misses
-system.cpu1.icache.overall_misses::total          510                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst     11347500                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total     11347500                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst     11347500                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total     11347500                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst     11347500                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total     11347500                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst        22757                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total        22757                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst        22757                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total        22757                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst        22757                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total        22757                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.022411                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.022411                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.022411                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.022411                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.022411                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.022411                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst        22250                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total        22250                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst        22250                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total        22250                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst        22250                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total        22250                       # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs        33000                       # number of cycles access was blocked
+system.cpu1.icache.occ_blocks::cpu1.inst    90.902674                       # Average occupied blocks per requestor
+system.cpu1.icache.occ_percent::cpu1.inst     0.177544                       # Average percentage of cache occupancy
+system.cpu1.icache.occ_percent::total        0.177544                       # Average percentage of cache occupancy
+system.cpu1.icache.ReadReq_hits::cpu1.inst        23372                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total          23372                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst        23372                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total           23372                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst        23372                       # number of overall hits
+system.cpu1.icache.overall_hits::total          23372                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst          517                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total          517                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst          517                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total           517                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst          517                       # number of overall misses
+system.cpu1.icache.overall_misses::total          517                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst     11874500                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total     11874500                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst     11874500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total     11874500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst     11874500                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total     11874500                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst        23889                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total        23889                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst        23889                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total        23889                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst        23889                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total        23889                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.021642                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.021642                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.021642                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.021642                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.021642                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.021642                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 22968.085106                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 22968.085106                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 22968.085106                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 22968.085106                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 22968.085106                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 22968.085106                       # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs        32000                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                1                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs        33000                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs        32000                       # average number of cycles each access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst           74                       # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total           74                       # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst           74                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total           74                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst           74                       # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total           74                       # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst           81                       # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total           81                       # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst           81                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total           81                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst           81                       # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total           81                       # number of overall MSHR hits
 system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst          436                       # number of ReadReq MSHR misses
 system.cpu1.icache.ReadReq_mshr_misses::total          436                       # number of ReadReq MSHR misses
 system.cpu1.icache.demand_mshr_misses::cpu1.inst          436                       # number of demand (read+write) MSHR misses
 system.cpu1.icache.demand_mshr_misses::total          436                       # number of demand (read+write) MSHR misses
 system.cpu1.icache.overall_mshr_misses::cpu1.inst          436                       # number of overall MSHR misses
 system.cpu1.icache.overall_mshr_misses::total          436                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst      8591500                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total      8591500                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst      8591500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total      8591500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst      8591500                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total      8591500                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.019159                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.019159                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.019159                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.019159                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.019159                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.019159                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 19705.275229                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 19705.275229                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 19705.275229                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 19705.275229                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 19705.275229                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 19705.275229                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst      8863000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total      8863000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst      8863000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total      8863000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst      8863000                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total      8863000                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.018251                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.018251                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.018251                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.018251                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.018251                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.018251                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 20327.981651                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 20327.981651                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 20327.981651                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 20327.981651                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 20327.981651                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 20327.981651                       # average overall mshr miss latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dcache.replacements                     0                       # number of replacements
-system.cpu1.dcache.tagsinuse                27.650583                       # Cycle average of tags in use
-system.cpu1.dcache.total_refs                   40148                       # Total number of references to valid blocks.
+system.cpu1.dcache.tagsinuse                27.508331                       # Cycle average of tags in use
+system.cpu1.dcache.total_refs                   38240                       # Total number of references to valid blocks.
 system.cpu1.dcache.sampled_refs                    29                       # Sample count of references to valid blocks.
-system.cpu1.dcache.avg_refs               1384.413793                       # Average number of references to valid blocks.
+system.cpu1.dcache.avg_refs               1318.620690                       # Average number of references to valid blocks.
 system.cpu1.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::cpu1.data    27.650583                       # Average occupied blocks per requestor
-system.cpu1.dcache.occ_percent::cpu1.data     0.054005                       # Average percentage of cache occupancy
-system.cpu1.dcache.occ_percent::total        0.054005                       # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::cpu1.data        44622                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total          44622                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data        33643                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total         33643                       # number of WriteReq hits
-system.cpu1.dcache.SwapReq_hits::cpu1.data           16                       # number of SwapReq hits
-system.cpu1.dcache.SwapReq_hits::total             16                       # number of SwapReq hits
-system.cpu1.dcache.demand_hits::cpu1.data        78265                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total           78265                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data        78265                       # number of overall hits
-system.cpu1.dcache.overall_hits::total          78265                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data          425                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total          425                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data          154                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total          154                       # number of WriteReq misses
-system.cpu1.dcache.SwapReq_misses::cpu1.data           52                       # number of SwapReq misses
-system.cpu1.dcache.SwapReq_misses::total           52                       # number of SwapReq misses
-system.cpu1.dcache.demand_misses::cpu1.data          579                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total           579                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data          579                       # number of overall misses
-system.cpu1.dcache.overall_misses::total          579                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data      9294500                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total      9294500                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data      3142500                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total      3142500                       # number of WriteReq miss cycles
-system.cpu1.dcache.SwapReq_miss_latency::cpu1.data      1219000                       # number of SwapReq miss cycles
-system.cpu1.dcache.SwapReq_miss_latency::total      1219000                       # number of SwapReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data     12437000                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total     12437000                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data     12437000                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total     12437000                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data        45047                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total        45047                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data        33797                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total        33797                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SwapReq_accesses::cpu1.data           68                       # number of SwapReq accesses(hits+misses)
-system.cpu1.dcache.SwapReq_accesses::total           68                       # number of SwapReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data        78844                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total        78844                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data        78844                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total        78844                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.009435                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.009435                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.004557                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.004557                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SwapReq_miss_rate::cpu1.data     0.764706                       # miss rate for SwapReq accesses
-system.cpu1.dcache.SwapReq_miss_rate::total     0.764706                       # miss rate for SwapReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.007344                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.007344                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.007344                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.007344                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 21869.411765                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 21869.411765                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20405.844156                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 20405.844156                       # average WriteReq miss latency
-system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 23442.307692                       # average SwapReq miss latency
-system.cpu1.dcache.SwapReq_avg_miss_latency::total 23442.307692                       # average SwapReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21480.138169                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 21480.138169                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21480.138169                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 21480.138169                       # average overall miss latency
+system.cpu1.dcache.occ_blocks::cpu1.data    27.508331                       # Average occupied blocks per requestor
+system.cpu1.dcache.occ_percent::cpu1.data     0.053727                       # Average percentage of cache occupancy
+system.cpu1.dcache.occ_percent::total        0.053727                       # Average percentage of cache occupancy
+system.cpu1.dcache.ReadReq_hits::cpu1.data        43171                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total          43171                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data        31745                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total         31745                       # number of WriteReq hits
+system.cpu1.dcache.SwapReq_hits::cpu1.data           15                       # number of SwapReq hits
+system.cpu1.dcache.SwapReq_hits::total             15                       # number of SwapReq hits
+system.cpu1.dcache.demand_hits::cpu1.data        74916                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total           74916                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data        74916                       # number of overall hits
+system.cpu1.dcache.overall_hits::total          74916                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data          395                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total          395                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data          134                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total          134                       # number of WriteReq misses
+system.cpu1.dcache.SwapReq_misses::cpu1.data           55                       # number of SwapReq misses
+system.cpu1.dcache.SwapReq_misses::total           55                       # number of SwapReq misses
+system.cpu1.dcache.demand_misses::cpu1.data          529                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total           529                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data          529                       # number of overall misses
+system.cpu1.dcache.overall_misses::total          529                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data     11922500                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total     11922500                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data      3308000                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total      3308000                       # number of WriteReq miss cycles
+system.cpu1.dcache.SwapReq_miss_latency::cpu1.data      1319000                       # number of SwapReq miss cycles
+system.cpu1.dcache.SwapReq_miss_latency::total      1319000                       # number of SwapReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data     15230500                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total     15230500                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data     15230500                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total     15230500                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data        43566                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total        43566                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data        31879                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total        31879                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SwapReq_accesses::cpu1.data           70                       # number of SwapReq accesses(hits+misses)
+system.cpu1.dcache.SwapReq_accesses::total           70                       # number of SwapReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data        75445                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total        75445                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data        75445                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total        75445                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.009067                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.009067                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.004203                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.004203                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SwapReq_miss_rate::cpu1.data     0.785714                       # miss rate for SwapReq accesses
+system.cpu1.dcache.SwapReq_miss_rate::total     0.785714                       # miss rate for SwapReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.007012                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.007012                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.007012                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.007012                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 30183.544304                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 30183.544304                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24686.567164                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 24686.567164                       # average WriteReq miss latency
+system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 23981.818182                       # average SwapReq miss latency
+system.cpu1.dcache.SwapReq_avg_miss_latency::total 23981.818182                       # average SwapReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 28791.115312                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 28791.115312                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 28791.115312                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 28791.115312                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -961,366 +961,366 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          266                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total          266                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data           47                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total           47                       # number of WriteReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data          313                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total          313                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data          313                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total          313                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data          159                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total          159                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data          107                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total          107                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data           52                       # number of SwapReq MSHR misses
-system.cpu1.dcache.SwapReq_mshr_misses::total           52                       # number of SwapReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          229                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total          229                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data           34                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total           34                       # number of WriteReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data          263                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total          263                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data          263                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total          263                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data          166                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total          166                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data          100                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total          100                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data           55                       # number of SwapReq MSHR misses
+system.cpu1.dcache.SwapReq_mshr_misses::total           55                       # number of SwapReq MSHR misses
 system.cpu1.dcache.demand_mshr_misses::cpu1.data          266                       # number of demand (read+write) MSHR misses
 system.cpu1.dcache.demand_mshr_misses::total          266                       # number of demand (read+write) MSHR misses
 system.cpu1.dcache.overall_mshr_misses::cpu1.data          266                       # number of overall MSHR misses
 system.cpu1.dcache.overall_mshr_misses::total          266                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data      2405000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total      2405000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data      1693500                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total      1693500                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data      1063000                       # number of SwapReq MSHR miss cycles
-system.cpu1.dcache.SwapReq_mshr_miss_latency::total      1063000                       # number of SwapReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data      4098500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total      4098500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data      4098500                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total      4098500                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.003530                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.003530                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.003166                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.003166                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data     0.764706                       # mshr miss rate for SwapReq accesses
-system.cpu1.dcache.SwapReq_mshr_miss_rate::total     0.764706                       # mshr miss rate for SwapReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.003374                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.003374                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.003374                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.003374                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15125.786164                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15125.786164                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15827.102804                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15827.102804                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 20442.307692                       # average SwapReq mshr miss latency
-system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 20442.307692                       # average SwapReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15407.894737                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15407.894737                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15407.894737                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15407.894737                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data      3273504                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total      3273504                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data      1639000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total      1639000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data      1148500                       # number of SwapReq MSHR miss cycles
+system.cpu1.dcache.SwapReq_mshr_miss_latency::total      1148500                       # number of SwapReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data      4912504                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total      4912504                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data      4912504                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total      4912504                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.003810                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.003810                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.003137                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.003137                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data     0.785714                       # mshr miss rate for SwapReq accesses
+system.cpu1.dcache.SwapReq_mshr_miss_rate::total     0.785714                       # mshr miss rate for SwapReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.003526                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.003526                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.003526                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.003526                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 19719.903614                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 19719.903614                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data        16390                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total        16390                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 20881.818182                       # average SwapReq mshr miss latency
+system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 20881.818182                       # average SwapReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18468.060150                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18468.060150                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18468.060150                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18468.060150                       # average overall mshr miss latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu2.numCycles                          187552                       # number of cpu cycles simulated
+system.cpu2.numCycles                          191032                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.BPredUnit.lookups                   49236                       # Number of BP lookups
-system.cpu2.BPredUnit.condPredicted             46105                       # Number of conditional branches predicted
-system.cpu2.BPredUnit.condIncorrect              1532                       # Number of conditional branches incorrect
-system.cpu2.BPredUnit.BTBLookups                42466                       # Number of BTB lookups
-system.cpu2.BPredUnit.BTBHits                   41429                       # Number of BTB hits
+system.cpu2.BPredUnit.lookups                   57390                       # Number of BP lookups
+system.cpu2.BPredUnit.condPredicted             54193                       # Number of conditional branches predicted
+system.cpu2.BPredUnit.condIncorrect              1550                       # Number of conditional branches incorrect
+system.cpu2.BPredUnit.BTBLookups                50681                       # Number of BTB lookups
+system.cpu2.BPredUnit.BTBHits                   49645                       # Number of BTB hits
 system.cpu2.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.BPredUnit.usedRAS                     825                       # Number of times the RAS was used to get a target.
+system.cpu2.BPredUnit.usedRAS                     804                       # Number of times the RAS was used to get a target.
 system.cpu2.BPredUnit.RASInCorrect                232                       # Number of incorrect RAS predictions.
-system.cpu2.fetch.icacheStallCycles             33274                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts                        268508                       # Number of instructions fetch has processed
-system.cpu2.fetch.Branches                      49236                       # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches             42254                       # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles                        98143                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles                   4464                       # Number of cycles fetch has spent squashing
-system.cpu2.fetch.BlockedCycles                 42536                       # Number of cycles fetch has spent blocked
+system.cpu2.fetch.icacheStallCycles             29539                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts                        321276                       # Number of instructions fetch has processed
+system.cpu2.fetch.Branches                      57390                       # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches             50449                       # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles                       112230                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles                   4473                       # Number of cycles fetch has spent squashing
+system.cpu2.fetch.BlockedCycles                 35583                       # Number of cycles fetch has spent blocked
 system.cpu2.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.NoActiveThreadStallCycles         6571                       # Number of stall cycles due to no active thread to fetch from
-system.cpu2.fetch.PendingTrapStallCycles         1082                       # Number of stall cycles due to pending traps
-system.cpu2.fetch.CacheLines                    24716                       # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes                  294                       # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.rateDist::samples            184466                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean             1.455596                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev            2.059567                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.NoActiveThreadStallCycles         6761                       # Number of stall cycles due to no active thread to fetch from
+system.cpu2.fetch.PendingTrapStallCycles         1077                       # Number of stall cycles due to pending traps
+system.cpu2.fetch.CacheLines                    20533                       # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes                  334                       # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.rateDist::samples            188044                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean             1.708515                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev            2.158633                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0                   86323     46.80%     46.80% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1                   50944     27.62%     74.41% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2                    8337      4.52%     78.93% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3                    3301      1.79%     80.72% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4                     755      0.41%     81.13% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5                   29086     15.77%     96.90% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6                    1170      0.63%     97.53% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7                     883      0.48%     98.01% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8                    3667      1.99%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0                   75814     40.32%     40.32% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1                   56962     30.29%     70.61% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2                    6138      3.26%     73.87% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3                    3348      1.78%     75.65% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4                     769      0.41%     76.06% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5                   39287     20.89%     96.95% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6                    1207      0.64%     97.60% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7                     911      0.48%     98.08% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8                    3608      1.92%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total              184466                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate                 0.262519                       # Number of branch fetches per cycle
-system.cpu2.fetch.rate                       1.431646                       # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles                   41063                       # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles                36807                       # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles                    89946                       # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles                 7224                       # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles                  2855                       # Number of cycles decode is squashing
-system.cpu2.decode.DecodedInsts                264281                       # Number of instructions handled by decode
-system.cpu2.rename.SquashCycles                  2855                       # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles                   41843                       # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles                  22202                       # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles         13743                       # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles                    82992                       # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles                14260                       # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts                261668                       # Number of instructions processed by rename
-system.cpu2.rename.IQFullEvents                    19                       # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LSQFullEvents                   57                       # Number of times rename has blocked due to LSQ full
-system.cpu2.rename.RenamedOperands             181221                       # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups               490993                       # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups          490993                       # Number of integer rename lookups
-system.cpu2.rename.CommittedMaps               165322                       # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps                   15899                       # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts              1233                       # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts          1350                       # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts                    17036                       # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads               71489                       # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores              32632                       # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads            34884                       # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores           27362                       # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded                    213682                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded               8649                       # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued                   217360                       # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued               54                       # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined          13263                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined        11908                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved           765                       # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples       184466                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean        1.178320                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev       1.292872                       # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total              188044                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate                 0.300421                       # Number of branch fetches per cycle
+system.cpu2.fetch.rate                       1.681792                       # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles                   35225                       # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles                31967                       # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles                   106013                       # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles                 5229                       # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles                  2849                       # Number of cycles decode is squashing
+system.cpu2.decode.DecodedInsts                316907                       # Number of instructions handled by decode
+system.cpu2.rename.SquashCycles                  2849                       # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles                   36004                       # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles                  16323                       # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles         14784                       # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles                   101094                       # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles                10229                       # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts                314547                       # Number of instructions processed by rename
+system.cpu2.rename.IQFullEvents                    23                       # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LSQFullEvents                   56                       # Number of times rename has blocked due to LSQ full
+system.cpu2.rename.RenamedOperands             220052                       # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups               605102                       # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups          605102                       # Number of integer rename lookups
+system.cpu2.rename.CommittedMaps               204228                       # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps                   15824                       # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts              1236                       # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts          1356                       # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts                    12873                       # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads               89800                       # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores              42907                       # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads            42940                       # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores           37601                       # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded                    260749                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded               6485                       # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued                   262481                       # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued              146                       # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined          13131                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined        11780                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved           687                       # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples       188044                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean        1.395849                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev       1.314415                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0              84063     45.57%     45.57% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1              29277     15.87%     61.44% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2              32764     17.76%     79.20% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3              33297     18.05%     97.25% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4               3312      1.80%     99.05% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5               1277      0.69%     99.74% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6                362      0.20%     99.94% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7                 53      0.03%     99.97% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8                 61      0.03%    100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0              73292     38.98%     38.98% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1              23055     12.26%     51.24% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2              43065     22.90%     74.14% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3              43582     23.18%     97.31% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4               3340      1.78%     99.09% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5               1248      0.66%     99.75% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6                346      0.18%     99.94% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7                 54      0.03%     99.97% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8                 62      0.03%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total         184466                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total         188044                       # Number of insts issued each cycle
 system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu                     20      6.64%      6.64% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult                     0      0.00%      6.64% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv                      0      0.00%      6.64% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd                    0      0.00%      6.64% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp                    0      0.00%      6.64% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt                    0      0.00%      6.64% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult                   0      0.00%      6.64% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv                    0      0.00%      6.64% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%      6.64% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd                     0      0.00%      6.64% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%      6.64% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu                     0      0.00%      6.64% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp                     0      0.00%      6.64% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt                     0      0.00%      6.64% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc                    0      0.00%      6.64% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult                    0      0.00%      6.64% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%      6.64% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift                   0      0.00%      6.64% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%      6.64% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%      6.64% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%      6.64% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%      6.64% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%      6.64% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%      6.64% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%      6.64% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%      6.64% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%      6.64% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%      6.64% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%      6.64% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead                    71     23.59%     30.23% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite                  210     69.77%    100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu                     21      6.65%      6.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult                     0      0.00%      6.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv                      0      0.00%      6.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd                    0      0.00%      6.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp                    0      0.00%      6.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt                    0      0.00%      6.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult                   0      0.00%      6.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv                    0      0.00%      6.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%      6.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd                     0      0.00%      6.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%      6.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu                     0      0.00%      6.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp                     0      0.00%      6.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt                     0      0.00%      6.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc                    0      0.00%      6.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult                    0      0.00%      6.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%      6.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift                   0      0.00%      6.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%      6.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%      6.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%      6.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%      6.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%      6.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%      6.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%      6.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%      6.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%      6.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%      6.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%      6.65% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead                    85     26.90%     33.54% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite                  210     66.46%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu2.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu               107542     49.48%     49.48% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult                   0      0.00%     49.48% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     49.48% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     49.48% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     49.48% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     49.48% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     49.48% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     49.48% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     49.48% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     49.48% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     49.48% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     49.48% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     49.48% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     49.48% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     49.48% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     49.48% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     49.48% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     49.48% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     49.48% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     49.48% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     49.48% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     49.48% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     49.48% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     49.48% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     49.48% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     49.48% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     49.48% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     49.48% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     49.48% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead               77871     35.83%     85.30% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite              31947     14.70%    100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu               126143     48.06%     48.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult                   0      0.00%     48.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     48.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     48.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     48.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     48.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     48.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     48.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     48.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     48.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     48.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     48.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     48.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     48.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     48.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     48.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     48.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     48.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     48.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     48.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     48.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     48.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     48.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     48.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     48.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     48.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     48.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     48.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     48.06% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead               94161     35.87%     83.93% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite              42177     16.07%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total                217360                       # Type of FU issued
-system.cpu2.iq.rate                          1.158932                       # Inst issue rate
-system.cpu2.iq.fu_busy_cnt                        301                       # FU busy when requested
-system.cpu2.iq.fu_busy_rate                  0.001385                       # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads            619541                       # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes           235636                       # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses       215243                       # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.FU_type_0::total                262481                       # Type of FU issued
+system.cpu2.iq.rate                          1.374016                       # Inst issue rate
+system.cpu2.iq.fu_busy_cnt                        316                       # FU busy when requested
+system.cpu2.iq.fu_busy_rate                  0.001204                       # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads            713468                       # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes           280402                       # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses       260315                       # Number of integer instruction queue wakeup accesses
 system.cpu2.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
 system.cpu2.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
 system.cpu2.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses                217661                       # Number of integer alu accesses
+system.cpu2.iq.int_alu_accesses                262797                       # Number of integer alu accesses
 system.cpu2.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads           27206                       # Number of loads that had data forwarded from stores
+system.cpu2.iew.lsq.thread0.forwLoads           37443                       # Number of loads that had data forwarded from stores
 system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads         2801                       # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses            8                       # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation           42                       # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores         1615                       # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedLoads         2702                       # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses            6                       # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation           37                       # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores         1644                       # Number of stores squashed
 system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu2.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
 system.cpu2.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles                  2855                       # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles                   1726                       # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles                   52                       # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts             258195                       # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts              386                       # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts                71489                       # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts               32632                       # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts              1140                       # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents                    46                       # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewSquashCycles                  2849                       # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles                   1860                       # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles                   77                       # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts             311245                       # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts              407                       # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts                89800                       # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts               42907                       # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts              1163                       # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents                    74                       # Number of times the IQ has become full, causing a stall
 system.cpu2.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents            42                       # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect           513                       # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect         1199                       # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts                1712                       # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts               215982                       # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts                70400                       # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts             1378                       # Number of squashed instructions skipped in execute
+system.cpu2.iew.memOrderViolationEvents            37                       # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect           516                       # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect         1201                       # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts                1717                       # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts               261072                       # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts                88760                       # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts             1409                       # Number of squashed instructions skipped in execute
 system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu2.iew.exec_nop                        35864                       # number of nop insts executed
-system.cpu2.iew.exec_refs                      102255                       # number of memory reference insts executed
-system.cpu2.iew.exec_branches                   45260                       # Number of branches executed
-system.cpu2.iew.exec_stores                     31855                       # Number of stores executed
-system.cpu2.iew.exec_rate                    1.151585                       # Inst execution rate
-system.cpu2.iew.wb_sent                        215555                       # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count                       215243                       # cumulative count of insts written-back
-system.cpu2.iew.wb_producers                   119078                       # num instructions producing a value
-system.cpu2.iew.wb_consumers                   124002                       # num instructions consuming a value
+system.cpu2.iew.exec_nop                        44011                       # number of nop insts executed
+system.cpu2.iew.exec_refs                      130847                       # number of memory reference insts executed
+system.cpu2.iew.exec_branches                   53503                       # Number of branches executed
+system.cpu2.iew.exec_stores                     42087                       # Number of stores executed
+system.cpu2.iew.exec_rate                    1.366640                       # Inst execution rate
+system.cpu2.iew.wb_sent                        260613                       # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count                       260315                       # cumulative count of insts written-back
+system.cpu2.iew.wb_producers                   147697                       # num instructions producing a value
+system.cpu2.iew.wb_consumers                   152590                       # num instructions consuming a value
 system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate                      1.147644                       # insts written-back per cycle
-system.cpu2.iew.wb_fanout                    0.960291                       # average fanout of values written-back
+system.cpu2.iew.wb_rate                      1.362677                       # insts written-back per cycle
+system.cpu2.iew.wb_fanout                    0.967934                       # average fanout of values written-back
 system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitCommittedInsts        242999                       # The number of committed instructions
-system.cpu2.commit.commitCommittedOps          242999                       # The number of committed instructions
-system.cpu2.commit.commitSquashedInsts          15188                       # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls           7884                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts             1532                       # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples       175041                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean     1.388240                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev     1.921152                       # Number of insts commited each cycle
+system.cpu2.commit.commitCommittedInsts        296145                       # The number of committed instructions
+system.cpu2.commit.commitCommittedOps          296145                       # The number of committed instructions
+system.cpu2.commit.commitSquashedInsts          15092                       # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls           5798                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts             1550                       # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples       178435                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean     1.659680                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev     2.032759                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0        85384     48.78%     48.78% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1        43145     24.65%     73.43% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2         6226      3.56%     76.98% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3         8763      5.01%     81.99% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4         1523      0.87%     82.86% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5        27601     15.77%     98.63% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6          589      0.34%     98.97% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7          998      0.57%     99.54% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8          812      0.46%    100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0        72400     40.57%     40.57% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1        51371     28.79%     69.36% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2         6245      3.50%     72.86% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3         6660      3.73%     76.60% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4         1539      0.86%     77.46% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5        37793     21.18%     98.64% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6          621      0.35%     98.99% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7          991      0.56%     99.54% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8          815      0.46%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total       175041                       # Number of insts commited each cycle
-system.cpu2.commit.committedInsts              242999                       # Number of instructions committed
-system.cpu2.commit.committedOps                242999                       # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total       178435                       # Number of insts commited each cycle
+system.cpu2.commit.committedInsts              296145                       # Number of instructions committed
+system.cpu2.commit.committedOps                296145                       # Number of ops (including micro ops) committed
 system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu2.commit.refs                         99705                       # Number of memory references committed
-system.cpu2.commit.loads                        68688                       # Number of loads committed
-system.cpu2.commit.membars                       7170                       # Number of memory barriers committed
-system.cpu2.commit.branches                     44148                       # Number of branches committed
+system.cpu2.commit.refs                        128361                       # Number of memory references committed
+system.cpu2.commit.loads                        87098                       # Number of loads committed
+system.cpu2.commit.membars                       5084                       # Number of memory barriers committed
+system.cpu2.commit.branches                     52312                       # Number of branches committed
 system.cpu2.commit.fp_insts                         0                       # Number of committed floating point instructions.
-system.cpu2.commit.int_insts                   165976                       # Number of committed integer instructions.
+system.cpu2.commit.int_insts                   202794                       # Number of committed integer instructions.
 system.cpu2.commit.function_calls                 322                       # Number of function calls committed.
-system.cpu2.commit.bw_lim_events                  812                       # number cycles where commit BW limit reached
+system.cpu2.commit.bw_lim_events                  815                       # number cycles where commit BW limit reached
 system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu2.rob.rob_reads                      431829                       # The number of ROB reads
-system.cpu2.rob.rob_writes                     519243                       # The number of ROB writes
-system.cpu2.timesIdled                            226                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles                           3086                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles                       35636                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts                     200891                       # Number of Instructions Simulated
-system.cpu2.committedOps                       200891                       # Number of Ops (including micro ops) Simulated
-system.cpu2.committedInsts_total               200891                       # Number of Instructions Simulated
-system.cpu2.cpi                              0.933601                       # CPI: Cycles Per Instruction
-system.cpu2.cpi_total                        0.933601                       # CPI: Total CPI of All Threads
-system.cpu2.ipc                              1.071122                       # IPC: Instructions Per Cycle
-system.cpu2.ipc_total                        1.071122                       # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads                  366578                       # number of integer regfile reads
-system.cpu2.int_regfile_writes                 171642                       # number of integer regfile writes
+system.cpu2.rob.rob_reads                      488270                       # The number of ROB reads
+system.cpu2.rob.rob_writes                     625337                       # The number of ROB writes
+system.cpu2.timesIdled                            230                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles                           2988                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles                       36850                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts                     247959                       # Number of Instructions Simulated
+system.cpu2.committedOps                       247959                       # Number of Ops (including micro ops) Simulated
+system.cpu2.committedInsts_total               247959                       # Number of Instructions Simulated
+system.cpu2.cpi                              0.770418                       # CPI: Cycles Per Instruction
+system.cpu2.cpi_total                        0.770418                       # CPI: Total CPI of All Threads
+system.cpu2.ipc                              1.297997                       # IPC: Instructions Per Cycle
+system.cpu2.ipc_total                        1.297997                       # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads                  452595                       # number of integer regfile reads
+system.cpu2.int_regfile_writes                 210629                       # number of integer regfile writes
 system.cpu2.fp_regfile_writes                      64                       # number of floating regfile writes
-system.cpu2.misc_regfile_reads                 103931                       # number of misc regfile reads
+system.cpu2.misc_regfile_reads                 132559                       # number of misc regfile reads
 system.cpu2.misc_regfile_writes                   646                       # number of misc regfile writes
-system.cpu2.icache.replacements                   324                       # number of replacements
-system.cpu2.icache.tagsinuse                83.306019                       # Cycle average of tags in use
-system.cpu2.icache.total_refs                   24210                       # Total number of references to valid blocks.
+system.cpu2.icache.replacements                   322                       # number of replacements
+system.cpu2.icache.tagsinuse                84.182173                       # Cycle average of tags in use
+system.cpu2.icache.total_refs                   20037                       # Total number of references to valid blocks.
 system.cpu2.icache.sampled_refs                   438                       # Sample count of references to valid blocks.
-system.cpu2.icache.avg_refs                 55.273973                       # Average number of references to valid blocks.
+system.cpu2.icache.avg_refs                 45.746575                       # Average number of references to valid blocks.
 system.cpu2.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu2.icache.occ_blocks::cpu2.inst    83.306019                       # Average occupied blocks per requestor
-system.cpu2.icache.occ_percent::cpu2.inst     0.162707                       # Average percentage of cache occupancy
-system.cpu2.icache.occ_percent::total        0.162707                       # Average percentage of cache occupancy
-system.cpu2.icache.ReadReq_hits::cpu2.inst        24210                       # number of ReadReq hits
-system.cpu2.icache.ReadReq_hits::total          24210                       # number of ReadReq hits
-system.cpu2.icache.demand_hits::cpu2.inst        24210                       # number of demand (read+write) hits
-system.cpu2.icache.demand_hits::total           24210                       # number of demand (read+write) hits
-system.cpu2.icache.overall_hits::cpu2.inst        24210                       # number of overall hits
-system.cpu2.icache.overall_hits::total          24210                       # number of overall hits
-system.cpu2.icache.ReadReq_misses::cpu2.inst          506                       # number of ReadReq misses
-system.cpu2.icache.ReadReq_misses::total          506                       # number of ReadReq misses
-system.cpu2.icache.demand_misses::cpu2.inst          506                       # number of demand (read+write) misses
-system.cpu2.icache.demand_misses::total           506                       # number of demand (read+write) misses
-system.cpu2.icache.overall_misses::cpu2.inst          506                       # number of overall misses
-system.cpu2.icache.overall_misses::total          506                       # number of overall misses
-system.cpu2.icache.ReadReq_miss_latency::cpu2.inst      7060500                       # number of ReadReq miss cycles
-system.cpu2.icache.ReadReq_miss_latency::total      7060500                       # number of ReadReq miss cycles
-system.cpu2.icache.demand_miss_latency::cpu2.inst      7060500                       # number of demand (read+write) miss cycles
-system.cpu2.icache.demand_miss_latency::total      7060500                       # number of demand (read+write) miss cycles
-system.cpu2.icache.overall_miss_latency::cpu2.inst      7060500                       # number of overall miss cycles
-system.cpu2.icache.overall_miss_latency::total      7060500                       # number of overall miss cycles
-system.cpu2.icache.ReadReq_accesses::cpu2.inst        24716                       # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.ReadReq_accesses::total        24716                       # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.demand_accesses::cpu2.inst        24716                       # number of demand (read+write) accesses
-system.cpu2.icache.demand_accesses::total        24716                       # number of demand (read+write) accesses
-system.cpu2.icache.overall_accesses::cpu2.inst        24716                       # number of overall (read+write) accesses
-system.cpu2.icache.overall_accesses::total        24716                       # number of overall (read+write) accesses
-system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.020473                       # miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_miss_rate::total     0.020473                       # miss rate for ReadReq accesses
-system.cpu2.icache.demand_miss_rate::cpu2.inst     0.020473                       # miss rate for demand accesses
-system.cpu2.icache.demand_miss_rate::total     0.020473                       # miss rate for demand accesses
-system.cpu2.icache.overall_miss_rate::cpu2.inst     0.020473                       # miss rate for overall accesses
-system.cpu2.icache.overall_miss_rate::total     0.020473                       # miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13953.557312                       # average ReadReq miss latency
-system.cpu2.icache.ReadReq_avg_miss_latency::total 13953.557312                       # average ReadReq miss latency
-system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13953.557312                       # average overall miss latency
-system.cpu2.icache.demand_avg_miss_latency::total 13953.557312                       # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13953.557312                       # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency::total 13953.557312                       # average overall miss latency
+system.cpu2.icache.occ_blocks::cpu2.inst    84.182173                       # Average occupied blocks per requestor
+system.cpu2.icache.occ_percent::cpu2.inst     0.164418                       # Average percentage of cache occupancy
+system.cpu2.icache.occ_percent::total        0.164418                       # Average percentage of cache occupancy
+system.cpu2.icache.ReadReq_hits::cpu2.inst        20037                       # number of ReadReq hits
+system.cpu2.icache.ReadReq_hits::total          20037                       # number of ReadReq hits
+system.cpu2.icache.demand_hits::cpu2.inst        20037                       # number of demand (read+write) hits
+system.cpu2.icache.demand_hits::total           20037                       # number of demand (read+write) hits
+system.cpu2.icache.overall_hits::cpu2.inst        20037                       # number of overall hits
+system.cpu2.icache.overall_hits::total          20037                       # number of overall hits
+system.cpu2.icache.ReadReq_misses::cpu2.inst          496                       # number of ReadReq misses
+system.cpu2.icache.ReadReq_misses::total          496                       # number of ReadReq misses
+system.cpu2.icache.demand_misses::cpu2.inst          496                       # number of demand (read+write) misses
+system.cpu2.icache.demand_misses::total           496                       # number of demand (read+write) misses
+system.cpu2.icache.overall_misses::cpu2.inst          496                       # number of overall misses
+system.cpu2.icache.overall_misses::total          496                       # number of overall misses
+system.cpu2.icache.ReadReq_miss_latency::cpu2.inst      7608500                       # number of ReadReq miss cycles
+system.cpu2.icache.ReadReq_miss_latency::total      7608500                       # number of ReadReq miss cycles
+system.cpu2.icache.demand_miss_latency::cpu2.inst      7608500                       # number of demand (read+write) miss cycles
+system.cpu2.icache.demand_miss_latency::total      7608500                       # number of demand (read+write) miss cycles
+system.cpu2.icache.overall_miss_latency::cpu2.inst      7608500                       # number of overall miss cycles
+system.cpu2.icache.overall_miss_latency::total      7608500                       # number of overall miss cycles
+system.cpu2.icache.ReadReq_accesses::cpu2.inst        20533                       # number of ReadReq accesses(hits+misses)
+system.cpu2.icache.ReadReq_accesses::total        20533                       # number of ReadReq accesses(hits+misses)
+system.cpu2.icache.demand_accesses::cpu2.inst        20533                       # number of demand (read+write) accesses
+system.cpu2.icache.demand_accesses::total        20533                       # number of demand (read+write) accesses
+system.cpu2.icache.overall_accesses::cpu2.inst        20533                       # number of overall (read+write) accesses
+system.cpu2.icache.overall_accesses::total        20533                       # number of overall (read+write) accesses
+system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.024156                       # miss rate for ReadReq accesses
+system.cpu2.icache.ReadReq_miss_rate::total     0.024156                       # miss rate for ReadReq accesses
+system.cpu2.icache.demand_miss_rate::cpu2.inst     0.024156                       # miss rate for demand accesses
+system.cpu2.icache.demand_miss_rate::total     0.024156                       # miss rate for demand accesses
+system.cpu2.icache.overall_miss_rate::cpu2.inst     0.024156                       # miss rate for overall accesses
+system.cpu2.icache.overall_miss_rate::total     0.024156                       # miss rate for overall accesses
+system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15339.717742                       # average ReadReq miss latency
+system.cpu2.icache.ReadReq_avg_miss_latency::total 15339.717742                       # average ReadReq miss latency
+system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15339.717742                       # average overall miss latency
+system.cpu2.icache.demand_avg_miss_latency::total 15339.717742                       # average overall miss latency
+system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15339.717742                       # average overall miss latency
+system.cpu2.icache.overall_avg_miss_latency::total 15339.717742                       # average overall miss latency
 system.cpu2.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu2.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1329,106 +1329,106 @@ system.cpu2.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu2.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu2.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst           68                       # number of ReadReq MSHR hits
-system.cpu2.icache.ReadReq_mshr_hits::total           68                       # number of ReadReq MSHR hits
-system.cpu2.icache.demand_mshr_hits::cpu2.inst           68                       # number of demand (read+write) MSHR hits
-system.cpu2.icache.demand_mshr_hits::total           68                       # number of demand (read+write) MSHR hits
-system.cpu2.icache.overall_mshr_hits::cpu2.inst           68                       # number of overall MSHR hits
-system.cpu2.icache.overall_mshr_hits::total           68                       # number of overall MSHR hits
+system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst           58                       # number of ReadReq MSHR hits
+system.cpu2.icache.ReadReq_mshr_hits::total           58                       # number of ReadReq MSHR hits
+system.cpu2.icache.demand_mshr_hits::cpu2.inst           58                       # number of demand (read+write) MSHR hits
+system.cpu2.icache.demand_mshr_hits::total           58                       # number of demand (read+write) MSHR hits
+system.cpu2.icache.overall_mshr_hits::cpu2.inst           58                       # number of overall MSHR hits
+system.cpu2.icache.overall_mshr_hits::total           58                       # number of overall MSHR hits
 system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst          438                       # number of ReadReq MSHR misses
 system.cpu2.icache.ReadReq_mshr_misses::total          438                       # number of ReadReq MSHR misses
 system.cpu2.icache.demand_mshr_misses::cpu2.inst          438                       # number of demand (read+write) MSHR misses
 system.cpu2.icache.demand_mshr_misses::total          438                       # number of demand (read+write) MSHR misses
 system.cpu2.icache.overall_mshr_misses::cpu2.inst          438                       # number of overall MSHR misses
 system.cpu2.icache.overall_mshr_misses::total          438                       # number of overall MSHR misses
-system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst      5136000                       # number of ReadReq MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_latency::total      5136000                       # number of ReadReq MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst      5136000                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency::total      5136000                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst      5136000                       # number of overall MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::total      5136000                       # number of overall MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.017721                       # mshr miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_mshr_miss_rate::total     0.017721                       # mshr miss rate for ReadReq accesses
-system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst     0.017721                       # mshr miss rate for demand accesses
-system.cpu2.icache.demand_mshr_miss_rate::total     0.017721                       # mshr miss rate for demand accesses
-system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst     0.017721                       # mshr miss rate for overall accesses
-system.cpu2.icache.overall_mshr_miss_rate::total     0.017721                       # mshr miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11726.027397                       # average ReadReq mshr miss latency
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 11726.027397                       # average ReadReq mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 11726.027397                       # average overall mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::total 11726.027397                       # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 11726.027397                       # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::total 11726.027397                       # average overall mshr miss latency
+system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst      5673500                       # number of ReadReq MSHR miss cycles
+system.cpu2.icache.ReadReq_mshr_miss_latency::total      5673500                       # number of ReadReq MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst      5673500                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_latency::total      5673500                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst      5673500                       # number of overall MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_latency::total      5673500                       # number of overall MSHR miss cycles
+system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.021332                       # mshr miss rate for ReadReq accesses
+system.cpu2.icache.ReadReq_mshr_miss_rate::total     0.021332                       # mshr miss rate for ReadReq accesses
+system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst     0.021332                       # mshr miss rate for demand accesses
+system.cpu2.icache.demand_mshr_miss_rate::total     0.021332                       # mshr miss rate for demand accesses
+system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst     0.021332                       # mshr miss rate for overall accesses
+system.cpu2.icache.overall_mshr_miss_rate::total     0.021332                       # mshr miss rate for overall accesses
+system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12953.196347                       # average ReadReq mshr miss latency
+system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12953.196347                       # average ReadReq mshr miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12953.196347                       # average overall mshr miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency::total 12953.196347                       # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12953.196347                       # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency::total 12953.196347                       # average overall mshr miss latency
 system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu2.dcache.replacements                     0                       # number of replacements
-system.cpu2.dcache.tagsinuse                24.973314                       # Cycle average of tags in use
-system.cpu2.dcache.total_refs                   37203                       # Total number of references to valid blocks.
+system.cpu2.dcache.tagsinuse                24.868946                       # Cycle average of tags in use
+system.cpu2.dcache.total_refs                   47444                       # Total number of references to valid blocks.
 system.cpu2.dcache.sampled_refs                    28                       # Sample count of references to valid blocks.
-system.cpu2.dcache.avg_refs               1328.678571                       # Average number of references to valid blocks.
+system.cpu2.dcache.avg_refs               1694.428571                       # Average number of references to valid blocks.
 system.cpu2.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu2.dcache.occ_blocks::cpu2.data    24.973314                       # Average occupied blocks per requestor
-system.cpu2.dcache.occ_percent::cpu2.data     0.048776                       # Average percentage of cache occupancy
-system.cpu2.dcache.occ_percent::total        0.048776                       # Average percentage of cache occupancy
-system.cpu2.dcache.ReadReq_hits::cpu2.data        42731                       # number of ReadReq hits
-system.cpu2.dcache.ReadReq_hits::total          42731                       # number of ReadReq hits
-system.cpu2.dcache.WriteReq_hits::cpu2.data        30798                       # number of WriteReq hits
-system.cpu2.dcache.WriteReq_hits::total         30798                       # number of WriteReq hits
-system.cpu2.dcache.SwapReq_hits::cpu2.data           14                       # number of SwapReq hits
-system.cpu2.dcache.SwapReq_hits::total             14                       # number of SwapReq hits
-system.cpu2.dcache.demand_hits::cpu2.data        73529                       # number of demand (read+write) hits
-system.cpu2.dcache.demand_hits::total           73529                       # number of demand (read+write) hits
-system.cpu2.dcache.overall_hits::cpu2.data        73529                       # number of overall hits
-system.cpu2.dcache.overall_hits::total          73529                       # number of overall hits
-system.cpu2.dcache.ReadReq_misses::cpu2.data          443                       # number of ReadReq misses
-system.cpu2.dcache.ReadReq_misses::total          443                       # number of ReadReq misses
-system.cpu2.dcache.WriteReq_misses::cpu2.data          151                       # number of WriteReq misses
-system.cpu2.dcache.WriteReq_misses::total          151                       # number of WriteReq misses
-system.cpu2.dcache.SwapReq_misses::cpu2.data           54                       # number of SwapReq misses
-system.cpu2.dcache.SwapReq_misses::total           54                       # number of SwapReq misses
-system.cpu2.dcache.demand_misses::cpu2.data          594                       # number of demand (read+write) misses
-system.cpu2.dcache.demand_misses::total           594                       # number of demand (read+write) misses
-system.cpu2.dcache.overall_misses::cpu2.data          594                       # number of overall misses
-system.cpu2.dcache.overall_misses::total          594                       # number of overall misses
-system.cpu2.dcache.ReadReq_miss_latency::cpu2.data      9862000                       # number of ReadReq miss cycles
-system.cpu2.dcache.ReadReq_miss_latency::total      9862000                       # number of ReadReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency::cpu2.data      2806000                       # number of WriteReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency::total      2806000                       # number of WriteReq miss cycles
-system.cpu2.dcache.SwapReq_miss_latency::cpu2.data      1173500                       # number of SwapReq miss cycles
-system.cpu2.dcache.SwapReq_miss_latency::total      1173500                       # number of SwapReq miss cycles
-system.cpu2.dcache.demand_miss_latency::cpu2.data     12668000                       # number of demand (read+write) miss cycles
-system.cpu2.dcache.demand_miss_latency::total     12668000                       # number of demand (read+write) miss cycles
-system.cpu2.dcache.overall_miss_latency::cpu2.data     12668000                       # number of overall miss cycles
-system.cpu2.dcache.overall_miss_latency::total     12668000                       # number of overall miss cycles
-system.cpu2.dcache.ReadReq_accesses::cpu2.data        43174                       # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.ReadReq_accesses::total        43174                       # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::cpu2.data        30949                       # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::total        30949                       # number of WriteReq accesses(hits+misses)
+system.cpu2.dcache.occ_blocks::cpu2.data    24.868946                       # Average occupied blocks per requestor
+system.cpu2.dcache.occ_percent::cpu2.data     0.048572                       # Average percentage of cache occupancy
+system.cpu2.dcache.occ_percent::total        0.048572                       # Average percentage of cache occupancy
+system.cpu2.dcache.ReadReq_hits::cpu2.data        50906                       # number of ReadReq hits
+system.cpu2.dcache.ReadReq_hits::total          50906                       # number of ReadReq hits
+system.cpu2.dcache.WriteReq_hits::cpu2.data        41055                       # number of WriteReq hits
+system.cpu2.dcache.WriteReq_hits::total         41055                       # number of WriteReq hits
+system.cpu2.dcache.SwapReq_hits::cpu2.data           12                       # number of SwapReq hits
+system.cpu2.dcache.SwapReq_hits::total             12                       # number of SwapReq hits
+system.cpu2.dcache.demand_hits::cpu2.data        91961                       # number of demand (read+write) hits
+system.cpu2.dcache.demand_hits::total           91961                       # number of demand (read+write) hits
+system.cpu2.dcache.overall_hits::cpu2.data        91961                       # number of overall hits
+system.cpu2.dcache.overall_hits::total          91961                       # number of overall hits
+system.cpu2.dcache.ReadReq_misses::cpu2.data          392                       # number of ReadReq misses
+system.cpu2.dcache.ReadReq_misses::total          392                       # number of ReadReq misses
+system.cpu2.dcache.WriteReq_misses::cpu2.data          140                       # number of WriteReq misses
+system.cpu2.dcache.WriteReq_misses::total          140                       # number of WriteReq misses
+system.cpu2.dcache.SwapReq_misses::cpu2.data           56                       # number of SwapReq misses
+system.cpu2.dcache.SwapReq_misses::total           56                       # number of SwapReq misses
+system.cpu2.dcache.demand_misses::cpu2.data          532                       # number of demand (read+write) misses
+system.cpu2.dcache.demand_misses::total           532                       # number of demand (read+write) misses
+system.cpu2.dcache.overall_misses::cpu2.data          532                       # number of overall misses
+system.cpu2.dcache.overall_misses::total          532                       # number of overall misses
+system.cpu2.dcache.ReadReq_miss_latency::cpu2.data     10132000                       # number of ReadReq miss cycles
+system.cpu2.dcache.ReadReq_miss_latency::total     10132000                       # number of ReadReq miss cycles
+system.cpu2.dcache.WriteReq_miss_latency::cpu2.data      3391500                       # number of WriteReq miss cycles
+system.cpu2.dcache.WriteReq_miss_latency::total      3391500                       # number of WriteReq miss cycles
+system.cpu2.dcache.SwapReq_miss_latency::cpu2.data      1227500                       # number of SwapReq miss cycles
+system.cpu2.dcache.SwapReq_miss_latency::total      1227500                       # number of SwapReq miss cycles
+system.cpu2.dcache.demand_miss_latency::cpu2.data     13523500                       # number of demand (read+write) miss cycles
+system.cpu2.dcache.demand_miss_latency::total     13523500                       # number of demand (read+write) miss cycles
+system.cpu2.dcache.overall_miss_latency::cpu2.data     13523500                       # number of overall miss cycles
+system.cpu2.dcache.overall_miss_latency::total     13523500                       # number of overall miss cycles
+system.cpu2.dcache.ReadReq_accesses::cpu2.data        51298                       # number of ReadReq accesses(hits+misses)
+system.cpu2.dcache.ReadReq_accesses::total        51298                       # number of ReadReq accesses(hits+misses)
+system.cpu2.dcache.WriteReq_accesses::cpu2.data        41195                       # number of WriteReq accesses(hits+misses)
+system.cpu2.dcache.WriteReq_accesses::total        41195                       # number of WriteReq accesses(hits+misses)
 system.cpu2.dcache.SwapReq_accesses::cpu2.data           68                       # number of SwapReq accesses(hits+misses)
 system.cpu2.dcache.SwapReq_accesses::total           68                       # number of SwapReq accesses(hits+misses)
-system.cpu2.dcache.demand_accesses::cpu2.data        74123                       # number of demand (read+write) accesses
-system.cpu2.dcache.demand_accesses::total        74123                       # number of demand (read+write) accesses
-system.cpu2.dcache.overall_accesses::cpu2.data        74123                       # number of overall (read+write) accesses
-system.cpu2.dcache.overall_accesses::total        74123                       # number of overall (read+write) accesses
-system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.010261                       # miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_miss_rate::total     0.010261                       # miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.004879                       # miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::total     0.004879                       # miss rate for WriteReq accesses
-system.cpu2.dcache.SwapReq_miss_rate::cpu2.data     0.794118                       # miss rate for SwapReq accesses
-system.cpu2.dcache.SwapReq_miss_rate::total     0.794118                       # miss rate for SwapReq accesses
-system.cpu2.dcache.demand_miss_rate::cpu2.data     0.008014                       # miss rate for demand accesses
-system.cpu2.dcache.demand_miss_rate::total     0.008014                       # miss rate for demand accesses
-system.cpu2.dcache.overall_miss_rate::cpu2.data     0.008014                       # miss rate for overall accesses
-system.cpu2.dcache.overall_miss_rate::total     0.008014                       # miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 22261.851016                       # average ReadReq miss latency
-system.cpu2.dcache.ReadReq_avg_miss_latency::total 22261.851016                       # average ReadReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 18582.781457                       # average WriteReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency::total 18582.781457                       # average WriteReq miss latency
-system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 21731.481481                       # average SwapReq miss latency
-system.cpu2.dcache.SwapReq_avg_miss_latency::total 21731.481481                       # average SwapReq miss latency
-system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 21326.599327                       # average overall miss latency
-system.cpu2.dcache.demand_avg_miss_latency::total 21326.599327                       # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 21326.599327                       # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::total 21326.599327                       # average overall miss latency
+system.cpu2.dcache.demand_accesses::cpu2.data        92493                       # number of demand (read+write) accesses
+system.cpu2.dcache.demand_accesses::total        92493                       # number of demand (read+write) accesses
+system.cpu2.dcache.overall_accesses::cpu2.data        92493                       # number of overall (read+write) accesses
+system.cpu2.dcache.overall_accesses::total        92493                       # number of overall (read+write) accesses
+system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.007642                       # miss rate for ReadReq accesses
+system.cpu2.dcache.ReadReq_miss_rate::total     0.007642                       # miss rate for ReadReq accesses
+system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.003398                       # miss rate for WriteReq accesses
+system.cpu2.dcache.WriteReq_miss_rate::total     0.003398                       # miss rate for WriteReq accesses
+system.cpu2.dcache.SwapReq_miss_rate::cpu2.data     0.823529                       # miss rate for SwapReq accesses
+system.cpu2.dcache.SwapReq_miss_rate::total     0.823529                       # miss rate for SwapReq accesses
+system.cpu2.dcache.demand_miss_rate::cpu2.data     0.005752                       # miss rate for demand accesses
+system.cpu2.dcache.demand_miss_rate::total     0.005752                       # miss rate for demand accesses
+system.cpu2.dcache.overall_miss_rate::cpu2.data     0.005752                       # miss rate for overall accesses
+system.cpu2.dcache.overall_miss_rate::total     0.005752                       # miss rate for overall accesses
+system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 25846.938776                       # average ReadReq miss latency
+system.cpu2.dcache.ReadReq_avg_miss_latency::total 25846.938776                       # average ReadReq miss latency
+system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data        24225                       # average WriteReq miss latency
+system.cpu2.dcache.WriteReq_avg_miss_latency::total        24225                       # average WriteReq miss latency
+system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 21919.642857                       # average SwapReq miss latency
+system.cpu2.dcache.SwapReq_avg_miss_latency::total 21919.642857                       # average SwapReq miss latency
+system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 25420.112782                       # average overall miss latency
+system.cpu2.dcache.demand_avg_miss_latency::total 25420.112782                       # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 25420.112782                       # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency::total 25420.112782                       # average overall miss latency
 system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1437,366 +1437,366 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu2.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu2.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data          279                       # number of ReadReq MSHR hits
-system.cpu2.dcache.ReadReq_mshr_hits::total          279                       # number of ReadReq MSHR hits
-system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data           47                       # number of WriteReq MSHR hits
-system.cpu2.dcache.WriteReq_mshr_hits::total           47                       # number of WriteReq MSHR hits
-system.cpu2.dcache.demand_mshr_hits::cpu2.data          326                       # number of demand (read+write) MSHR hits
-system.cpu2.dcache.demand_mshr_hits::total          326                       # number of demand (read+write) MSHR hits
-system.cpu2.dcache.overall_mshr_hits::cpu2.data          326                       # number of overall MSHR hits
-system.cpu2.dcache.overall_mshr_hits::total          326                       # number of overall MSHR hits
-system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data          164                       # number of ReadReq MSHR misses
-system.cpu2.dcache.ReadReq_mshr_misses::total          164                       # number of ReadReq MSHR misses
-system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data          104                       # number of WriteReq MSHR misses
-system.cpu2.dcache.WriteReq_mshr_misses::total          104                       # number of WriteReq MSHR misses
-system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data           54                       # number of SwapReq MSHR misses
-system.cpu2.dcache.SwapReq_mshr_misses::total           54                       # number of SwapReq MSHR misses
-system.cpu2.dcache.demand_mshr_misses::cpu2.data          268                       # number of demand (read+write) MSHR misses
-system.cpu2.dcache.demand_mshr_misses::total          268                       # number of demand (read+write) MSHR misses
-system.cpu2.dcache.overall_mshr_misses::cpu2.data          268                       # number of overall MSHR misses
-system.cpu2.dcache.overall_mshr_misses::total          268                       # number of overall MSHR misses
-system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data      2336000                       # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_latency::total      2336000                       # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data      1419000                       # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::total      1419000                       # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data      1011500                       # number of SwapReq MSHR miss cycles
-system.cpu2.dcache.SwapReq_mshr_miss_latency::total      1011500                       # number of SwapReq MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data      3755000                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::total      3755000                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data      3755000                       # number of overall MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::total      3755000                       # number of overall MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.003799                       # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_mshr_miss_rate::total     0.003799                       # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.003360                       # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate::total     0.003360                       # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data     0.794118                       # mshr miss rate for SwapReq accesses
-system.cpu2.dcache.SwapReq_mshr_miss_rate::total     0.794118                       # mshr miss rate for SwapReq accesses
-system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data     0.003616                       # mshr miss rate for demand accesses
-system.cpu2.dcache.demand_mshr_miss_rate::total     0.003616                       # mshr miss rate for demand accesses
-system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data     0.003616                       # mshr miss rate for overall accesses
-system.cpu2.dcache.overall_mshr_miss_rate::total     0.003616                       # mshr miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14243.902439                       # average ReadReq mshr miss latency
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 14243.902439                       # average ReadReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13644.230769                       # average WriteReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13644.230769                       # average WriteReq mshr miss latency
-system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 18731.481481                       # average SwapReq mshr miss latency
-system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 18731.481481                       # average SwapReq mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 14011.194030                       # average overall mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::total 14011.194030                       # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 14011.194030                       # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::total 14011.194030                       # average overall mshr miss latency
+system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data          241                       # number of ReadReq MSHR hits
+system.cpu2.dcache.ReadReq_mshr_hits::total          241                       # number of ReadReq MSHR hits
+system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data           35                       # number of WriteReq MSHR hits
+system.cpu2.dcache.WriteReq_mshr_hits::total           35                       # number of WriteReq MSHR hits
+system.cpu2.dcache.demand_mshr_hits::cpu2.data          276                       # number of demand (read+write) MSHR hits
+system.cpu2.dcache.demand_mshr_hits::total          276                       # number of demand (read+write) MSHR hits
+system.cpu2.dcache.overall_mshr_hits::cpu2.data          276                       # number of overall MSHR hits
+system.cpu2.dcache.overall_mshr_hits::total          276                       # number of overall MSHR hits
+system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data          151                       # number of ReadReq MSHR misses
+system.cpu2.dcache.ReadReq_mshr_misses::total          151                       # number of ReadReq MSHR misses
+system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data          105                       # number of WriteReq MSHR misses
+system.cpu2.dcache.WriteReq_mshr_misses::total          105                       # number of WriteReq MSHR misses
+system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data           56                       # number of SwapReq MSHR misses
+system.cpu2.dcache.SwapReq_mshr_misses::total           56                       # number of SwapReq MSHR misses
+system.cpu2.dcache.demand_mshr_misses::cpu2.data          256                       # number of demand (read+write) MSHR misses
+system.cpu2.dcache.demand_mshr_misses::total          256                       # number of demand (read+write) MSHR misses
+system.cpu2.dcache.overall_mshr_misses::cpu2.data          256                       # number of overall MSHR misses
+system.cpu2.dcache.overall_mshr_misses::total          256                       # number of overall MSHR misses
+system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data      2456507                       # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_latency::total      2456507                       # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data      1732500                       # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_latency::total      1732500                       # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data      1052000                       # number of SwapReq MSHR miss cycles
+system.cpu2.dcache.SwapReq_mshr_miss_latency::total      1052000                       # number of SwapReq MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data      4189007                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency::total      4189007                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data      4189007                       # number of overall MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::total      4189007                       # number of overall MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.002944                       # mshr miss rate for ReadReq accesses
+system.cpu2.dcache.ReadReq_mshr_miss_rate::total     0.002944                       # mshr miss rate for ReadReq accesses
+system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.002549                       # mshr miss rate for WriteReq accesses
+system.cpu2.dcache.WriteReq_mshr_miss_rate::total     0.002549                       # mshr miss rate for WriteReq accesses
+system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data     0.823529                       # mshr miss rate for SwapReq accesses
+system.cpu2.dcache.SwapReq_mshr_miss_rate::total     0.823529                       # mshr miss rate for SwapReq accesses
+system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data     0.002768                       # mshr miss rate for demand accesses
+system.cpu2.dcache.demand_mshr_miss_rate::total     0.002768                       # mshr miss rate for demand accesses
+system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data     0.002768                       # mshr miss rate for overall accesses
+system.cpu2.dcache.overall_mshr_miss_rate::total     0.002768                       # mshr miss rate for overall accesses
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16268.258278                       # average ReadReq mshr miss latency
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 16268.258278                       # average ReadReq mshr miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data        16500                       # average WriteReq mshr miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total        16500                       # average WriteReq mshr miss latency
+system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 18785.714286                       # average SwapReq mshr miss latency
+system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 18785.714286                       # average SwapReq mshr miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 16363.308594                       # average overall mshr miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency::total 16363.308594                       # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 16363.308594                       # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency::total 16363.308594                       # average overall mshr miss latency
 system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu3.numCycles                          187286                       # number of cpu cycles simulated
+system.cpu3.numCycles                          190752                       # number of cpu cycles simulated
 system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu3.BPredUnit.lookups                   59110                       # Number of BP lookups
-system.cpu3.BPredUnit.condPredicted             55955                       # Number of conditional branches predicted
-system.cpu3.BPredUnit.condIncorrect              1573                       # Number of conditional branches incorrect
-system.cpu3.BPredUnit.BTBLookups                52456                       # Number of BTB lookups
-system.cpu3.BPredUnit.BTBHits                   51388                       # Number of BTB hits
+system.cpu3.BPredUnit.lookups                   53643                       # Number of BP lookups
+system.cpu3.BPredUnit.condPredicted             50394                       # Number of conditional branches predicted
+system.cpu3.BPredUnit.condIncorrect              1547                       # Number of conditional branches incorrect
+system.cpu3.BPredUnit.BTBLookups                46912                       # Number of BTB lookups
+system.cpu3.BPredUnit.BTBHits                   45897                       # Number of BTB hits
 system.cpu3.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu3.BPredUnit.usedRAS                     831                       # Number of times the RAS was used to get a target.
+system.cpu3.BPredUnit.usedRAS                     838                       # Number of times the RAS was used to get a target.
 system.cpu3.BPredUnit.RASInCorrect                232                       # Number of incorrect RAS predictions.
-system.cpu3.fetch.icacheStallCycles             27555                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu3.fetch.Insts                        332776                       # Number of instructions fetch has processed
-system.cpu3.fetch.Branches                      59110                       # Number of branches that fetch encountered
-system.cpu3.fetch.predictedBranches             52219                       # Number of branches that fetch has predicted taken
-system.cpu3.fetch.Cycles                       115081                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu3.fetch.SquashCycles                   4575                       # Number of cycles fetch has spent squashing
-system.cpu3.fetch.BlockedCycles                 31846                       # Number of cycles fetch has spent blocked
+system.cpu3.fetch.icacheStallCycles             31381                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu3.fetch.Insts                        296607                       # Number of instructions fetch has processed
+system.cpu3.fetch.Branches                      53643                       # Number of branches that fetch encountered
+system.cpu3.fetch.predictedBranches             46735                       # Number of branches that fetch has predicted taken
+system.cpu3.fetch.Cycles                       105748                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu3.fetch.SquashCycles                   4379                       # Number of cycles fetch has spent squashing
+system.cpu3.fetch.BlockedCycles                 39758                       # Number of cycles fetch has spent blocked
 system.cpu3.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu3.fetch.NoActiveThreadStallCycles         6567                       # Number of stall cycles due to no active thread to fetch from
-system.cpu3.fetch.PendingTrapStallCycles         1060                       # Number of stall cycles due to pending traps
-system.cpu3.fetch.CacheLines                    19062                       # Number of cache lines fetched
-system.cpu3.fetch.IcacheSquashes                  312                       # Number of outstanding Icache misses that were squashed
-system.cpu3.fetch.rateDist::samples            185045                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::mean             1.798352                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::stdev            2.183167                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.NoActiveThreadStallCycles         6743                       # Number of stall cycles due to no active thread to fetch from
+system.cpu3.fetch.PendingTrapStallCycles         1058                       # Number of stall cycles due to pending traps
+system.cpu3.fetch.CacheLines                    22503                       # Number of cache lines fetched
+system.cpu3.fetch.IcacheSquashes                  317                       # Number of outstanding Icache misses that were squashed
+system.cpu3.fetch.rateDist::samples            187456                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::mean             1.582275                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::stdev            2.112091                       # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::0                   69964     37.81%     37.81% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::1                   58012     31.35%     69.16% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::2                    5498      2.97%     72.13% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::3                    3553      1.92%     74.05% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::4                     717      0.39%     74.44% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::5                   41629     22.50%     96.93% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::6                    1211      0.65%     97.59% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::7                     858      0.46%     98.05% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::8                    3603      1.95%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::0                   81708     43.59%     43.59% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::1                   54260     28.95%     72.53% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::2                    7170      3.82%     76.36% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::3                    3258      1.74%     78.10% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::4                     706      0.38%     78.47% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::5                   34710     18.52%     96.99% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::6                    1204      0.64%     97.63% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::7                     885      0.47%     98.10% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::8                    3555      1.90%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::total              185045                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.branchRate                 0.315614                       # Number of branch fetches per cycle
-system.cpu3.fetch.rate                       1.776833                       # Number of inst fetches per cycle
-system.cpu3.decode.IdleCycles                   32638                       # Number of cycles decode is idle
-system.cpu3.decode.BlockedCycles                28853                       # Number of cycles decode is blocked
-system.cpu3.decode.RunCycles                   109537                       # Number of cycles decode is running
-system.cpu3.decode.UnblockCycles                 4519                       # Number of cycles decode is unblocking
-system.cpu3.decode.SquashCycles                  2931                       # Number of cycles decode is squashing
-system.cpu3.decode.DecodedInsts                328437                       # Number of instructions handled by decode
-system.cpu3.rename.SquashCycles                  2931                       # Number of cycles rename is squashing
-system.cpu3.rename.IdleCycles                   33475                       # Number of cycles rename is idle
-system.cpu3.rename.BlockCycles                  14026                       # Number of cycles rename is blocking
-system.cpu3.rename.serializeStallCycles         13970                       # count of cycles rename stalled for serializing inst
-system.cpu3.rename.RunCycles                   105232                       # Number of cycles rename is running
-system.cpu3.rename.UnblockCycles                 8844                       # Number of cycles rename is unblocking
-system.cpu3.rename.RenamedInsts                325744                       # Number of instructions processed by rename
-system.cpu3.rename.IQFullEvents                    27                       # Number of times rename has blocked due to IQ full
-system.cpu3.rename.LSQFullEvents                   59                       # Number of times rename has blocked due to LSQ full
-system.cpu3.rename.RenamedOperands             228226                       # Number of destination operands rename has renamed
-system.cpu3.rename.RenameLookups               629601                       # Number of register rename lookups that rename has made
-system.cpu3.rename.int_rename_lookups          629601                       # Number of integer rename lookups
-system.cpu3.rename.CommittedMaps               212325                       # Number of HB maps that are committed
-system.cpu3.rename.UndoneMaps                   15901                       # Number of HB maps that are undone due to squashing
-system.cpu3.rename.serializingInsts              1261                       # count of serializing insts renamed
-system.cpu3.rename.tempSerializingInsts          1383                       # count of temporary serializing insts renamed
-system.cpu3.rename.skidInsts                    11670                       # count of insts added to the skid buffer
-system.cpu3.memDep0.insertedLoads               93735                       # Number of loads inserted to the mem dependence unit.
-system.cpu3.memDep0.insertedStores              45116                       # Number of stores inserted to the mem dependence unit.
-system.cpu3.memDep0.conflictingLoads            44692                       # Number of conflicting loads.
-system.cpu3.memDep0.conflictingStores           39822                       # Number of conflicting stores.
-system.cpu3.iq.iqInstsAdded                    270564                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu3.iq.iqNonSpecInstsAdded               6038                       # Number of non-speculative instructions added to the IQ
-system.cpu3.iq.iqInstsIssued                   271349                       # Number of instructions issued
+system.cpu3.fetch.rateDist::total              187456                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.branchRate                 0.281219                       # Number of branch fetches per cycle
+system.cpu3.fetch.rate                       1.554935                       # Number of inst fetches per cycle
+system.cpu3.decode.IdleCycles                   37941                       # Number of cycles decode is idle
+system.cpu3.decode.BlockedCycles                35250                       # Number of cycles decode is blocked
+system.cpu3.decode.RunCycles                    98653                       # Number of cycles decode is running
+system.cpu3.decode.UnblockCycles                 6106                       # Number of cycles decode is unblocking
+system.cpu3.decode.SquashCycles                  2763                       # Number of cycles decode is squashing
+system.cpu3.decode.DecodedInsts                292333                       # Number of instructions handled by decode
+system.cpu3.rename.SquashCycles                  2763                       # Number of cycles rename is squashing
+system.cpu3.rename.IdleCycles                   38724                       # Number of cycles rename is idle
+system.cpu3.rename.BlockCycles                  18900                       # Number of cycles rename is blocking
+system.cpu3.rename.serializeStallCycles         15518                       # count of cycles rename stalled for serializing inst
+system.cpu3.rename.RunCycles                    92845                       # Number of cycles rename is running
+system.cpu3.rename.UnblockCycles                11963                       # Number of cycles rename is unblocking
+system.cpu3.rename.RenamedInsts                289904                       # Number of instructions processed by rename
+system.cpu3.rename.IQFullEvents                     5                       # Number of times rename has blocked due to IQ full
+system.cpu3.rename.LSQFullEvents                   41                       # Number of times rename has blocked due to LSQ full
+system.cpu3.rename.RenamedOperands             201915                       # Number of destination operands rename has renamed
+system.cpu3.rename.RenameLookups               552179                       # Number of register rename lookups that rename has made
+system.cpu3.rename.int_rename_lookups          552179                       # Number of integer rename lookups
+system.cpu3.rename.CommittedMaps               186764                       # Number of HB maps that are committed
+system.cpu3.rename.UndoneMaps                   15151                       # Number of HB maps that are undone due to squashing
+system.cpu3.rename.serializingInsts              1285                       # count of serializing insts renamed
+system.cpu3.rename.tempSerializingInsts          1418                       # count of temporary serializing insts renamed
+system.cpu3.rename.skidInsts                    14719                       # count of insts added to the skid buffer
+system.cpu3.memDep0.insertedLoads               81367                       # Number of loads inserted to the mem dependence unit.
+system.cpu3.memDep0.insertedStores              38245                       # Number of stores inserted to the mem dependence unit.
+system.cpu3.memDep0.conflictingLoads            39205                       # Number of conflicting loads.
+system.cpu3.memDep0.conflictingStores           32957                       # Number of conflicting stores.
+system.cpu3.iq.iqInstsAdded                    238924                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu3.iq.iqNonSpecInstsAdded               7473                       # Number of non-speculative instructions added to the IQ
+system.cpu3.iq.iqInstsIssued                   241868                       # Number of instructions issued
 system.cpu3.iq.iqSquashedInstsIssued              117                       # Number of squashed instructions issued
-system.cpu3.iq.iqSquashedInstsExamined          13410                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu3.iq.iqSquashedOperandsExamined        12382                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu3.iq.iqSquashedNonSpecRemoved           838                       # Number of squashed non-spec instructions that were removed
-system.cpu3.iq.issued_per_cycle::samples       185045                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::mean        1.466395                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::stdev       1.313251                       # Number of insts issued each cycle
+system.cpu3.iq.iqSquashedInstsExamined          12521                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu3.iq.iqSquashedOperandsExamined        10991                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu3.iq.iqSquashedNonSpecRemoved           722                       # Number of squashed non-spec instructions that were removed
+system.cpu3.iq.issued_per_cycle::samples       187456                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::mean        1.290265                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::stdev       1.307286                       # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::0              67828     36.65%     36.65% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::1              21223     11.47%     48.12% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::2              45218     24.44%     72.56% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::3              45760     24.73%     97.29% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::4               3300      1.78%     99.07% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::5               1261      0.68%     99.75% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::6                341      0.18%     99.94% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::0              79218     42.26%     42.26% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::1              25849     13.79%     56.05% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::2              38415     20.49%     76.54% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::3              38999     20.80%     97.35% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::4               3297      1.76%     99.10% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::5               1241      0.66%     99.77% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::6                322      0.17%     99.94% # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::7                 53      0.03%     99.97% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::8                 61      0.03%    100.00% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::8                 62      0.03%    100.00% # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::total         185045                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::total         187456                       # Number of insts issued each cycle
 system.cpu3.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntAlu                     21      6.80%      6.80% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntMult                     0      0.00%      6.80% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntDiv                      0      0.00%      6.80% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatAdd                    0      0.00%      6.80% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCmp                    0      0.00%      6.80% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCvt                    0      0.00%      6.80% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatMult                   0      0.00%      6.80% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatDiv                    0      0.00%      6.80% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%      6.80% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAdd                     0      0.00%      6.80% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%      6.80% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAlu                     0      0.00%      6.80% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCmp                     0      0.00%      6.80% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCvt                     0      0.00%      6.80% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMisc                    0      0.00%      6.80% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMult                    0      0.00%      6.80% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%      6.80% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShift                   0      0.00%      6.80% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%      6.80% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%      6.80% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%      6.80% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%      6.80% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%      6.80% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%      6.80% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%      6.80% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%      6.80% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%      6.80% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%      6.80% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%      6.80% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemRead                    78     25.24%     32.04% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemWrite                  210     67.96%    100.00% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntAlu                     22      7.19%      7.19% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntMult                     0      0.00%      7.19% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntDiv                      0      0.00%      7.19% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatAdd                    0      0.00%      7.19% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCmp                    0      0.00%      7.19% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCvt                    0      0.00%      7.19% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatMult                   0      0.00%      7.19% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatDiv                    0      0.00%      7.19% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%      7.19% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAdd                     0      0.00%      7.19% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%      7.19% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAlu                     0      0.00%      7.19% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCmp                     0      0.00%      7.19% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCvt                     0      0.00%      7.19% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMisc                    0      0.00%      7.19% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMult                    0      0.00%      7.19% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%      7.19% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShift                   0      0.00%      7.19% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%      7.19% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%      7.19% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%      7.19% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%      7.19% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%      7.19% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%      7.19% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%      7.19% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%      7.19% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%      7.19% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%      7.19% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%      7.19% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemRead                    74     24.18%     31.37% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemWrite                  210     68.63%    100.00% # attempts to use FU when none available
 system.cpu3.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu3.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu3.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntAlu               129621     47.77%     47.77% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntMult                   0      0.00%     47.77% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntDiv                    0      0.00%     47.77% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatAdd                  0      0.00%     47.77% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     47.77% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     47.77% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     47.77% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     47.77% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     47.77% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     47.77% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     47.77% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     47.77% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     47.77% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     47.77% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     47.77% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     47.77% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     47.77% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     47.77% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     47.77% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     47.77% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     47.77% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     47.77% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     47.77% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     47.77% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     47.77% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMisc             0      0.00%     47.77% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     47.77% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     47.77% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     47.77% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemRead               97351     35.88%     83.65% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemWrite              44377     16.35%    100.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntAlu               117603     48.62%     48.62% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntMult                   0      0.00%     48.62% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntDiv                    0      0.00%     48.62% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatAdd                  0      0.00%     48.62% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     48.62% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     48.62% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     48.62% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     48.62% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     48.62% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     48.62% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     48.62% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     48.62% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     48.62% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     48.62% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     48.62% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     48.62% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     48.62% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     48.62% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     48.62% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     48.62% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     48.62% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     48.62% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     48.62% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     48.62% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     48.62% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMisc             0      0.00%     48.62% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     48.62% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     48.62% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     48.62% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemRead               86736     35.86%     84.48% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemWrite              37529     15.52%    100.00% # Type of FU issued
 system.cpu3.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu3.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::total                271349                       # Type of FU issued
-system.cpu3.iq.rate                          1.448848                       # Inst issue rate
-system.cpu3.iq.fu_busy_cnt                        309                       # FU busy when requested
-system.cpu3.iq.fu_busy_rate                  0.001139                       # FU busy rate (busy events/executed inst)
-system.cpu3.iq.int_inst_queue_reads            728169                       # Number of integer instruction queue reads
-system.cpu3.iq.int_inst_queue_writes           290051                       # Number of integer instruction queue writes
-system.cpu3.iq.int_inst_queue_wakeup_accesses       269261                       # Number of integer instruction queue wakeup accesses
+system.cpu3.iq.FU_type_0::total                241868                       # Type of FU issued
+system.cpu3.iq.rate                          1.267971                       # Inst issue rate
+system.cpu3.iq.fu_busy_cnt                        306                       # FU busy when requested
+system.cpu3.iq.fu_busy_rate                  0.001265                       # FU busy rate (busy events/executed inst)
+system.cpu3.iq.int_inst_queue_reads            671615                       # Number of integer instruction queue reads
+system.cpu3.iq.int_inst_queue_writes           258950                       # Number of integer instruction queue writes
+system.cpu3.iq.int_inst_queue_wakeup_accesses       239863                       # Number of integer instruction queue wakeup accesses
 system.cpu3.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
 system.cpu3.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
 system.cpu3.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu3.iq.int_alu_accesses                271658                       # Number of integer alu accesses
+system.cpu3.iq.int_alu_accesses                242174                       # Number of integer alu accesses
 system.cpu3.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
-system.cpu3.iew.lsq.thread0.forwLoads           39639                       # Number of loads that had data forwarded from stores
+system.cpu3.iew.lsq.thread0.forwLoads           32833                       # Number of loads that had data forwarded from stores
 system.cpu3.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu3.iew.lsq.thread0.squashedLoads         2895                       # Number of loads squashed
-system.cpu3.iew.lsq.thread0.ignoredResponses            6                       # Number of memory responses ignored because the instruction is squashed
-system.cpu3.iew.lsq.thread0.memOrderViolation           39                       # Number of memory ordering violations
-system.cpu3.iew.lsq.thread0.squashedStores         1672                       # Number of stores squashed
+system.cpu3.iew.lsq.thread0.squashedLoads         2526                       # Number of loads squashed
+system.cpu3.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
+system.cpu3.iew.lsq.thread0.memOrderViolation           32                       # Number of memory ordering violations
+system.cpu3.iew.lsq.thread0.squashedStores         1583                       # Number of stores squashed
 system.cpu3.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu3.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu3.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
 system.cpu3.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu3.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu3.iew.iewSquashCycles                  2931                       # Number of cycles IEW is squashing
-system.cpu3.iew.iewBlockCycles                   1690                       # Number of cycles IEW is blocking
+system.cpu3.iew.iewSquashCycles                  2763                       # Number of cycles IEW is squashing
+system.cpu3.iew.iewBlockCycles                   1788                       # Number of cycles IEW is blocking
 system.cpu3.iew.iewUnblockCycles                   60                       # Number of cycles IEW is unblocking
-system.cpu3.iew.iewDispatchedInsts             322365                       # Number of instructions dispatched to IQ
-system.cpu3.iew.iewDispSquashedInsts              383                       # Number of squashed instructions skipped by dispatch
-system.cpu3.iew.iewDispLoadInsts                93735                       # Number of dispatched load instructions
-system.cpu3.iew.iewDispStoreInsts               45116                       # Number of dispatched store instructions
-system.cpu3.iew.iewDispNonSpecInsts              1181                       # Number of dispatched non-speculative instructions
-system.cpu3.iew.iewIQFullEvents                    62                       # Number of times the IQ has become full, causing a stall
+system.cpu3.iew.iewDispatchedInsts             286739                       # Number of instructions dispatched to IQ
+system.cpu3.iew.iewDispSquashedInsts              413                       # Number of squashed instructions skipped by dispatch
+system.cpu3.iew.iewDispLoadInsts                81367                       # Number of dispatched load instructions
+system.cpu3.iew.iewDispStoreInsts               38245                       # Number of dispatched store instructions
+system.cpu3.iew.iewDispNonSpecInsts              1210                       # Number of dispatched non-speculative instructions
+system.cpu3.iew.iewIQFullEvents                    58                       # Number of times the IQ has become full, causing a stall
 system.cpu3.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
-system.cpu3.iew.memOrderViolationEvents            39                       # Number of memory order violations
-system.cpu3.iew.predictedTakenIncorrect           528                       # Number of branches that were predicted taken incorrectly
-system.cpu3.iew.predictedNotTakenIncorrect         1218                       # Number of branches that were predicted not taken incorrectly
-system.cpu3.iew.branchMispredicts                1746                       # Number of branch mispredicts detected at execute
-system.cpu3.iew.iewExecutedInsts               269989                       # Number of executed instructions
-system.cpu3.iew.iewExecLoadInsts                92559                       # Number of load instructions executed
-system.cpu3.iew.iewExecSquashedInsts             1360                       # Number of squashed instructions skipped in execute
+system.cpu3.iew.memOrderViolationEvents            32                       # Number of memory order violations
+system.cpu3.iew.predictedTakenIncorrect           503                       # Number of branches that were predicted taken incorrectly
+system.cpu3.iew.predictedNotTakenIncorrect         1210                       # Number of branches that were predicted not taken incorrectly
+system.cpu3.iew.branchMispredicts                1713                       # Number of branch mispredicts detected at execute
+system.cpu3.iew.iewExecutedInsts               240581                       # Number of executed instructions
+system.cpu3.iew.iewExecLoadInsts                80413                       # Number of load instructions executed
+system.cpu3.iew.iewExecSquashedInsts             1287                       # Number of squashed instructions skipped in execute
 system.cpu3.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu3.iew.exec_nop                        45763                       # number of nop insts executed
-system.cpu3.iew.exec_refs                      136843                       # number of memory reference insts executed
-system.cpu3.iew.exec_branches                   55022                       # Number of branches executed
-system.cpu3.iew.exec_stores                     44284                       # Number of stores executed
-system.cpu3.iew.exec_rate                    1.441587                       # Inst execution rate
-system.cpu3.iew.wb_sent                        269584                       # cumulative count of insts sent to commit
-system.cpu3.iew.wb_count                       269261                       # cumulative count of insts written-back
-system.cpu3.iew.wb_producers                   153664                       # num instructions producing a value
-system.cpu3.iew.wb_consumers                   158539                       # num instructions consuming a value
+system.cpu3.iew.exec_nop                        40342                       # number of nop insts executed
+system.cpu3.iew.exec_refs                      117868                       # number of memory reference insts executed
+system.cpu3.iew.exec_branches                   49825                       # Number of branches executed
+system.cpu3.iew.exec_stores                     37455                       # Number of stores executed
+system.cpu3.iew.exec_rate                    1.261224                       # Inst execution rate
+system.cpu3.iew.wb_sent                        240146                       # cumulative count of insts sent to commit
+system.cpu3.iew.wb_count                       239863                       # cumulative count of insts written-back
+system.cpu3.iew.wb_producers                   134653                       # num instructions producing a value
+system.cpu3.iew.wb_consumers                   139524                       # num instructions consuming a value
 system.cpu3.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu3.iew.wb_rate                      1.437700                       # insts written-back per cycle
-system.cpu3.iew.wb_fanout                    0.969250                       # average fanout of values written-back
+system.cpu3.iew.wb_rate                      1.257460                       # insts written-back per cycle
+system.cpu3.iew.wb_fanout                    0.965088                       # average fanout of values written-back
 system.cpu3.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu3.commit.commitCommittedInsts        306791                       # The number of committed instructions
-system.cpu3.commit.commitCommittedOps          306791                       # The number of committed instructions
-system.cpu3.commit.commitSquashedInsts          15574                       # The number of squashed insts skipped by commit
-system.cpu3.commit.commitNonSpecStalls           5200                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu3.commit.branchMispredicts             1573                       # The number of times a branch was mispredicted
-system.cpu3.commit.committed_per_cycle::samples       175548                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::mean     1.747619                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::stdev     2.056560                       # Number of insts commited each cycle
+system.cpu3.commit.commitCommittedInsts        272332                       # The number of committed instructions
+system.cpu3.commit.commitCommittedOps          272332                       # The number of committed instructions
+system.cpu3.commit.commitSquashedInsts          14381                       # The number of squashed insts skipped by commit
+system.cpu3.commit.commitNonSpecStalls           6751                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu3.commit.branchMispredicts             1547                       # The number of times a branch was mispredicted
+system.cpu3.commit.committed_per_cycle::samples       177951                       # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::mean     1.530376                       # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::stdev     1.985731                       # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::0        66312     37.77%     37.77% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::1        53003     30.19%     67.97% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::2         6220      3.54%     71.51% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::3         6065      3.45%     74.97% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::4         1526      0.87%     75.83% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::5        40098     22.84%     98.68% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::6          522      0.30%     98.97% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::7          989      0.56%     99.54% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::0        79207     44.51%     44.51% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::1        47739     26.83%     71.34% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::2         6222      3.50%     74.83% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::3         7617      4.28%     79.11% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::4         1549      0.87%     79.98% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::5        33224     18.67%     98.66% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::6          582      0.33%     98.98% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::7          998      0.56%     99.54% # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::8          813      0.46%    100.00% # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::total       175548                       # Number of insts commited each cycle
-system.cpu3.commit.committedInsts              306791                       # Number of instructions committed
-system.cpu3.commit.committedOps                306791                       # Number of ops (including micro ops) committed
+system.cpu3.commit.committed_per_cycle::total       177951                       # Number of insts commited each cycle
+system.cpu3.commit.committedInsts              272332                       # Number of instructions committed
+system.cpu3.commit.committedOps                272332                       # Number of ops (including micro ops) committed
 system.cpu3.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu3.commit.refs                        134284                       # Number of memory references committed
-system.cpu3.commit.loads                        90840                       # Number of loads committed
-system.cpu3.commit.membars                       4481                       # Number of memory barriers committed
-system.cpu3.commit.branches                     53890                       # Number of branches committed
+system.cpu3.commit.refs                        115503                       # Number of memory references committed
+system.cpu3.commit.loads                        78841                       # Number of loads committed
+system.cpu3.commit.membars                       6036                       # Number of memory barriers committed
+system.cpu3.commit.branches                     48661                       # Number of branches committed
 system.cpu3.commit.fp_insts                         0                       # Number of committed floating point instructions.
-system.cpu3.commit.int_insts                   210289                       # Number of committed integer instructions.
+system.cpu3.commit.int_insts                   186284                       # Number of committed integer instructions.
 system.cpu3.commit.function_calls                 322                       # Number of function calls committed.
 system.cpu3.commit.bw_lim_events                  813                       # number cycles where commit BW limit reached
 system.cpu3.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu3.rob.rob_reads                      496513                       # The number of ROB reads
-system.cpu3.rob.rob_writes                     647676                       # The number of ROB writes
-system.cpu3.timesIdled                            218                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu3.idleCycles                           2241                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu3.quiesceCycles                       35902                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu3.committedInsts                     257635                       # Number of Instructions Simulated
-system.cpu3.committedOps                       257635                       # Number of Ops (including micro ops) Simulated
-system.cpu3.committedInsts_total               257635                       # Number of Instructions Simulated
-system.cpu3.cpi                              0.726943                       # CPI: Cycles Per Instruction
-system.cpu3.cpi_total                        0.726943                       # CPI: Total CPI of All Threads
-system.cpu3.ipc                              1.375623                       # IPC: Instructions Per Cycle
-system.cpu3.ipc_total                        1.375623                       # IPC: Total IPC of All Threads
-system.cpu3.int_regfile_reads                  470214                       # number of integer regfile reads
-system.cpu3.int_regfile_writes                 218594                       # number of integer regfile writes
+system.cpu3.rob.rob_reads                      463264                       # The number of ROB reads
+system.cpu3.rob.rob_writes                     576197                       # The number of ROB writes
+system.cpu3.timesIdled                            226                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu3.idleCycles                           3296                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu3.quiesceCycles                       37130                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu3.committedInsts                     226846                       # Number of Instructions Simulated
+system.cpu3.committedOps                       226846                       # Number of Ops (including micro ops) Simulated
+system.cpu3.committedInsts_total               226846                       # Number of Instructions Simulated
+system.cpu3.cpi                              0.840888                       # CPI: Cycles Per Instruction
+system.cpu3.cpi_total                        0.840888                       # CPI: Total CPI of All Threads
+system.cpu3.ipc                              1.189220                       # IPC: Instructions Per Cycle
+system.cpu3.ipc_total                        1.189220                       # IPC: Total IPC of All Threads
+system.cpu3.int_regfile_reads                  413495                       # number of integer regfile reads
+system.cpu3.int_regfile_writes                 192863                       # number of integer regfile writes
 system.cpu3.fp_regfile_writes                      64                       # number of floating regfile writes
-system.cpu3.misc_regfile_reads                 138505                       # number of misc regfile reads
+system.cpu3.misc_regfile_reads                 119579                       # number of misc regfile reads
 system.cpu3.misc_regfile_writes                   646                       # number of misc regfile writes
-system.cpu3.icache.replacements                   322                       # number of replacements
-system.cpu3.icache.tagsinuse                87.207959                       # Cycle average of tags in use
-system.cpu3.icache.total_refs                   18566                       # Total number of references to valid blocks.
-system.cpu3.icache.sampled_refs                   436                       # Sample count of references to valid blocks.
-system.cpu3.icache.avg_refs                 42.582569                       # Average number of references to valid blocks.
+system.cpu3.icache.replacements                   323                       # number of replacements
+system.cpu3.icache.tagsinuse                88.254899                       # Cycle average of tags in use
+system.cpu3.icache.total_refs                   21999                       # Total number of references to valid blocks.
+system.cpu3.icache.sampled_refs                   439                       # Sample count of references to valid blocks.
+system.cpu3.icache.avg_refs                 50.111617                       # Average number of references to valid blocks.
 system.cpu3.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu3.icache.occ_blocks::cpu3.inst    87.207959                       # Average occupied blocks per requestor
-system.cpu3.icache.occ_percent::cpu3.inst     0.170328                       # Average percentage of cache occupancy
-system.cpu3.icache.occ_percent::total        0.170328                       # Average percentage of cache occupancy
-system.cpu3.icache.ReadReq_hits::cpu3.inst        18566                       # number of ReadReq hits
-system.cpu3.icache.ReadReq_hits::total          18566                       # number of ReadReq hits
-system.cpu3.icache.demand_hits::cpu3.inst        18566                       # number of demand (read+write) hits
-system.cpu3.icache.demand_hits::total           18566                       # number of demand (read+write) hits
-system.cpu3.icache.overall_hits::cpu3.inst        18566                       # number of overall hits
-system.cpu3.icache.overall_hits::total          18566                       # number of overall hits
-system.cpu3.icache.ReadReq_misses::cpu3.inst          496                       # number of ReadReq misses
-system.cpu3.icache.ReadReq_misses::total          496                       # number of ReadReq misses
-system.cpu3.icache.demand_misses::cpu3.inst          496                       # number of demand (read+write) misses
-system.cpu3.icache.demand_misses::total           496                       # number of demand (read+write) misses
-system.cpu3.icache.overall_misses::cpu3.inst          496                       # number of overall misses
-system.cpu3.icache.overall_misses::total          496                       # number of overall misses
-system.cpu3.icache.ReadReq_miss_latency::cpu3.inst      6966500                       # number of ReadReq miss cycles
-system.cpu3.icache.ReadReq_miss_latency::total      6966500                       # number of ReadReq miss cycles
-system.cpu3.icache.demand_miss_latency::cpu3.inst      6966500                       # number of demand (read+write) miss cycles
-system.cpu3.icache.demand_miss_latency::total      6966500                       # number of demand (read+write) miss cycles
-system.cpu3.icache.overall_miss_latency::cpu3.inst      6966500                       # number of overall miss cycles
-system.cpu3.icache.overall_miss_latency::total      6966500                       # number of overall miss cycles
-system.cpu3.icache.ReadReq_accesses::cpu3.inst        19062                       # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.ReadReq_accesses::total        19062                       # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.demand_accesses::cpu3.inst        19062                       # number of demand (read+write) accesses
-system.cpu3.icache.demand_accesses::total        19062                       # number of demand (read+write) accesses
-system.cpu3.icache.overall_accesses::cpu3.inst        19062                       # number of overall (read+write) accesses
-system.cpu3.icache.overall_accesses::total        19062                       # number of overall (read+write) accesses
-system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.026020                       # miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_miss_rate::total     0.026020                       # miss rate for ReadReq accesses
-system.cpu3.icache.demand_miss_rate::cpu3.inst     0.026020                       # miss rate for demand accesses
-system.cpu3.icache.demand_miss_rate::total     0.026020                       # miss rate for demand accesses
-system.cpu3.icache.overall_miss_rate::cpu3.inst     0.026020                       # miss rate for overall accesses
-system.cpu3.icache.overall_miss_rate::total     0.026020                       # miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14045.362903                       # average ReadReq miss latency
-system.cpu3.icache.ReadReq_avg_miss_latency::total 14045.362903                       # average ReadReq miss latency
-system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14045.362903                       # average overall miss latency
-system.cpu3.icache.demand_avg_miss_latency::total 14045.362903                       # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14045.362903                       # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency::total 14045.362903                       # average overall miss latency
+system.cpu3.icache.occ_blocks::cpu3.inst    88.254899                       # Average occupied blocks per requestor
+system.cpu3.icache.occ_percent::cpu3.inst     0.172373                       # Average percentage of cache occupancy
+system.cpu3.icache.occ_percent::total        0.172373                       # Average percentage of cache occupancy
+system.cpu3.icache.ReadReq_hits::cpu3.inst        21999                       # number of ReadReq hits
+system.cpu3.icache.ReadReq_hits::total          21999                       # number of ReadReq hits
+system.cpu3.icache.demand_hits::cpu3.inst        21999                       # number of demand (read+write) hits
+system.cpu3.icache.demand_hits::total           21999                       # number of demand (read+write) hits
+system.cpu3.icache.overall_hits::cpu3.inst        21999                       # number of overall hits
+system.cpu3.icache.overall_hits::total          21999                       # number of overall hits
+system.cpu3.icache.ReadReq_misses::cpu3.inst          504                       # number of ReadReq misses
+system.cpu3.icache.ReadReq_misses::total          504                       # number of ReadReq misses
+system.cpu3.icache.demand_misses::cpu3.inst          504                       # number of demand (read+write) misses
+system.cpu3.icache.demand_misses::total           504                       # number of demand (read+write) misses
+system.cpu3.icache.overall_misses::cpu3.inst          504                       # number of overall misses
+system.cpu3.icache.overall_misses::total          504                       # number of overall misses
+system.cpu3.icache.ReadReq_miss_latency::cpu3.inst      7701000                       # number of ReadReq miss cycles
+system.cpu3.icache.ReadReq_miss_latency::total      7701000                       # number of ReadReq miss cycles
+system.cpu3.icache.demand_miss_latency::cpu3.inst      7701000                       # number of demand (read+write) miss cycles
+system.cpu3.icache.demand_miss_latency::total      7701000                       # number of demand (read+write) miss cycles
+system.cpu3.icache.overall_miss_latency::cpu3.inst      7701000                       # number of overall miss cycles
+system.cpu3.icache.overall_miss_latency::total      7701000                       # number of overall miss cycles
+system.cpu3.icache.ReadReq_accesses::cpu3.inst        22503                       # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.ReadReq_accesses::total        22503                       # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.demand_accesses::cpu3.inst        22503                       # number of demand (read+write) accesses
+system.cpu3.icache.demand_accesses::total        22503                       # number of demand (read+write) accesses
+system.cpu3.icache.overall_accesses::cpu3.inst        22503                       # number of overall (read+write) accesses
+system.cpu3.icache.overall_accesses::total        22503                       # number of overall (read+write) accesses
+system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.022397                       # miss rate for ReadReq accesses
+system.cpu3.icache.ReadReq_miss_rate::total     0.022397                       # miss rate for ReadReq accesses
+system.cpu3.icache.demand_miss_rate::cpu3.inst     0.022397                       # miss rate for demand accesses
+system.cpu3.icache.demand_miss_rate::total     0.022397                       # miss rate for demand accesses
+system.cpu3.icache.overall_miss_rate::cpu3.inst     0.022397                       # miss rate for overall accesses
+system.cpu3.icache.overall_miss_rate::total     0.022397                       # miss rate for overall accesses
+system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 15279.761905                       # average ReadReq miss latency
+system.cpu3.icache.ReadReq_avg_miss_latency::total 15279.761905                       # average ReadReq miss latency
+system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 15279.761905                       # average overall miss latency
+system.cpu3.icache.demand_avg_miss_latency::total 15279.761905                       # average overall miss latency
+system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 15279.761905                       # average overall miss latency
+system.cpu3.icache.overall_avg_miss_latency::total 15279.761905                       # average overall miss latency
 system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1805,106 +1805,106 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu3.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu3.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu3.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst           60                       # number of ReadReq MSHR hits
-system.cpu3.icache.ReadReq_mshr_hits::total           60                       # number of ReadReq MSHR hits
-system.cpu3.icache.demand_mshr_hits::cpu3.inst           60                       # number of demand (read+write) MSHR hits
-system.cpu3.icache.demand_mshr_hits::total           60                       # number of demand (read+write) MSHR hits
-system.cpu3.icache.overall_mshr_hits::cpu3.inst           60                       # number of overall MSHR hits
-system.cpu3.icache.overall_mshr_hits::total           60                       # number of overall MSHR hits
-system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst          436                       # number of ReadReq MSHR misses
-system.cpu3.icache.ReadReq_mshr_misses::total          436                       # number of ReadReq MSHR misses
-system.cpu3.icache.demand_mshr_misses::cpu3.inst          436                       # number of demand (read+write) MSHR misses
-system.cpu3.icache.demand_mshr_misses::total          436                       # number of demand (read+write) MSHR misses
-system.cpu3.icache.overall_mshr_misses::cpu3.inst          436                       # number of overall MSHR misses
-system.cpu3.icache.overall_mshr_misses::total          436                       # number of overall MSHR misses
-system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst      5084500                       # number of ReadReq MSHR miss cycles
-system.cpu3.icache.ReadReq_mshr_miss_latency::total      5084500                       # number of ReadReq MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst      5084500                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_latency::total      5084500                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst      5084500                       # number of overall MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency::total      5084500                       # number of overall MSHR miss cycles
-system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.022873                       # mshr miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_mshr_miss_rate::total     0.022873                       # mshr miss rate for ReadReq accesses
-system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst     0.022873                       # mshr miss rate for demand accesses
-system.cpu3.icache.demand_mshr_miss_rate::total     0.022873                       # mshr miss rate for demand accesses
-system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst     0.022873                       # mshr miss rate for overall accesses
-system.cpu3.icache.overall_mshr_miss_rate::total     0.022873                       # mshr miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11661.697248                       # average ReadReq mshr miss latency
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 11661.697248                       # average ReadReq mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11661.697248                       # average overall mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency::total 11661.697248                       # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11661.697248                       # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency::total 11661.697248                       # average overall mshr miss latency
+system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst           65                       # number of ReadReq MSHR hits
+system.cpu3.icache.ReadReq_mshr_hits::total           65                       # number of ReadReq MSHR hits
+system.cpu3.icache.demand_mshr_hits::cpu3.inst           65                       # number of demand (read+write) MSHR hits
+system.cpu3.icache.demand_mshr_hits::total           65                       # number of demand (read+write) MSHR hits
+system.cpu3.icache.overall_mshr_hits::cpu3.inst           65                       # number of overall MSHR hits
+system.cpu3.icache.overall_mshr_hits::total           65                       # number of overall MSHR hits
+system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst          439                       # number of ReadReq MSHR misses
+system.cpu3.icache.ReadReq_mshr_misses::total          439                       # number of ReadReq MSHR misses
+system.cpu3.icache.demand_mshr_misses::cpu3.inst          439                       # number of demand (read+write) MSHR misses
+system.cpu3.icache.demand_mshr_misses::total          439                       # number of demand (read+write) MSHR misses
+system.cpu3.icache.overall_mshr_misses::cpu3.inst          439                       # number of overall MSHR misses
+system.cpu3.icache.overall_mshr_misses::total          439                       # number of overall MSHR misses
+system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst      5678000                       # number of ReadReq MSHR miss cycles
+system.cpu3.icache.ReadReq_mshr_miss_latency::total      5678000                       # number of ReadReq MSHR miss cycles
+system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst      5678000                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.icache.demand_mshr_miss_latency::total      5678000                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst      5678000                       # number of overall MSHR miss cycles
+system.cpu3.icache.overall_mshr_miss_latency::total      5678000                       # number of overall MSHR miss cycles
+system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.019509                       # mshr miss rate for ReadReq accesses
+system.cpu3.icache.ReadReq_mshr_miss_rate::total     0.019509                       # mshr miss rate for ReadReq accesses
+system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst     0.019509                       # mshr miss rate for demand accesses
+system.cpu3.icache.demand_mshr_miss_rate::total     0.019509                       # mshr miss rate for demand accesses
+system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst     0.019509                       # mshr miss rate for overall accesses
+system.cpu3.icache.overall_mshr_miss_rate::total     0.019509                       # mshr miss rate for overall accesses
+system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12933.940774                       # average ReadReq mshr miss latency
+system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12933.940774                       # average ReadReq mshr miss latency
+system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12933.940774                       # average overall mshr miss latency
+system.cpu3.icache.demand_avg_mshr_miss_latency::total 12933.940774                       # average overall mshr miss latency
+system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12933.940774                       # average overall mshr miss latency
+system.cpu3.icache.overall_avg_mshr_miss_latency::total 12933.940774                       # average overall mshr miss latency
 system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu3.dcache.replacements                     0                       # number of replacements
-system.cpu3.dcache.tagsinuse                26.205436                       # Cycle average of tags in use
-system.cpu3.dcache.total_refs                   49620                       # Total number of references to valid blocks.
+system.cpu3.dcache.tagsinuse                26.059158                       # Cycle average of tags in use
+system.cpu3.dcache.total_refs                   42792                       # Total number of references to valid blocks.
 system.cpu3.dcache.sampled_refs                    28                       # Sample count of references to valid blocks.
-system.cpu3.dcache.avg_refs               1772.142857                       # Average number of references to valid blocks.
+system.cpu3.dcache.avg_refs               1528.285714                       # Average number of references to valid blocks.
 system.cpu3.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu3.dcache.occ_blocks::cpu3.data    26.205436                       # Average occupied blocks per requestor
-system.cpu3.dcache.occ_percent::cpu3.data     0.051182                       # Average percentage of cache occupancy
-system.cpu3.dcache.occ_percent::total        0.051182                       # Average percentage of cache occupancy
-system.cpu3.dcache.ReadReq_hits::cpu3.data        52477                       # number of ReadReq hits
-system.cpu3.dcache.ReadReq_hits::total          52477                       # number of ReadReq hits
-system.cpu3.dcache.WriteReq_hits::cpu3.data        43221                       # number of WriteReq hits
-system.cpu3.dcache.WriteReq_hits::total         43221                       # number of WriteReq hits
-system.cpu3.dcache.SwapReq_hits::cpu3.data           12                       # number of SwapReq hits
-system.cpu3.dcache.SwapReq_hits::total             12                       # number of SwapReq hits
-system.cpu3.dcache.demand_hits::cpu3.data        95698                       # number of demand (read+write) hits
-system.cpu3.dcache.demand_hits::total           95698                       # number of demand (read+write) hits
-system.cpu3.dcache.overall_hits::cpu3.data        95698                       # number of overall hits
-system.cpu3.dcache.overall_hits::total          95698                       # number of overall hits
-system.cpu3.dcache.ReadReq_misses::cpu3.data          424                       # number of ReadReq misses
-system.cpu3.dcache.ReadReq_misses::total          424                       # number of ReadReq misses
-system.cpu3.dcache.WriteReq_misses::cpu3.data          150                       # number of WriteReq misses
-system.cpu3.dcache.WriteReq_misses::total          150                       # number of WriteReq misses
-system.cpu3.dcache.SwapReq_misses::cpu3.data           61                       # number of SwapReq misses
-system.cpu3.dcache.SwapReq_misses::total           61                       # number of SwapReq misses
-system.cpu3.dcache.demand_misses::cpu3.data          574                       # number of demand (read+write) misses
-system.cpu3.dcache.demand_misses::total           574                       # number of demand (read+write) misses
-system.cpu3.dcache.overall_misses::cpu3.data          574                       # number of overall misses
-system.cpu3.dcache.overall_misses::total          574                       # number of overall misses
-system.cpu3.dcache.ReadReq_miss_latency::cpu3.data      8617000                       # number of ReadReq miss cycles
-system.cpu3.dcache.ReadReq_miss_latency::total      8617000                       # number of ReadReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency::cpu3.data      2850000                       # number of WriteReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency::total      2850000                       # number of WriteReq miss cycles
-system.cpu3.dcache.SwapReq_miss_latency::cpu3.data      1161500                       # number of SwapReq miss cycles
-system.cpu3.dcache.SwapReq_miss_latency::total      1161500                       # number of SwapReq miss cycles
-system.cpu3.dcache.demand_miss_latency::cpu3.data     11467000                       # number of demand (read+write) miss cycles
-system.cpu3.dcache.demand_miss_latency::total     11467000                       # number of demand (read+write) miss cycles
-system.cpu3.dcache.overall_miss_latency::cpu3.data     11467000                       # number of overall miss cycles
-system.cpu3.dcache.overall_miss_latency::total     11467000                       # number of overall miss cycles
-system.cpu3.dcache.ReadReq_accesses::cpu3.data        52901                       # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.ReadReq_accesses::total        52901                       # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::cpu3.data        43371                       # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::total        43371                       # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.SwapReq_accesses::cpu3.data           73                       # number of SwapReq accesses(hits+misses)
-system.cpu3.dcache.SwapReq_accesses::total           73                       # number of SwapReq accesses(hits+misses)
-system.cpu3.dcache.demand_accesses::cpu3.data        96272                       # number of demand (read+write) accesses
-system.cpu3.dcache.demand_accesses::total        96272                       # number of demand (read+write) accesses
-system.cpu3.dcache.overall_accesses::cpu3.data        96272                       # number of overall (read+write) accesses
-system.cpu3.dcache.overall_accesses::total        96272                       # number of overall (read+write) accesses
-system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.008015                       # miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_miss_rate::total     0.008015                       # miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.003459                       # miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::total     0.003459                       # miss rate for WriteReq accesses
-system.cpu3.dcache.SwapReq_miss_rate::cpu3.data     0.835616                       # miss rate for SwapReq accesses
-system.cpu3.dcache.SwapReq_miss_rate::total     0.835616                       # miss rate for SwapReq accesses
-system.cpu3.dcache.demand_miss_rate::cpu3.data     0.005962                       # miss rate for demand accesses
-system.cpu3.dcache.demand_miss_rate::total     0.005962                       # miss rate for demand accesses
-system.cpu3.dcache.overall_miss_rate::cpu3.data     0.005962                       # miss rate for overall accesses
-system.cpu3.dcache.overall_miss_rate::total     0.005962                       # miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 20323.113208                       # average ReadReq miss latency
-system.cpu3.dcache.ReadReq_avg_miss_latency::total 20323.113208                       # average ReadReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data        19000                       # average WriteReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::total        19000                       # average WriteReq miss latency
-system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 19040.983607                       # average SwapReq miss latency
-system.cpu3.dcache.SwapReq_avg_miss_latency::total 19040.983607                       # average SwapReq miss latency
-system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 19977.351916                       # average overall miss latency
-system.cpu3.dcache.demand_avg_miss_latency::total 19977.351916                       # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 19977.351916                       # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::total 19977.351916                       # average overall miss latency
+system.cpu3.dcache.occ_blocks::cpu3.data    26.059158                       # Average occupied blocks per requestor
+system.cpu3.dcache.occ_percent::cpu3.data     0.050897                       # Average percentage of cache occupancy
+system.cpu3.dcache.occ_percent::total        0.050897                       # Average percentage of cache occupancy
+system.cpu3.dcache.ReadReq_hits::cpu3.data        47204                       # number of ReadReq hits
+system.cpu3.dcache.ReadReq_hits::total          47204                       # number of ReadReq hits
+system.cpu3.dcache.WriteReq_hits::cpu3.data        36453                       # number of WriteReq hits
+system.cpu3.dcache.WriteReq_hits::total         36453                       # number of WriteReq hits
+system.cpu3.dcache.SwapReq_hits::cpu3.data           14                       # number of SwapReq hits
+system.cpu3.dcache.SwapReq_hits::total             14                       # number of SwapReq hits
+system.cpu3.dcache.demand_hits::cpu3.data        83657                       # number of demand (read+write) hits
+system.cpu3.dcache.demand_hits::total           83657                       # number of demand (read+write) hits
+system.cpu3.dcache.overall_hits::cpu3.data        83657                       # number of overall hits
+system.cpu3.dcache.overall_hits::total          83657                       # number of overall hits
+system.cpu3.dcache.ReadReq_misses::cpu3.data          361                       # number of ReadReq misses
+system.cpu3.dcache.ReadReq_misses::total          361                       # number of ReadReq misses
+system.cpu3.dcache.WriteReq_misses::cpu3.data          140                       # number of WriteReq misses
+system.cpu3.dcache.WriteReq_misses::total          140                       # number of WriteReq misses
+system.cpu3.dcache.SwapReq_misses::cpu3.data           55                       # number of SwapReq misses
+system.cpu3.dcache.SwapReq_misses::total           55                       # number of SwapReq misses
+system.cpu3.dcache.demand_misses::cpu3.data          501                       # number of demand (read+write) misses
+system.cpu3.dcache.demand_misses::total           501                       # number of demand (read+write) misses
+system.cpu3.dcache.overall_misses::cpu3.data          501                       # number of overall misses
+system.cpu3.dcache.overall_misses::total          501                       # number of overall misses
+system.cpu3.dcache.ReadReq_miss_latency::cpu3.data      9450000                       # number of ReadReq miss cycles
+system.cpu3.dcache.ReadReq_miss_latency::total      9450000                       # number of ReadReq miss cycles
+system.cpu3.dcache.WriteReq_miss_latency::cpu3.data      3328500                       # number of WriteReq miss cycles
+system.cpu3.dcache.WriteReq_miss_latency::total      3328500                       # number of WriteReq miss cycles
+system.cpu3.dcache.SwapReq_miss_latency::cpu3.data      1305500                       # number of SwapReq miss cycles
+system.cpu3.dcache.SwapReq_miss_latency::total      1305500                       # number of SwapReq miss cycles
+system.cpu3.dcache.demand_miss_latency::cpu3.data     12778500                       # number of demand (read+write) miss cycles
+system.cpu3.dcache.demand_miss_latency::total     12778500                       # number of demand (read+write) miss cycles
+system.cpu3.dcache.overall_miss_latency::cpu3.data     12778500                       # number of overall miss cycles
+system.cpu3.dcache.overall_miss_latency::total     12778500                       # number of overall miss cycles
+system.cpu3.dcache.ReadReq_accesses::cpu3.data        47565                       # number of ReadReq accesses(hits+misses)
+system.cpu3.dcache.ReadReq_accesses::total        47565                       # number of ReadReq accesses(hits+misses)
+system.cpu3.dcache.WriteReq_accesses::cpu3.data        36593                       # number of WriteReq accesses(hits+misses)
+system.cpu3.dcache.WriteReq_accesses::total        36593                       # number of WriteReq accesses(hits+misses)
+system.cpu3.dcache.SwapReq_accesses::cpu3.data           69                       # number of SwapReq accesses(hits+misses)
+system.cpu3.dcache.SwapReq_accesses::total           69                       # number of SwapReq accesses(hits+misses)
+system.cpu3.dcache.demand_accesses::cpu3.data        84158                       # number of demand (read+write) accesses
+system.cpu3.dcache.demand_accesses::total        84158                       # number of demand (read+write) accesses
+system.cpu3.dcache.overall_accesses::cpu3.data        84158                       # number of overall (read+write) accesses
+system.cpu3.dcache.overall_accesses::total        84158                       # number of overall (read+write) accesses
+system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.007590                       # miss rate for ReadReq accesses
+system.cpu3.dcache.ReadReq_miss_rate::total     0.007590                       # miss rate for ReadReq accesses
+system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.003826                       # miss rate for WriteReq accesses
+system.cpu3.dcache.WriteReq_miss_rate::total     0.003826                       # miss rate for WriteReq accesses
+system.cpu3.dcache.SwapReq_miss_rate::cpu3.data     0.797101                       # miss rate for SwapReq accesses
+system.cpu3.dcache.SwapReq_miss_rate::total     0.797101                       # miss rate for SwapReq accesses
+system.cpu3.dcache.demand_miss_rate::cpu3.data     0.005953                       # miss rate for demand accesses
+system.cpu3.dcache.demand_miss_rate::total     0.005953                       # miss rate for demand accesses
+system.cpu3.dcache.overall_miss_rate::cpu3.data     0.005953                       # miss rate for overall accesses
+system.cpu3.dcache.overall_miss_rate::total     0.005953                       # miss rate for overall accesses
+system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 26177.285319                       # average ReadReq miss latency
+system.cpu3.dcache.ReadReq_avg_miss_latency::total 26177.285319                       # average ReadReq miss latency
+system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data        23775                       # average WriteReq miss latency
+system.cpu3.dcache.WriteReq_avg_miss_latency::total        23775                       # average WriteReq miss latency
+system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 23736.363636                       # average SwapReq miss latency
+system.cpu3.dcache.SwapReq_avg_miss_latency::total 23736.363636                       # average SwapReq miss latency
+system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 25505.988024                       # average overall miss latency
+system.cpu3.dcache.demand_avg_miss_latency::total 25505.988024                       # average overall miss latency
+system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 25505.988024                       # average overall miss latency
+system.cpu3.dcache.overall_avg_miss_latency::total 25505.988024                       # average overall miss latency
 system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1913,288 +1913,288 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu3.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu3.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data          264                       # number of ReadReq MSHR hits
-system.cpu3.dcache.ReadReq_mshr_hits::total          264                       # number of ReadReq MSHR hits
-system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data           46                       # number of WriteReq MSHR hits
-system.cpu3.dcache.WriteReq_mshr_hits::total           46                       # number of WriteReq MSHR hits
-system.cpu3.dcache.demand_mshr_hits::cpu3.data          310                       # number of demand (read+write) MSHR hits
-system.cpu3.dcache.demand_mshr_hits::total          310                       # number of demand (read+write) MSHR hits
-system.cpu3.dcache.overall_mshr_hits::cpu3.data          310                       # number of overall MSHR hits
-system.cpu3.dcache.overall_mshr_hits::total          310                       # number of overall MSHR hits
-system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data          160                       # number of ReadReq MSHR misses
-system.cpu3.dcache.ReadReq_mshr_misses::total          160                       # number of ReadReq MSHR misses
-system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data          104                       # number of WriteReq MSHR misses
-system.cpu3.dcache.WriteReq_mshr_misses::total          104                       # number of WriteReq MSHR misses
-system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data           61                       # number of SwapReq MSHR misses
-system.cpu3.dcache.SwapReq_mshr_misses::total           61                       # number of SwapReq MSHR misses
-system.cpu3.dcache.demand_mshr_misses::cpu3.data          264                       # number of demand (read+write) MSHR misses
-system.cpu3.dcache.demand_mshr_misses::total          264                       # number of demand (read+write) MSHR misses
-system.cpu3.dcache.overall_mshr_misses::cpu3.data          264                       # number of overall MSHR misses
-system.cpu3.dcache.overall_mshr_misses::total          264                       # number of overall MSHR misses
-system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data      1797000                       # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.ReadReq_mshr_miss_latency::total      1797000                       # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data      1508500                       # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency::total      1508500                       # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data       978500                       # number of SwapReq MSHR miss cycles
-system.cpu3.dcache.SwapReq_mshr_miss_latency::total       978500                       # number of SwapReq MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data      3305500                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency::total      3305500                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data      3305500                       # number of overall MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency::total      3305500                       # number of overall MSHR miss cycles
-system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.003025                       # mshr miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_mshr_miss_rate::total     0.003025                       # mshr miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.002398                       # mshr miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_mshr_miss_rate::total     0.002398                       # mshr miss rate for WriteReq accesses
-system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data     0.835616                       # mshr miss rate for SwapReq accesses
-system.cpu3.dcache.SwapReq_mshr_miss_rate::total     0.835616                       # mshr miss rate for SwapReq accesses
-system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data     0.002742                       # mshr miss rate for demand accesses
-system.cpu3.dcache.demand_mshr_miss_rate::total     0.002742                       # mshr miss rate for demand accesses
-system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data     0.002742                       # mshr miss rate for overall accesses
-system.cpu3.dcache.overall_mshr_miss_rate::total     0.002742                       # mshr miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 11231.250000                       # average ReadReq mshr miss latency
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 11231.250000                       # average ReadReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 14504.807692                       # average WriteReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 14504.807692                       # average WriteReq mshr miss latency
-system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 16040.983607                       # average SwapReq mshr miss latency
-system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 16040.983607                       # average SwapReq mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 12520.833333                       # average overall mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency::total 12520.833333                       # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 12520.833333                       # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency::total 12520.833333                       # average overall mshr miss latency
+system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data          206                       # number of ReadReq MSHR hits
+system.cpu3.dcache.ReadReq_mshr_hits::total          206                       # number of ReadReq MSHR hits
+system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data           33                       # number of WriteReq MSHR hits
+system.cpu3.dcache.WriteReq_mshr_hits::total           33                       # number of WriteReq MSHR hits
+system.cpu3.dcache.demand_mshr_hits::cpu3.data          239                       # number of demand (read+write) MSHR hits
+system.cpu3.dcache.demand_mshr_hits::total          239                       # number of demand (read+write) MSHR hits
+system.cpu3.dcache.overall_mshr_hits::cpu3.data          239                       # number of overall MSHR hits
+system.cpu3.dcache.overall_mshr_hits::total          239                       # number of overall MSHR hits
+system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data          155                       # number of ReadReq MSHR misses
+system.cpu3.dcache.ReadReq_mshr_misses::total          155                       # number of ReadReq MSHR misses
+system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data          107                       # number of WriteReq MSHR misses
+system.cpu3.dcache.WriteReq_mshr_misses::total          107                       # number of WriteReq MSHR misses
+system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data           55                       # number of SwapReq MSHR misses
+system.cpu3.dcache.SwapReq_mshr_misses::total           55                       # number of SwapReq MSHR misses
+system.cpu3.dcache.demand_mshr_misses::cpu3.data          262                       # number of demand (read+write) MSHR misses
+system.cpu3.dcache.demand_mshr_misses::total          262                       # number of demand (read+write) MSHR misses
+system.cpu3.dcache.overall_mshr_misses::cpu3.data          262                       # number of overall MSHR misses
+system.cpu3.dcache.overall_mshr_misses::total          262                       # number of overall MSHR misses
+system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data      2585504                       # number of ReadReq MSHR miss cycles
+system.cpu3.dcache.ReadReq_mshr_miss_latency::total      2585504                       # number of ReadReq MSHR miss cycles
+system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data      1735000                       # number of WriteReq MSHR miss cycles
+system.cpu3.dcache.WriteReq_mshr_miss_latency::total      1735000                       # number of WriteReq MSHR miss cycles
+system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data      1134500                       # number of SwapReq MSHR miss cycles
+system.cpu3.dcache.SwapReq_mshr_miss_latency::total      1134500                       # number of SwapReq MSHR miss cycles
+system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data      4320504                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.dcache.demand_mshr_miss_latency::total      4320504                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data      4320504                       # number of overall MSHR miss cycles
+system.cpu3.dcache.overall_mshr_miss_latency::total      4320504                       # number of overall MSHR miss cycles
+system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.003259                       # mshr miss rate for ReadReq accesses
+system.cpu3.dcache.ReadReq_mshr_miss_rate::total     0.003259                       # mshr miss rate for ReadReq accesses
+system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.002924                       # mshr miss rate for WriteReq accesses
+system.cpu3.dcache.WriteReq_mshr_miss_rate::total     0.002924                       # mshr miss rate for WriteReq accesses
+system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data     0.797101                       # mshr miss rate for SwapReq accesses
+system.cpu3.dcache.SwapReq_mshr_miss_rate::total     0.797101                       # mshr miss rate for SwapReq accesses
+system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data     0.003113                       # mshr miss rate for demand accesses
+system.cpu3.dcache.demand_mshr_miss_rate::total     0.003113                       # mshr miss rate for demand accesses
+system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data     0.003113                       # mshr miss rate for overall accesses
+system.cpu3.dcache.overall_mshr_miss_rate::total     0.003113                       # mshr miss rate for overall accesses
+system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 16680.670968                       # average ReadReq mshr miss latency
+system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 16680.670968                       # average ReadReq mshr miss latency
+system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 16214.953271                       # average WriteReq mshr miss latency
+system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 16214.953271                       # average WriteReq mshr miss latency
+system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 20627.272727                       # average SwapReq mshr miss latency
+system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 20627.272727                       # average SwapReq mshr miss latency
+system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 16490.473282                       # average overall mshr miss latency
+system.cpu3.dcache.demand_avg_mshr_miss_latency::total 16490.473282                       # average overall mshr miss latency
+system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 16490.473282                       # average overall mshr miss latency
+system.cpu3.dcache.overall_avg_mshr_miss_latency::total 16490.473282                       # average overall mshr miss latency
 system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.l2c.replacements                             0                       # number of replacements
-system.l2c.tagsinuse                       436.530480                       # Cycle average of tags in use
-system.l2c.total_refs                            1479                       # Total number of references to valid blocks.
-system.l2c.sampled_refs                           536                       # Sample count of references to valid blocks.
-system.l2c.avg_refs                          2.759328                       # Average number of references to valid blocks.
+system.l2c.tagsinuse                       436.890326                       # Cycle average of tags in use
+system.l2c.total_refs                            1480                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                           538                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                          2.750929                       # Average number of references to valid blocks.
 system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks            0.840422                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst           294.533073                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data            59.606311                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.inst            70.480803                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.data             5.728880                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu2.inst             1.673039                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu2.data             0.734409                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu3.inst             2.156423                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu3.data             0.777117                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::writebacks            0.838452                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst           294.676580                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data            59.534459                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst            68.181124                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.data             5.702984                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu2.inst             2.344879                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu2.data             0.730463                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu3.inst             4.107761                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu3.data             0.773625                       # Average occupied blocks per requestor
 system.l2c.occ_percent::writebacks           0.000013                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.inst            0.004494                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.data            0.000910                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.inst            0.001075                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.inst            0.004496                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.data            0.000908                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.inst            0.001040                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu1.data            0.000087                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu2.inst            0.000026                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu2.inst            0.000036                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu2.data            0.000011                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu3.inst            0.000033                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu3.inst            0.000063                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu3.data            0.000012                       # Average percentage of cache occupancy
-system.l2c.occ_percent::total                0.006661                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0.inst                238                       # number of ReadReq hits
+system.l2c.occ_percent::total                0.006666                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu0.inst                239                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu0.data                  5                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst                347                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst                350                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu1.data                  5                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.inst                431                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.inst                428                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu2.data                 11                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu3.inst                431                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu3.data                 11                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                   1479                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                   1480                       # number of ReadReq hits
 system.l2c.Writeback_hits::writebacks               1                       # number of Writeback hits
 system.l2c.Writeback_hits::total                    1                       # number of Writeback hits
 system.l2c.UpgradeReq_hits::cpu0.data               3                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::total                   3                       # number of UpgradeReq hits
-system.l2c.demand_hits::cpu0.inst                 238                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst                 239                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu0.data                   5                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst                 347                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst                 350                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu1.data                   5                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst                 431                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.inst                 428                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu2.data                  11                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu3.inst                 431                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu3.data                  11                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                    1479                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst                238                       # number of overall hits
+system.l2c.demand_hits::total                    1480                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.inst                239                       # number of overall hits
 system.l2c.overall_hits::cpu0.data                  5                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst                347                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst                350                       # number of overall hits
 system.l2c.overall_hits::cpu1.data                  5                       # number of overall hits
-system.l2c.overall_hits::cpu2.inst                431                       # number of overall hits
+system.l2c.overall_hits::cpu2.inst                428                       # number of overall hits
 system.l2c.overall_hits::cpu2.data                 11                       # number of overall hits
 system.l2c.overall_hits::cpu3.inst                431                       # number of overall hits
 system.l2c.overall_hits::cpu3.data                 11                       # number of overall hits
-system.l2c.overall_hits::total                   1479                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.inst              361                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data               75                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst               89                       # number of ReadReq misses
+system.l2c.overall_hits::total                   1480                       # number of overall hits
+system.l2c.ReadReq_misses::cpu0.inst              363                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data               74                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst               86                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu1.data                7                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.inst                7                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.inst               10                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu2.data                1                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3.inst                5                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu3.inst                8                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu3.data                1                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                  546                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data            23                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data            20                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2.data            19                       # number of UpgradeReq misses
+system.l2c.ReadReq_misses::total                  550                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data            20                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data            15                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu2.data            21                       # number of UpgradeReq misses
 system.l2c.UpgradeReq_misses::cpu3.data            19                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total                81                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total                75                       # number of UpgradeReq misses
 system.l2c.ReadExReq_misses::cpu0.data             94                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::cpu1.data             13                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::cpu2.data             12                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::cpu3.data             12                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::total                131                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.inst               361                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data               169                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst                89                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst               363                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data               168                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst                86                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu1.data                20                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.inst                 7                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.inst                10                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu2.data                13                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.inst                 5                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu3.inst                 8                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu3.data                13                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                   677                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst              361                       # number of overall misses
-system.l2c.overall_misses::cpu0.data              169                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst               89                       # number of overall misses
+system.l2c.demand_misses::total                   681                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.inst              363                       # number of overall misses
+system.l2c.overall_misses::cpu0.data              168                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst               86                       # number of overall misses
 system.l2c.overall_misses::cpu1.data               20                       # number of overall misses
-system.l2c.overall_misses::cpu2.inst                7                       # number of overall misses
+system.l2c.overall_misses::cpu2.inst               10                       # number of overall misses
 system.l2c.overall_misses::cpu2.data               13                       # number of overall misses
-system.l2c.overall_misses::cpu3.inst                5                       # number of overall misses
+system.l2c.overall_misses::cpu3.inst                8                       # number of overall misses
 system.l2c.overall_misses::cpu3.data               13                       # number of overall misses
-system.l2c.overall_misses::total                  677                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.inst     18817000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data      3930500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst      4612000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data       366000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.inst       304000                       # number of ReadReq miss cycles
+system.l2c.overall_misses::total                  681                       # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu0.inst     19255500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.data      4177000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst      4495500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data       377500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.inst       449500                       # number of ReadReq miss cycles
 system.l2c.ReadReq_miss_latency::cpu2.data        52500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu3.inst       254000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu3.inst       388000                       # number of ReadReq miss cycles
 system.l2c.ReadReq_miss_latency::cpu3.data        52500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total       28388500                       # number of ReadReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data      4938500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data       681500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu2.data       629500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu3.data       628000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total      6877500                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.inst     18817000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data      8869000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst      4612000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data      1047500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.inst       304000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.data       682000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.inst       254000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.data       680500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total        35266000                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.inst     18817000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data      8869000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst      4612000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data      1047500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.inst       304000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.data       682000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.inst       254000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.data       680500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total       35266000                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.inst            599                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data             80                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_miss_latency::total       29248000                       # number of ReadReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data      5163500                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data       751000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu2.data       663000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu3.data       658499                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total      7235999                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu0.inst     19255500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data      9340500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst      4495500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data      1128500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.inst       449500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.data       715500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3.inst       388000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3.data       710999                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total        36483999                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.inst     19255500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data      9340500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst      4495500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data      1128500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.inst       449500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.data       715500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.inst       388000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.data       710999                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total       36483999                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.inst            602                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data             79                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::cpu1.inst            436                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::cpu1.data             12                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::cpu2.inst            438                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::cpu2.data             12                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu3.inst            436                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu3.inst            439                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::cpu3.data             12                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total               2025                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total               2030                       # number of ReadReq accesses(hits+misses)
 system.l2c.Writeback_accesses::writebacks            1                       # number of Writeback accesses(hits+misses)
 system.l2c.Writeback_accesses::total                1                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data           26                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data           20                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2.data           19                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data           23                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data           15                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu2.data           21                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::cpu3.data           19                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total              84                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total              78                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::cpu0.data           94                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::cpu1.data           13                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::cpu2.data           12                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::cpu3.data           12                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::total              131                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst             599                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data             174                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst             602                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data             173                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu1.inst             436                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu1.data              25                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu2.inst             438                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu2.data              24                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.inst             436                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.inst             439                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu3.data              24                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total                2156                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst            599                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data            174                       # number of overall (read+write) accesses
+system.l2c.demand_accesses::total                2161                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst            602                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data            173                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu1.inst            436                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu1.data             25                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu2.inst            438                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu2.data             24                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.inst            436                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.inst            439                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu3.data             24                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total               2156                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.602671                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.937500                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.204128                       # miss rate for ReadReq accesses
+system.l2c.overall_accesses::total               2161                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.602990                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.936709                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.197248                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu1.data      0.583333                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.inst      0.015982                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.inst      0.022831                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu2.data      0.083333                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu3.inst      0.011468                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu3.inst      0.018223                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu3.data      0.083333                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.269630                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.884615                       # miss rate for UpgradeReq accesses
+system.l2c.ReadReq_miss_rate::total          0.270936                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.869565                       # miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_miss_rate::cpu2.data            1                       # miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_miss_rate::cpu3.data            1                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.964286                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.961538                       # miss rate for UpgradeReq accesses
 system.l2c.ReadExReq_miss_rate::cpu0.data            1                       # miss rate for ReadExReq accesses
 system.l2c.ReadExReq_miss_rate::cpu1.data            1                       # miss rate for ReadExReq accesses
 system.l2c.ReadExReq_miss_rate::cpu2.data            1                       # miss rate for ReadExReq accesses
 system.l2c.ReadExReq_miss_rate::cpu3.data            1                       # miss rate for ReadExReq accesses
 system.l2c.ReadExReq_miss_rate::total               1                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.602671                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.971264                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.204128                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.602990                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.971098                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.197248                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu1.data       0.800000                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst       0.015982                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.inst       0.022831                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu2.data       0.541667                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.inst       0.011468                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.inst       0.018223                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu3.data       0.541667                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.314007                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.602671                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.971264                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.204128                       # miss rate for overall accesses
+system.l2c.demand_miss_rate::total           0.315132                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.602990                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.971098                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.197248                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu1.data      0.800000                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst      0.015982                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.inst      0.022831                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu2.data      0.541667                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.inst      0.011468                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.inst      0.018223                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu3.data      0.541667                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.314007                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52124.653740                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 52406.666667                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51820.224719                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 52285.714286                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.inst 43428.571429                       # average ReadReq miss latency
+system.l2c.overall_miss_rate::total          0.315132                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53045.454545                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.data 56445.945946                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52273.255814                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 53928.571429                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.inst        44950                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu2.data        52500                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu3.inst        50800                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu3.inst        48500                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu3.data        52500                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 51993.589744                       # average ReadReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52537.234043                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52423.076923                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52458.333333                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52333.333333                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total        52500                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 52124.653740                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 52479.289941                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 51820.224719                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data        52375                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.inst 43428.571429                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.data 52461.538462                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.inst        50800                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.data 52346.153846                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 52091.580502                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 52124.653740                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 52479.289941                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 51820.224719                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data        52375                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.inst 43428.571429                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.data 52461.538462                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.inst        50800                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.data 52346.153846                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 52091.580502                       # average overall miss latency
+system.l2c.ReadReq_avg_miss_latency::total 53178.181818                       # average ReadReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 54930.851064                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 57769.230769                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu2.data        55250                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu3.data 54874.916667                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 55236.633588                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 53045.454545                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 55598.214286                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 52273.255814                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data        56425                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.inst        44950                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.data 55038.461538                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.inst        48500                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.data 54692.230769                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 53574.154185                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 53045.454545                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 55598.214286                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 52273.255814                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data        56425                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.inst        44950                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.data 55038.461538                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.inst        48500                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.data 54692.230769                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 53574.154185                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -2203,166 +2203,166 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.ReadReq_mshr_hits::cpu1.inst             1                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu1.inst             2                       # number of ReadReq MSHR hits
 system.l2c.ReadReq_mshr_hits::cpu2.inst             5                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu3.inst             1                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total                 7                       # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst              1                       # number of demand (read+write) MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu3.inst             2                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::total                 9                       # number of ReadReq MSHR hits
+system.l2c.demand_mshr_hits::cpu1.inst              2                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_hits::cpu2.inst              5                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu3.inst              1                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                  7                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst             1                       # number of overall MSHR hits
+system.l2c.demand_mshr_hits::cpu3.inst              2                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                  9                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu1.inst             2                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::cpu2.inst             5                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu3.inst             1                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                 7                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu0.inst          361                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.data           75                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst           88                       # number of ReadReq MSHR misses
+system.l2c.overall_mshr_hits::cpu3.inst             2                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total                 9                       # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses::cpu0.inst          363                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.data           74                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.inst           84                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu1.data            7                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.inst            2                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.inst            5                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu2.data            1                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu3.inst            4                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu3.inst            6                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu3.data            1                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total             539                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data           23                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data           20                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu2.data           19                       # number of UpgradeReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total             541                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data           20                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data           15                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu2.data           21                       # number of UpgradeReq MSHR misses
 system.l2c.UpgradeReq_mshr_misses::cpu3.data           19                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total           81                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total           75                       # number of UpgradeReq MSHR misses
 system.l2c.ReadExReq_mshr_misses::cpu0.data           94                       # number of ReadExReq MSHR misses
 system.l2c.ReadExReq_mshr_misses::cpu1.data           13                       # number of ReadExReq MSHR misses
 system.l2c.ReadExReq_mshr_misses::cpu2.data           12                       # number of ReadExReq MSHR misses
 system.l2c.ReadExReq_mshr_misses::cpu3.data           12                       # number of ReadExReq MSHR misses
 system.l2c.ReadExReq_mshr_misses::total           131                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst          361                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data          169                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst           88                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst          363                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data          168                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst           84                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu1.data           20                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.inst            2                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.inst            5                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu2.data           13                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu3.inst            4                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu3.inst            6                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu3.data           13                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total              670                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst          361                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data          169                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst           88                       # number of overall MSHR misses
+system.l2c.demand_mshr_misses::total              672                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst          363                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data          168                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst           84                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu1.data           20                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.inst            2                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.inst            5                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu2.data           13                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu3.inst            4                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu3.inst            6                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu3.data           13                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total             670                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst     14412000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.data      3017000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst      3521000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data       280000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.inst        80000                       # number of ReadReq MSHR miss cycles
+system.l2c.overall_mshr_misses::total             672                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst     14840000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.data      3282500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst      3420000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data       291500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.inst       200000                       # number of ReadReq MSHR miss cycles
 system.l2c.ReadReq_mshr_miss_latency::cpu2.data        40000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu3.inst       160000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu3.inst       240000                       # number of ReadReq MSHR miss cycles
 system.l2c.ReadReq_mshr_miss_latency::cpu3.data        40000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total     21550000                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data       920000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data       800000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data       760000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data       760500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total      3240500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data      3791500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data       522500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu2.data       483500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu3.data       481500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total      5279000                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst     14412000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data      6808500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst      3521000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data       802500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.inst        80000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.data       523500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.inst       160000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.data       521500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total     26829000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst     14412000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data      6808500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst      3521000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data       802500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.inst        80000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.data       523500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.inst       160000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.data       521500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total     26829000                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.602671                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.937500                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.201835                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_latency::total     22354000                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data       800000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data       600000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data       844000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data       765000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total      3009000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data      4019000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data       593500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2.data       516500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu3.data       511500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total      5640500                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst     14840000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data      7301500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst      3420000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data       885000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.inst       200000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.data       556500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.inst       240000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.data       551500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total     27994500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst     14840000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data      7301500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst      3420000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data       885000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.inst       200000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.data       556500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.inst       240000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.data       551500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total     27994500                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.602990                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.936709                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.192661                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.583333                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.004566                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.011416                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.083333                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu3.inst     0.009174                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu3.inst     0.013667                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::cpu3.data     0.083333                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.266173                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.884615                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.266502                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.869565                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.964286                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.961538                       # mshr miss rate for UpgradeReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.602671                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.971264                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.201835                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.602990                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.971098                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.192661                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu1.data     0.800000                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst     0.004566                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst     0.011416                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu2.data     0.541667                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.inst     0.009174                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.inst     0.013667                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu3.data     0.541667                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.310761                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.602671                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.971264                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.201835                       # mshr miss rate for overall accesses
+system.l2c.demand_mshr_miss_rate::total      0.310967                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.602990                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.971098                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.192661                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu1.data     0.800000                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst     0.004566                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst     0.011416                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu2.data     0.541667                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.inst     0.009174                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.inst     0.013667                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu3.data     0.541667                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.310761                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39922.437673                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40226.666667                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40011.363636                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data        40000                       # average ReadReq mshr miss latency
+system.l2c.overall_mshr_miss_rate::total     0.310967                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40881.542700                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 44358.108108                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40714.285714                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 41642.857143                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst        40000                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data        40000                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst        40000                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data        40000                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 39981.447124                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 41319.778189                       # average ReadReq mshr miss latency
 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data        40000                       # average UpgradeReq mshr miss latency
 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data        40000                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data        40000                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40026.315789                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40006.172840                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40335.106383                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40192.307692                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40291.666667                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data        40125                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 40297.709924                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39922.437673                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40286.982249                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40011.363636                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data        40125                       # average overall mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40190.476190                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40263.157895                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total        40120                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 42755.319149                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 45653.846154                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 43041.666667                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data        42625                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 43057.251908                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40881.542700                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 43461.309524                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40714.285714                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data        44250                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu2.inst        40000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40269.230769                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 42807.692308                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu3.inst        40000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40115.384615                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 40043.283582                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39922.437673                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40286.982249                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40011.363636                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data        40125                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.data 42423.076923                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 41658.482143                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40881.542700                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 43461.309524                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40714.285714                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data        44250                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu2.inst        40000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40269.230769                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 42807.692308                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu3.inst        40000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40115.384615                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 40043.283582                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.data 42423.076923                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 41658.482143                       # average overall mshr miss latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
index cf4b383de..55888365a 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
@@ -449,7 +449,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.physmem.port[0]
 slave=system.l2c.mem_side system.system_port
 
@@ -471,7 +471,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.l2c.cpu_side
 slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
 
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
index 145ab230c..900805018 100755
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:06:58
-gem5 started Jun 28 2012 22:54:12
+gem5 compiled Jul  2 2012 08:54:18
+gem5 started Jul  2 2012 11:32:06
 gem5 executing on zizzer
 command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp
 Global frequency set at 1000000000000 ticks per second
@@ -10,73 +10,73 @@ info: Entering event queue @ 0.  Starting simulation...
 Init done
 [Iteration 1, Thread 1] Got lock
 [Iteration 1, Thread 1] Critical section done, previously next=0, now next=1
-[Iteration 1, Thread 3] Got lock
-[Iteration 1, Thread 3] Critical section done, previously next=1, now next=3
 [Iteration 1, Thread 2] Got lock
-[Iteration 1, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 1, Thread 2] Critical section done, previously next=1, now next=2
+[Iteration 1, Thread 3] Got lock
+[Iteration 1, Thread 3] Critical section done, previously next=2, now next=3
 Iteration 1 completed
-[Iteration 2, Thread 2] Got lock
-[Iteration 2, Thread 2] Critical section done, previously next=0, now next=2
-[Iteration 2, Thread 3] Got lock
-[Iteration 2, Thread 3] Critical section done, previously next=2, now next=3
 [Iteration 2, Thread 1] Got lock
-[Iteration 2, Thread 1] Critical section done, previously next=3, now next=1
+[Iteration 2, Thread 1] Critical section done, previously next=0, now next=1
+[Iteration 2, Thread 3] Got lock
+[Iteration 2, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 2, Thread 2] Got lock
+[Iteration 2, Thread 2] Critical section done, previously next=3, now next=2
 Iteration 2 completed
+[Iteration 3, Thread 1] Got lock
+[Iteration 3, Thread 1] Critical section done, previously next=0, now next=1
 [Iteration 3, Thread 3] Got lock
-[Iteration 3, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 3, Thread 3] Critical section done, previously next=1, now next=3
 [Iteration 3, Thread 2] Got lock
 [Iteration 3, Thread 2] Critical section done, previously next=3, now next=2
-[Iteration 3, Thread 1] Got lock
-[Iteration 3, Thread 1] Critical section done, previously next=2, now next=1
 Iteration 3 completed
-[Iteration 4, Thread 2] Got lock
-[Iteration 4, Thread 2] Critical section done, previously next=0, now next=2
-[Iteration 4, Thread 3] Got lock
-[Iteration 4, Thread 3] Critical section done, previously next=2, now next=3
 [Iteration 4, Thread 1] Got lock
-[Iteration 4, Thread 1] Critical section done, previously next=3, now next=1
+[Iteration 4, Thread 1] Critical section done, previously next=0, now next=1
+[Iteration 4, Thread 3] Got lock
+[Iteration 4, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 4, Thread 2] Got lock
+[Iteration 4, Thread 2] Critical section done, previously next=3, now next=2
 Iteration 4 completed
+[Iteration 5, Thread 1] Got lock
+[Iteration 5, Thread 1] Critical section done, previously next=0, now next=1
 [Iteration 5, Thread 3] Got lock
-[Iteration 5, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 5, Thread 3] Critical section done, previously next=1, now next=3
 [Iteration 5, Thread 2] Got lock
 [Iteration 5, Thread 2] Critical section done, previously next=3, now next=2
-[Iteration 5, Thread 1] Got lock
-[Iteration 5, Thread 1] Critical section done, previously next=2, now next=1
 Iteration 5 completed
-[Iteration 6, Thread 2] Got lock
-[Iteration 6, Thread 2] Critical section done, previously next=0, now next=2
-[Iteration 6, Thread 3] Got lock
-[Iteration 6, Thread 3] Critical section done, previously next=2, now next=3
 [Iteration 6, Thread 1] Got lock
-[Iteration 6, Thread 1] Critical section done, previously next=3, now next=1
+[Iteration 6, Thread 1] Critical section done, previously next=0, now next=1
+[Iteration 6, Thread 3] Got lock
+[Iteration 6, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 6, Thread 2] Got lock
+[Iteration 6, Thread 2] Critical section done, previously next=3, now next=2
 Iteration 6 completed
+[Iteration 7, Thread 1] Got lock
+[Iteration 7, Thread 1] Critical section done, previously next=0, now next=1
 [Iteration 7, Thread 3] Got lock
-[Iteration 7, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 7, Thread 3] Critical section done, previously next=1, now next=3
 [Iteration 7, Thread 2] Got lock
 [Iteration 7, Thread 2] Critical section done, previously next=3, now next=2
-[Iteration 7, Thread 1] Got lock
-[Iteration 7, Thread 1] Critical section done, previously next=2, now next=1
 Iteration 7 completed
-[Iteration 8, Thread 2] Got lock
-[Iteration 8, Thread 2] Critical section done, previously next=0, now next=2
-[Iteration 8, Thread 3] Got lock
-[Iteration 8, Thread 3] Critical section done, previously next=2, now next=3
 [Iteration 8, Thread 1] Got lock
-[Iteration 8, Thread 1] Critical section done, previously next=3, now next=1
+[Iteration 8, Thread 1] Critical section done, previously next=0, now next=1
+[Iteration 8, Thread 3] Got lock
+[Iteration 8, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 8, Thread 2] Got lock
+[Iteration 8, Thread 2] Critical section done, previously next=3, now next=2
 Iteration 8 completed
+[Iteration 9, Thread 1] Got lock
+[Iteration 9, Thread 1] Critical section done, previously next=0, now next=1
 [Iteration 9, Thread 3] Got lock
-[Iteration 9, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 9, Thread 3] Critical section done, previously next=1, now next=3
 [Iteration 9, Thread 2] Got lock
 [Iteration 9, Thread 2] Critical section done, previously next=3, now next=2
-[Iteration 9, Thread 1] Got lock
-[Iteration 9, Thread 1] Critical section done, previously next=2, now next=1
 Iteration 9 completed
-[Iteration 10, Thread 2] Got lock
-[Iteration 10, Thread 2] Critical section done, previously next=0, now next=2
 [Iteration 10, Thread 1] Got lock
-[Iteration 10, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 10, Thread 1] Critical section done, previously next=0, now next=1
+[Iteration 10, Thread 2] Got lock
+[Iteration 10, Thread 2] Critical section done, previously next=1, now next=2
 [Iteration 10, Thread 3] Got lock
-[Iteration 10, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 10, Thread 3] Critical section done, previously next=2, now next=3
 Iteration 10 completed
 PASSED :-)
-Exiting @ tick 262299000 because target called exit()
+Exiting @ tick 268912000 because target called exit()
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
index c654a221f..ea05c2e9c 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
@@ -1,130 +1,130 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000262                       # Number of seconds simulated
-sim_ticks                                   262299000                       # Number of ticks simulated
-final_tick                                  262299000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000269                       # Number of seconds simulated
+sim_ticks                                   268912000                       # Number of ticks simulated
+final_tick                                  268912000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1271827                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1271784                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              503510999                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 230932                       # Number of bytes of host memory used
-host_seconds                                     0.52                       # Real time elapsed on the host
-sim_insts                                      662502                       # Number of instructions simulated
-sim_ops                                        662502                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 548575                       # Simulator instruction rate (inst/s)
+host_op_rate                                   548567                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              220132321                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 230896                       # Number of bytes of host memory used
+host_seconds                                     1.22                       # Real time elapsed on the host
+sim_insts                                      670117                       # Number of instructions simulated
+sim_ops                                        670117                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu0.inst            18240                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.data            10560                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.inst             3776                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.data             1408                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst              576                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data             1024                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.inst               64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.data              960                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst              128                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data              960                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.inst              512                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.data             1024                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                36608                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read::cpu0.inst        18240                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::cpu1.inst         3776                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst          576                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu3.inst           64                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst          128                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu3.inst          512                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total           22656                       # Number of instructions bytes read from this memory
 system.physmem.num_reads::cpu0.inst               285                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.data               165                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.inst                59                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.data                22                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst                 9                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data                16                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.inst                 1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.data                15                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst                 2                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data                15                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.inst                 8                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.data                16                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   572                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu0.inst            69538961                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            40259399                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst            14395785                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             5367920                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst             2195967                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data             3903942                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst              243996                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data             3659945                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               139565915                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst       69538961                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst       14395785                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst        2195967                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst         243996                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total           86374710                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst           69538961                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           40259399                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst           14395785                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            5367920                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst            2195967                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data            3903942                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst             243996                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data            3659945                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              139565915                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst            67828881                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data            39269352                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst            14041768                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             5235914                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst              475992                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data             3569941                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.inst             1903969                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.data             3807937                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               136133754                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst       67828881                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst       14041768                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst         475992                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu3.inst        1903969                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total           84250610                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst           67828881                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           39269352                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst           14041768                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            5235914                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst             475992                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data            3569941                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.inst            1903969                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.data            3807937                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              136133754                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu0.workload.num_syscalls                  89                       # Number of system calls
-system.cpu0.numCycles                          524598                       # number of cpu cycles simulated
+system.cpu0.numCycles                          537824                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                     158353                       # Number of instructions committed
-system.cpu0.committedOps                       158353                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses               109064                       # Number of integer alu accesses
+system.cpu0.committedInsts                     160927                       # Number of instructions committed
+system.cpu0.committedOps                       160927                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses               110780                       # Number of integer alu accesses
 system.cpu0.num_fp_alu_accesses                     0                       # Number of float alu accesses
 system.cpu0.num_func_calls                        390                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts        25994                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                      109064                       # number of integer instructions
+system.cpu0.num_conditional_control_insts        26423                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                      110780                       # number of integer instructions
 system.cpu0.num_fp_insts                            0                       # number of float instructions
-system.cpu0.num_int_register_reads             315336                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes            110671                       # number of times the integer registers were written
+system.cpu0.num_int_register_reads             320484                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes            112387                       # number of times the integer registers were written
 system.cpu0.num_fp_register_reads                   0                       # number of times the floating registers were read
 system.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                        73905                       # number of memory refs
-system.cpu0.num_load_insts                      48930                       # Number of load instructions
-system.cpu0.num_store_insts                     24975                       # Number of store instructions
+system.cpu0.num_mem_refs                        75192                       # number of memory refs
+system.cpu0.num_load_insts                      49788                       # Number of load instructions
+system.cpu0.num_store_insts                     25404                       # Number of store instructions
 system.cpu0.num_idle_cycles                         0                       # Number of idle cycles
-system.cpu0.num_busy_cycles                    524598                       # Number of busy cycles
+system.cpu0.num_busy_cycles                    537824                       # Number of busy cycles
 system.cpu0.not_idle_fraction                       1                       # Percentage of non-idle cycles
 system.cpu0.idle_fraction                           0                       # Percentage of idle cycles
 system.cpu0.icache.replacements                   215                       # number of replacements
-system.cpu0.icache.tagsinuse               212.479251                       # Cycle average of tags in use
-system.cpu0.icache.total_refs                  157949                       # Total number of references to valid blocks.
+system.cpu0.icache.tagsinuse               212.253377                       # Cycle average of tags in use
+system.cpu0.icache.total_refs                  160523                       # Total number of references to valid blocks.
 system.cpu0.icache.sampled_refs                   467                       # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs                338.220557                       # Average number of references to valid blocks.
+system.cpu0.icache.avg_refs                343.732334                       # Average number of references to valid blocks.
 system.cpu0.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst   212.479251                       # Average occupied blocks per requestor
-system.cpu0.icache.occ_percent::cpu0.inst     0.414999                       # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::total        0.414999                       # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst       157949                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total         157949                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst       157949                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total          157949                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst       157949                       # number of overall hits
-system.cpu0.icache.overall_hits::total         157949                       # number of overall hits
+system.cpu0.icache.occ_blocks::cpu0.inst   212.253377                       # Average occupied blocks per requestor
+system.cpu0.icache.occ_percent::cpu0.inst     0.414557                       # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::total        0.414557                       # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits::cpu0.inst       160523                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total         160523                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst       160523                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total          160523                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst       160523                       # number of overall hits
+system.cpu0.icache.overall_hits::total         160523                       # number of overall hits
 system.cpu0.icache.ReadReq_misses::cpu0.inst          467                       # number of ReadReq misses
 system.cpu0.icache.ReadReq_misses::total          467                       # number of ReadReq misses
 system.cpu0.icache.demand_misses::cpu0.inst          467                       # number of demand (read+write) misses
 system.cpu0.icache.demand_misses::total           467                       # number of demand (read+write) misses
 system.cpu0.icache.overall_misses::cpu0.inst          467                       # number of overall misses
 system.cpu0.icache.overall_misses::total          467                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst     18524000                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total     18524000                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst     18524000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total     18524000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst     18524000                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total     18524000                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst       158416                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total       158416                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst       158416                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total       158416                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst       158416                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total       158416                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.002948                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.002948                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.002948                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.002948                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.002948                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.002948                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 39665.952891                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 39665.952891                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 39665.952891                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 39665.952891                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 39665.952891                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 39665.952891                       # average overall miss latency
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst     18554000                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total     18554000                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst     18554000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total     18554000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst     18554000                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total     18554000                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst       160990                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total       160990                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst       160990                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total       160990                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst       160990                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total       160990                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.002901                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.002901                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.002901                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.002901                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.002901                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.002901                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 39730.192719                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 39730.192719                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 39730.192719                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 39730.192719                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 39730.192719                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 39730.192719                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -139,44 +139,44 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst          467
 system.cpu0.icache.demand_mshr_misses::total          467                       # number of demand (read+write) MSHR misses
 system.cpu0.icache.overall_mshr_misses::cpu0.inst          467                       # number of overall MSHR misses
 system.cpu0.icache.overall_mshr_misses::total          467                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst     17123000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total     17123000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst     17123000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total     17123000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst     17123000                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total     17123000                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.002948                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.002948                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.002948                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.002948                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.002948                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.002948                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36665.952891                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36665.952891                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36665.952891                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 36665.952891                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36665.952891                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 36665.952891                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst     17153000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total     17153000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst     17153000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total     17153000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst     17153000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total     17153000                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.002901                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.002901                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.002901                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.002901                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.002901                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.002901                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36730.192719                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36730.192719                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36730.192719                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 36730.192719                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36730.192719                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 36730.192719                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu0.dcache.replacements                     2                       # number of replacements
-system.cpu0.dcache.tagsinuse               145.603716                       # Cycle average of tags in use
-system.cpu0.dcache.total_refs                   73381                       # Total number of references to valid blocks.
+system.cpu0.dcache.tagsinuse               145.513886                       # Cycle average of tags in use
+system.cpu0.dcache.total_refs                   74668                       # Total number of references to valid blocks.
 system.cpu0.dcache.sampled_refs                   167                       # Sample count of references to valid blocks.
-system.cpu0.dcache.avg_refs                439.407186                       # Average number of references to valid blocks.
+system.cpu0.dcache.avg_refs                447.113772                       # Average number of references to valid blocks.
 system.cpu0.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::cpu0.data   145.603716                       # Average occupied blocks per requestor
-system.cpu0.dcache.occ_percent::cpu0.data     0.284382                       # Average percentage of cache occupancy
-system.cpu0.dcache.occ_percent::total        0.284382                       # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::cpu0.data        48758                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total          48758                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data        24741                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total         24741                       # number of WriteReq hits
+system.cpu0.dcache.occ_blocks::cpu0.data   145.513886                       # Average occupied blocks per requestor
+system.cpu0.dcache.occ_percent::cpu0.data     0.284207                       # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::total        0.284207                       # Average percentage of cache occupancy
+system.cpu0.dcache.ReadReq_hits::cpu0.data        49616                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total          49616                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data        25170                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total         25170                       # number of WriteReq hits
 system.cpu0.dcache.SwapReq_hits::cpu0.data           16                       # number of SwapReq hits
 system.cpu0.dcache.SwapReq_hits::total             16                       # number of SwapReq hits
-system.cpu0.dcache.demand_hits::cpu0.data        73499                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total           73499                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data        73499                       # number of overall hits
-system.cpu0.dcache.overall_hits::total          73499                       # number of overall hits
+system.cpu0.dcache.demand_hits::cpu0.data        74786                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total           74786                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data        74786                       # number of overall hits
+system.cpu0.dcache.overall_hits::total          74786                       # number of overall hits
 system.cpu0.dcache.ReadReq_misses::cpu0.data          162                       # number of ReadReq misses
 system.cpu0.dcache.ReadReq_misses::total          162                       # number of ReadReq misses
 system.cpu0.dcache.WriteReq_misses::cpu0.data          183                       # number of WriteReq misses
@@ -187,46 +187,46 @@ system.cpu0.dcache.demand_misses::cpu0.data          345                       #
 system.cpu0.dcache.demand_misses::total           345                       # number of demand (read+write) misses
 system.cpu0.dcache.overall_misses::cpu0.data          345                       # number of overall misses
 system.cpu0.dcache.overall_misses::total          345                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data      4747000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total      4747000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data      7176000                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total      7176000                       # number of WriteReq miss cycles
-system.cpu0.dcache.SwapReq_miss_latency::cpu0.data       389000                       # number of SwapReq miss cycles
-system.cpu0.dcache.SwapReq_miss_latency::total       389000                       # number of SwapReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data     11923000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total     11923000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data     11923000                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total     11923000                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data        48920                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total        48920                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data        24924                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total        24924                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data      5171000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total      5171000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data      7310000                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total      7310000                       # number of WriteReq miss cycles
+system.cpu0.dcache.SwapReq_miss_latency::cpu0.data       522000                       # number of SwapReq miss cycles
+system.cpu0.dcache.SwapReq_miss_latency::total       522000                       # number of SwapReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data     12481000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total     12481000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data     12481000                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total     12481000                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data        49778                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total        49778                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data        25353                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total        25353                       # number of WriteReq accesses(hits+misses)
 system.cpu0.dcache.SwapReq_accesses::cpu0.data           42                       # number of SwapReq accesses(hits+misses)
 system.cpu0.dcache.SwapReq_accesses::total           42                       # number of SwapReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data        73844                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total        73844                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data        73844                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total        73844                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.003312                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.003312                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.007342                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.007342                       # miss rate for WriteReq accesses
+system.cpu0.dcache.demand_accesses::cpu0.data        75131                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total        75131                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data        75131                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total        75131                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.003254                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.003254                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.007218                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.007218                       # miss rate for WriteReq accesses
 system.cpu0.dcache.SwapReq_miss_rate::cpu0.data     0.619048                       # miss rate for SwapReq accesses
 system.cpu0.dcache.SwapReq_miss_rate::total     0.619048                       # miss rate for SwapReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.004672                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.004672                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.004672                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.004672                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 29302.469136                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 29302.469136                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39213.114754                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 39213.114754                       # average WriteReq miss latency
-system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 14961.538462                       # average SwapReq miss latency
-system.cpu0.dcache.SwapReq_avg_miss_latency::total 14961.538462                       # average SwapReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34559.420290                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 34559.420290                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34559.420290                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 34559.420290                       # average overall miss latency
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.004592                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.004592                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.004592                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.004592                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31919.753086                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 31919.753086                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39945.355191                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 39945.355191                       # average WriteReq miss latency
+system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 20076.923077                       # average SwapReq miss latency
+system.cpu0.dcache.SwapReq_avg_miss_latency::total 20076.923077                       # average SwapReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36176.811594                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 36176.811594                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36176.811594                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 36176.811594                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -247,104 +247,104 @@ system.cpu0.dcache.demand_mshr_misses::cpu0.data          345
 system.cpu0.dcache.demand_mshr_misses::total          345                       # number of demand (read+write) MSHR misses
 system.cpu0.dcache.overall_mshr_misses::cpu0.data          345                       # number of overall MSHR misses
 system.cpu0.dcache.overall_mshr_misses::total          345                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data      4261000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total      4261000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data      6627000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total      6627000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data       311000                       # number of SwapReq MSHR miss cycles
-system.cpu0.dcache.SwapReq_mshr_miss_latency::total       311000                       # number of SwapReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data     10888000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total     10888000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data     10888000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total     10888000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.003312                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.003312                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.007342                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.007342                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data      4684001                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total      4684001                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data      6761000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total      6761000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data       444000                       # number of SwapReq MSHR miss cycles
+system.cpu0.dcache.SwapReq_mshr_miss_latency::total       444000                       # number of SwapReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data     11445001                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total     11445001                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data     11445001                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total     11445001                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.003254                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.003254                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.007218                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.007218                       # mshr miss rate for WriteReq accesses
 system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data     0.619048                       # mshr miss rate for SwapReq accesses
 system.cpu0.dcache.SwapReq_mshr_miss_rate::total     0.619048                       # mshr miss rate for SwapReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.004672                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.004672                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.004672                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.004672                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26302.469136                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26302.469136                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36213.114754                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36213.114754                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 11961.538462                       # average SwapReq mshr miss latency
-system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 11961.538462                       # average SwapReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31559.420290                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31559.420290                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31559.420290                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31559.420290                       # average overall mshr miss latency
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.004592                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.004592                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.004592                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.004592                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28913.586420                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28913.586420                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36945.355191                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36945.355191                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17076.923077                       # average SwapReq mshr miss latency
+system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17076.923077                       # average SwapReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 33173.915942                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 33173.915942                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 33173.915942                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 33173.915942                       # average overall mshr miss latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.numCycles                          524598                       # number of cpu cycles simulated
+system.cpu1.numCycles                          537824                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                     172389                       # Number of instructions committed
-system.cpu1.committedOps                       172389                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses               107964                       # Number of integer alu accesses
+system.cpu1.committedInsts                     159902                       # Number of instructions committed
+system.cpu1.committedOps                       159902                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses               114536                       # Number of integer alu accesses
 system.cpu1.num_fp_alu_accesses                     0                       # Number of float alu accesses
 system.cpu1.num_func_calls                        637                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts        36219                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                      107964                       # number of integer instructions
+system.cpu1.num_conditional_control_insts        26689                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                      114536                       # number of integer instructions
 system.cpu1.num_fp_insts                            0                       # number of float instructions
-system.cpu1.num_int_register_reads             249169                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes             92792                       # number of times the integer registers were written
+system.cpu1.num_int_register_reads             313629                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes            121810                       # number of times the integer registers were written
 system.cpu1.num_fp_register_reads                   0                       # number of times the floating registers were read
 system.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                        47914                       # number of memory refs
-system.cpu1.num_load_insts                      39632                       # Number of load instructions
-system.cpu1.num_store_insts                      8282                       # Number of store instructions
-system.cpu1.num_idle_cycles              68732.001738                       # Number of idle cycles
-system.cpu1.num_busy_cycles              455865.998262                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.868982                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.131018                       # Percentage of idle cycles
+system.cpu1.num_mem_refs                        64016                       # number of memory refs
+system.cpu1.num_load_insts                      42937                       # Number of load instructions
+system.cpu1.num_store_insts                     21079                       # Number of store instructions
+system.cpu1.num_idle_cycles              71606.001734                       # Number of idle cycles
+system.cpu1.num_busy_cycles              466217.998266                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.866860                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.133140                       # Percentage of idle cycles
 system.cpu1.icache.replacements                   280                       # number of replacements
-system.cpu1.icache.tagsinuse                70.077944                       # Cycle average of tags in use
-system.cpu1.icache.total_refs                  172056                       # Total number of references to valid blocks.
+system.cpu1.icache.tagsinuse                69.902178                       # Cycle average of tags in use
+system.cpu1.icache.total_refs                  159569                       # Total number of references to valid blocks.
 system.cpu1.icache.sampled_refs                   366                       # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs                470.098361                       # Average number of references to valid blocks.
+system.cpu1.icache.avg_refs                435.980874                       # Average number of references to valid blocks.
 system.cpu1.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::cpu1.inst    70.077944                       # Average occupied blocks per requestor
-system.cpu1.icache.occ_percent::cpu1.inst     0.136871                       # Average percentage of cache occupancy
-system.cpu1.icache.occ_percent::total        0.136871                       # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst       172056                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total         172056                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst       172056                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total          172056                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst       172056                       # number of overall hits
-system.cpu1.icache.overall_hits::total         172056                       # number of overall hits
+system.cpu1.icache.occ_blocks::cpu1.inst    69.902178                       # Average occupied blocks per requestor
+system.cpu1.icache.occ_percent::cpu1.inst     0.136528                       # Average percentage of cache occupancy
+system.cpu1.icache.occ_percent::total        0.136528                       # Average percentage of cache occupancy
+system.cpu1.icache.ReadReq_hits::cpu1.inst       159569                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total         159569                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst       159569                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total          159569                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst       159569                       # number of overall hits
+system.cpu1.icache.overall_hits::total         159569                       # number of overall hits
 system.cpu1.icache.ReadReq_misses::cpu1.inst          366                       # number of ReadReq misses
 system.cpu1.icache.ReadReq_misses::total          366                       # number of ReadReq misses
 system.cpu1.icache.demand_misses::cpu1.inst          366                       # number of demand (read+write) misses
 system.cpu1.icache.demand_misses::total           366                       # number of demand (read+write) misses
 system.cpu1.icache.overall_misses::cpu1.inst          366                       # number of overall misses
 system.cpu1.icache.overall_misses::total          366                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst      7921500                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total      7921500                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst      7921500                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total      7921500                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst      7921500                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total      7921500                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst       172422                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total       172422                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst       172422                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total       172422                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst       172422                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total       172422                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.002123                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.002123                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.002123                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.002123                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.002123                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.002123                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 21643.442623                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 21643.442623                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 21643.442623                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 21643.442623                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 21643.442623                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 21643.442623                       # average overall miss latency
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst      7984500                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total      7984500                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst      7984500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total      7984500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst      7984500                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total      7984500                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst       159935                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total       159935                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst       159935                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total       159935                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst       159935                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total       159935                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.002288                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.002288                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.002288                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.002288                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.002288                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.002288                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 21815.573770                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 21815.573770                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 21815.573770                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 21815.573770                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 21815.573770                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 21815.573770                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -359,94 +359,94 @@ system.cpu1.icache.demand_mshr_misses::cpu1.inst          366
 system.cpu1.icache.demand_mshr_misses::total          366                       # number of demand (read+write) MSHR misses
 system.cpu1.icache.overall_mshr_misses::cpu1.inst          366                       # number of overall MSHR misses
 system.cpu1.icache.overall_mshr_misses::total          366                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst      6823000                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total      6823000                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst      6823000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total      6823000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst      6823000                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total      6823000                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.002123                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.002123                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.002123                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.002123                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.002123                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.002123                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18642.076503                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18642.076503                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18642.076503                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 18642.076503                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18642.076503                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 18642.076503                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst      6886000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total      6886000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst      6886000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total      6886000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst      6886000                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total      6886000                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.002288                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.002288                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.002288                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.002288                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.002288                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.002288                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18814.207650                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18814.207650                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18814.207650                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 18814.207650                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18814.207650                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 18814.207650                       # average overall mshr miss latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dcache.replacements                     0                       # number of replacements
-system.cpu1.dcache.tagsinuse                27.731444                       # Cycle average of tags in use
-system.cpu1.dcache.total_refs                   18765                       # Total number of references to valid blocks.
+system.cpu1.dcache.tagsinuse                27.730072                       # Cycle average of tags in use
+system.cpu1.dcache.total_refs                   44449                       # Total number of references to valid blocks.
 system.cpu1.dcache.sampled_refs                    29                       # Sample count of references to valid blocks.
-system.cpu1.dcache.avg_refs                647.068966                       # Average number of references to valid blocks.
+system.cpu1.dcache.avg_refs               1532.724138                       # Average number of references to valid blocks.
 system.cpu1.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::cpu1.data    27.731444                       # Average occupied blocks per requestor
-system.cpu1.dcache.occ_percent::cpu1.data     0.054163                       # Average percentage of cache occupancy
-system.cpu1.dcache.occ_percent::total        0.054163                       # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::cpu1.data        39445                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total          39445                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data         8099                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total          8099                       # number of WriteReq hits
-system.cpu1.dcache.SwapReq_hits::cpu1.data           18                       # number of SwapReq hits
-system.cpu1.dcache.SwapReq_hits::total             18                       # number of SwapReq hits
-system.cpu1.dcache.demand_hits::cpu1.data        47544                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total           47544                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data        47544                       # number of overall hits
-system.cpu1.dcache.overall_hits::total          47544                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data          179                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total          179                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data           98                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total           98                       # number of WriteReq misses
-system.cpu1.dcache.SwapReq_misses::cpu1.data           65                       # number of SwapReq misses
-system.cpu1.dcache.SwapReq_misses::total           65                       # number of SwapReq misses
-system.cpu1.dcache.demand_misses::cpu1.data          277                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total           277                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data          277                       # number of overall misses
-system.cpu1.dcache.overall_misses::total          277                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data      3683000                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total      3683000                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data      1838000                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total      1838000                       # number of WriteReq miss cycles
-system.cpu1.dcache.SwapReq_miss_latency::cpu1.data       415000                       # number of SwapReq miss cycles
-system.cpu1.dcache.SwapReq_miss_latency::total       415000                       # number of SwapReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data      5521000                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total      5521000                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data      5521000                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total      5521000                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data        39624                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total        39624                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data         8197                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total         8197                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SwapReq_accesses::cpu1.data           83                       # number of SwapReq accesses(hits+misses)
-system.cpu1.dcache.SwapReq_accesses::total           83                       # number of SwapReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data        47821                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total        47821                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data        47821                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total        47821                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.004517                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.004517                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.011956                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.011956                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SwapReq_miss_rate::cpu1.data     0.783133                       # miss rate for SwapReq accesses
-system.cpu1.dcache.SwapReq_miss_rate::total     0.783133                       # miss rate for SwapReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.005792                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.005792                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.005792                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.005792                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20575.418994                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 20575.418994                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18755.102041                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 18755.102041                       # average WriteReq miss latency
-system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data  6384.615385                       # average SwapReq miss latency
-system.cpu1.dcache.SwapReq_avg_miss_latency::total  6384.615385                       # average SwapReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19931.407942                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 19931.407942                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19931.407942                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 19931.407942                       # average overall miss latency
+system.cpu1.dcache.occ_blocks::cpu1.data    27.730072                       # Average occupied blocks per requestor
+system.cpu1.dcache.occ_percent::cpu1.data     0.054160                       # Average percentage of cache occupancy
+system.cpu1.dcache.occ_percent::total        0.054160                       # Average percentage of cache occupancy
+system.cpu1.dcache.ReadReq_hits::cpu1.data        42776                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total          42776                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data        20903                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total         20903                       # number of WriteReq hits
+system.cpu1.dcache.SwapReq_hits::cpu1.data           10                       # number of SwapReq hits
+system.cpu1.dcache.SwapReq_hits::total             10                       # number of SwapReq hits
+system.cpu1.dcache.demand_hits::cpu1.data        63679                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total           63679                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data        63679                       # number of overall hits
+system.cpu1.dcache.overall_hits::total          63679                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data          153                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total          153                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data          106                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total          106                       # number of WriteReq misses
+system.cpu1.dcache.SwapReq_misses::cpu1.data           58                       # number of SwapReq misses
+system.cpu1.dcache.SwapReq_misses::total           58                       # number of SwapReq misses
+system.cpu1.dcache.demand_misses::cpu1.data          259                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total           259                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data          259                       # number of overall misses
+system.cpu1.dcache.overall_misses::total          259                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data      3030000                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total      3030000                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data      2410000                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total      2410000                       # number of WriteReq miss cycles
+system.cpu1.dcache.SwapReq_miss_latency::cpu1.data       772000                       # number of SwapReq miss cycles
+system.cpu1.dcache.SwapReq_miss_latency::total       772000                       # number of SwapReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data      5440000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total      5440000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data      5440000                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total      5440000                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data        42929                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total        42929                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data        21009                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total        21009                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SwapReq_accesses::cpu1.data           68                       # number of SwapReq accesses(hits+misses)
+system.cpu1.dcache.SwapReq_accesses::total           68                       # number of SwapReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data        63938                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total        63938                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data        63938                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total        63938                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.003564                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.003564                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.005045                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.005045                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SwapReq_miss_rate::cpu1.data     0.852941                       # miss rate for SwapReq accesses
+system.cpu1.dcache.SwapReq_miss_rate::total     0.852941                       # miss rate for SwapReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.004051                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.004051                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.004051                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.004051                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19803.921569                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 19803.921569                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22735.849057                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 22735.849057                       # average WriteReq miss latency
+system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 13310.344828                       # average SwapReq miss latency
+system.cpu1.dcache.SwapReq_avg_miss_latency::total 13310.344828                       # average SwapReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21003.861004                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 21003.861004                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21003.861004                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 21003.861004                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -455,114 +455,114 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data          179                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total          179                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data           98                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total           98                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data           65                       # number of SwapReq MSHR misses
-system.cpu1.dcache.SwapReq_mshr_misses::total           65                       # number of SwapReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data          277                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total          277                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data          277                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total          277                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data      3146000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total      3146000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data      1544000                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total      1544000                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data       220000                       # number of SwapReq MSHR miss cycles
-system.cpu1.dcache.SwapReq_mshr_miss_latency::total       220000                       # number of SwapReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data      4690000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total      4690000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data      4690000                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total      4690000                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.004517                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.004517                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.011956                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.011956                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data     0.783133                       # mshr miss rate for SwapReq accesses
-system.cpu1.dcache.SwapReq_mshr_miss_rate::total     0.783133                       # mshr miss rate for SwapReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.005792                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.005792                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.005792                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.005792                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17575.418994                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 17575.418994                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15755.102041                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15755.102041                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data  3384.615385                       # average SwapReq mshr miss latency
-system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total  3384.615385                       # average SwapReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16931.407942                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16931.407942                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16931.407942                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16931.407942                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data          153                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total          153                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data          106                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total          106                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data           58                       # number of SwapReq MSHR misses
+system.cpu1.dcache.SwapReq_mshr_misses::total           58                       # number of SwapReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data          259                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total          259                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data          259                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total          259                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data      2570001                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total      2570001                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data      2092000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total      2092000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data       598000                       # number of SwapReq MSHR miss cycles
+system.cpu1.dcache.SwapReq_mshr_miss_latency::total       598000                       # number of SwapReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data      4662001                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total      4662001                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data      4662001                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total      4662001                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.003564                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.003564                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.005045                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.005045                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data     0.852941                       # mshr miss rate for SwapReq accesses
+system.cpu1.dcache.SwapReq_mshr_miss_rate::total     0.852941                       # mshr miss rate for SwapReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.004051                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.004051                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.004051                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.004051                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 16797.392157                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 16797.392157                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19735.849057                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19735.849057                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 10310.344828                       # average SwapReq mshr miss latency
+system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 10310.344828                       # average SwapReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18000.003861                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18000.003861                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18000.003861                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18000.003861                       # average overall mshr miss latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu2.numCycles                          524598                       # number of cpu cycles simulated
+system.cpu2.numCycles                          537824                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.committedInsts                     165564                       # Number of instructions committed
-system.cpu2.committedOps                       165564                       # Number of ops (including micro ops) committed
-system.cpu2.num_int_alu_accesses               112387                       # Number of integer alu accesses
+system.cpu2.committedInsts                     177221                       # Number of instructions committed
+system.cpu2.committedOps                       177221                       # Number of ops (including micro ops) committed
+system.cpu2.num_int_alu_accesses               109567                       # Number of integer alu accesses
 system.cpu2.num_fp_alu_accesses                     0                       # Number of float alu accesses
 system.cpu2.num_func_calls                        637                       # number of times a function call or return occured
-system.cpu2.num_conditional_control_insts        30599                       # number of instructions that are conditional controls
-system.cpu2.num_int_insts                      112387                       # number of integer instructions
+system.cpu2.num_conditional_control_insts        37840                       # number of instructions that are conditional controls
+system.cpu2.num_int_insts                      109567                       # number of integer instructions
 system.cpu2.num_fp_insts                            0                       # number of float instructions
-system.cpu2.num_int_register_reads             289349                       # number of times the integer registers were read
-system.cpu2.num_int_register_writes            110679                       # number of times the integer registers were written
+system.cpu2.num_int_register_reads             249142                       # number of times the integer registers were read
+system.cpu2.num_int_register_writes             92045                       # number of times the integer registers were written
 system.cpu2.num_fp_register_reads                   0                       # number of times the floating registers were read
 system.cpu2.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu2.num_mem_refs                        57957                       # number of memory refs
-system.cpu2.num_load_insts                      41868                       # Number of load instructions
-system.cpu2.num_store_insts                     16089                       # Number of store instructions
-system.cpu2.num_idle_cycles              68998.001737                       # Number of idle cycles
-system.cpu2.num_busy_cycles              455599.998263                       # Number of busy cycles
-system.cpu2.not_idle_fraction                0.868475                       # Percentage of non-idle cycles
-system.cpu2.idle_fraction                    0.131525                       # Percentage of idle cycles
-system.cpu2.icache.replacements                   280                       # number of replacements
-system.cpu2.icache.tagsinuse                65.602896                       # Cycle average of tags in use
-system.cpu2.icache.total_refs                  165231                       # Total number of references to valid blocks.
-system.cpu2.icache.sampled_refs                   366                       # Sample count of references to valid blocks.
-system.cpu2.icache.avg_refs                451.450820                       # Average number of references to valid blocks.
+system.cpu2.num_mem_refs                        47896                       # number of memory refs
+system.cpu2.num_load_insts                      40447                       # Number of load instructions
+system.cpu2.num_store_insts                      7449                       # Number of store instructions
+system.cpu2.num_idle_cycles              71882.001733                       # Number of idle cycles
+system.cpu2.num_busy_cycles              465941.998267                       # Number of busy cycles
+system.cpu2.not_idle_fraction                0.866347                       # Percentage of non-idle cycles
+system.cpu2.idle_fraction                    0.133653                       # Percentage of idle cycles
+system.cpu2.icache.replacements                   281                       # number of replacements
+system.cpu2.icache.tagsinuse                67.531468                       # Cycle average of tags in use
+system.cpu2.icache.total_refs                  176887                       # Total number of references to valid blocks.
+system.cpu2.icache.sampled_refs                   367                       # Sample count of references to valid blocks.
+system.cpu2.icache.avg_refs                481.980926                       # Average number of references to valid blocks.
 system.cpu2.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu2.icache.occ_blocks::cpu2.inst    65.602896                       # Average occupied blocks per requestor
-system.cpu2.icache.occ_percent::cpu2.inst     0.128131                       # Average percentage of cache occupancy
-system.cpu2.icache.occ_percent::total        0.128131                       # Average percentage of cache occupancy
-system.cpu2.icache.ReadReq_hits::cpu2.inst       165231                       # number of ReadReq hits
-system.cpu2.icache.ReadReq_hits::total         165231                       # number of ReadReq hits
-system.cpu2.icache.demand_hits::cpu2.inst       165231                       # number of demand (read+write) hits
-system.cpu2.icache.demand_hits::total          165231                       # number of demand (read+write) hits
-system.cpu2.icache.overall_hits::cpu2.inst       165231                       # number of overall hits
-system.cpu2.icache.overall_hits::total         165231                       # number of overall hits
-system.cpu2.icache.ReadReq_misses::cpu2.inst          366                       # number of ReadReq misses
-system.cpu2.icache.ReadReq_misses::total          366                       # number of ReadReq misses
-system.cpu2.icache.demand_misses::cpu2.inst          366                       # number of demand (read+write) misses
-system.cpu2.icache.demand_misses::total           366                       # number of demand (read+write) misses
-system.cpu2.icache.overall_misses::cpu2.inst          366                       # number of overall misses
-system.cpu2.icache.overall_misses::total          366                       # number of overall misses
-system.cpu2.icache.ReadReq_miss_latency::cpu2.inst      5648500                       # number of ReadReq miss cycles
-system.cpu2.icache.ReadReq_miss_latency::total      5648500                       # number of ReadReq miss cycles
-system.cpu2.icache.demand_miss_latency::cpu2.inst      5648500                       # number of demand (read+write) miss cycles
-system.cpu2.icache.demand_miss_latency::total      5648500                       # number of demand (read+write) miss cycles
-system.cpu2.icache.overall_miss_latency::cpu2.inst      5648500                       # number of overall miss cycles
-system.cpu2.icache.overall_miss_latency::total      5648500                       # number of overall miss cycles
-system.cpu2.icache.ReadReq_accesses::cpu2.inst       165597                       # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.ReadReq_accesses::total       165597                       # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.demand_accesses::cpu2.inst       165597                       # number of demand (read+write) accesses
-system.cpu2.icache.demand_accesses::total       165597                       # number of demand (read+write) accesses
-system.cpu2.icache.overall_accesses::cpu2.inst       165597                       # number of overall (read+write) accesses
-system.cpu2.icache.overall_accesses::total       165597                       # number of overall (read+write) accesses
-system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.002210                       # miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_miss_rate::total     0.002210                       # miss rate for ReadReq accesses
-system.cpu2.icache.demand_miss_rate::cpu2.inst     0.002210                       # miss rate for demand accesses
-system.cpu2.icache.demand_miss_rate::total     0.002210                       # miss rate for demand accesses
-system.cpu2.icache.overall_miss_rate::cpu2.inst     0.002210                       # miss rate for overall accesses
-system.cpu2.icache.overall_miss_rate::total     0.002210                       # miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15433.060109                       # average ReadReq miss latency
-system.cpu2.icache.ReadReq_avg_miss_latency::total 15433.060109                       # average ReadReq miss latency
-system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15433.060109                       # average overall miss latency
-system.cpu2.icache.demand_avg_miss_latency::total 15433.060109                       # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15433.060109                       # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency::total 15433.060109                       # average overall miss latency
+system.cpu2.icache.occ_blocks::cpu2.inst    67.531468                       # Average occupied blocks per requestor
+system.cpu2.icache.occ_percent::cpu2.inst     0.131897                       # Average percentage of cache occupancy
+system.cpu2.icache.occ_percent::total        0.131897                       # Average percentage of cache occupancy
+system.cpu2.icache.ReadReq_hits::cpu2.inst       176887                       # number of ReadReq hits
+system.cpu2.icache.ReadReq_hits::total         176887                       # number of ReadReq hits
+system.cpu2.icache.demand_hits::cpu2.inst       176887                       # number of demand (read+write) hits
+system.cpu2.icache.demand_hits::total          176887                       # number of demand (read+write) hits
+system.cpu2.icache.overall_hits::cpu2.inst       176887                       # number of overall hits
+system.cpu2.icache.overall_hits::total         176887                       # number of overall hits
+system.cpu2.icache.ReadReq_misses::cpu2.inst          367                       # number of ReadReq misses
+system.cpu2.icache.ReadReq_misses::total          367                       # number of ReadReq misses
+system.cpu2.icache.demand_misses::cpu2.inst          367                       # number of demand (read+write) misses
+system.cpu2.icache.demand_misses::total           367                       # number of demand (read+write) misses
+system.cpu2.icache.overall_misses::cpu2.inst          367                       # number of overall misses
+system.cpu2.icache.overall_misses::total          367                       # number of overall misses
+system.cpu2.icache.ReadReq_miss_latency::cpu2.inst      5709500                       # number of ReadReq miss cycles
+system.cpu2.icache.ReadReq_miss_latency::total      5709500                       # number of ReadReq miss cycles
+system.cpu2.icache.demand_miss_latency::cpu2.inst      5709500                       # number of demand (read+write) miss cycles
+system.cpu2.icache.demand_miss_latency::total      5709500                       # number of demand (read+write) miss cycles
+system.cpu2.icache.overall_miss_latency::cpu2.inst      5709500                       # number of overall miss cycles
+system.cpu2.icache.overall_miss_latency::total      5709500                       # number of overall miss cycles
+system.cpu2.icache.ReadReq_accesses::cpu2.inst       177254                       # number of ReadReq accesses(hits+misses)
+system.cpu2.icache.ReadReq_accesses::total       177254                       # number of ReadReq accesses(hits+misses)
+system.cpu2.icache.demand_accesses::cpu2.inst       177254                       # number of demand (read+write) accesses
+system.cpu2.icache.demand_accesses::total       177254                       # number of demand (read+write) accesses
+system.cpu2.icache.overall_accesses::cpu2.inst       177254                       # number of overall (read+write) accesses
+system.cpu2.icache.overall_accesses::total       177254                       # number of overall (read+write) accesses
+system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.002070                       # miss rate for ReadReq accesses
+system.cpu2.icache.ReadReq_miss_rate::total     0.002070                       # miss rate for ReadReq accesses
+system.cpu2.icache.demand_miss_rate::cpu2.inst     0.002070                       # miss rate for demand accesses
+system.cpu2.icache.demand_miss_rate::total     0.002070                       # miss rate for demand accesses
+system.cpu2.icache.overall_miss_rate::cpu2.inst     0.002070                       # miss rate for overall accesses
+system.cpu2.icache.overall_miss_rate::total     0.002070                       # miss rate for overall accesses
+system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15557.220708                       # average ReadReq miss latency
+system.cpu2.icache.ReadReq_avg_miss_latency::total 15557.220708                       # average ReadReq miss latency
+system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15557.220708                       # average overall miss latency
+system.cpu2.icache.demand_avg_miss_latency::total 15557.220708                       # average overall miss latency
+system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15557.220708                       # average overall miss latency
+system.cpu2.icache.overall_avg_miss_latency::total 15557.220708                       # average overall miss latency
 system.cpu2.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu2.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -571,100 +571,100 @@ system.cpu2.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu2.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu2.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst          366                       # number of ReadReq MSHR misses
-system.cpu2.icache.ReadReq_mshr_misses::total          366                       # number of ReadReq MSHR misses
-system.cpu2.icache.demand_mshr_misses::cpu2.inst          366                       # number of demand (read+write) MSHR misses
-system.cpu2.icache.demand_mshr_misses::total          366                       # number of demand (read+write) MSHR misses
-system.cpu2.icache.overall_mshr_misses::cpu2.inst          366                       # number of overall MSHR misses
-system.cpu2.icache.overall_mshr_misses::total          366                       # number of overall MSHR misses
-system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst      4550500                       # number of ReadReq MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_latency::total      4550500                       # number of ReadReq MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst      4550500                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency::total      4550500                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst      4550500                       # number of overall MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::total      4550500                       # number of overall MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.002210                       # mshr miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_mshr_miss_rate::total     0.002210                       # mshr miss rate for ReadReq accesses
-system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst     0.002210                       # mshr miss rate for demand accesses
-system.cpu2.icache.demand_mshr_miss_rate::total     0.002210                       # mshr miss rate for demand accesses
-system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst     0.002210                       # mshr miss rate for overall accesses
-system.cpu2.icache.overall_mshr_miss_rate::total     0.002210                       # mshr miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12433.060109                       # average ReadReq mshr miss latency
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12433.060109                       # average ReadReq mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12433.060109                       # average overall mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::total 12433.060109                       # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12433.060109                       # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::total 12433.060109                       # average overall mshr miss latency
+system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst          367                       # number of ReadReq MSHR misses
+system.cpu2.icache.ReadReq_mshr_misses::total          367                       # number of ReadReq MSHR misses
+system.cpu2.icache.demand_mshr_misses::cpu2.inst          367                       # number of demand (read+write) MSHR misses
+system.cpu2.icache.demand_mshr_misses::total          367                       # number of demand (read+write) MSHR misses
+system.cpu2.icache.overall_mshr_misses::cpu2.inst          367                       # number of overall MSHR misses
+system.cpu2.icache.overall_mshr_misses::total          367                       # number of overall MSHR misses
+system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst      4608500                       # number of ReadReq MSHR miss cycles
+system.cpu2.icache.ReadReq_mshr_miss_latency::total      4608500                       # number of ReadReq MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst      4608500                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_latency::total      4608500                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst      4608500                       # number of overall MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_latency::total      4608500                       # number of overall MSHR miss cycles
+system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.002070                       # mshr miss rate for ReadReq accesses
+system.cpu2.icache.ReadReq_mshr_miss_rate::total     0.002070                       # mshr miss rate for ReadReq accesses
+system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst     0.002070                       # mshr miss rate for demand accesses
+system.cpu2.icache.demand_mshr_miss_rate::total     0.002070                       # mshr miss rate for demand accesses
+system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst     0.002070                       # mshr miss rate for overall accesses
+system.cpu2.icache.overall_mshr_miss_rate::total     0.002070                       # mshr miss rate for overall accesses
+system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12557.220708                       # average ReadReq mshr miss latency
+system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12557.220708                       # average ReadReq mshr miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12557.220708                       # average overall mshr miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency::total 12557.220708                       # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12557.220708                       # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency::total 12557.220708                       # average overall mshr miss latency
 system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu2.dcache.replacements                     0                       # number of replacements
-system.cpu2.dcache.tagsinuse                25.974144                       # Cycle average of tags in use
-system.cpu2.dcache.total_refs                   34436                       # Total number of references to valid blocks.
+system.cpu2.dcache.tagsinuse                26.637011                       # Cycle average of tags in use
+system.cpu2.dcache.total_refs                   17171                       # Total number of references to valid blocks.
 system.cpu2.dcache.sampled_refs                    29                       # Sample count of references to valid blocks.
-system.cpu2.dcache.avg_refs               1187.448276                       # Average number of references to valid blocks.
+system.cpu2.dcache.avg_refs                592.103448                       # Average number of references to valid blocks.
 system.cpu2.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu2.dcache.occ_blocks::cpu2.data    25.974144                       # Average occupied blocks per requestor
-system.cpu2.dcache.occ_percent::cpu2.data     0.050731                       # Average percentage of cache occupancy
-system.cpu2.dcache.occ_percent::total        0.050731                       # Average percentage of cache occupancy
-system.cpu2.dcache.ReadReq_hits::cpu2.data        41706                       # number of ReadReq hits
-system.cpu2.dcache.ReadReq_hits::total          41706                       # number of ReadReq hits
-system.cpu2.dcache.WriteReq_hits::cpu2.data        15916                       # number of WriteReq hits
-system.cpu2.dcache.WriteReq_hits::total         15916                       # number of WriteReq hits
-system.cpu2.dcache.SwapReq_hits::cpu2.data           11                       # number of SwapReq hits
-system.cpu2.dcache.SwapReq_hits::total             11                       # number of SwapReq hits
-system.cpu2.dcache.demand_hits::cpu2.data        57622                       # number of demand (read+write) hits
-system.cpu2.dcache.demand_hits::total           57622                       # number of demand (read+write) hits
-system.cpu2.dcache.overall_hits::cpu2.data        57622                       # number of overall hits
-system.cpu2.dcache.overall_hits::total          57622                       # number of overall hits
-system.cpu2.dcache.ReadReq_misses::cpu2.data          154                       # number of ReadReq misses
-system.cpu2.dcache.ReadReq_misses::total          154                       # number of ReadReq misses
-system.cpu2.dcache.WriteReq_misses::cpu2.data          109                       # number of WriteReq misses
-system.cpu2.dcache.WriteReq_misses::total          109                       # number of WriteReq misses
+system.cpu2.dcache.occ_blocks::cpu2.data    26.637011                       # Average occupied blocks per requestor
+system.cpu2.dcache.occ_percent::cpu2.data     0.052025                       # Average percentage of cache occupancy
+system.cpu2.dcache.occ_percent::total        0.052025                       # Average percentage of cache occupancy
+system.cpu2.dcache.ReadReq_hits::cpu2.data        40266                       # number of ReadReq hits
+system.cpu2.dcache.ReadReq_hits::total          40266                       # number of ReadReq hits
+system.cpu2.dcache.WriteReq_hits::cpu2.data         7273                       # number of WriteReq hits
+system.cpu2.dcache.WriteReq_hits::total          7273                       # number of WriteReq hits
+system.cpu2.dcache.SwapReq_hits::cpu2.data           18                       # number of SwapReq hits
+system.cpu2.dcache.SwapReq_hits::total             18                       # number of SwapReq hits
+system.cpu2.dcache.demand_hits::cpu2.data        47539                       # number of demand (read+write) hits
+system.cpu2.dcache.demand_hits::total           47539                       # number of demand (read+write) hits
+system.cpu2.dcache.overall_hits::cpu2.data        47539                       # number of overall hits
+system.cpu2.dcache.overall_hits::total          47539                       # number of overall hits
+system.cpu2.dcache.ReadReq_misses::cpu2.data          173                       # number of ReadReq misses
+system.cpu2.dcache.ReadReq_misses::total          173                       # number of ReadReq misses
+system.cpu2.dcache.WriteReq_misses::cpu2.data          105                       # number of WriteReq misses
+system.cpu2.dcache.WriteReq_misses::total          105                       # number of WriteReq misses
 system.cpu2.dcache.SwapReq_misses::cpu2.data           51                       # number of SwapReq misses
 system.cpu2.dcache.SwapReq_misses::total           51                       # number of SwapReq misses
-system.cpu2.dcache.demand_misses::cpu2.data          263                       # number of demand (read+write) misses
-system.cpu2.dcache.demand_misses::total           263                       # number of demand (read+write) misses
-system.cpu2.dcache.overall_misses::cpu2.data          263                       # number of overall misses
-system.cpu2.dcache.overall_misses::total          263                       # number of overall misses
-system.cpu2.dcache.ReadReq_miss_latency::cpu2.data      2498000                       # number of ReadReq miss cycles
-system.cpu2.dcache.ReadReq_miss_latency::total      2498000                       # number of ReadReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency::cpu2.data      2031000                       # number of WriteReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency::total      2031000                       # number of WriteReq miss cycles
-system.cpu2.dcache.SwapReq_miss_latency::cpu2.data       305000                       # number of SwapReq miss cycles
-system.cpu2.dcache.SwapReq_miss_latency::total       305000                       # number of SwapReq miss cycles
-system.cpu2.dcache.demand_miss_latency::cpu2.data      4529000                       # number of demand (read+write) miss cycles
-system.cpu2.dcache.demand_miss_latency::total      4529000                       # number of demand (read+write) miss cycles
-system.cpu2.dcache.overall_miss_latency::cpu2.data      4529000                       # number of overall miss cycles
-system.cpu2.dcache.overall_miss_latency::total      4529000                       # number of overall miss cycles
-system.cpu2.dcache.ReadReq_accesses::cpu2.data        41860                       # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.ReadReq_accesses::total        41860                       # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::cpu2.data        16025                       # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::total        16025                       # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.SwapReq_accesses::cpu2.data           62                       # number of SwapReq accesses(hits+misses)
-system.cpu2.dcache.SwapReq_accesses::total           62                       # number of SwapReq accesses(hits+misses)
-system.cpu2.dcache.demand_accesses::cpu2.data        57885                       # number of demand (read+write) accesses
-system.cpu2.dcache.demand_accesses::total        57885                       # number of demand (read+write) accesses
-system.cpu2.dcache.overall_accesses::cpu2.data        57885                       # number of overall (read+write) accesses
-system.cpu2.dcache.overall_accesses::total        57885                       # number of overall (read+write) accesses
-system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.003679                       # miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_miss_rate::total     0.003679                       # miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.006802                       # miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::total     0.006802                       # miss rate for WriteReq accesses
-system.cpu2.dcache.SwapReq_miss_rate::cpu2.data     0.822581                       # miss rate for SwapReq accesses
-system.cpu2.dcache.SwapReq_miss_rate::total     0.822581                       # miss rate for SwapReq accesses
-system.cpu2.dcache.demand_miss_rate::cpu2.data     0.004543                       # miss rate for demand accesses
-system.cpu2.dcache.demand_miss_rate::total     0.004543                       # miss rate for demand accesses
-system.cpu2.dcache.overall_miss_rate::cpu2.data     0.004543                       # miss rate for overall accesses
-system.cpu2.dcache.overall_miss_rate::total     0.004543                       # miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16220.779221                       # average ReadReq miss latency
-system.cpu2.dcache.ReadReq_avg_miss_latency::total 16220.779221                       # average ReadReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 18633.027523                       # average WriteReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency::total 18633.027523                       # average WriteReq miss latency
-system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data  5980.392157                       # average SwapReq miss latency
-system.cpu2.dcache.SwapReq_avg_miss_latency::total  5980.392157                       # average SwapReq miss latency
-system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17220.532319                       # average overall miss latency
-system.cpu2.dcache.demand_avg_miss_latency::total 17220.532319                       # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17220.532319                       # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::total 17220.532319                       # average overall miss latency
+system.cpu2.dcache.demand_misses::cpu2.data          278                       # number of demand (read+write) misses
+system.cpu2.dcache.demand_misses::total           278                       # number of demand (read+write) misses
+system.cpu2.dcache.overall_misses::cpu2.data          278                       # number of overall misses
+system.cpu2.dcache.overall_misses::total          278                       # number of overall misses
+system.cpu2.dcache.ReadReq_miss_latency::cpu2.data      3995000                       # number of ReadReq miss cycles
+system.cpu2.dcache.ReadReq_miss_latency::total      3995000                       # number of ReadReq miss cycles
+system.cpu2.dcache.WriteReq_miss_latency::cpu2.data      2318000                       # number of WriteReq miss cycles
+system.cpu2.dcache.WriteReq_miss_latency::total      2318000                       # number of WriteReq miss cycles
+system.cpu2.dcache.SwapReq_miss_latency::cpu2.data       814000                       # number of SwapReq miss cycles
+system.cpu2.dcache.SwapReq_miss_latency::total       814000                       # number of SwapReq miss cycles
+system.cpu2.dcache.demand_miss_latency::cpu2.data      6313000                       # number of demand (read+write) miss cycles
+system.cpu2.dcache.demand_miss_latency::total      6313000                       # number of demand (read+write) miss cycles
+system.cpu2.dcache.overall_miss_latency::cpu2.data      6313000                       # number of overall miss cycles
+system.cpu2.dcache.overall_miss_latency::total      6313000                       # number of overall miss cycles
+system.cpu2.dcache.ReadReq_accesses::cpu2.data        40439                       # number of ReadReq accesses(hits+misses)
+system.cpu2.dcache.ReadReq_accesses::total        40439                       # number of ReadReq accesses(hits+misses)
+system.cpu2.dcache.WriteReq_accesses::cpu2.data         7378                       # number of WriteReq accesses(hits+misses)
+system.cpu2.dcache.WriteReq_accesses::total         7378                       # number of WriteReq accesses(hits+misses)
+system.cpu2.dcache.SwapReq_accesses::cpu2.data           69                       # number of SwapReq accesses(hits+misses)
+system.cpu2.dcache.SwapReq_accesses::total           69                       # number of SwapReq accesses(hits+misses)
+system.cpu2.dcache.demand_accesses::cpu2.data        47817                       # number of demand (read+write) accesses
+system.cpu2.dcache.demand_accesses::total        47817                       # number of demand (read+write) accesses
+system.cpu2.dcache.overall_accesses::cpu2.data        47817                       # number of overall (read+write) accesses
+system.cpu2.dcache.overall_accesses::total        47817                       # number of overall (read+write) accesses
+system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.004278                       # miss rate for ReadReq accesses
+system.cpu2.dcache.ReadReq_miss_rate::total     0.004278                       # miss rate for ReadReq accesses
+system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.014231                       # miss rate for WriteReq accesses
+system.cpu2.dcache.WriteReq_miss_rate::total     0.014231                       # miss rate for WriteReq accesses
+system.cpu2.dcache.SwapReq_miss_rate::cpu2.data     0.739130                       # miss rate for SwapReq accesses
+system.cpu2.dcache.SwapReq_miss_rate::total     0.739130                       # miss rate for SwapReq accesses
+system.cpu2.dcache.demand_miss_rate::cpu2.data     0.005814                       # miss rate for demand accesses
+system.cpu2.dcache.demand_miss_rate::total     0.005814                       # miss rate for demand accesses
+system.cpu2.dcache.overall_miss_rate::cpu2.data     0.005814                       # miss rate for overall accesses
+system.cpu2.dcache.overall_miss_rate::total     0.005814                       # miss rate for overall accesses
+system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 23092.485549                       # average ReadReq miss latency
+system.cpu2.dcache.ReadReq_avg_miss_latency::total 23092.485549                       # average ReadReq miss latency
+system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 22076.190476                       # average WriteReq miss latency
+system.cpu2.dcache.WriteReq_avg_miss_latency::total 22076.190476                       # average WriteReq miss latency
+system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 15960.784314                       # average SwapReq miss latency
+system.cpu2.dcache.SwapReq_avg_miss_latency::total 15960.784314                       # average SwapReq miss latency
+system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 22708.633094                       # average overall miss latency
+system.cpu2.dcache.demand_avg_miss_latency::total 22708.633094                       # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 22708.633094                       # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency::total 22708.633094                       # average overall miss latency
 system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -673,114 +673,114 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu2.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu2.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data          154                       # number of ReadReq MSHR misses
-system.cpu2.dcache.ReadReq_mshr_misses::total          154                       # number of ReadReq MSHR misses
-system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data          109                       # number of WriteReq MSHR misses
-system.cpu2.dcache.WriteReq_mshr_misses::total          109                       # number of WriteReq MSHR misses
+system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data          173                       # number of ReadReq MSHR misses
+system.cpu2.dcache.ReadReq_mshr_misses::total          173                       # number of ReadReq MSHR misses
+system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data          105                       # number of WriteReq MSHR misses
+system.cpu2.dcache.WriteReq_mshr_misses::total          105                       # number of WriteReq MSHR misses
 system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data           51                       # number of SwapReq MSHR misses
 system.cpu2.dcache.SwapReq_mshr_misses::total           51                       # number of SwapReq MSHR misses
-system.cpu2.dcache.demand_mshr_misses::cpu2.data          263                       # number of demand (read+write) MSHR misses
-system.cpu2.dcache.demand_mshr_misses::total          263                       # number of demand (read+write) MSHR misses
-system.cpu2.dcache.overall_mshr_misses::cpu2.data          263                       # number of overall MSHR misses
-system.cpu2.dcache.overall_mshr_misses::total          263                       # number of overall MSHR misses
-system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data      2036000                       # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_latency::total      2036000                       # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data      1704000                       # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::total      1704000                       # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data       152000                       # number of SwapReq MSHR miss cycles
-system.cpu2.dcache.SwapReq_mshr_miss_latency::total       152000                       # number of SwapReq MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data      3740000                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::total      3740000                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data      3740000                       # number of overall MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::total      3740000                       # number of overall MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.003679                       # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_mshr_miss_rate::total     0.003679                       # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.006802                       # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate::total     0.006802                       # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data     0.822581                       # mshr miss rate for SwapReq accesses
-system.cpu2.dcache.SwapReq_mshr_miss_rate::total     0.822581                       # mshr miss rate for SwapReq accesses
-system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data     0.004543                       # mshr miss rate for demand accesses
-system.cpu2.dcache.demand_mshr_miss_rate::total     0.004543                       # mshr miss rate for demand accesses
-system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data     0.004543                       # mshr miss rate for overall accesses
-system.cpu2.dcache.overall_mshr_miss_rate::total     0.004543                       # mshr miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13220.779221                       # average ReadReq mshr miss latency
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 13220.779221                       # average ReadReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15633.027523                       # average WriteReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15633.027523                       # average WriteReq mshr miss latency
-system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data  2980.392157                       # average SwapReq mshr miss latency
-system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total  2980.392157                       # average SwapReq mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 14220.532319                       # average overall mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::total 14220.532319                       # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 14220.532319                       # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::total 14220.532319                       # average overall mshr miss latency
+system.cpu2.dcache.demand_mshr_misses::cpu2.data          278                       # number of demand (read+write) MSHR misses
+system.cpu2.dcache.demand_mshr_misses::total          278                       # number of demand (read+write) MSHR misses
+system.cpu2.dcache.overall_mshr_misses::cpu2.data          278                       # number of overall MSHR misses
+system.cpu2.dcache.overall_mshr_misses::total          278                       # number of overall MSHR misses
+system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data      3476000                       # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_latency::total      3476000                       # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data      2003000                       # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_latency::total      2003000                       # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data       661000                       # number of SwapReq MSHR miss cycles
+system.cpu2.dcache.SwapReq_mshr_miss_latency::total       661000                       # number of SwapReq MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data      5479000                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency::total      5479000                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data      5479000                       # number of overall MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::total      5479000                       # number of overall MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.004278                       # mshr miss rate for ReadReq accesses
+system.cpu2.dcache.ReadReq_mshr_miss_rate::total     0.004278                       # mshr miss rate for ReadReq accesses
+system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.014231                       # mshr miss rate for WriteReq accesses
+system.cpu2.dcache.WriteReq_mshr_miss_rate::total     0.014231                       # mshr miss rate for WriteReq accesses
+system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data     0.739130                       # mshr miss rate for SwapReq accesses
+system.cpu2.dcache.SwapReq_mshr_miss_rate::total     0.739130                       # mshr miss rate for SwapReq accesses
+system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data     0.005814                       # mshr miss rate for demand accesses
+system.cpu2.dcache.demand_mshr_miss_rate::total     0.005814                       # mshr miss rate for demand accesses
+system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data     0.005814                       # mshr miss rate for overall accesses
+system.cpu2.dcache.overall_mshr_miss_rate::total     0.005814                       # mshr miss rate for overall accesses
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 20092.485549                       # average ReadReq mshr miss latency
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 20092.485549                       # average ReadReq mshr miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 19076.190476                       # average WriteReq mshr miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 19076.190476                       # average WriteReq mshr miss latency
+system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 12960.784314                       # average SwapReq mshr miss latency
+system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 12960.784314                       # average SwapReq mshr miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 19708.633094                       # average overall mshr miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency::total 19708.633094                       # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 19708.633094                       # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency::total 19708.633094                       # average overall mshr miss latency
 system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu3.numCycles                          524598                       # number of cpu cycles simulated
+system.cpu3.numCycles                          537824                       # number of cpu cycles simulated
 system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu3.committedInsts                     166196                       # Number of instructions committed
-system.cpu3.committedOps                       166196                       # Number of ops (including micro ops) committed
-system.cpu3.num_int_alu_accesses               112131                       # Number of integer alu accesses
+system.cpu3.committedInsts                     172067                       # Number of instructions committed
+system.cpu3.committedOps                       172067                       # Number of ops (including micro ops) committed
+system.cpu3.num_int_alu_accesses               111206                       # Number of integer alu accesses
 system.cpu3.num_fp_alu_accesses                     0                       # Number of float alu accesses
 system.cpu3.num_func_calls                        637                       # number of times a function call or return occured
-system.cpu3.num_conditional_control_insts        31040                       # number of instructions that are conditional controls
-system.cpu3.num_int_insts                      112131                       # number of integer instructions
+system.cpu3.num_conditional_control_insts        34437                       # number of instructions that are conditional controls
+system.cpu3.num_int_insts                      111206                       # number of integer instructions
 system.cpu3.num_fp_insts                            0                       # number of float instructions
-system.cpu3.num_int_register_reads             286557                       # number of times the integer registers were read
-system.cpu3.num_int_register_writes            109409                       # number of times the integer registers were written
+system.cpu3.num_int_register_reads             269314                       # number of times the integer registers were read
+system.cpu3.num_int_register_writes            101322                       # number of times the integer registers were written
 system.cpu3.num_fp_register_reads                   0                       # number of times the floating registers were read
 system.cpu3.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu3.num_mem_refs                        57260                       # number of memory refs
-system.cpu3.num_load_insts                      41737                       # Number of load instructions
-system.cpu3.num_store_insts                     15523                       # Number of store instructions
-system.cpu3.num_idle_cycles              69252.001736                       # Number of idle cycles
-system.cpu3.num_busy_cycles              455345.998264                       # Number of busy cycles
-system.cpu3.not_idle_fraction                0.867990                       # Percentage of non-idle cycles
-system.cpu3.idle_fraction                    0.132010                       # Percentage of idle cycles
-system.cpu3.icache.replacements                   281                       # number of replacements
-system.cpu3.icache.tagsinuse                67.739564                       # Cycle average of tags in use
-system.cpu3.icache.total_refs                  165862                       # Total number of references to valid blocks.
-system.cpu3.icache.sampled_refs                   367                       # Sample count of references to valid blocks.
-system.cpu3.icache.avg_refs                451.940054                       # Average number of references to valid blocks.
+system.cpu3.num_mem_refs                        52937                       # number of memory refs
+system.cpu3.num_load_insts                      41268                       # Number of load instructions
+system.cpu3.num_store_insts                     11669                       # Number of store instructions
+system.cpu3.num_idle_cycles              72158.001732                       # Number of idle cycles
+system.cpu3.num_busy_cycles              465665.998268                       # Number of busy cycles
+system.cpu3.not_idle_fraction                0.865833                       # Percentage of non-idle cycles
+system.cpu3.idle_fraction                    0.134167                       # Percentage of idle cycles
+system.cpu3.icache.replacements                   280                       # number of replacements
+system.cpu3.icache.tagsinuse                65.342080                       # Cycle average of tags in use
+system.cpu3.icache.total_refs                  171734                       # Total number of references to valid blocks.
+system.cpu3.icache.sampled_refs                   366                       # Sample count of references to valid blocks.
+system.cpu3.icache.avg_refs                469.218579                       # Average number of references to valid blocks.
 system.cpu3.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu3.icache.occ_blocks::cpu3.inst    67.739564                       # Average occupied blocks per requestor
-system.cpu3.icache.occ_percent::cpu3.inst     0.132304                       # Average percentage of cache occupancy
-system.cpu3.icache.occ_percent::total        0.132304                       # Average percentage of cache occupancy
-system.cpu3.icache.ReadReq_hits::cpu3.inst       165862                       # number of ReadReq hits
-system.cpu3.icache.ReadReq_hits::total         165862                       # number of ReadReq hits
-system.cpu3.icache.demand_hits::cpu3.inst       165862                       # number of demand (read+write) hits
-system.cpu3.icache.demand_hits::total          165862                       # number of demand (read+write) hits
-system.cpu3.icache.overall_hits::cpu3.inst       165862                       # number of overall hits
-system.cpu3.icache.overall_hits::total         165862                       # number of overall hits
-system.cpu3.icache.ReadReq_misses::cpu3.inst          367                       # number of ReadReq misses
-system.cpu3.icache.ReadReq_misses::total          367                       # number of ReadReq misses
-system.cpu3.icache.demand_misses::cpu3.inst          367                       # number of demand (read+write) misses
-system.cpu3.icache.demand_misses::total           367                       # number of demand (read+write) misses
-system.cpu3.icache.overall_misses::cpu3.inst          367                       # number of overall misses
-system.cpu3.icache.overall_misses::total          367                       # number of overall misses
-system.cpu3.icache.ReadReq_miss_latency::cpu3.inst      5533500                       # number of ReadReq miss cycles
-system.cpu3.icache.ReadReq_miss_latency::total      5533500                       # number of ReadReq miss cycles
-system.cpu3.icache.demand_miss_latency::cpu3.inst      5533500                       # number of demand (read+write) miss cycles
-system.cpu3.icache.demand_miss_latency::total      5533500                       # number of demand (read+write) miss cycles
-system.cpu3.icache.overall_miss_latency::cpu3.inst      5533500                       # number of overall miss cycles
-system.cpu3.icache.overall_miss_latency::total      5533500                       # number of overall miss cycles
-system.cpu3.icache.ReadReq_accesses::cpu3.inst       166229                       # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.ReadReq_accesses::total       166229                       # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.demand_accesses::cpu3.inst       166229                       # number of demand (read+write) accesses
-system.cpu3.icache.demand_accesses::total       166229                       # number of demand (read+write) accesses
-system.cpu3.icache.overall_accesses::cpu3.inst       166229                       # number of overall (read+write) accesses
-system.cpu3.icache.overall_accesses::total       166229                       # number of overall (read+write) accesses
-system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.002208                       # miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_miss_rate::total     0.002208                       # miss rate for ReadReq accesses
-system.cpu3.icache.demand_miss_rate::cpu3.inst     0.002208                       # miss rate for demand accesses
-system.cpu3.icache.demand_miss_rate::total     0.002208                       # miss rate for demand accesses
-system.cpu3.icache.overall_miss_rate::cpu3.inst     0.002208                       # miss rate for overall accesses
-system.cpu3.icache.overall_miss_rate::total     0.002208                       # miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 15077.656676                       # average ReadReq miss latency
-system.cpu3.icache.ReadReq_avg_miss_latency::total 15077.656676                       # average ReadReq miss latency
-system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 15077.656676                       # average overall miss latency
-system.cpu3.icache.demand_avg_miss_latency::total 15077.656676                       # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 15077.656676                       # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency::total 15077.656676                       # average overall miss latency
+system.cpu3.icache.occ_blocks::cpu3.inst    65.342080                       # Average occupied blocks per requestor
+system.cpu3.icache.occ_percent::cpu3.inst     0.127621                       # Average percentage of cache occupancy
+system.cpu3.icache.occ_percent::total        0.127621                       # Average percentage of cache occupancy
+system.cpu3.icache.ReadReq_hits::cpu3.inst       171734                       # number of ReadReq hits
+system.cpu3.icache.ReadReq_hits::total         171734                       # number of ReadReq hits
+system.cpu3.icache.demand_hits::cpu3.inst       171734                       # number of demand (read+write) hits
+system.cpu3.icache.demand_hits::total          171734                       # number of demand (read+write) hits
+system.cpu3.icache.overall_hits::cpu3.inst       171734                       # number of overall hits
+system.cpu3.icache.overall_hits::total         171734                       # number of overall hits
+system.cpu3.icache.ReadReq_misses::cpu3.inst          366                       # number of ReadReq misses
+system.cpu3.icache.ReadReq_misses::total          366                       # number of ReadReq misses
+system.cpu3.icache.demand_misses::cpu3.inst          366                       # number of demand (read+write) misses
+system.cpu3.icache.demand_misses::total           366                       # number of demand (read+write) misses
+system.cpu3.icache.overall_misses::cpu3.inst          366                       # number of overall misses
+system.cpu3.icache.overall_misses::total          366                       # number of overall misses
+system.cpu3.icache.ReadReq_miss_latency::cpu3.inst      5645500                       # number of ReadReq miss cycles
+system.cpu3.icache.ReadReq_miss_latency::total      5645500                       # number of ReadReq miss cycles
+system.cpu3.icache.demand_miss_latency::cpu3.inst      5645500                       # number of demand (read+write) miss cycles
+system.cpu3.icache.demand_miss_latency::total      5645500                       # number of demand (read+write) miss cycles
+system.cpu3.icache.overall_miss_latency::cpu3.inst      5645500                       # number of overall miss cycles
+system.cpu3.icache.overall_miss_latency::total      5645500                       # number of overall miss cycles
+system.cpu3.icache.ReadReq_accesses::cpu3.inst       172100                       # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.ReadReq_accesses::total       172100                       # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.demand_accesses::cpu3.inst       172100                       # number of demand (read+write) accesses
+system.cpu3.icache.demand_accesses::total       172100                       # number of demand (read+write) accesses
+system.cpu3.icache.overall_accesses::cpu3.inst       172100                       # number of overall (read+write) accesses
+system.cpu3.icache.overall_accesses::total       172100                       # number of overall (read+write) accesses
+system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.002127                       # miss rate for ReadReq accesses
+system.cpu3.icache.ReadReq_miss_rate::total     0.002127                       # miss rate for ReadReq accesses
+system.cpu3.icache.demand_miss_rate::cpu3.inst     0.002127                       # miss rate for demand accesses
+system.cpu3.icache.demand_miss_rate::total     0.002127                       # miss rate for demand accesses
+system.cpu3.icache.overall_miss_rate::cpu3.inst     0.002127                       # miss rate for overall accesses
+system.cpu3.icache.overall_miss_rate::total     0.002127                       # miss rate for overall accesses
+system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 15424.863388                       # average ReadReq miss latency
+system.cpu3.icache.ReadReq_avg_miss_latency::total 15424.863388                       # average ReadReq miss latency
+system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 15424.863388                       # average overall miss latency
+system.cpu3.icache.demand_avg_miss_latency::total 15424.863388                       # average overall miss latency
+system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 15424.863388                       # average overall miss latency
+system.cpu3.icache.overall_avg_miss_latency::total 15424.863388                       # average overall miss latency
 system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -789,100 +789,100 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu3.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu3.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu3.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst          367                       # number of ReadReq MSHR misses
-system.cpu3.icache.ReadReq_mshr_misses::total          367                       # number of ReadReq MSHR misses
-system.cpu3.icache.demand_mshr_misses::cpu3.inst          367                       # number of demand (read+write) MSHR misses
-system.cpu3.icache.demand_mshr_misses::total          367                       # number of demand (read+write) MSHR misses
-system.cpu3.icache.overall_mshr_misses::cpu3.inst          367                       # number of overall MSHR misses
-system.cpu3.icache.overall_mshr_misses::total          367                       # number of overall MSHR misses
-system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst      4432500                       # number of ReadReq MSHR miss cycles
-system.cpu3.icache.ReadReq_mshr_miss_latency::total      4432500                       # number of ReadReq MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst      4432500                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_latency::total      4432500                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst      4432500                       # number of overall MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency::total      4432500                       # number of overall MSHR miss cycles
-system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.002208                       # mshr miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_mshr_miss_rate::total     0.002208                       # mshr miss rate for ReadReq accesses
-system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst     0.002208                       # mshr miss rate for demand accesses
-system.cpu3.icache.demand_mshr_miss_rate::total     0.002208                       # mshr miss rate for demand accesses
-system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst     0.002208                       # mshr miss rate for overall accesses
-system.cpu3.icache.overall_mshr_miss_rate::total     0.002208                       # mshr miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12077.656676                       # average ReadReq mshr miss latency
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12077.656676                       # average ReadReq mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12077.656676                       # average overall mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency::total 12077.656676                       # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12077.656676                       # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency::total 12077.656676                       # average overall mshr miss latency
+system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst          366                       # number of ReadReq MSHR misses
+system.cpu3.icache.ReadReq_mshr_misses::total          366                       # number of ReadReq MSHR misses
+system.cpu3.icache.demand_mshr_misses::cpu3.inst          366                       # number of demand (read+write) MSHR misses
+system.cpu3.icache.demand_mshr_misses::total          366                       # number of demand (read+write) MSHR misses
+system.cpu3.icache.overall_mshr_misses::cpu3.inst          366                       # number of overall MSHR misses
+system.cpu3.icache.overall_mshr_misses::total          366                       # number of overall MSHR misses
+system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst      4547000                       # number of ReadReq MSHR miss cycles
+system.cpu3.icache.ReadReq_mshr_miss_latency::total      4547000                       # number of ReadReq MSHR miss cycles
+system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst      4547000                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.icache.demand_mshr_miss_latency::total      4547000                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst      4547000                       # number of overall MSHR miss cycles
+system.cpu3.icache.overall_mshr_miss_latency::total      4547000                       # number of overall MSHR miss cycles
+system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.002127                       # mshr miss rate for ReadReq accesses
+system.cpu3.icache.ReadReq_mshr_miss_rate::total     0.002127                       # mshr miss rate for ReadReq accesses
+system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst     0.002127                       # mshr miss rate for demand accesses
+system.cpu3.icache.demand_mshr_miss_rate::total     0.002127                       # mshr miss rate for demand accesses
+system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst     0.002127                       # mshr miss rate for overall accesses
+system.cpu3.icache.overall_mshr_miss_rate::total     0.002127                       # mshr miss rate for overall accesses
+system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12423.497268                       # average ReadReq mshr miss latency
+system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12423.497268                       # average ReadReq mshr miss latency
+system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12423.497268                       # average overall mshr miss latency
+system.cpu3.icache.demand_avg_mshr_miss_latency::total 12423.497268                       # average overall mshr miss latency
+system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12423.497268                       # average overall mshr miss latency
+system.cpu3.icache.overall_avg_mshr_miss_latency::total 12423.497268                       # average overall mshr miss latency
 system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu3.dcache.replacements                     0                       # number of replacements
-system.cpu3.dcache.tagsinuse                26.774212                       # Cycle average of tags in use
-system.cpu3.dcache.total_refs                   33417                       # Total number of references to valid blocks.
+system.cpu3.dcache.tagsinuse                25.848817                       # Cycle average of tags in use
+system.cpu3.dcache.total_refs                   25744                       # Total number of references to valid blocks.
 system.cpu3.dcache.sampled_refs                    30                       # Sample count of references to valid blocks.
-system.cpu3.dcache.avg_refs               1113.900000                       # Average number of references to valid blocks.
+system.cpu3.dcache.avg_refs                858.133333                       # Average number of references to valid blocks.
 system.cpu3.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu3.dcache.occ_blocks::cpu3.data    26.774212                       # Average occupied blocks per requestor
-system.cpu3.dcache.occ_percent::cpu3.data     0.052293                       # Average percentage of cache occupancy
-system.cpu3.dcache.occ_percent::total        0.052293                       # Average percentage of cache occupancy
-system.cpu3.dcache.ReadReq_hits::cpu3.data        41574                       # number of ReadReq hits
-system.cpu3.dcache.ReadReq_hits::total          41574                       # number of ReadReq hits
-system.cpu3.dcache.WriteReq_hits::cpu3.data        15348                       # number of WriteReq hits
-system.cpu3.dcache.WriteReq_hits::total         15348                       # number of WriteReq hits
-system.cpu3.dcache.SwapReq_hits::cpu3.data           11                       # number of SwapReq hits
-system.cpu3.dcache.SwapReq_hits::total             11                       # number of SwapReq hits
-system.cpu3.dcache.demand_hits::cpu3.data        56922                       # number of demand (read+write) hits
-system.cpu3.dcache.demand_hits::total           56922                       # number of demand (read+write) hits
-system.cpu3.dcache.overall_hits::cpu3.data        56922                       # number of overall hits
-system.cpu3.dcache.overall_hits::total          56922                       # number of overall hits
-system.cpu3.dcache.ReadReq_misses::cpu3.data          155                       # number of ReadReq misses
-system.cpu3.dcache.ReadReq_misses::total          155                       # number of ReadReq misses
-system.cpu3.dcache.WriteReq_misses::cpu3.data          108                       # number of WriteReq misses
-system.cpu3.dcache.WriteReq_misses::total          108                       # number of WriteReq misses
-system.cpu3.dcache.SwapReq_misses::cpu3.data           54                       # number of SwapReq misses
-system.cpu3.dcache.SwapReq_misses::total           54                       # number of SwapReq misses
-system.cpu3.dcache.demand_misses::cpu3.data          263                       # number of demand (read+write) misses
-system.cpu3.dcache.demand_misses::total           263                       # number of demand (read+write) misses
-system.cpu3.dcache.overall_misses::cpu3.data          263                       # number of overall misses
-system.cpu3.dcache.overall_misses::total          263                       # number of overall misses
-system.cpu3.dcache.ReadReq_miss_latency::cpu3.data      2537000                       # number of ReadReq miss cycles
-system.cpu3.dcache.ReadReq_miss_latency::total      2537000                       # number of ReadReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency::cpu3.data      2026000                       # number of WriteReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency::total      2026000                       # number of WriteReq miss cycles
-system.cpu3.dcache.SwapReq_miss_latency::cpu3.data       326000                       # number of SwapReq miss cycles
-system.cpu3.dcache.SwapReq_miss_latency::total       326000                       # number of SwapReq miss cycles
-system.cpu3.dcache.demand_miss_latency::cpu3.data      4563000                       # number of demand (read+write) miss cycles
-system.cpu3.dcache.demand_miss_latency::total      4563000                       # number of demand (read+write) miss cycles
-system.cpu3.dcache.overall_miss_latency::cpu3.data      4563000                       # number of overall miss cycles
-system.cpu3.dcache.overall_miss_latency::total      4563000                       # number of overall miss cycles
-system.cpu3.dcache.ReadReq_accesses::cpu3.data        41729                       # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.ReadReq_accesses::total        41729                       # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::cpu3.data        15456                       # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::total        15456                       # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.SwapReq_accesses::cpu3.data           65                       # number of SwapReq accesses(hits+misses)
-system.cpu3.dcache.SwapReq_accesses::total           65                       # number of SwapReq accesses(hits+misses)
-system.cpu3.dcache.demand_accesses::cpu3.data        57185                       # number of demand (read+write) accesses
-system.cpu3.dcache.demand_accesses::total        57185                       # number of demand (read+write) accesses
-system.cpu3.dcache.overall_accesses::cpu3.data        57185                       # number of overall (read+write) accesses
-system.cpu3.dcache.overall_accesses::total        57185                       # number of overall (read+write) accesses
-system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.003714                       # miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_miss_rate::total     0.003714                       # miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.006988                       # miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::total     0.006988                       # miss rate for WriteReq accesses
-system.cpu3.dcache.SwapReq_miss_rate::cpu3.data     0.830769                       # miss rate for SwapReq accesses
-system.cpu3.dcache.SwapReq_miss_rate::total     0.830769                       # miss rate for SwapReq accesses
-system.cpu3.dcache.demand_miss_rate::cpu3.data     0.004599                       # miss rate for demand accesses
-system.cpu3.dcache.demand_miss_rate::total     0.004599                       # miss rate for demand accesses
-system.cpu3.dcache.overall_miss_rate::cpu3.data     0.004599                       # miss rate for overall accesses
-system.cpu3.dcache.overall_miss_rate::total     0.004599                       # miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 16367.741935                       # average ReadReq miss latency
-system.cpu3.dcache.ReadReq_avg_miss_latency::total 16367.741935                       # average ReadReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 18759.259259                       # average WriteReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::total 18759.259259                       # average WriteReq miss latency
-system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data  6037.037037                       # average SwapReq miss latency
-system.cpu3.dcache.SwapReq_avg_miss_latency::total  6037.037037                       # average SwapReq miss latency
-system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 17349.809886                       # average overall miss latency
-system.cpu3.dcache.demand_avg_miss_latency::total 17349.809886                       # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 17349.809886                       # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::total 17349.809886                       # average overall miss latency
+system.cpu3.dcache.occ_blocks::cpu3.data    25.848817                       # Average occupied blocks per requestor
+system.cpu3.dcache.occ_percent::cpu3.data     0.050486                       # Average percentage of cache occupancy
+system.cpu3.dcache.occ_percent::total        0.050486                       # Average percentage of cache occupancy
+system.cpu3.dcache.ReadReq_hits::cpu3.data        41084                       # number of ReadReq hits
+system.cpu3.dcache.ReadReq_hits::total          41084                       # number of ReadReq hits
+system.cpu3.dcache.WriteReq_hits::cpu3.data        11491                       # number of WriteReq hits
+system.cpu3.dcache.WriteReq_hits::total         11491                       # number of WriteReq hits
+system.cpu3.dcache.SwapReq_hits::cpu3.data           12                       # number of SwapReq hits
+system.cpu3.dcache.SwapReq_hits::total             12                       # number of SwapReq hits
+system.cpu3.dcache.demand_hits::cpu3.data        52575                       # number of demand (read+write) hits
+system.cpu3.dcache.demand_hits::total           52575                       # number of demand (read+write) hits
+system.cpu3.dcache.overall_hits::cpu3.data        52575                       # number of overall hits
+system.cpu3.dcache.overall_hits::total          52575                       # number of overall hits
+system.cpu3.dcache.ReadReq_misses::cpu3.data          176                       # number of ReadReq misses
+system.cpu3.dcache.ReadReq_misses::total          176                       # number of ReadReq misses
+system.cpu3.dcache.WriteReq_misses::cpu3.data          105                       # number of WriteReq misses
+system.cpu3.dcache.WriteReq_misses::total          105                       # number of WriteReq misses
+system.cpu3.dcache.SwapReq_misses::cpu3.data           59                       # number of SwapReq misses
+system.cpu3.dcache.SwapReq_misses::total           59                       # number of SwapReq misses
+system.cpu3.dcache.demand_misses::cpu3.data          281                       # number of demand (read+write) misses
+system.cpu3.dcache.demand_misses::total           281                       # number of demand (read+write) misses
+system.cpu3.dcache.overall_misses::cpu3.data          281                       # number of overall misses
+system.cpu3.dcache.overall_misses::total          281                       # number of overall misses
+system.cpu3.dcache.ReadReq_miss_latency::cpu3.data      4401000                       # number of ReadReq miss cycles
+system.cpu3.dcache.ReadReq_miss_latency::total      4401000                       # number of ReadReq miss cycles
+system.cpu3.dcache.WriteReq_miss_latency::cpu3.data      1861000                       # number of WriteReq miss cycles
+system.cpu3.dcache.WriteReq_miss_latency::total      1861000                       # number of WriteReq miss cycles
+system.cpu3.dcache.SwapReq_miss_latency::cpu3.data       928000                       # number of SwapReq miss cycles
+system.cpu3.dcache.SwapReq_miss_latency::total       928000                       # number of SwapReq miss cycles
+system.cpu3.dcache.demand_miss_latency::cpu3.data      6262000                       # number of demand (read+write) miss cycles
+system.cpu3.dcache.demand_miss_latency::total      6262000                       # number of demand (read+write) miss cycles
+system.cpu3.dcache.overall_miss_latency::cpu3.data      6262000                       # number of overall miss cycles
+system.cpu3.dcache.overall_miss_latency::total      6262000                       # number of overall miss cycles
+system.cpu3.dcache.ReadReq_accesses::cpu3.data        41260                       # number of ReadReq accesses(hits+misses)
+system.cpu3.dcache.ReadReq_accesses::total        41260                       # number of ReadReq accesses(hits+misses)
+system.cpu3.dcache.WriteReq_accesses::cpu3.data        11596                       # number of WriteReq accesses(hits+misses)
+system.cpu3.dcache.WriteReq_accesses::total        11596                       # number of WriteReq accesses(hits+misses)
+system.cpu3.dcache.SwapReq_accesses::cpu3.data           71                       # number of SwapReq accesses(hits+misses)
+system.cpu3.dcache.SwapReq_accesses::total           71                       # number of SwapReq accesses(hits+misses)
+system.cpu3.dcache.demand_accesses::cpu3.data        52856                       # number of demand (read+write) accesses
+system.cpu3.dcache.demand_accesses::total        52856                       # number of demand (read+write) accesses
+system.cpu3.dcache.overall_accesses::cpu3.data        52856                       # number of overall (read+write) accesses
+system.cpu3.dcache.overall_accesses::total        52856                       # number of overall (read+write) accesses
+system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.004266                       # miss rate for ReadReq accesses
+system.cpu3.dcache.ReadReq_miss_rate::total     0.004266                       # miss rate for ReadReq accesses
+system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.009055                       # miss rate for WriteReq accesses
+system.cpu3.dcache.WriteReq_miss_rate::total     0.009055                       # miss rate for WriteReq accesses
+system.cpu3.dcache.SwapReq_miss_rate::cpu3.data     0.830986                       # miss rate for SwapReq accesses
+system.cpu3.dcache.SwapReq_miss_rate::total     0.830986                       # miss rate for SwapReq accesses
+system.cpu3.dcache.demand_miss_rate::cpu3.data     0.005316                       # miss rate for demand accesses
+system.cpu3.dcache.demand_miss_rate::total     0.005316                       # miss rate for demand accesses
+system.cpu3.dcache.overall_miss_rate::cpu3.data     0.005316                       # miss rate for overall accesses
+system.cpu3.dcache.overall_miss_rate::total     0.005316                       # miss rate for overall accesses
+system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 25005.681818                       # average ReadReq miss latency
+system.cpu3.dcache.ReadReq_avg_miss_latency::total 25005.681818                       # average ReadReq miss latency
+system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 17723.809524                       # average WriteReq miss latency
+system.cpu3.dcache.WriteReq_avg_miss_latency::total 17723.809524                       # average WriteReq miss latency
+system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 15728.813559                       # average SwapReq miss latency
+system.cpu3.dcache.SwapReq_avg_miss_latency::total 15728.813559                       # average SwapReq miss latency
+system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 22284.697509                       # average overall miss latency
+system.cpu3.dcache.demand_avg_miss_latency::total 22284.697509                       # average overall miss latency
+system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 22284.697509                       # average overall miss latency
+system.cpu3.dcache.overall_avg_miss_latency::total 22284.697509                       # average overall miss latency
 system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -891,81 +891,81 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu3.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu3.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data          155                       # number of ReadReq MSHR misses
-system.cpu3.dcache.ReadReq_mshr_misses::total          155                       # number of ReadReq MSHR misses
-system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data          108                       # number of WriteReq MSHR misses
-system.cpu3.dcache.WriteReq_mshr_misses::total          108                       # number of WriteReq MSHR misses
-system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data           54                       # number of SwapReq MSHR misses
-system.cpu3.dcache.SwapReq_mshr_misses::total           54                       # number of SwapReq MSHR misses
-system.cpu3.dcache.demand_mshr_misses::cpu3.data          263                       # number of demand (read+write) MSHR misses
-system.cpu3.dcache.demand_mshr_misses::total          263                       # number of demand (read+write) MSHR misses
-system.cpu3.dcache.overall_mshr_misses::cpu3.data          263                       # number of overall MSHR misses
-system.cpu3.dcache.overall_mshr_misses::total          263                       # number of overall MSHR misses
-system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data      2072000                       # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.ReadReq_mshr_miss_latency::total      2072000                       # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data      1702000                       # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency::total      1702000                       # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data       164000                       # number of SwapReq MSHR miss cycles
-system.cpu3.dcache.SwapReq_mshr_miss_latency::total       164000                       # number of SwapReq MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data      3774000                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency::total      3774000                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data      3774000                       # number of overall MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency::total      3774000                       # number of overall MSHR miss cycles
-system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.003714                       # mshr miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_mshr_miss_rate::total     0.003714                       # mshr miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.006988                       # mshr miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_mshr_miss_rate::total     0.006988                       # mshr miss rate for WriteReq accesses
-system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data     0.830769                       # mshr miss rate for SwapReq accesses
-system.cpu3.dcache.SwapReq_mshr_miss_rate::total     0.830769                       # mshr miss rate for SwapReq accesses
-system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data     0.004599                       # mshr miss rate for demand accesses
-system.cpu3.dcache.demand_mshr_miss_rate::total     0.004599                       # mshr miss rate for demand accesses
-system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data     0.004599                       # mshr miss rate for overall accesses
-system.cpu3.dcache.overall_mshr_miss_rate::total     0.004599                       # mshr miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 13367.741935                       # average ReadReq mshr miss latency
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 13367.741935                       # average ReadReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15759.259259                       # average WriteReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15759.259259                       # average WriteReq mshr miss latency
-system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data  3037.037037                       # average SwapReq mshr miss latency
-system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total  3037.037037                       # average SwapReq mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 14349.809886                       # average overall mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency::total 14349.809886                       # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 14349.809886                       # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency::total 14349.809886                       # average overall mshr miss latency
+system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data          176                       # number of ReadReq MSHR misses
+system.cpu3.dcache.ReadReq_mshr_misses::total          176                       # number of ReadReq MSHR misses
+system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data          105                       # number of WriteReq MSHR misses
+system.cpu3.dcache.WriteReq_mshr_misses::total          105                       # number of WriteReq MSHR misses
+system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data           59                       # number of SwapReq MSHR misses
+system.cpu3.dcache.SwapReq_mshr_misses::total           59                       # number of SwapReq MSHR misses
+system.cpu3.dcache.demand_mshr_misses::cpu3.data          281                       # number of demand (read+write) MSHR misses
+system.cpu3.dcache.demand_mshr_misses::total          281                       # number of demand (read+write) MSHR misses
+system.cpu3.dcache.overall_mshr_misses::cpu3.data          281                       # number of overall MSHR misses
+system.cpu3.dcache.overall_mshr_misses::total          281                       # number of overall MSHR misses
+system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data      3873000                       # number of ReadReq MSHR miss cycles
+system.cpu3.dcache.ReadReq_mshr_miss_latency::total      3873000                       # number of ReadReq MSHR miss cycles
+system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data      1546000                       # number of WriteReq MSHR miss cycles
+system.cpu3.dcache.WriteReq_mshr_miss_latency::total      1546000                       # number of WriteReq MSHR miss cycles
+system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data       751000                       # number of SwapReq MSHR miss cycles
+system.cpu3.dcache.SwapReq_mshr_miss_latency::total       751000                       # number of SwapReq MSHR miss cycles
+system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data      5419000                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.dcache.demand_mshr_miss_latency::total      5419000                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data      5419000                       # number of overall MSHR miss cycles
+system.cpu3.dcache.overall_mshr_miss_latency::total      5419000                       # number of overall MSHR miss cycles
+system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.004266                       # mshr miss rate for ReadReq accesses
+system.cpu3.dcache.ReadReq_mshr_miss_rate::total     0.004266                       # mshr miss rate for ReadReq accesses
+system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.009055                       # mshr miss rate for WriteReq accesses
+system.cpu3.dcache.WriteReq_mshr_miss_rate::total     0.009055                       # mshr miss rate for WriteReq accesses
+system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data     0.830986                       # mshr miss rate for SwapReq accesses
+system.cpu3.dcache.SwapReq_mshr_miss_rate::total     0.830986                       # mshr miss rate for SwapReq accesses
+system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data     0.005316                       # mshr miss rate for demand accesses
+system.cpu3.dcache.demand_mshr_miss_rate::total     0.005316                       # mshr miss rate for demand accesses
+system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data     0.005316                       # mshr miss rate for overall accesses
+system.cpu3.dcache.overall_mshr_miss_rate::total     0.005316                       # mshr miss rate for overall accesses
+system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 22005.681818                       # average ReadReq mshr miss latency
+system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 22005.681818                       # average ReadReq mshr miss latency
+system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 14723.809524                       # average WriteReq mshr miss latency
+system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 14723.809524                       # average WriteReq mshr miss latency
+system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 12728.813559                       # average SwapReq mshr miss latency
+system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 12728.813559                       # average SwapReq mshr miss latency
+system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 19284.697509                       # average overall mshr miss latency
+system.cpu3.dcache.demand_avg_mshr_miss_latency::total 19284.697509                       # average overall mshr miss latency
+system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 19284.697509                       # average overall mshr miss latency
+system.cpu3.dcache.overall_avg_mshr_miss_latency::total 19284.697509                       # average overall mshr miss latency
 system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.l2c.replacements                             0                       # number of replacements
-system.l2c.tagsinuse                       349.180649                       # Cycle average of tags in use
-system.l2c.total_refs                            1220                       # Total number of references to valid blocks.
+system.l2c.tagsinuse                       348.808930                       # Cycle average of tags in use
+system.l2c.total_refs                            1221                       # Total number of references to valid blocks.
 system.l2c.sampled_refs                           429                       # Sample count of references to valid blocks.
-system.l2c.avg_refs                          2.843823                       # Average number of references to valid blocks.
+system.l2c.avg_refs                          2.846154                       # Average number of references to valid blocks.
 system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks            0.889759                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst           231.859241                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data            54.220371                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.inst            51.601321                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.data             6.129070                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu2.inst             1.917102                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu2.data             0.831909                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu3.inst             0.887228                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu3.data             0.844647                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::writebacks            0.888060                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst           231.678051                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data            54.187452                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst            51.469392                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.data             6.113383                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu2.inst             1.770981                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu2.data             0.842116                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu3.inst             1.030371                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu3.data             0.829126                       # Average occupied blocks per requestor
 system.l2c.occ_percent::writebacks           0.000014                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.inst            0.003538                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.inst            0.003535                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu0.data            0.000827                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.inst            0.000787                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.data            0.000094                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu2.inst            0.000029                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.inst            0.000785                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.data            0.000093                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu2.inst            0.000027                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu2.data            0.000013                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu3.inst            0.000014                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu3.inst            0.000016                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu3.data            0.000013                       # Average percentage of cache occupancy
-system.l2c.occ_percent::total                0.005328                       # Average percentage of cache occupancy
+system.l2c.occ_percent::total                0.005322                       # Average percentage of cache occupancy
 system.l2c.ReadReq_hits::cpu0.inst                182                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu0.data                  5                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu1.inst                300                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu1.data                  3                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.inst                354                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.inst                355                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu2.data                  9                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu3.inst                358                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu3.data                  9                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                   1220                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                   1221                       # number of ReadReq hits
 system.l2c.Writeback_hits::writebacks               1                       # number of Writeback hits
 system.l2c.Writeback_hits::total                    1                       # number of Writeback hits
 system.l2c.UpgradeReq_hits::cpu0.data               2                       # number of UpgradeReq hits
@@ -974,34 +974,34 @@ system.l2c.demand_hits::cpu0.inst                 182                       # nu
 system.l2c.demand_hits::cpu0.data                   5                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu1.inst                 300                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu1.data                   3                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst                 354                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.inst                 355                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu2.data                   9                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu3.inst                 358                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu3.data                   9                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                    1220                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                    1221                       # number of demand (read+write) hits
 system.l2c.overall_hits::cpu0.inst                182                       # number of overall hits
 system.l2c.overall_hits::cpu0.data                  5                       # number of overall hits
 system.l2c.overall_hits::cpu1.inst                300                       # number of overall hits
 system.l2c.overall_hits::cpu1.data                  3                       # number of overall hits
-system.l2c.overall_hits::cpu2.inst                354                       # number of overall hits
+system.l2c.overall_hits::cpu2.inst                355                       # number of overall hits
 system.l2c.overall_hits::cpu2.data                  9                       # number of overall hits
 system.l2c.overall_hits::cpu3.inst                358                       # number of overall hits
 system.l2c.overall_hits::cpu3.data                  9                       # number of overall hits
-system.l2c.overall_hits::total                   1220                       # number of overall hits
+system.l2c.overall_hits::total                   1221                       # number of overall hits
 system.l2c.ReadReq_misses::cpu0.inst              285                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu0.data               66                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu1.inst               66                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu1.data                8                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu2.inst               12                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu2.data                2                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3.inst                9                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu3.inst                8                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu3.data                2                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                  450                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                  449                       # number of ReadReq misses
 system.l2c.UpgradeReq_misses::cpu0.data            28                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data            11                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2.data            15                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu3.data            15                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total                69                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data            20                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu2.data            27                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu3.data            11                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total                86                       # number of UpgradeReq misses
 system.l2c.ReadExReq_misses::cpu0.data             99                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::cpu1.data             15                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::cpu2.data             14                       # number of ReadExReq misses
@@ -1013,66 +1013,66 @@ system.l2c.demand_misses::cpu1.inst                66                       # nu
 system.l2c.demand_misses::cpu1.data                23                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu2.inst                12                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu2.data                16                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.inst                 9                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu3.inst                 8                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu3.data                16                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                   592                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                   591                       # number of demand (read+write) misses
 system.l2c.overall_misses::cpu0.inst              285                       # number of overall misses
 system.l2c.overall_misses::cpu0.data              165                       # number of overall misses
 system.l2c.overall_misses::cpu1.inst               66                       # number of overall misses
 system.l2c.overall_misses::cpu1.data               23                       # number of overall misses
 system.l2c.overall_misses::cpu2.inst               12                       # number of overall misses
 system.l2c.overall_misses::cpu2.data               16                       # number of overall misses
-system.l2c.overall_misses::cpu3.inst                9                       # number of overall misses
+system.l2c.overall_misses::cpu3.inst                8                       # number of overall misses
 system.l2c.overall_misses::cpu3.data               16                       # number of overall misses
-system.l2c.overall_misses::total                  592                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.inst     14822000                       # number of ReadReq miss cycles
+system.l2c.overall_misses::total                  591                       # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu0.inst     14828000                       # number of ReadReq miss cycles
 system.l2c.ReadReq_miss_latency::cpu0.data      3432000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst      3402000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data       411000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.inst       615000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.data       104000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu3.inst       446000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu3.data       101000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total       23333000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst      3308000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data       398000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.inst       529000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.data        95000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu3.inst       418000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu3.data       104000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total       23112000                       # number of ReadReq miss cycles
 system.l2c.ReadExReq_miss_latency::cpu0.data      5148000                       # number of ReadExReq miss cycles
 system.l2c.ReadExReq_miss_latency::cpu1.data       780000                       # number of ReadExReq miss cycles
 system.l2c.ReadExReq_miss_latency::cpu2.data       728000                       # number of ReadExReq miss cycles
 system.l2c.ReadExReq_miss_latency::cpu3.data       728000                       # number of ReadExReq miss cycles
 system.l2c.ReadExReq_miss_latency::total      7384000                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.inst     14822000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.inst     14828000                       # number of demand (read+write) miss cycles
 system.l2c.demand_miss_latency::cpu0.data      8580000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst      3402000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data      1191000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.inst       615000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.data       832000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.inst       446000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.data       829000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total        30717000                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.inst     14822000                       # number of overall miss cycles
+system.l2c.demand_miss_latency::cpu1.inst      3308000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data      1178000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.inst       529000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.data       823000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3.inst       418000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3.data       832000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total        30496000                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.inst     14828000                       # number of overall miss cycles
 system.l2c.overall_miss_latency::cpu0.data      8580000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst      3402000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data      1191000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.inst       615000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.data       832000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.inst       446000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.data       829000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total       30717000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst      3308000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data      1178000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.inst       529000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.data       823000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.inst       418000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.data       832000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total       30496000                       # number of overall miss cycles
 system.l2c.ReadReq_accesses::cpu0.inst            467                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::cpu0.data             71                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::cpu1.inst            366                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::cpu1.data             11                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.inst            366                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.inst            367                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::cpu2.data             11                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu3.inst            367                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu3.inst            366                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::cpu3.data             11                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::total               1670                       # number of ReadReq accesses(hits+misses)
 system.l2c.Writeback_accesses::writebacks            1                       # number of Writeback accesses(hits+misses)
 system.l2c.Writeback_accesses::total                1                       # number of Writeback accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::cpu0.data           30                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data           11                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2.data           15                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu3.data           15                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total              71                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data           20                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu2.data           27                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu3.data           11                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total              88                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::cpu0.data           99                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::cpu1.data           15                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::cpu2.data           14                       # number of ReadExReq accesses(hits+misses)
@@ -1082,34 +1082,34 @@ system.l2c.demand_accesses::cpu0.inst             467                       # nu
 system.l2c.demand_accesses::cpu0.data             170                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu1.inst             366                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu1.data              26                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.inst             366                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.inst             367                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu2.data              25                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.inst             367                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.inst             366                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu3.data              25                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::total                1812                       # number of demand (read+write) accesses
 system.l2c.overall_accesses::cpu0.inst            467                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu0.data            170                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu1.inst            366                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu1.data             26                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.inst            366                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.inst            367                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu2.data             25                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.inst            367                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.inst            366                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu3.data             25                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::total               1812                       # number of overall (read+write) accesses
 system.l2c.ReadReq_miss_rate::cpu0.inst      0.610278                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu0.data      0.929577                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu1.inst      0.180328                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu1.data      0.727273                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.inst      0.032787                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.inst      0.032698                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu2.data      0.181818                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu3.inst      0.024523                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu3.inst      0.021858                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu3.data      0.181818                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.269461                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.268862                       # miss rate for ReadReq accesses
 system.l2c.UpgradeReq_miss_rate::cpu0.data     0.933333                       # miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_miss_rate::cpu2.data            1                       # miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_miss_rate::cpu3.data            1                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.971831                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.977273                       # miss rate for UpgradeReq accesses
 system.l2c.ReadExReq_miss_rate::cpu0.data            1                       # miss rate for ReadExReq accesses
 system.l2c.ReadExReq_miss_rate::cpu1.data            1                       # miss rate for ReadExReq accesses
 system.l2c.ReadExReq_miss_rate::cpu2.data            1                       # miss rate for ReadExReq accesses
@@ -1119,52 +1119,52 @@ system.l2c.demand_miss_rate::cpu0.inst       0.610278                       # mi
 system.l2c.demand_miss_rate::cpu0.data       0.970588                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu1.inst       0.180328                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu1.data       0.884615                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst       0.032787                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.inst       0.032698                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu2.data       0.640000                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.inst       0.024523                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.inst       0.021858                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu3.data       0.640000                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.326711                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.326159                       # miss rate for demand accesses
 system.l2c.overall_miss_rate::cpu0.inst      0.610278                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu0.data      0.970588                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu1.inst      0.180328                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu1.data      0.884615                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst      0.032787                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.inst      0.032698                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu2.data      0.640000                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.inst      0.024523                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.inst      0.021858                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu3.data      0.640000                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.326711                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52007.017544                       # average ReadReq miss latency
+system.l2c.overall_miss_rate::total          0.326159                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52028.070175                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu0.data        52000                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51545.454545                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data        51375                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.inst        51250                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.data        52000                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu3.inst 49555.555556                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu3.data        50500                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 51851.111111                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 50121.212121                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data        49750                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.inst 44083.333333                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.data        47500                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu3.inst        52250                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu3.data        52000                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 51474.387528                       # average ReadReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::cpu0.data        52000                       # average ReadExReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::cpu1.data        52000                       # average ReadExReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::cpu2.data        52000                       # average ReadExReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::cpu3.data        52000                       # average ReadExReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::total        52000                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 52007.017544                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 52028.070175                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu0.data        52000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 51545.454545                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 51782.608696                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.inst        51250                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.data        52000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.inst 49555.555556                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.data 51812.500000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 51886.824324                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 52007.017544                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 50121.212121                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 51217.391304                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.inst 44083.333333                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.data 51437.500000                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.inst        52250                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.data        52000                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 51600.676819                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 52028.070175                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu0.data        52000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 51545.454545                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 51782.608696                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.inst        51250                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.data        52000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.inst 49555.555556                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.data 51812.500000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 51886.824324                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 50121.212121                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 51217.391304                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.inst 44083.333333                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.data 51437.500000                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.inst        52250                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.data        52000                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 51600.676819                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -1175,36 +1175,33 @@ system.l2c.fast_writes                              0                       # nu
 system.l2c.cache_copies                             0                       # number of cache copies performed
 system.l2c.ReadReq_mshr_hits::cpu1.inst             7                       # number of ReadReq MSHR hits
 system.l2c.ReadReq_mshr_hits::cpu1.data             1                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu2.inst             3                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu3.inst             8                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu3.data             1                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total                20                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu2.inst            10                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu2.data             1                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::total                19                       # number of ReadReq MSHR hits
 system.l2c.demand_mshr_hits::cpu1.inst              7                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_hits::cpu1.data              1                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu2.inst              3                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu3.inst              8                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu3.data              1                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                 20                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu2.inst             10                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu2.data              1                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                 19                       # number of demand (read+write) MSHR hits
 system.l2c.overall_mshr_hits::cpu1.inst             7                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::cpu1.data             1                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu2.inst             3                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu3.inst             8                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu3.data             1                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                20                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu2.inst            10                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu2.data             1                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total                19                       # number of overall MSHR hits
 system.l2c.ReadReq_mshr_misses::cpu0.inst          285                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu0.data           66                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu1.inst           59                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu1.data            7                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.inst            9                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.data            2                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu3.inst            1                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu3.data            1                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.inst            2                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.data            1                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu3.inst            8                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu3.data            2                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::total             430                       # number of ReadReq MSHR misses
 system.l2c.UpgradeReq_mshr_misses::cpu0.data           28                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data           11                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu2.data           15                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu3.data           15                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total           69                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data           20                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu2.data           27                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu3.data           11                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total           86                       # number of UpgradeReq MSHR misses
 system.l2c.ReadExReq_mshr_misses::cpu0.data           99                       # number of ReadExReq MSHR misses
 system.l2c.ReadExReq_mshr_misses::cpu1.data           15                       # number of ReadExReq MSHR misses
 system.l2c.ReadExReq_mshr_misses::cpu2.data           14                       # number of ReadExReq MSHR misses
@@ -1214,71 +1211,71 @@ system.l2c.demand_mshr_misses::cpu0.inst          285                       # nu
 system.l2c.demand_mshr_misses::cpu0.data          165                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu1.inst           59                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu1.data           22                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.inst            9                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.data           16                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu3.inst            1                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu3.data           15                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.inst            2                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.data           15                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu3.inst            8                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu3.data           16                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::total              572                       # number of demand (read+write) MSHR misses
 system.l2c.overall_mshr_misses::cpu0.inst          285                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu0.data          165                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu1.inst           59                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu1.data           22                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.inst            9                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.data           16                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu3.inst            1                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu3.data           15                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.inst            2                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.data           15                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu3.inst            8                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu3.data           16                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::total             572                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst     11402000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst     11408000                       # number of ReadReq MSHR miss cycles
 system.l2c.ReadReq_mshr_miss_latency::cpu0.data      2640000                       # number of ReadReq MSHR miss cycles
 system.l2c.ReadReq_mshr_miss_latency::cpu1.inst      2360000                       # number of ReadReq MSHR miss cycles
 system.l2c.ReadReq_mshr_miss_latency::cpu1.data       280000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.inst       361000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.data        80000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu3.inst        40000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu3.data        40000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total     17203000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.inst        80000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.data        40000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu3.inst       322000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu3.data        80000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total     17210000                       # number of ReadReq MSHR miss cycles
 system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data      1120000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data       440000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data       600000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data       600000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total      2760000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data       800000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data      1080000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data       440000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total      3440000                       # number of UpgradeReq MSHR miss cycles
 system.l2c.ReadExReq_mshr_miss_latency::cpu0.data      3960000                       # number of ReadExReq MSHR miss cycles
 system.l2c.ReadExReq_mshr_miss_latency::cpu1.data       600000                       # number of ReadExReq MSHR miss cycles
 system.l2c.ReadExReq_mshr_miss_latency::cpu2.data       560000                       # number of ReadExReq MSHR miss cycles
 system.l2c.ReadExReq_mshr_miss_latency::cpu3.data       560000                       # number of ReadExReq MSHR miss cycles
 system.l2c.ReadExReq_mshr_miss_latency::total      5680000                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst     11402000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst     11408000                       # number of demand (read+write) MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu0.data      6600000                       # number of demand (read+write) MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu1.inst      2360000                       # number of demand (read+write) MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu1.data       880000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.inst       361000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.data       640000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.inst        40000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.data       600000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total     22883000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst     11402000                       # number of overall MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.inst        80000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.data       600000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.inst       322000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.data       640000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total     22890000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst     11408000                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu0.data      6600000                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu1.inst      2360000                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu1.data       880000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.inst       361000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.data       640000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.inst        40000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.data       600000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total     22883000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.inst        80000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.data       600000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.inst       322000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.data       640000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total     22890000                       # number of overall MSHR miss cycles
 system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.610278                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.929577                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.161202                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.636364                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.024590                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.181818                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu3.inst     0.002725                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu3.data     0.090909                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.005450                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.090909                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu3.inst     0.021858                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu3.data     0.181818                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::total     0.257485                       # mshr miss rate for ReadReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.933333                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.971831                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.977273                       # mshr miss rate for UpgradeReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for ReadExReq accesses
@@ -1288,29 +1285,29 @@ system.l2c.demand_mshr_miss_rate::cpu0.inst     0.610278                       #
 system.l2c.demand_mshr_miss_rate::cpu0.data     0.970588                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu1.inst     0.161202                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu1.data     0.846154                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst     0.024590                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.data     0.640000                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.inst     0.002725                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.data     0.600000                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst     0.005450                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data     0.600000                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.inst     0.021858                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.data     0.640000                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::total      0.315673                       # mshr miss rate for demand accesses
 system.l2c.overall_mshr_miss_rate::cpu0.inst     0.610278                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu0.data     0.970588                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu1.inst     0.161202                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu1.data     0.846154                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst     0.024590                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.data     0.640000                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.inst     0.002725                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.data     0.600000                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst     0.005450                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data     0.600000                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.inst     0.021858                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.data     0.640000                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::total     0.315673                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40007.017544                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40028.070175                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data        40000                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst        40000                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data        40000                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40111.111111                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst        40000                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data        40000                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst        40000                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst        40250                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data        40000                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 40006.976744                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 40023.255814                       # average ReadReq mshr miss latency
 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data        40000                       # average UpgradeReq mshr miss latency
 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data        40000                       # average UpgradeReq mshr miss latency
 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data        40000                       # average UpgradeReq mshr miss latency
@@ -1321,24 +1318,24 @@ system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data        40000
 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data        40000                       # average ReadExReq mshr miss latency
 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data        40000                       # average ReadExReq mshr miss latency
 system.l2c.ReadExReq_avg_mshr_miss_latency::total        40000                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40007.017544                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40028.070175                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.data        40000                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu1.inst        40000                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu1.data        40000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40111.111111                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst        40000                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu2.data        40000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.inst        40000                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.inst        40250                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu3.data        40000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 40005.244755                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40007.017544                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 40017.482517                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40028.070175                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.data        40000                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu1.inst        40000                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu1.data        40000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40111.111111                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst        40000                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu2.data        40000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.inst        40000                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.inst        40250                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu3.data        40000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 40005.244755                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 40017.482517                       # average overall mshr miss latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr
index a874a3f37..b8bd8a115 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr
@@ -1,74 +1,74 @@
-system.cpu4: completed 10000 read, 5380 write accesses @22344646
-system.cpu6: completed 10000 read, 5214 write accesses @22747629
-system.cpu7: completed 10000 read, 5415 write accesses @22929508
-system.cpu2: completed 10000 read, 5407 write accesses @23019836
-system.cpu5: completed 10000 read, 5331 write accesses @23061044
-system.cpu0: completed 10000 read, 5432 write accesses @23140146
-system.cpu3: completed 10000 read, 5376 write accesses @23188049
-system.cpu1: completed 10000 read, 5387 write accesses @23350185
-system.cpu4: completed 20000 read, 10814 write accesses @44761691
-system.cpu7: completed 20000 read, 10827 write accesses @45213444
-system.cpu1: completed 20000 read, 10711 write accesses @45275122
-system.cpu6: completed 20000 read, 10548 write accesses @45324102
-system.cpu3: completed 20000 read, 10701 write accesses @45506880
-system.cpu2: completed 20000 read, 10922 write accesses @45734056
-system.cpu5: completed 20000 read, 10686 write accesses @45942373
-system.cpu0: completed 20000 read, 10937 write accesses @46044746
-system.cpu7: completed 30000 read, 16167 write accesses @66979485
-system.cpu4: completed 30000 read, 16361 write accesses @67223162
-system.cpu6: completed 30000 read, 15931 write accesses @67873351
-system.cpu3: completed 30000 read, 16353 write accesses @68348826
-system.cpu5: completed 30000 read, 16080 write accesses @68377482
-system.cpu1: completed 30000 read, 16196 write accesses @68419268
-system.cpu0: completed 30000 read, 16219 write accesses @68619325
-system.cpu2: completed 30000 read, 16526 write accesses @68648506
-system.cpu4: completed 40000 read, 21581 write accesses @88592659
-system.cpu7: completed 40000 read, 21651 write accesses @88863809
-system.cpu6: completed 40000 read, 21187 write accesses @89230569
-system.cpu1: completed 40000 read, 21556 write accesses @89813083
-system.cpu2: completed 40000 read, 21771 write accesses @90046604
-system.cpu3: completed 40000 read, 21725 write accesses @90210729
-system.cpu5: completed 40000 read, 21435 write accesses @90283858
-system.cpu0: completed 40000 read, 21836 write accesses @90947960
-system.cpu4: completed 50000 read, 27034 write accesses @111338978
-system.cpu6: completed 50000 read, 26346 write accesses @111492478
-system.cpu1: completed 50000 read, 26820 write accesses @112199634
-system.cpu7: completed 50000 read, 27390 write accesses @112358430
-system.cpu5: completed 50000 read, 26711 write accesses @112747804
-system.cpu3: completed 50000 read, 27030 write accesses @113062631
-system.cpu2: completed 50000 read, 27246 write accesses @113387493
-system.cpu0: completed 50000 read, 27088 write accesses @113621350
-system.cpu4: completed 60000 read, 32322 write accesses @134108306
-system.cpu6: completed 60000 read, 31811 write accesses @134700049
-system.cpu2: completed 60000 read, 32452 write accesses @135470855
-system.cpu1: completed 60000 read, 32239 write accesses @135474213
-system.cpu7: completed 60000 read, 32783 write accesses @135487924
-system.cpu5: completed 60000 read, 32297 write accesses @135551091
-system.cpu3: completed 60000 read, 32475 write accesses @135953364
-system.cpu0: completed 60000 read, 32594 write accesses @136506452
-system.cpu4: completed 70000 read, 37624 write accesses @156509147
-system.cpu6: completed 70000 read, 37191 write accesses @157507230
-system.cpu2: completed 70000 read, 37791 write accesses @158024045
-system.cpu7: completed 70000 read, 38252 write accesses @158415918
-system.cpu1: completed 70000 read, 37644 write accesses @158423190
-system.cpu5: completed 70000 read, 37691 write accesses @158678523
-system.cpu3: completed 70000 read, 38021 write accesses @158813067
-system.cpu0: completed 70000 read, 37965 write accesses @159679646
-system.cpu4: completed 80000 read, 42948 write accesses @178855235
-system.cpu6: completed 80000 read, 42510 write accesses @180069540
-system.cpu2: completed 80000 read, 43201 write accesses @180702038
-system.cpu1: completed 80000 read, 43267 write accesses @181114200
-system.cpu7: completed 80000 read, 43705 write accesses @181378010
-system.cpu3: completed 80000 read, 43552 write accesses @181443642
-system.cpu5: completed 80000 read, 43080 write accesses @181574154
-system.cpu0: completed 80000 read, 43418 write accesses @182451715
-system.cpu4: completed 90000 read, 48279 write accesses @201435873
-system.cpu6: completed 90000 read, 47918 write accesses @202390012
-system.cpu2: completed 90000 read, 48513 write accesses @203087400
-system.cpu1: completed 90000 read, 48611 write accesses @203141768
-system.cpu7: completed 90000 read, 48973 write accesses @204050544
-system.cpu5: completed 90000 read, 48423 write accesses @204299514
-system.cpu0: completed 90000 read, 48663 write accesses @204396348
-system.cpu3: completed 90000 read, 48999 write accesses @204475748
-system.cpu4: completed 100000 read, 53697 write accesses @224044586
+system.cpu3: completed 10000 read, 5269 write accesses @22241329
+system.cpu6: completed 10000 read, 5339 write accesses @22510874
+system.cpu4: completed 10000 read, 5452 write accesses @22618520
+system.cpu2: completed 10000 read, 5274 write accesses @22652245
+system.cpu5: completed 10000 read, 5225 write accesses @22698654
+system.cpu0: completed 10000 read, 5313 write accesses @22972460
+system.cpu1: completed 10000 read, 5425 write accesses @23112052
+system.cpu7: completed 10000 read, 5664 write accesses @23303588
+system.cpu3: completed 20000 read, 10591 write accesses @44494817
+system.cpu6: completed 20000 read, 10810 write accesses @44620430
+system.cpu2: completed 20000 read, 10802 write accesses @45009184
+system.cpu0: completed 20000 read, 10643 write accesses @45009224
+system.cpu5: completed 20000 read, 10647 write accesses @45039314
+system.cpu1: completed 20000 read, 10757 write accesses @45068735
+system.cpu4: completed 20000 read, 10808 write accesses @45199458
+system.cpu7: completed 20000 read, 11080 write accesses @45757070
+system.cpu2: completed 30000 read, 16115 write accesses @67069204
+system.cpu3: completed 30000 read, 16110 write accesses @67286000
+system.cpu5: completed 30000 read, 16163 write accesses @67388496
+system.cpu4: completed 30000 read, 16262 write accesses @67495238
+system.cpu6: completed 30000 read, 16234 write accesses @67566368
+system.cpu0: completed 30000 read, 16102 write accesses @67625583
+system.cpu1: completed 30000 read, 16288 write accesses @67665372
+system.cpu7: completed 30000 read, 16608 write accesses @68406261
+system.cpu4: completed 40000 read, 21521 write accesses @88522458
+system.cpu2: completed 40000 read, 21461 write accesses @88760475
+system.cpu5: completed 40000 read, 21540 write accesses @88851958
+system.cpu3: completed 40000 read, 21536 write accesses @88901742
+system.cpu6: completed 40000 read, 21498 write accesses @88910943
+system.cpu1: completed 40000 read, 21730 write accesses @89071047
+system.cpu0: completed 40000 read, 21414 write accesses @89232143
+system.cpu7: completed 40000 read, 22063 write accesses @90453997
+system.cpu4: completed 50000 read, 26910 write accesses @111349230
+system.cpu1: completed 50000 read, 26996 write accesses @111399385
+system.cpu2: completed 50000 read, 26807 write accesses @111571994
+system.cpu6: completed 50000 read, 26876 write accesses @111619105
+system.cpu3: completed 50000 read, 27009 write accesses @111789131
+system.cpu0: completed 50000 read, 26777 write accesses @111829265
+system.cpu5: completed 50000 read, 26952 write accesses @111861140
+system.cpu7: completed 50000 read, 27397 write accesses @112901639
+system.cpu1: completed 60000 read, 32331 write accesses @134016224
+system.cpu2: completed 60000 read, 32246 write accesses @134236668
+system.cpu4: completed 60000 read, 32290 write accesses @134236929
+system.cpu5: completed 60000 read, 32370 write accesses @134256674
+system.cpu6: completed 60000 read, 32444 write accesses @134707450
+system.cpu0: completed 60000 read, 32183 write accesses @134767456
+system.cpu3: completed 60000 read, 32423 write accesses @134996472
+system.cpu7: completed 60000 read, 32735 write accesses @135678114
+system.cpu2: completed 70000 read, 37600 write accesses @156516476
+system.cpu1: completed 70000 read, 37730 write accesses @156721328
+system.cpu5: completed 70000 read, 37748 write accesses @156805205
+system.cpu6: completed 70000 read, 37760 write accesses @156910635
+system.cpu4: completed 70000 read, 37725 write accesses @156961462
+system.cpu0: completed 70000 read, 37635 write accesses @158012668
+system.cpu3: completed 70000 read, 37942 write accesses @158279756
+system.cpu7: completed 70000 read, 38031 write accesses @158283192
+system.cpu5: completed 80000 read, 43255 write accesses @179067469
+system.cpu2: completed 80000 read, 43125 write accesses @179091672
+system.cpu1: completed 80000 read, 43134 write accesses @179182044
+system.cpu6: completed 80000 read, 43119 write accesses @179350821
+system.cpu4: completed 80000 read, 43054 write accesses @179621308
+system.cpu7: completed 80000 read, 43393 write accesses @180749386
+system.cpu0: completed 80000 read, 43229 write accesses @180793374
+system.cpu3: completed 80000 read, 43339 write accesses @180920432
+system.cpu6: completed 90000 read, 48363 write accesses @201441693
+system.cpu2: completed 90000 read, 48516 write accesses @201463344
+system.cpu5: completed 90000 read, 48731 write accesses @201471872
+system.cpu1: completed 90000 read, 48576 write accesses @201752753
+system.cpu4: completed 90000 read, 48432 write accesses @201853284
+system.cpu7: completed 90000 read, 48666 write accesses @202980078
+system.cpu3: completed 90000 read, 48647 write accesses @203163876
+system.cpu0: completed 90000 read, 48482 write accesses @203365064
+system.cpu6: completed 100000 read, 53510 write accesses @223713460
 hack: be nice to actually delete the event here
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout
index 2045d5848..ed860ddcf 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:05:18
-gem5 started Jun 28 2012 22:09:54
+gem5 compiled Jul  2 2012 08:30:56
+gem5 started Jul  2 2012 09:08:41
 gem5 executing on zizzer
 command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA/tests/fast/quick/se/50.memtest/alpha/linux/memtest
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 224044586 because maximum number of loads reached
+Exiting @ tick 223713460 because maximum number of loads reached
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt
index 9c1b7f7cc..1fe48d0c8 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt
@@ -1,637 +1,640 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000224                       # Number of seconds simulated
-sim_ticks                                   224044586                       # Number of ticks simulated
-final_tick                                  224044586                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                   223713460                       # Number of ticks simulated
+final_tick                                  223713460                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_tick_rate                                1786168                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 347548                       # Number of bytes of host memory used
-host_seconds                                   125.43                       # Real time elapsed on the host
-system.physmem.bytes_read::cpu0                 89715                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1                 89291                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2                 88175                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3                 85667                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu4                 87042                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu5                 87583                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu6                 89679                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu7                 83220                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               700372                       # Number of bytes read from this memory
-system.physmem.bytes_written::writebacks       455360                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0               5322                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1               5377                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu2               5241                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu3               5325                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu4               5339                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu5               5367                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu6               5444                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu7               5417                       # Number of bytes written to this memory
-system.physmem.bytes_written::total            498192                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0                  11091                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1                  11171                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2                  11126                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3                  11075                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu4                  11127                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu5                  11038                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu6                  11244                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu7                  11085                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                 88957                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks            7115                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0                  5322                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1                  5377                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu2                  5241                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu3                  5325                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu4                  5339                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu5                  5367                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu6                  5444                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu7                  5417                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                49947                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0                400433689                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1                398541208                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2                393560057                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3                382365856                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu4                388503028                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu5                390917726                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu6                400273006                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu7                371443923                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              3126038493                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks        2032452594                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0                23754200                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1                23999687                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu2                23392665                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu3                23767591                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu4                23830078                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu5                23955053                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu6                24298735                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu7                24178223                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total             2223628827                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks        2032452594                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0               424187889                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1               422540895                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2               416952722                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3               406133447                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu4               412333106                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu5               414872779                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu6               424571741                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu7               395622146                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             5349667320                       # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements                         14607                       # number of replacements
-system.l2c.tagsinuse                       798.832185                       # Cycle average of tags in use
-system.l2c.total_refs                          150557                       # Total number of references to valid blocks.
-system.l2c.sampled_refs                         15432                       # Sample count of references to valid blocks.
-system.l2c.avg_refs                          9.756156                       # Average number of references to valid blocks.
+host_tick_rate                                1721618                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 347508                       # Number of bytes of host memory used
+host_seconds                                   129.94                       # Real time elapsed on the host
+system.physmem.bytes_read::cpu0                 81065                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1                 82807                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2                 84800                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3                 80115                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu4                 83878                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu5                 83050                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu6                 84723                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu7                 83101                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               663539                       # Number of bytes read from this memory
+system.physmem.bytes_written::writebacks       423360                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0               5290                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1               5393                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu2               5404                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu3               5324                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu4               5344                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu5               5398                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu6               5445                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu7               5412                       # Number of bytes written to this memory
+system.physmem.bytes_written::total            466370                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0                  11135                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1                  11050                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2                  11090                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3                  11067                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu4                  11176                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu5                  11041                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu6                  11139                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu7                  11029                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                 88727                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks            6615                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0                  5290                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1                  5393                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu2                  5404                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu3                  5324                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu4                  5344                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu5                  5398                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu6                  5445                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu7                  5412                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                49625                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0                362360852                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1                370147599                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2                379056316                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3                358114349                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu4                374934973                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu5                371233810                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu6                378712126                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu7                371461780                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              2966021803                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks        1892420778                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0                23646320                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1                24106730                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu2                24155900                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu3                23798300                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu4                23887700                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu5                24129080                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu6                24339170                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu7                24191660                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total             2084675638                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks        1892420778                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0               386007172                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1               394254329                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2               403212216                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3               381912648                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu4               398822673                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu5               395362890                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu6               403051296                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu7               395653440                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             5050697441                       # Total bandwidth to/from this memory (bytes/s)
+system.l2c.replacements                         13635                       # number of replacements
+system.l2c.tagsinuse                       790.382632                       # Cycle average of tags in use
+system.l2c.total_refs                          148986                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                         14447                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                         10.312591                       # Average number of references to valid blocks.
 system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks          740.812109                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0                  7.661361                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1                  7.247095                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu2                  7.177515                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu3                  6.855610                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu4                  7.321397                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu5                  7.120032                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu6                  7.753138                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu7                  6.883928                       # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks           0.723449                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0                 0.007482                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1                 0.007077                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu2                 0.007009                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu3                 0.006695                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu4                 0.007150                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu5                 0.006953                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu6                 0.007571                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu7                 0.006723                       # Average percentage of cache occupancy
-system.l2c.occ_percent::total                0.780110                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0                   10638                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1                   10673                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2                   10871                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3                   10613                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu4                   10754                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu5                   10954                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu6                   10851                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu7                   10889                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                  86243                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks           75632                       # number of Writeback hits
-system.l2c.Writeback_hits::total                75632                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0                  330                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1                  349                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2                  360                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu3                  350                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu4                  332                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu5                  339                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu6                  326                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu7                  357                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                2743                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0                  1980                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1                  1883                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu2                  1924                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu3                  2003                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu4                  1977                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu5                  1920                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu6                  1982                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu7                  1896                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total                15565                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0                    12618                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1                    12556                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2                    12795                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3                    12616                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu4                    12731                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu5                    12874                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu6                    12833                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu7                    12785                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                  101808                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0                   12618                       # number of overall hits
-system.l2c.overall_hits::cpu1                   12556                       # number of overall hits
-system.l2c.overall_hits::cpu2                   12795                       # number of overall hits
-system.l2c.overall_hits::cpu3                   12616                       # number of overall hits
-system.l2c.overall_hits::cpu4                   12731                       # number of overall hits
-system.l2c.overall_hits::cpu5                   12874                       # number of overall hits
-system.l2c.overall_hits::cpu6                   12833                       # number of overall hits
-system.l2c.overall_hits::cpu7                   12785                       # number of overall hits
-system.l2c.overall_hits::total                 101808                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0                   834                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1                   832                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2                   822                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3                   780                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu4                   790                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu5                   794                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu6                   838                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu7                   736                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                 6426                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0               1913                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1               1876                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2               1922                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu3               2012                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu4               1999                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu5               1918                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu6               1887                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu7               1932                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             15459                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0                4394                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1                4308                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2                4316                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu3                4354                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu4                4292                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu5                4292                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu6                4233                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu7                4328                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total              34517                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0                   5228                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1                   5140                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2                   5138                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3                   5134                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu4                   5082                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu5                   5086                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu6                   5071                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu7                   5064                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                 40943                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0                  5228                       # number of overall misses
-system.l2c.overall_misses::cpu1                  5140                       # number of overall misses
-system.l2c.overall_misses::cpu2                  5138                       # number of overall misses
-system.l2c.overall_misses::cpu3                  5134                       # number of overall misses
-system.l2c.overall_misses::cpu4                  5082                       # number of overall misses
-system.l2c.overall_misses::cpu5                  5086                       # number of overall misses
-system.l2c.overall_misses::cpu6                  5071                       # number of overall misses
-system.l2c.overall_misses::cpu7                  5064                       # number of overall misses
-system.l2c.overall_misses::total                40943                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0        41350032                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1        41129977                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2        40786420                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu3        38596362                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu4        39278271                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu5        39541044                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu6        41568753                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu7        36525760                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total      318776619                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0     49804280                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1     51885731                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu2     53676097                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu3     52486307                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu4     52437029                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu5     51272005                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu6     52254582                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu7     52654576                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total    416470607                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0     219461654                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1     215283667                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu2     215604529                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu3     217440085                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu4     214512687                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu5     214479862                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu6     211622352                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu7     216182446                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   1724587282                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0        260811686                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1        256413644                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2        256390949                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3        256036447                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu4        253790958                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu5        254020906                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu6        253191105                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu7        252708206                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total      2043363901                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0       260811686                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1       256413644                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2       256390949                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3       256036447                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu4       253790958                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu5       254020906                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu6       253191105                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu7       252708206                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total     2043363901                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0               11472                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1               11505                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2               11693                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu3               11393                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu4               11544                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu5               11748                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu6               11689                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu7               11625                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total              92669                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks        75632                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total            75632                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0             2243                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1             2225                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2             2282                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu3             2362                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu4             2331                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu5             2257                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu6             2213                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu7             2289                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total           18202                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0              6374                       # number of ReadExReq accesses(hits+misses)
+system.l2c.occ_blocks::writebacks          735.582494                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0                  6.455373                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1                  6.652747                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu2                  6.865494                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu3                  6.639169                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu4                  7.152690                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu5                  7.266868                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu6                  7.044725                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu7                  6.723074                       # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks           0.718342                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0                 0.006304                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1                 0.006497                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu2                 0.006705                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu3                 0.006484                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu4                 0.006985                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu5                 0.007097                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu6                 0.006880                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu7                 0.006566                       # Average percentage of cache occupancy
+system.l2c.occ_percent::total                0.771858                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu0                   10736                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1                   10614                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2                   10598                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu3                   10656                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu4                   10639                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu5                   10502                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu6                   10784                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu7                   10768                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                  85297                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks           74602                       # number of Writeback hits
+system.l2c.Writeback_hits::total                74602                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0                  364                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1                  332                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu2                  337                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu3                  343                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu4                  366                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu5                  372                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu6                  359                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu7                  320                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                2793                       # number of UpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0                  1921                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1                  1802                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu2                  1826                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu3                  1918                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu4                  1884                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu5                  1935                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu6                  1883                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu7                  1847                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total                15016                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu0                    12657                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1                    12416                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2                    12424                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu3                    12574                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu4                    12523                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu5                    12437                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu6                    12667                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu7                    12615                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                  100313                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0                   12657                       # number of overall hits
+system.l2c.overall_hits::cpu1                   12416                       # number of overall hits
+system.l2c.overall_hits::cpu2                   12424                       # number of overall hits
+system.l2c.overall_hits::cpu3                   12574                       # number of overall hits
+system.l2c.overall_hits::cpu4                   12523                       # number of overall hits
+system.l2c.overall_hits::cpu5                   12437                       # number of overall hits
+system.l2c.overall_hits::cpu6                   12667                       # number of overall hits
+system.l2c.overall_hits::cpu7                   12615                       # number of overall hits
+system.l2c.overall_hits::total                 100313                       # number of overall hits
+system.l2c.ReadReq_misses::cpu0                   732                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1                   746                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2                   787                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu3                   736                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu4                   779                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu5                   768                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu6                   802                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu7                   756                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                 6106                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0               1954                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1               1934                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu2               2007                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu3               1961                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu4               1921                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu5               2008                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu6               1917                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu7               1898                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total             15600                       # number of UpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0                4348                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1                4389                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu2                4257                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu3                4320                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu4                4350                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu5                4337                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu6                4234                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu7                4290                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total              34525                       # number of ReadExReq misses
+system.l2c.demand_misses::cpu0                   5080                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1                   5135                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2                   5044                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu3                   5056                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu4                   5129                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu5                   5105                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu6                   5036                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu7                   5046                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                 40631                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0                  5080                       # number of overall misses
+system.l2c.overall_misses::cpu1                  5135                       # number of overall misses
+system.l2c.overall_misses::cpu2                  5044                       # number of overall misses
+system.l2c.overall_misses::cpu3                  5056                       # number of overall misses
+system.l2c.overall_misses::cpu4                  5129                       # number of overall misses
+system.l2c.overall_misses::cpu5                  5105                       # number of overall misses
+system.l2c.overall_misses::cpu6                  5036                       # number of overall misses
+system.l2c.overall_misses::cpu7                  5046                       # number of overall misses
+system.l2c.overall_misses::total                40631                       # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu0        36182301                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1        37095182                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2        38839912                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu3        36320452                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu4        38654457                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu5        37981477                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu6        39913673                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu7        37420167                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total      302407621                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu0     51570624                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1     52824724                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu2     55089368                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu3     54044648                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu4     51434616                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu5     55447032                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu6     51075446                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu7     51050152                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total    422536610                       # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0     217343370                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1     219324999                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu2     212745239                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu3     215838098                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu4     217293309                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu5     216702467                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu6     211504918                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu7     214216755                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   1724969155                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu0        253525671                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1        256420181                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2        251585151                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3        252158550                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu4        255947766                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu5        254683944                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu6        251418591                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu7        251636922                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total      2027376776                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0       253525671                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1       256420181                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2       251585151                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3       252158550                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu4       255947766                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu5       254683944                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu6       251418591                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu7       251636922                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total     2027376776                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0               11468                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1               11360                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2               11385                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu3               11392                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu4               11418                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu5               11270                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu6               11586                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu7               11524                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total              91403                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks        74602                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total            74602                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0             2318                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1             2266                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu2             2344                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu3             2304                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu4             2287                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu5             2380                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu6             2276                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu7             2218                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total           18393                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0              6269                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::cpu1              6191                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu2              6240                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu3              6357                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu4              6269                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu5              6212                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu6              6215                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu7              6224                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total            50082                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0                17846                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1                17696                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2                17933                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3                17750                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu4                17813                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu5                17960                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu6                17904                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu7                17849                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total              142751                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0               17846                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1               17696                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2               17933                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3               17750                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu4               17813                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu5               17960                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu6               17904                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu7               17849                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total             142751                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0           0.072699                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1           0.072316                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2           0.070298                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu3           0.068463                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu4           0.068434                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu5           0.067586                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu6           0.071691                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu7           0.063312                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.069344                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0        0.852876                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1        0.843146                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2        0.842244                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu3        0.851820                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu4        0.857572                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu5        0.849801                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu6        0.852689                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu7        0.844037                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.849302                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0         0.689363                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1         0.695849                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2         0.691667                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu3         0.684914                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu4         0.684639                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu5         0.690921                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu6         0.681094                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu7         0.695373                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.689210                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0            0.292951                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1            0.290461                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2            0.286511                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3            0.289239                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu4            0.285297                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu5            0.283185                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu6            0.283233                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu7            0.283713                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.286814                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0           0.292951                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1           0.290461                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2           0.286511                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3           0.289239                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu4           0.285297                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu5           0.283185                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu6           0.283233                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu7           0.283713                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.286814                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0 49580.374101                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1 49435.068510                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2 49618.515815                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu3 49482.515385                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu4 49719.330380                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu5 49799.803526                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu6 49604.717184                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu7 49627.391304                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 49607.316993                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0 26034.647151                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1 27657.639126                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu2 27927.209677                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu3 26086.633698                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu4 26231.630315                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu5 26732.015120                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu6 27691.882353                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu7 27253.921325                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 26940.332945                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0 49945.756486                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1 49972.996054                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2 49954.710148                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu3 49940.304318                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu4 49979.656803                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu5 49972.008854                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu6 49993.468462                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu7 49949.733364                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 49963.417504                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0 49887.468630                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1 49885.922957                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2 49900.924290                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3 49870.753214                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu4 49939.188902                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu5 49945.125049                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu6 49929.225991                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu7 49902.884281                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 49907.527563                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0 49887.468630                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1 49885.922957                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2 49900.924290                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3 49870.753214                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu4 49939.188902                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu5 49945.125049                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu6 49929.225991                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu7 49902.884281                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 49907.527563                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs             97509                       # number of cycles access was blocked
+system.l2c.ReadExReq_accesses::cpu2              6083                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu3              6238                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu4              6234                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu5              6272                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu6              6117                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu7              6137                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total            49541                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0                17737                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1                17551                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2                17468                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3                17630                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu4                17652                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu5                17542                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu6                17703                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu7                17661                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total              140944                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0               17737                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1               17551                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2               17468                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3               17630                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu4               17652                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu5               17542                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu6               17703                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu7               17661                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total             140944                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0           0.063830                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1           0.065669                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2           0.069126                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu3           0.064607                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu4           0.068226                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu5           0.068146                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu6           0.069221                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu7           0.065602                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.066803                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0        0.842968                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1        0.853486                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu2        0.856229                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu3        0.851128                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu4        0.839965                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu5        0.843697                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu6        0.842267                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu7        0.855726                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.848149                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0         0.693572                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1         0.708932                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu2         0.699819                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu3         0.692530                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu4         0.697786                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu5         0.691486                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu6         0.692169                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu7         0.699039                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.696898                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0            0.286407                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1            0.292576                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2            0.288757                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3            0.286784                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu4            0.290562                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu5            0.291016                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu6            0.284472                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu7            0.285714                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.288278                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0           0.286407                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1           0.292576                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2           0.288757                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3           0.286784                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu4           0.290562                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu5           0.291016                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu6           0.284472                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu7           0.285714                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.288278                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu0 49429.372951                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1 49725.445040                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2 49351.857687                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu3 49348.440217                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu4 49620.612323                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu5 49455.048177                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu6 49767.672070                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu7 49497.575397                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 49526.305437                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0 26392.335722                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1 27313.714581                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu2 27448.613852                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu3 27559.738909                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu4 26774.917231                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu5 27613.063745                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu6 26643.425143                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu7 26896.813488                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 27085.680128                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0 49986.975621                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1 49971.519481                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu2 49975.390886                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu3 49962.522685                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu4 49952.484828                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu5 49965.982707                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu6 49953.924894                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu7 49933.975524                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 49962.900941                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0 49906.628150                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1 49935.770399                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2 49878.102895                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3 49873.130934                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu4 49902.079548                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu5 49889.117336                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu6 49924.263503                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu7 49868.593341                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 49897.289656                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0 49906.628150                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1 49935.770399                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2 49878.102895                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3 49873.130934                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu4 49902.079548                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu5 49889.117336                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu6 49924.263503                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu7 49868.593341                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 49897.289656                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs             96627                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                       14                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                       19                       # number of cycles access was blocked
 system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs   6964.928571                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs   5085.631579                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks                7115                       # number of writebacks
-system.l2c.writebacks::total                     7115                       # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu0                 22                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1                 23                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu2                 22                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu3                 24                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu4                 13                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu5                 15                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu6                 19                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu7                 17                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total               155                       # number of ReadReq MSHR hits
-system.l2c.UpgradeReq_mshr_hits::cpu1               4                       # number of UpgradeReq MSHR hits
+system.l2c.writebacks::writebacks                6616                       # number of writebacks
+system.l2c.writebacks::total                     6616                       # number of writebacks
+system.l2c.ReadReq_mshr_hits::cpu0                 18                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu1                 10                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu2                 24                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu3                 23                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu4                 22                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu5                 19                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu6                 17                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu7                 24                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::total               157                       # number of ReadReq MSHR hits
+system.l2c.UpgradeReq_mshr_hits::cpu0               2                       # number of UpgradeReq MSHR hits
+system.l2c.UpgradeReq_mshr_hits::cpu1               1                       # number of UpgradeReq MSHR hits
 system.l2c.UpgradeReq_mshr_hits::cpu2               1                       # number of UpgradeReq MSHR hits
 system.l2c.UpgradeReq_mshr_hits::cpu3               1                       # number of UpgradeReq MSHR hits
 system.l2c.UpgradeReq_mshr_hits::cpu4               1                       # number of UpgradeReq MSHR hits
-system.l2c.UpgradeReq_mshr_hits::cpu5               2                       # number of UpgradeReq MSHR hits
-system.l2c.UpgradeReq_mshr_hits::total              9                       # number of UpgradeReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu0               13                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu1                8                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu2               13                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu3               15                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu4               15                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu5                9                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu6                4                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::cpu7               12                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_hits::total              89                       # number of ReadExReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0                  35                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1                  31                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu2                  35                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu3                  39                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu4                  28                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu5                  24                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu6                  23                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu7                  29                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                244                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0                 35                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1                 31                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu2                 35                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu3                 39                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu4                 28                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu5                 24                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu6                 23                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu7                 29                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total               244                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu0              812                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1              809                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2              800                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu3              756                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu4              777                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu5              779                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu6              819                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu7              719                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total            6271                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0          1913                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1          1872                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu2          1921                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu3          2011                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu4          1998                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu5          1916                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu6          1887                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu7          1932                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total        15450                       # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0           4381                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1           4300                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu2           4303                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu3           4339                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu4           4277                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu5           4283                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu6           4229                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu7           4316                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total         34428                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0              5193                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1              5109                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2              5103                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu3              5095                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu4              5054                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu5              5062                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu6              5048                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu7              5035                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total            40699                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0             5193                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1             5109                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2             5103                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu3             5095                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu4             5054                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu5             5062                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu6             5048                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu7             5035                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total           40699                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0     32483716                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1     32363556                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2     32004501                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu3     30243000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu4     31083178                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu5     31162243                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu6     32763319                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu7     28723011                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total    250826524                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0     76520708                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1     74880632                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu2     76840756                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu3     80440711                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu4     79880909                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu5     76600687                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu6     75440727                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu7     77280682                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total    617885812                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0    175203645                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1    171923291                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu2    172082750                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu3    173484044                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu4    171083248                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu5    171323717                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu6    169163499                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu7    172603062                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   1376867256                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0    207687361                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1    204286847                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2    204087251                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3    203727044                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu4    202166426                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu5    202485960                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu6    201926818                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu7    201326073                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total   1627693780                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0    207687361                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1    204286847                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2    204087251                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3    203727044                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu4    202166426                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu5    202485960                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu6    201926818                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu7    201326073                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total   1627693780                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0    393605068                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1    397164440                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu2    396084825                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu3    395564887                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu4    396845191                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu5    392884701                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu6    399924937                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu7    397605829                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   3169679878                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0    212842079                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1    215082041                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu2    209602015                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu3    213002165                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu4    213521784                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu5    214681989                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu6    217761849                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu7    216562185                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   1713056107                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0    606447147                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1    612246481                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu2    605686840                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu3    608567052                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu4    610366975                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu5    607566690                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu6    617686786                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu7    614168014                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   4882735985                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0      0.070781                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1      0.070317                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2      0.068417                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu3      0.066357                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu4      0.067308                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu5      0.066309                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu6      0.070066                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu7      0.061849                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.067671                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0     0.852876                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1     0.841348                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2     0.841805                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu3     0.851397                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu4     0.857143                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu5     0.848914                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu6     0.852689                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu7     0.844037                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.848808                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0     0.687324                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1     0.694557                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2     0.689583                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu3     0.682555                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu4     0.682246                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu5     0.689472                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu6     0.680451                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu7     0.693445                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.687433                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0       0.290990                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1       0.288709                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2       0.284559                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3       0.287042                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu4       0.283725                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu5       0.281849                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu6       0.281948                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu7       0.282089                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.285105                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0      0.290990                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1      0.288709                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2      0.284559                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3      0.287042                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu4      0.283725                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu5      0.281849                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu6      0.281948                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu7      0.282089                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.285105                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 40004.576355                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 40004.395550                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 40005.626250                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 40003.968254                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 40004.090090                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 40002.879332                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 40004.052503                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 39948.554937                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 39997.851060                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 40000.370099                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 40000.337607                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 40000.393545                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 40000.353555                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 39980.434935                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 39979.481733                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 39979.187599                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 40000.353002                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 39992.609191                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 39991.701666                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 39982.160698                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 39991.343249                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 39982.494584                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 40000.759411                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 40000.867850                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 40000.827382                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 39991.441613                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 39992.658766                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0 39993.714808                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1 39985.681542                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2 39993.582403                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3 39985.680864                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu4 40001.271468                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu5 40001.177400                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu6 40001.350634                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu7 39985.317378                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 39993.458807                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0 39993.714808                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1 39985.681542                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2 39993.582403                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3 39985.680864                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu4 40001.271468                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu5 40001.177400                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu6 40001.350634                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu7 39985.317378                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 39993.458807                       # average overall mshr miss latency
+system.l2c.UpgradeReq_mshr_hits::cpu5               1                       # number of UpgradeReq MSHR hits
+system.l2c.UpgradeReq_mshr_hits::cpu6               1                       # number of UpgradeReq MSHR hits
+system.l2c.UpgradeReq_mshr_hits::cpu7               4                       # number of UpgradeReq MSHR hits
+system.l2c.UpgradeReq_mshr_hits::total             12                       # number of UpgradeReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu0                6                       # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu1               13                       # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu2                9                       # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu3                9                       # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu4               12                       # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu5               11                       # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu6               10                       # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu7               15                       # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::total              85                       # number of ReadExReq MSHR hits
+system.l2c.demand_mshr_hits::cpu0                  24                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1                  23                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu2                  33                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu3                  32                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu4                  34                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu5                  30                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu6                  27                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu7                  39                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                242                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu0                 24                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1                 23                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu2                 33                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu3                 32                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu4                 34                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu5                 30                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu6                 27                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu7                 39                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total               242                       # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses::cpu0              714                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1              736                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2              763                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu3              713                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu4              757                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu5              749                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu6              785                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu7              732                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total            5949                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0          1952                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1          1933                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu2          2006                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu3          1960                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu4          1920                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu5          2007                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu6          1916                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu7          1894                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total        15588                       # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0           4342                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1           4376                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu2           4248                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu3           4311                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu4           4338                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu5           4326                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu6           4224                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu7           4275                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total         34440                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0              5056                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1              5112                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2              5011                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu3              5024                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu4              5095                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu5              5075                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu6              5009                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu7              5007                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total            40389                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0             5056                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1             5112                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2             5011                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu3             5024                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu4             5095                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu5             5075                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu6             5009                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu7             5007                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total           40389                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu0     28564754                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1     29444935                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2     30526423                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu3     28524830                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu4     30284517                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu5     29963728                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu6     31404851                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu7     29284664                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total    237998702                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0     78081132                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1     77281042                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu2     80241204                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu3     78401138                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu4     76801198                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu5     80241160                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu6     76640992                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu7     75761030                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    623448896                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0    173685720                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1    175005460                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2    169924253                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu3    172445652                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu4    173444745                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu5    173045540                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu6    168925276                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu7    170965174                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   1377441820                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0    202250474                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1    204450395                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2    200450676                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3    200970482                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu4    203729262                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu5    203009268                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu6    200330127                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu7    200249838                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   1615440522                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0    202250474                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1    204450395                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2    200450676                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3    200970482                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu4    203729262                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu5    203009268                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu6    200330127                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu7    200249838                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   1615440522                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0    400927744                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1    396406972                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu2    396807484                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu3    398767759                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu4    400808423                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu5    395927220                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu6    398767355                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu7    395367613                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   3183780570                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0    211603917                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1    215684252                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu2    216163665                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu3    212923402                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu4    213723846                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu5    215924115                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu6    217803639                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu7    216444289                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   1720271125                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0    612531661                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1    612091224                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2    612971149                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu3    611691161                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu4    614532269                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu5    611851335                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu6    616570994                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu7    611811902                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   4904051695                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0      0.062260                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1      0.064789                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2      0.067018                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu3      0.062588                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu4      0.066299                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu5      0.066460                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu6      0.067754                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu7      0.063520                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.065085                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0     0.842105                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1     0.853045                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2     0.855802                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu3     0.850694                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu4     0.839528                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu5     0.843277                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu6     0.841828                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu7     0.853922                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.847496                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0     0.692614                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1     0.706832                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2     0.698340                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu3     0.691087                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu4     0.695861                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu5     0.689732                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu6     0.690535                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu7     0.696594                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.695182                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0       0.285054                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1       0.291265                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2       0.286867                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3       0.284969                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu4       0.288636                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu5       0.289306                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu6       0.282946                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu7       0.283506                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.286561                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0      0.285054                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1      0.291265                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2      0.286867                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3      0.284969                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu4      0.288636                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu5      0.289306                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu6      0.282946                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu7      0.283506                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.286561                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 40006.658263                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 40006.705163                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 40008.418087                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 40006.774194                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 40005.966975                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 40004.977303                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 40006.179618                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 40006.371585                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 40006.505631                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 40000.579918                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 39979.845835                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 40000.600199                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 40000.580612                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 40000.623958                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 39980.647733                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 40000.517745                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 40000.543823                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 39995.438542                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 40001.317365                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 39992.106947                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 40001.001177                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 40001.311065                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 39982.652144                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 40001.280629                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 39991.779356                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 39991.853567                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 39995.407085                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0 40002.071598                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1 39994.208725                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2 40002.130513                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3 40002.086385                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu4 39986.116192                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu5 40001.826207                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu6 39994.036135                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu7 39993.976034                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 39997.041818                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0 40002.071598                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1 39994.208725                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2 40002.130513                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3 40002.086385                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu4 39986.116192                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu5 40001.826207                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu6 39994.036135                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu7 39993.976034                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 39997.041818                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2          inf                       # average ReadReq mshr uncacheable latency
@@ -660,114 +663,114 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu6          inf
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu7          inf                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.cpu0.num_reads                           98637                       # number of read accesses completed
-system.cpu0.num_writes                          53345                       # number of write accesses completed
+system.cpu0.num_reads                           99016                       # number of read accesses completed
+system.cpu0.num_writes                          53340                       # number of write accesses completed
 system.cpu0.num_copies                              0                       # number of copy accesses completed
-system.cpu0.l1c.replacements                    22018                       # number of replacements
-system.cpu0.l1c.tagsinuse                  396.710521                       # Cycle average of tags in use
-system.cpu0.l1c.total_refs                      13223                       # Total number of references to valid blocks.
-system.cpu0.l1c.sampled_refs                    22420                       # Sample count of references to valid blocks.
-system.cpu0.l1c.avg_refs                     0.589786                       # Average number of references to valid blocks.
+system.cpu0.l1c.replacements                    21906                       # number of replacements
+system.cpu0.l1c.tagsinuse                  396.590239                       # Cycle average of tags in use
+system.cpu0.l1c.total_refs                      13140                       # Total number of references to valid blocks.
+system.cpu0.l1c.sampled_refs                    22312                       # Sample count of references to valid blocks.
+system.cpu0.l1c.avg_refs                     0.588921                       # Average number of references to valid blocks.
 system.cpu0.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.cpu0.l1c.occ_blocks::cpu0           396.710521                       # Average occupied blocks per requestor
-system.cpu0.l1c.occ_percent::cpu0            0.774825                       # Average percentage of cache occupancy
-system.cpu0.l1c.occ_percent::total           0.774825                       # Average percentage of cache occupancy
-system.cpu0.l1c.ReadReq_hits::cpu0               8580                       # number of ReadReq hits
-system.cpu0.l1c.ReadReq_hits::total              8580                       # number of ReadReq hits
-system.cpu0.l1c.WriteReq_hits::cpu0              1119                       # number of WriteReq hits
-system.cpu0.l1c.WriteReq_hits::total             1119                       # number of WriteReq hits
-system.cpu0.l1c.demand_hits::cpu0                9699                       # number of demand (read+write) hits
-system.cpu0.l1c.demand_hits::total               9699                       # number of demand (read+write) hits
-system.cpu0.l1c.overall_hits::cpu0               9699                       # number of overall hits
-system.cpu0.l1c.overall_hits::total              9699                       # number of overall hits
-system.cpu0.l1c.ReadReq_misses::cpu0            35932                       # number of ReadReq misses
-system.cpu0.l1c.ReadReq_misses::total           35932                       # number of ReadReq misses
-system.cpu0.l1c.WriteReq_misses::cpu0           23215                       # number of WriteReq misses
-system.cpu0.l1c.WriteReq_misses::total          23215                       # number of WriteReq misses
-system.cpu0.l1c.demand_misses::cpu0             59147                       # number of demand (read+write) misses
-system.cpu0.l1c.demand_misses::total            59147                       # number of demand (read+write) misses
-system.cpu0.l1c.overall_misses::cpu0            59147                       # number of overall misses
-system.cpu0.l1c.overall_misses::total           59147                       # number of overall misses
-system.cpu0.l1c.ReadReq_miss_latency::cpu0    928213854                       # number of ReadReq miss cycles
-system.cpu0.l1c.ReadReq_miss_latency::total    928213854                       # number of ReadReq miss cycles
-system.cpu0.l1c.WriteReq_miss_latency::cpu0    888665457                       # number of WriteReq miss cycles
-system.cpu0.l1c.WriteReq_miss_latency::total    888665457                       # number of WriteReq miss cycles
-system.cpu0.l1c.demand_miss_latency::cpu0   1816879311                       # number of demand (read+write) miss cycles
-system.cpu0.l1c.demand_miss_latency::total   1816879311                       # number of demand (read+write) miss cycles
-system.cpu0.l1c.overall_miss_latency::cpu0   1816879311                       # number of overall miss cycles
-system.cpu0.l1c.overall_miss_latency::total   1816879311                       # number of overall miss cycles
-system.cpu0.l1c.ReadReq_accesses::cpu0          44512                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.ReadReq_accesses::total         44512                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_accesses::cpu0         24334                       # number of WriteReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_accesses::total        24334                       # number of WriteReq accesses(hits+misses)
-system.cpu0.l1c.demand_accesses::cpu0           68846                       # number of demand (read+write) accesses
-system.cpu0.l1c.demand_accesses::total          68846                       # number of demand (read+write) accesses
-system.cpu0.l1c.overall_accesses::cpu0          68846                       # number of overall (read+write) accesses
-system.cpu0.l1c.overall_accesses::total         68846                       # number of overall (read+write) accesses
-system.cpu0.l1c.ReadReq_miss_rate::cpu0      0.807243                       # miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_miss_rate::total     0.807243                       # miss rate for ReadReq accesses
-system.cpu0.l1c.WriteReq_miss_rate::cpu0     0.954015                       # miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_miss_rate::total     0.954015                       # miss rate for WriteReq accesses
-system.cpu0.l1c.demand_miss_rate::cpu0       0.859120                       # miss rate for demand accesses
-system.cpu0.l1c.demand_miss_rate::total      0.859120                       # miss rate for demand accesses
-system.cpu0.l1c.overall_miss_rate::cpu0      0.859120                       # miss rate for overall accesses
-system.cpu0.l1c.overall_miss_rate::total     0.859120                       # miss rate for overall accesses
-system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 25832.512913                       # average ReadReq miss latency
-system.cpu0.l1c.ReadReq_avg_miss_latency::total 25832.512913                       # average ReadReq miss latency
-system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 38279.795692                       # average WriteReq miss latency
-system.cpu0.l1c.WriteReq_avg_miss_latency::total 38279.795692                       # average WriteReq miss latency
-system.cpu0.l1c.demand_avg_miss_latency::cpu0 30718.029841                       # average overall miss latency
-system.cpu0.l1c.demand_avg_miss_latency::total 30718.029841                       # average overall miss latency
-system.cpu0.l1c.overall_avg_miss_latency::cpu0 30718.029841                       # average overall miss latency
-system.cpu0.l1c.overall_avg_miss_latency::total 30718.029841                       # average overall miss latency
-system.cpu0.l1c.blocked_cycles::no_mshrs    213519076                       # number of cycles access was blocked
+system.cpu0.l1c.occ_blocks::cpu0           396.590239                       # Average occupied blocks per requestor
+system.cpu0.l1c.occ_percent::cpu0            0.774590                       # Average percentage of cache occupancy
+system.cpu0.l1c.occ_percent::total           0.774590                       # Average percentage of cache occupancy
+system.cpu0.l1c.ReadReq_hits::cpu0               8561                       # number of ReadReq hits
+system.cpu0.l1c.ReadReq_hits::total              8561                       # number of ReadReq hits
+system.cpu0.l1c.WriteReq_hits::cpu0              1051                       # number of WriteReq hits
+system.cpu0.l1c.WriteReq_hits::total             1051                       # number of WriteReq hits
+system.cpu0.l1c.demand_hits::cpu0                9612                       # number of demand (read+write) hits
+system.cpu0.l1c.demand_hits::total               9612                       # number of demand (read+write) hits
+system.cpu0.l1c.overall_hits::cpu0               9612                       # number of overall hits
+system.cpu0.l1c.overall_hits::total              9612                       # number of overall hits
+system.cpu0.l1c.ReadReq_misses::cpu0            35875                       # number of ReadReq misses
+system.cpu0.l1c.ReadReq_misses::total           35875                       # number of ReadReq misses
+system.cpu0.l1c.WriteReq_misses::cpu0           23186                       # number of WriteReq misses
+system.cpu0.l1c.WriteReq_misses::total          23186                       # number of WriteReq misses
+system.cpu0.l1c.demand_misses::cpu0             59061                       # number of demand (read+write) misses
+system.cpu0.l1c.demand_misses::total            59061                       # number of demand (read+write) misses
+system.cpu0.l1c.overall_misses::cpu0            59061                       # number of overall misses
+system.cpu0.l1c.overall_misses::total           59061                       # number of overall misses
+system.cpu0.l1c.ReadReq_miss_latency::cpu0    894906998                       # number of ReadReq miss cycles
+system.cpu0.l1c.ReadReq_miss_latency::total    894906998                       # number of ReadReq miss cycles
+system.cpu0.l1c.WriteReq_miss_latency::cpu0    820039819                       # number of WriteReq miss cycles
+system.cpu0.l1c.WriteReq_miss_latency::total    820039819                       # number of WriteReq miss cycles
+system.cpu0.l1c.demand_miss_latency::cpu0   1714946817                       # number of demand (read+write) miss cycles
+system.cpu0.l1c.demand_miss_latency::total   1714946817                       # number of demand (read+write) miss cycles
+system.cpu0.l1c.overall_miss_latency::cpu0   1714946817                       # number of overall miss cycles
+system.cpu0.l1c.overall_miss_latency::total   1714946817                       # number of overall miss cycles
+system.cpu0.l1c.ReadReq_accesses::cpu0          44436                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l1c.ReadReq_accesses::total         44436                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l1c.WriteReq_accesses::cpu0         24237                       # number of WriteReq accesses(hits+misses)
+system.cpu0.l1c.WriteReq_accesses::total        24237                       # number of WriteReq accesses(hits+misses)
+system.cpu0.l1c.demand_accesses::cpu0           68673                       # number of demand (read+write) accesses
+system.cpu0.l1c.demand_accesses::total          68673                       # number of demand (read+write) accesses
+system.cpu0.l1c.overall_accesses::cpu0          68673                       # number of overall (read+write) accesses
+system.cpu0.l1c.overall_accesses::total         68673                       # number of overall (read+write) accesses
+system.cpu0.l1c.ReadReq_miss_rate::cpu0      0.807341                       # miss rate for ReadReq accesses
+system.cpu0.l1c.ReadReq_miss_rate::total     0.807341                       # miss rate for ReadReq accesses
+system.cpu0.l1c.WriteReq_miss_rate::cpu0     0.956637                       # miss rate for WriteReq accesses
+system.cpu0.l1c.WriteReq_miss_rate::total     0.956637                       # miss rate for WriteReq accesses
+system.cpu0.l1c.demand_miss_rate::cpu0       0.860032                       # miss rate for demand accesses
+system.cpu0.l1c.demand_miss_rate::total      0.860032                       # miss rate for demand accesses
+system.cpu0.l1c.overall_miss_rate::cpu0      0.860032                       # miss rate for overall accesses
+system.cpu0.l1c.overall_miss_rate::total     0.860032                       # miss rate for overall accesses
+system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 24945.142801                       # average ReadReq miss latency
+system.cpu0.l1c.ReadReq_avg_miss_latency::total 24945.142801                       # average ReadReq miss latency
+system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 35367.886613                       # average WriteReq miss latency
+system.cpu0.l1c.WriteReq_avg_miss_latency::total 35367.886613                       # average WriteReq miss latency
+system.cpu0.l1c.demand_avg_miss_latency::cpu0 29036.874029                       # average overall miss latency
+system.cpu0.l1c.demand_avg_miss_latency::total 29036.874029                       # average overall miss latency
+system.cpu0.l1c.overall_avg_miss_latency::cpu0 29036.874029                       # average overall miss latency
+system.cpu0.l1c.overall_avg_miss_latency::total 29036.874029                       # average overall miss latency
+system.cpu0.l1c.blocked_cycles::no_mshrs    154642800                       # number of cycles access was blocked
 system.cpu0.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.l1c.blocked::no_mshrs               67191                       # number of cycles access was blocked
+system.cpu0.l1c.blocked::no_mshrs               53124                       # number of cycles access was blocked
 system.cpu0.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu0.l1c.avg_blocked_cycles::no_mshrs  3177.792800                       # average number of cycles each access was blocked
+system.cpu0.l1c.avg_blocked_cycles::no_mshrs  2910.978089                       # average number of cycles each access was blocked
 system.cpu0.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu0.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu0.l1c.writebacks::writebacks           9668                       # number of writebacks
-system.cpu0.l1c.writebacks::total                9668                       # number of writebacks
-system.cpu0.l1c.ReadReq_mshr_misses::cpu0        35932                       # number of ReadReq MSHR misses
-system.cpu0.l1c.ReadReq_mshr_misses::total        35932                       # number of ReadReq MSHR misses
-system.cpu0.l1c.WriteReq_mshr_misses::cpu0        23215                       # number of WriteReq MSHR misses
-system.cpu0.l1c.WriteReq_mshr_misses::total        23215                       # number of WriteReq MSHR misses
-system.cpu0.l1c.demand_mshr_misses::cpu0        59147                       # number of demand (read+write) MSHR misses
-system.cpu0.l1c.demand_mshr_misses::total        59147                       # number of demand (read+write) MSHR misses
-system.cpu0.l1c.overall_mshr_misses::cpu0        59147                       # number of overall MSHR misses
-system.cpu0.l1c.overall_mshr_misses::total        59147                       # number of overall MSHR misses
-system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0    892144080                       # number of ReadReq MSHR miss cycles
-system.cpu0.l1c.ReadReq_mshr_miss_latency::total    892144080                       # number of ReadReq MSHR miss cycles
-system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0    865359572                       # number of WriteReq MSHR miss cycles
-system.cpu0.l1c.WriteReq_mshr_miss_latency::total    865359572                       # number of WriteReq MSHR miss cycles
-system.cpu0.l1c.demand_mshr_miss_latency::cpu0   1757503652                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l1c.demand_mshr_miss_latency::total   1757503652                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l1c.overall_mshr_miss_latency::cpu0   1757503652                       # number of overall MSHR miss cycles
-system.cpu0.l1c.overall_mshr_miss_latency::total   1757503652                       # number of overall MSHR miss cycles
-system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0    897451639                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total    897451639                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0    561857596                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total    561857596                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0   1459309235                       # number of overall MSHR uncacheable cycles
-system.cpu0.l1c.overall_mshr_uncacheable_latency::total   1459309235                       # number of overall MSHR uncacheable cycles
-system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0     0.807243                       # mshr miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_mshr_miss_rate::total     0.807243                       # mshr miss rate for ReadReq accesses
-system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0     0.954015                       # mshr miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_mshr_miss_rate::total     0.954015                       # mshr miss rate for WriteReq accesses
-system.cpu0.l1c.demand_mshr_miss_rate::cpu0     0.859120                       # mshr miss rate for demand accesses
-system.cpu0.l1c.demand_mshr_miss_rate::total     0.859120                       # mshr miss rate for demand accesses
-system.cpu0.l1c.overall_mshr_miss_rate::cpu0     0.859120                       # mshr miss rate for overall accesses
-system.cpu0.l1c.overall_mshr_miss_rate::total     0.859120                       # mshr miss rate for overall accesses
-system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 24828.678615                       # average ReadReq mshr miss latency
-system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 24828.678615                       # average ReadReq mshr miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 37275.880767                       # average WriteReq mshr miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 37275.880767                       # average WriteReq mshr miss latency
-system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 29714.163897                       # average overall mshr miss latency
-system.cpu0.l1c.demand_avg_mshr_miss_latency::total 29714.163897                       # average overall mshr miss latency
-system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 29714.163897                       # average overall mshr miss latency
-system.cpu0.l1c.overall_avg_mshr_miss_latency::total 29714.163897                       # average overall mshr miss latency
+system.cpu0.l1c.writebacks::writebacks           9551                       # number of writebacks
+system.cpu0.l1c.writebacks::total                9551                       # number of writebacks
+system.cpu0.l1c.ReadReq_mshr_misses::cpu0        35875                       # number of ReadReq MSHR misses
+system.cpu0.l1c.ReadReq_mshr_misses::total        35875                       # number of ReadReq MSHR misses
+system.cpu0.l1c.WriteReq_mshr_misses::cpu0        23186                       # number of WriteReq MSHR misses
+system.cpu0.l1c.WriteReq_mshr_misses::total        23186                       # number of WriteReq MSHR misses
+system.cpu0.l1c.demand_mshr_misses::cpu0        59061                       # number of demand (read+write) MSHR misses
+system.cpu0.l1c.demand_mshr_misses::total        59061                       # number of demand (read+write) MSHR misses
+system.cpu0.l1c.overall_mshr_misses::cpu0        59061                       # number of overall MSHR misses
+system.cpu0.l1c.overall_mshr_misses::total        59061                       # number of overall MSHR misses
+system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0    858892486                       # number of ReadReq MSHR miss cycles
+system.cpu0.l1c.ReadReq_mshr_miss_latency::total    858892486                       # number of ReadReq MSHR miss cycles
+system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0    796764078                       # number of WriteReq MSHR miss cycles
+system.cpu0.l1c.WriteReq_mshr_miss_latency::total    796764078                       # number of WriteReq MSHR miss cycles
+system.cpu0.l1c.demand_mshr_miss_latency::cpu0   1655656564                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l1c.demand_mshr_miss_latency::total   1655656564                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l1c.overall_mshr_miss_latency::cpu0   1655656564                       # number of overall MSHR miss cycles
+system.cpu0.l1c.overall_mshr_miss_latency::total   1655656564                       # number of overall MSHR miss cycles
+system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0    681029068                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total    681029068                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0    670499371                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total    670499371                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0   1351528439                       # number of overall MSHR uncacheable cycles
+system.cpu0.l1c.overall_mshr_uncacheable_latency::total   1351528439                       # number of overall MSHR uncacheable cycles
+system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0     0.807341                       # mshr miss rate for ReadReq accesses
+system.cpu0.l1c.ReadReq_mshr_miss_rate::total     0.807341                       # mshr miss rate for ReadReq accesses
+system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0     0.956637                       # mshr miss rate for WriteReq accesses
+system.cpu0.l1c.WriteReq_mshr_miss_rate::total     0.956637                       # mshr miss rate for WriteReq accesses
+system.cpu0.l1c.demand_mshr_miss_rate::cpu0     0.860032                       # mshr miss rate for demand accesses
+system.cpu0.l1c.demand_mshr_miss_rate::total     0.860032                       # mshr miss rate for demand accesses
+system.cpu0.l1c.overall_mshr_miss_rate::cpu0     0.860032                       # mshr miss rate for overall accesses
+system.cpu0.l1c.overall_mshr_miss_rate::total     0.860032                       # mshr miss rate for overall accesses
+system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 23941.253965                       # average ReadReq mshr miss latency
+system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 23941.253965                       # average ReadReq mshr miss latency
+system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 34364.016130                       # average WriteReq mshr miss latency
+system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 34364.016130                       # average WriteReq mshr miss latency
+system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 28032.992398                       # average overall mshr miss latency
+system.cpu0.l1c.demand_avg_mshr_miss_latency::total 28032.992398                       # average overall mshr miss latency
+system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 28032.992398                       # average overall mshr miss latency
+system.cpu0.l1c.overall_avg_mshr_miss_latency::total 28032.992398                       # average overall mshr miss latency
 system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0          inf                       # average WriteReq mshr uncacheable latency
@@ -775,114 +778,114 @@ system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0          inf                       # average overall mshr uncacheable latency
 system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu1.num_reads                           99346                       # number of read accesses completed
-system.cpu1.num_writes                          53405                       # number of write accesses completed
+system.cpu1.num_reads                           99689                       # number of read accesses completed
+system.cpu1.num_writes                          53832                       # number of write accesses completed
 system.cpu1.num_copies                              0                       # number of copy accesses completed
-system.cpu1.l1c.replacements                    21836                       # number of replacements
-system.cpu1.l1c.tagsinuse                  395.252412                       # Cycle average of tags in use
-system.cpu1.l1c.total_refs                      13010                       # Total number of references to valid blocks.
-system.cpu1.l1c.sampled_refs                    22258                       # Sample count of references to valid blocks.
-system.cpu1.l1c.avg_refs                     0.584509                       # Average number of references to valid blocks.
+system.cpu1.l1c.replacements                    21971                       # number of replacements
+system.cpu1.l1c.tagsinuse                  397.434568                       # Cycle average of tags in use
+system.cpu1.l1c.total_refs                      13255                       # Total number of references to valid blocks.
+system.cpu1.l1c.sampled_refs                    22377                       # Sample count of references to valid blocks.
+system.cpu1.l1c.avg_refs                     0.592349                       # Average number of references to valid blocks.
 system.cpu1.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.cpu1.l1c.occ_blocks::cpu1           395.252412                       # Average occupied blocks per requestor
-system.cpu1.l1c.occ_percent::cpu1            0.771977                       # Average percentage of cache occupancy
-system.cpu1.l1c.occ_percent::total           0.771977                       # Average percentage of cache occupancy
-system.cpu1.l1c.ReadReq_hits::cpu1               8468                       # number of ReadReq hits
-system.cpu1.l1c.ReadReq_hits::total              8468                       # number of ReadReq hits
-system.cpu1.l1c.WriteReq_hits::cpu1              1045                       # number of WriteReq hits
-system.cpu1.l1c.WriteReq_hits::total             1045                       # number of WriteReq hits
-system.cpu1.l1c.demand_hits::cpu1                9513                       # number of demand (read+write) hits
-system.cpu1.l1c.demand_hits::total               9513                       # number of demand (read+write) hits
-system.cpu1.l1c.overall_hits::cpu1               9513                       # number of overall hits
-system.cpu1.l1c.overall_hits::total              9513                       # number of overall hits
-system.cpu1.l1c.ReadReq_misses::cpu1            36170                       # number of ReadReq misses
-system.cpu1.l1c.ReadReq_misses::total           36170                       # number of ReadReq misses
-system.cpu1.l1c.WriteReq_misses::cpu1           22843                       # number of WriteReq misses
-system.cpu1.l1c.WriteReq_misses::total          22843                       # number of WriteReq misses
-system.cpu1.l1c.demand_misses::cpu1             59013                       # number of demand (read+write) misses
-system.cpu1.l1c.demand_misses::total            59013                       # number of demand (read+write) misses
-system.cpu1.l1c.overall_misses::cpu1            59013                       # number of overall misses
-system.cpu1.l1c.overall_misses::total           59013                       # number of overall misses
-system.cpu1.l1c.ReadReq_miss_latency::cpu1    930956991                       # number of ReadReq miss cycles
-system.cpu1.l1c.ReadReq_miss_latency::total    930956991                       # number of ReadReq miss cycles
-system.cpu1.l1c.WriteReq_miss_latency::cpu1    873445374                       # number of WriteReq miss cycles
-system.cpu1.l1c.WriteReq_miss_latency::total    873445374                       # number of WriteReq miss cycles
-system.cpu1.l1c.demand_miss_latency::cpu1   1804402365                       # number of demand (read+write) miss cycles
-system.cpu1.l1c.demand_miss_latency::total   1804402365                       # number of demand (read+write) miss cycles
-system.cpu1.l1c.overall_miss_latency::cpu1   1804402365                       # number of overall miss cycles
-system.cpu1.l1c.overall_miss_latency::total   1804402365                       # number of overall miss cycles
-system.cpu1.l1c.ReadReq_accesses::cpu1          44638                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l1c.ReadReq_accesses::total         44638                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l1c.WriteReq_accesses::cpu1         23888                       # number of WriteReq accesses(hits+misses)
-system.cpu1.l1c.WriteReq_accesses::total        23888                       # number of WriteReq accesses(hits+misses)
-system.cpu1.l1c.demand_accesses::cpu1           68526                       # number of demand (read+write) accesses
-system.cpu1.l1c.demand_accesses::total          68526                       # number of demand (read+write) accesses
-system.cpu1.l1c.overall_accesses::cpu1          68526                       # number of overall (read+write) accesses
-system.cpu1.l1c.overall_accesses::total         68526                       # number of overall (read+write) accesses
-system.cpu1.l1c.ReadReq_miss_rate::cpu1      0.810296                       # miss rate for ReadReq accesses
-system.cpu1.l1c.ReadReq_miss_rate::total     0.810296                       # miss rate for ReadReq accesses
-system.cpu1.l1c.WriteReq_miss_rate::cpu1     0.956254                       # miss rate for WriteReq accesses
-system.cpu1.l1c.WriteReq_miss_rate::total     0.956254                       # miss rate for WriteReq accesses
-system.cpu1.l1c.demand_miss_rate::cpu1       0.861177                       # miss rate for demand accesses
-system.cpu1.l1c.demand_miss_rate::total      0.861177                       # miss rate for demand accesses
-system.cpu1.l1c.overall_miss_rate::cpu1      0.861177                       # miss rate for overall accesses
-system.cpu1.l1c.overall_miss_rate::total     0.861177                       # miss rate for overall accesses
-system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 25738.374095                       # average ReadReq miss latency
-system.cpu1.l1c.ReadReq_avg_miss_latency::total 25738.374095                       # average ReadReq miss latency
-system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 38236.894191                       # average WriteReq miss latency
-system.cpu1.l1c.WriteReq_avg_miss_latency::total 38236.894191                       # average WriteReq miss latency
-system.cpu1.l1c.demand_avg_miss_latency::cpu1 30576.353770                       # average overall miss latency
-system.cpu1.l1c.demand_avg_miss_latency::total 30576.353770                       # average overall miss latency
-system.cpu1.l1c.overall_avg_miss_latency::cpu1 30576.353770                       # average overall miss latency
-system.cpu1.l1c.overall_avg_miss_latency::total 30576.353770                       # average overall miss latency
-system.cpu1.l1c.blocked_cycles::no_mshrs    212850460                       # number of cycles access was blocked
+system.cpu1.l1c.occ_blocks::cpu1           397.434568                       # Average occupied blocks per requestor
+system.cpu1.l1c.occ_percent::cpu1            0.776239                       # Average percentage of cache occupancy
+system.cpu1.l1c.occ_percent::total           0.776239                       # Average percentage of cache occupancy
+system.cpu1.l1c.ReadReq_hits::cpu1               8630                       # number of ReadReq hits
+system.cpu1.l1c.ReadReq_hits::total              8630                       # number of ReadReq hits
+system.cpu1.l1c.WriteReq_hits::cpu1              1103                       # number of WriteReq hits
+system.cpu1.l1c.WriteReq_hits::total             1103                       # number of WriteReq hits
+system.cpu1.l1c.demand_hits::cpu1                9733                       # number of demand (read+write) hits
+system.cpu1.l1c.demand_hits::total               9733                       # number of demand (read+write) hits
+system.cpu1.l1c.overall_hits::cpu1               9733                       # number of overall hits
+system.cpu1.l1c.overall_hits::total              9733                       # number of overall hits
+system.cpu1.l1c.ReadReq_misses::cpu1            36139                       # number of ReadReq misses
+system.cpu1.l1c.ReadReq_misses::total           36139                       # number of ReadReq misses
+system.cpu1.l1c.WriteReq_misses::cpu1           23155                       # number of WriteReq misses
+system.cpu1.l1c.WriteReq_misses::total          23155                       # number of WriteReq misses
+system.cpu1.l1c.demand_misses::cpu1             59294                       # number of demand (read+write) misses
+system.cpu1.l1c.demand_misses::total            59294                       # number of demand (read+write) misses
+system.cpu1.l1c.overall_misses::cpu1            59294                       # number of overall misses
+system.cpu1.l1c.overall_misses::total           59294                       # number of overall misses
+system.cpu1.l1c.ReadReq_miss_latency::cpu1    902705787                       # number of ReadReq miss cycles
+system.cpu1.l1c.ReadReq_miss_latency::total    902705787                       # number of ReadReq miss cycles
+system.cpu1.l1c.WriteReq_miss_latency::cpu1    819450505                       # number of WriteReq miss cycles
+system.cpu1.l1c.WriteReq_miss_latency::total    819450505                       # number of WriteReq miss cycles
+system.cpu1.l1c.demand_miss_latency::cpu1   1722156292                       # number of demand (read+write) miss cycles
+system.cpu1.l1c.demand_miss_latency::total   1722156292                       # number of demand (read+write) miss cycles
+system.cpu1.l1c.overall_miss_latency::cpu1   1722156292                       # number of overall miss cycles
+system.cpu1.l1c.overall_miss_latency::total   1722156292                       # number of overall miss cycles
+system.cpu1.l1c.ReadReq_accesses::cpu1          44769                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l1c.ReadReq_accesses::total         44769                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l1c.WriteReq_accesses::cpu1         24258                       # number of WriteReq accesses(hits+misses)
+system.cpu1.l1c.WriteReq_accesses::total        24258                       # number of WriteReq accesses(hits+misses)
+system.cpu1.l1c.demand_accesses::cpu1           69027                       # number of demand (read+write) accesses
+system.cpu1.l1c.demand_accesses::total          69027                       # number of demand (read+write) accesses
+system.cpu1.l1c.overall_accesses::cpu1          69027                       # number of overall (read+write) accesses
+system.cpu1.l1c.overall_accesses::total         69027                       # number of overall (read+write) accesses
+system.cpu1.l1c.ReadReq_miss_rate::cpu1      0.807233                       # miss rate for ReadReq accesses
+system.cpu1.l1c.ReadReq_miss_rate::total     0.807233                       # miss rate for ReadReq accesses
+system.cpu1.l1c.WriteReq_miss_rate::cpu1     0.954530                       # miss rate for WriteReq accesses
+system.cpu1.l1c.WriteReq_miss_rate::total     0.954530                       # miss rate for WriteReq accesses
+system.cpu1.l1c.demand_miss_rate::cpu1       0.858997                       # miss rate for demand accesses
+system.cpu1.l1c.demand_miss_rate::total      0.858997                       # miss rate for demand accesses
+system.cpu1.l1c.overall_miss_rate::cpu1      0.858997                       # miss rate for overall accesses
+system.cpu1.l1c.overall_miss_rate::total     0.858997                       # miss rate for overall accesses
+system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 24978.715155                       # average ReadReq miss latency
+system.cpu1.l1c.ReadReq_avg_miss_latency::total 24978.715155                       # average ReadReq miss latency
+system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 35389.786439                       # average WriteReq miss latency
+system.cpu1.l1c.WriteReq_avg_miss_latency::total 35389.786439                       # average WriteReq miss latency
+system.cpu1.l1c.demand_avg_miss_latency::cpu1 29044.360171                       # average overall miss latency
+system.cpu1.l1c.demand_avg_miss_latency::total 29044.360171                       # average overall miss latency
+system.cpu1.l1c.overall_avg_miss_latency::cpu1 29044.360171                       # average overall miss latency
+system.cpu1.l1c.overall_avg_miss_latency::total 29044.360171                       # average overall miss latency
+system.cpu1.l1c.blocked_cycles::no_mshrs    155390130                       # number of cycles access was blocked
 system.cpu1.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.l1c.blocked::no_mshrs               67062                       # number of cycles access was blocked
+system.cpu1.l1c.blocked::no_mshrs               53247                       # number of cycles access was blocked
 system.cpu1.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu1.l1c.avg_blocked_cycles::no_mshrs  3173.935463                       # average number of cycles each access was blocked
+system.cpu1.l1c.avg_blocked_cycles::no_mshrs  2918.288918                       # average number of cycles each access was blocked
 system.cpu1.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu1.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu1.l1c.writebacks::writebacks           9414                       # number of writebacks
-system.cpu1.l1c.writebacks::total                9414                       # number of writebacks
-system.cpu1.l1c.ReadReq_mshr_misses::cpu1        36170                       # number of ReadReq MSHR misses
-system.cpu1.l1c.ReadReq_mshr_misses::total        36170                       # number of ReadReq MSHR misses
-system.cpu1.l1c.WriteReq_mshr_misses::cpu1        22843                       # number of WriteReq MSHR misses
-system.cpu1.l1c.WriteReq_mshr_misses::total        22843                       # number of WriteReq MSHR misses
-system.cpu1.l1c.demand_mshr_misses::cpu1        59013                       # number of demand (read+write) MSHR misses
-system.cpu1.l1c.demand_mshr_misses::total        59013                       # number of demand (read+write) MSHR misses
-system.cpu1.l1c.overall_mshr_misses::cpu1        59013                       # number of overall MSHR misses
-system.cpu1.l1c.overall_mshr_misses::total        59013                       # number of overall MSHR misses
-system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1    894646237                       # number of ReadReq MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_miss_latency::total    894646237                       # number of ReadReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1    850514976                       # number of WriteReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_latency::total    850514976                       # number of WriteReq MSHR miss cycles
-system.cpu1.l1c.demand_mshr_miss_latency::cpu1   1745161213                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.demand_mshr_miss_latency::total   1745161213                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_latency::cpu1   1745161213                       # number of overall MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_latency::total   1745161213                       # number of overall MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1    906808922                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total    906808922                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1    573615954                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total    573615954                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1   1480424876                       # number of overall MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_latency::total   1480424876                       # number of overall MSHR uncacheable cycles
-system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1     0.810296                       # mshr miss rate for ReadReq accesses
-system.cpu1.l1c.ReadReq_mshr_miss_rate::total     0.810296                       # mshr miss rate for ReadReq accesses
-system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1     0.956254                       # mshr miss rate for WriteReq accesses
-system.cpu1.l1c.WriteReq_mshr_miss_rate::total     0.956254                       # mshr miss rate for WriteReq accesses
-system.cpu1.l1c.demand_mshr_miss_rate::cpu1     0.861177                       # mshr miss rate for demand accesses
-system.cpu1.l1c.demand_mshr_miss_rate::total     0.861177                       # mshr miss rate for demand accesses
-system.cpu1.l1c.overall_mshr_miss_rate::cpu1     0.861177                       # mshr miss rate for overall accesses
-system.cpu1.l1c.overall_mshr_miss_rate::total     0.861177                       # mshr miss rate for overall accesses
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 24734.482638                       # average ReadReq mshr miss latency
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 24734.482638                       # average ReadReq mshr miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 37233.068161                       # average WriteReq mshr miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 37233.068161                       # average WriteReq mshr miss latency
-system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 29572.487638                       # average overall mshr miss latency
-system.cpu1.l1c.demand_avg_mshr_miss_latency::total 29572.487638                       # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 29572.487638                       # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency::total 29572.487638                       # average overall mshr miss latency
+system.cpu1.l1c.writebacks::writebacks           9603                       # number of writebacks
+system.cpu1.l1c.writebacks::total                9603                       # number of writebacks
+system.cpu1.l1c.ReadReq_mshr_misses::cpu1        36139                       # number of ReadReq MSHR misses
+system.cpu1.l1c.ReadReq_mshr_misses::total        36139                       # number of ReadReq MSHR misses
+system.cpu1.l1c.WriteReq_mshr_misses::cpu1        23155                       # number of WriteReq MSHR misses
+system.cpu1.l1c.WriteReq_mshr_misses::total        23155                       # number of WriteReq MSHR misses
+system.cpu1.l1c.demand_mshr_misses::cpu1        59294                       # number of demand (read+write) MSHR misses
+system.cpu1.l1c.demand_mshr_misses::total        59294                       # number of demand (read+write) MSHR misses
+system.cpu1.l1c.overall_mshr_misses::cpu1        59294                       # number of overall MSHR misses
+system.cpu1.l1c.overall_mshr_misses::total        59294                       # number of overall MSHR misses
+system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1    866427236                       # number of ReadReq MSHR miss cycles
+system.cpu1.l1c.ReadReq_mshr_miss_latency::total    866427236                       # number of ReadReq MSHR miss cycles
+system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1    796207895                       # number of WriteReq MSHR miss cycles
+system.cpu1.l1c.WriteReq_mshr_miss_latency::total    796207895                       # number of WriteReq MSHR miss cycles
+system.cpu1.l1c.demand_mshr_miss_latency::cpu1   1662635131                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l1c.demand_mshr_miss_latency::total   1662635131                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l1c.overall_mshr_miss_latency::cpu1   1662635131                       # number of overall MSHR miss cycles
+system.cpu1.l1c.overall_mshr_miss_latency::total   1662635131                       # number of overall MSHR miss cycles
+system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1    674093801                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total    674093801                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1    675943433                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total    675943433                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1   1350037234                       # number of overall MSHR uncacheable cycles
+system.cpu1.l1c.overall_mshr_uncacheable_latency::total   1350037234                       # number of overall MSHR uncacheable cycles
+system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1     0.807233                       # mshr miss rate for ReadReq accesses
+system.cpu1.l1c.ReadReq_mshr_miss_rate::total     0.807233                       # mshr miss rate for ReadReq accesses
+system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1     0.954530                       # mshr miss rate for WriteReq accesses
+system.cpu1.l1c.WriteReq_mshr_miss_rate::total     0.954530                       # mshr miss rate for WriteReq accesses
+system.cpu1.l1c.demand_mshr_miss_rate::cpu1     0.858997                       # mshr miss rate for demand accesses
+system.cpu1.l1c.demand_mshr_miss_rate::total     0.858997                       # mshr miss rate for demand accesses
+system.cpu1.l1c.overall_mshr_miss_rate::cpu1     0.858997                       # mshr miss rate for overall accesses
+system.cpu1.l1c.overall_mshr_miss_rate::total     0.858997                       # mshr miss rate for overall accesses
+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 23974.853648                       # average ReadReq mshr miss latency
+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 23974.853648                       # average ReadReq mshr miss latency
+system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 34386.002807                       # average WriteReq mshr miss latency
+system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 34386.002807                       # average WriteReq mshr miss latency
+system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 28040.529075                       # average overall mshr miss latency
+system.cpu1.l1c.demand_avg_mshr_miss_latency::total 28040.529075                       # average overall mshr miss latency
+system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 28040.529075                       # average overall mshr miss latency
+system.cpu1.l1c.overall_avg_mshr_miss_latency::total 28040.529075                       # average overall mshr miss latency
 system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1          inf                       # average WriteReq mshr uncacheable latency
@@ -890,114 +893,114 @@ system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1          inf                       # average overall mshr uncacheable latency
 system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu2.num_reads                           99179                       # number of read accesses completed
-system.cpu2.num_writes                          53408                       # number of write accesses completed
+system.cpu2.num_reads                           99864                       # number of read accesses completed
+system.cpu2.num_writes                          53679                       # number of write accesses completed
 system.cpu2.num_copies                              0                       # number of copy accesses completed
-system.cpu2.l1c.replacements                    21970                       # number of replacements
-system.cpu2.l1c.tagsinuse                  396.422513                       # Cycle average of tags in use
-system.cpu2.l1c.total_refs                      13458                       # Total number of references to valid blocks.
-system.cpu2.l1c.sampled_refs                    22394                       # Sample count of references to valid blocks.
-system.cpu2.l1c.avg_refs                     0.600965                       # Average number of references to valid blocks.
+system.cpu2.l1c.replacements                    22117                       # number of replacements
+system.cpu2.l1c.tagsinuse                  397.846327                       # Cycle average of tags in use
+system.cpu2.l1c.total_refs                      13470                       # Total number of references to valid blocks.
+system.cpu2.l1c.sampled_refs                    22518                       # Sample count of references to valid blocks.
+system.cpu2.l1c.avg_refs                     0.598188                       # Average number of references to valid blocks.
 system.cpu2.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.cpu2.l1c.occ_blocks::cpu2           396.422513                       # Average occupied blocks per requestor
-system.cpu2.l1c.occ_percent::cpu2            0.774263                       # Average percentage of cache occupancy
-system.cpu2.l1c.occ_percent::total           0.774263                       # Average percentage of cache occupancy
-system.cpu2.l1c.ReadReq_hits::cpu2               8875                       # number of ReadReq hits
-system.cpu2.l1c.ReadReq_hits::total              8875                       # number of ReadReq hits
-system.cpu2.l1c.WriteReq_hits::cpu2              1083                       # number of WriteReq hits
-system.cpu2.l1c.WriteReq_hits::total             1083                       # number of WriteReq hits
-system.cpu2.l1c.demand_hits::cpu2                9958                       # number of demand (read+write) hits
-system.cpu2.l1c.demand_hits::total               9958                       # number of demand (read+write) hits
-system.cpu2.l1c.overall_hits::cpu2               9958                       # number of overall hits
-system.cpu2.l1c.overall_hits::total              9958                       # number of overall hits
-system.cpu2.l1c.ReadReq_misses::cpu2            35921                       # number of ReadReq misses
-system.cpu2.l1c.ReadReq_misses::total           35921                       # number of ReadReq misses
-system.cpu2.l1c.WriteReq_misses::cpu2           23014                       # number of WriteReq misses
-system.cpu2.l1c.WriteReq_misses::total          23014                       # number of WriteReq misses
-system.cpu2.l1c.demand_misses::cpu2             58935                       # number of demand (read+write) misses
-system.cpu2.l1c.demand_misses::total            58935                       # number of demand (read+write) misses
-system.cpu2.l1c.overall_misses::cpu2            58935                       # number of overall misses
-system.cpu2.l1c.overall_misses::total           58935                       # number of overall misses
-system.cpu2.l1c.ReadReq_miss_latency::cpu2    936514854                       # number of ReadReq miss cycles
-system.cpu2.l1c.ReadReq_miss_latency::total    936514854                       # number of ReadReq miss cycles
-system.cpu2.l1c.WriteReq_miss_latency::cpu2    882688372                       # number of WriteReq miss cycles
-system.cpu2.l1c.WriteReq_miss_latency::total    882688372                       # number of WriteReq miss cycles
-system.cpu2.l1c.demand_miss_latency::cpu2   1819203226                       # number of demand (read+write) miss cycles
-system.cpu2.l1c.demand_miss_latency::total   1819203226                       # number of demand (read+write) miss cycles
-system.cpu2.l1c.overall_miss_latency::cpu2   1819203226                       # number of overall miss cycles
-system.cpu2.l1c.overall_miss_latency::total   1819203226                       # number of overall miss cycles
-system.cpu2.l1c.ReadReq_accesses::cpu2          44796                       # number of ReadReq accesses(hits+misses)
-system.cpu2.l1c.ReadReq_accesses::total         44796                       # number of ReadReq accesses(hits+misses)
-system.cpu2.l1c.WriteReq_accesses::cpu2         24097                       # number of WriteReq accesses(hits+misses)
-system.cpu2.l1c.WriteReq_accesses::total        24097                       # number of WriteReq accesses(hits+misses)
-system.cpu2.l1c.demand_accesses::cpu2           68893                       # number of demand (read+write) accesses
-system.cpu2.l1c.demand_accesses::total          68893                       # number of demand (read+write) accesses
-system.cpu2.l1c.overall_accesses::cpu2          68893                       # number of overall (read+write) accesses
-system.cpu2.l1c.overall_accesses::total         68893                       # number of overall (read+write) accesses
-system.cpu2.l1c.ReadReq_miss_rate::cpu2      0.801880                       # miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_miss_rate::total     0.801880                       # miss rate for ReadReq accesses
-system.cpu2.l1c.WriteReq_miss_rate::cpu2     0.955057                       # miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_miss_rate::total     0.955057                       # miss rate for WriteReq accesses
-system.cpu2.l1c.demand_miss_rate::cpu2       0.855457                       # miss rate for demand accesses
-system.cpu2.l1c.demand_miss_rate::total      0.855457                       # miss rate for demand accesses
-system.cpu2.l1c.overall_miss_rate::cpu2      0.855457                       # miss rate for overall accesses
-system.cpu2.l1c.overall_miss_rate::total     0.855457                       # miss rate for overall accesses
-system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 26071.513989                       # average ReadReq miss latency
-system.cpu2.l1c.ReadReq_avg_miss_latency::total 26071.513989                       # average ReadReq miss latency
-system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 38354.409142                       # average WriteReq miss latency
-system.cpu2.l1c.WriteReq_avg_miss_latency::total 38354.409142                       # average WriteReq miss latency
-system.cpu2.l1c.demand_avg_miss_latency::cpu2 30867.960058                       # average overall miss latency
-system.cpu2.l1c.demand_avg_miss_latency::total 30867.960058                       # average overall miss latency
-system.cpu2.l1c.overall_avg_miss_latency::cpu2 30867.960058                       # average overall miss latency
-system.cpu2.l1c.overall_avg_miss_latency::total 30867.960058                       # average overall miss latency
-system.cpu2.l1c.blocked_cycles::no_mshrs    215347558                       # number of cycles access was blocked
+system.cpu2.l1c.occ_blocks::cpu2           397.846327                       # Average occupied blocks per requestor
+system.cpu2.l1c.occ_percent::cpu2            0.777044                       # Average percentage of cache occupancy
+system.cpu2.l1c.occ_percent::total           0.777044                       # Average percentage of cache occupancy
+system.cpu2.l1c.ReadReq_hits::cpu2               8720                       # number of ReadReq hits
+system.cpu2.l1c.ReadReq_hits::total              8720                       # number of ReadReq hits
+system.cpu2.l1c.WriteReq_hits::cpu2              1090                       # number of WriteReq hits
+system.cpu2.l1c.WriteReq_hits::total             1090                       # number of WriteReq hits
+system.cpu2.l1c.demand_hits::cpu2                9810                       # number of demand (read+write) hits
+system.cpu2.l1c.demand_hits::total               9810                       # number of demand (read+write) hits
+system.cpu2.l1c.overall_hits::cpu2               9810                       # number of overall hits
+system.cpu2.l1c.overall_hits::total              9810                       # number of overall hits
+system.cpu2.l1c.ReadReq_misses::cpu2            36026                       # number of ReadReq misses
+system.cpu2.l1c.ReadReq_misses::total           36026                       # number of ReadReq misses
+system.cpu2.l1c.WriteReq_misses::cpu2           23186                       # number of WriteReq misses
+system.cpu2.l1c.WriteReq_misses::total          23186                       # number of WriteReq misses
+system.cpu2.l1c.demand_misses::cpu2             59212                       # number of demand (read+write) misses
+system.cpu2.l1c.demand_misses::total            59212                       # number of demand (read+write) misses
+system.cpu2.l1c.overall_misses::cpu2            59212                       # number of overall misses
+system.cpu2.l1c.overall_misses::total           59212                       # number of overall misses
+system.cpu2.l1c.ReadReq_miss_latency::cpu2    899117648                       # number of ReadReq miss cycles
+system.cpu2.l1c.ReadReq_miss_latency::total    899117648                       # number of ReadReq miss cycles
+system.cpu2.l1c.WriteReq_miss_latency::cpu2    813653609                       # number of WriteReq miss cycles
+system.cpu2.l1c.WriteReq_miss_latency::total    813653609                       # number of WriteReq miss cycles
+system.cpu2.l1c.demand_miss_latency::cpu2   1712771257                       # number of demand (read+write) miss cycles
+system.cpu2.l1c.demand_miss_latency::total   1712771257                       # number of demand (read+write) miss cycles
+system.cpu2.l1c.overall_miss_latency::cpu2   1712771257                       # number of overall miss cycles
+system.cpu2.l1c.overall_miss_latency::total   1712771257                       # number of overall miss cycles
+system.cpu2.l1c.ReadReq_accesses::cpu2          44746                       # number of ReadReq accesses(hits+misses)
+system.cpu2.l1c.ReadReq_accesses::total         44746                       # number of ReadReq accesses(hits+misses)
+system.cpu2.l1c.WriteReq_accesses::cpu2         24276                       # number of WriteReq accesses(hits+misses)
+system.cpu2.l1c.WriteReq_accesses::total        24276                       # number of WriteReq accesses(hits+misses)
+system.cpu2.l1c.demand_accesses::cpu2           69022                       # number of demand (read+write) accesses
+system.cpu2.l1c.demand_accesses::total          69022                       # number of demand (read+write) accesses
+system.cpu2.l1c.overall_accesses::cpu2          69022                       # number of overall (read+write) accesses
+system.cpu2.l1c.overall_accesses::total         69022                       # number of overall (read+write) accesses
+system.cpu2.l1c.ReadReq_miss_rate::cpu2      0.805122                       # miss rate for ReadReq accesses
+system.cpu2.l1c.ReadReq_miss_rate::total     0.805122                       # miss rate for ReadReq accesses
+system.cpu2.l1c.WriteReq_miss_rate::cpu2     0.955100                       # miss rate for WriteReq accesses
+system.cpu2.l1c.WriteReq_miss_rate::total     0.955100                       # miss rate for WriteReq accesses
+system.cpu2.l1c.demand_miss_rate::cpu2       0.857871                       # miss rate for demand accesses
+system.cpu2.l1c.demand_miss_rate::total      0.857871                       # miss rate for demand accesses
+system.cpu2.l1c.overall_miss_rate::cpu2      0.857871                       # miss rate for overall accesses
+system.cpu2.l1c.overall_miss_rate::total     0.857871                       # miss rate for overall accesses
+system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 24957.465386                       # average ReadReq miss latency
+system.cpu2.l1c.ReadReq_avg_miss_latency::total 24957.465386                       # average ReadReq miss latency
+system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 35092.452730                       # average WriteReq miss latency
+system.cpu2.l1c.WriteReq_avg_miss_latency::total 35092.452730                       # average WriteReq miss latency
+system.cpu2.l1c.demand_avg_miss_latency::cpu2 28926.083513                       # average overall miss latency
+system.cpu2.l1c.demand_avg_miss_latency::total 28926.083513                       # average overall miss latency
+system.cpu2.l1c.overall_avg_miss_latency::cpu2 28926.083513                       # average overall miss latency
+system.cpu2.l1c.overall_avg_miss_latency::total 28926.083513                       # average overall miss latency
+system.cpu2.l1c.blocked_cycles::no_mshrs    153072251                       # number of cycles access was blocked
 system.cpu2.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu2.l1c.blocked::no_mshrs               67274                       # number of cycles access was blocked
+system.cpu2.l1c.blocked::no_mshrs               52648                       # number of cycles access was blocked
 system.cpu2.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu2.l1c.avg_blocked_cycles::no_mshrs  3201.051788                       # average number of cycles each access was blocked
+system.cpu2.l1c.avg_blocked_cycles::no_mshrs  2907.465640                       # average number of cycles each access was blocked
 system.cpu2.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu2.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu2.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu2.l1c.writebacks::writebacks           9572                       # number of writebacks
-system.cpu2.l1c.writebacks::total                9572                       # number of writebacks
-system.cpu2.l1c.ReadReq_mshr_misses::cpu2        35921                       # number of ReadReq MSHR misses
-system.cpu2.l1c.ReadReq_mshr_misses::total        35921                       # number of ReadReq MSHR misses
-system.cpu2.l1c.WriteReq_mshr_misses::cpu2        23014                       # number of WriteReq MSHR misses
-system.cpu2.l1c.WriteReq_mshr_misses::total        23014                       # number of WriteReq MSHR misses
-system.cpu2.l1c.demand_mshr_misses::cpu2        58935                       # number of demand (read+write) MSHR misses
-system.cpu2.l1c.demand_mshr_misses::total        58935                       # number of demand (read+write) MSHR misses
-system.cpu2.l1c.overall_mshr_misses::cpu2        58935                       # number of overall MSHR misses
-system.cpu2.l1c.overall_mshr_misses::total        58935                       # number of overall MSHR misses
-system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2    900454097                       # number of ReadReq MSHR miss cycles
-system.cpu2.l1c.ReadReq_mshr_miss_latency::total    900454097                       # number of ReadReq MSHR miss cycles
-system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2    859588304                       # number of WriteReq MSHR miss cycles
-system.cpu2.l1c.WriteReq_mshr_miss_latency::total    859588304                       # number of WriteReq MSHR miss cycles
-system.cpu2.l1c.demand_mshr_miss_latency::cpu2   1760042401                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.demand_mshr_miss_latency::total   1760042401                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_latency::cpu2   1760042401                       # number of overall MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_latency::total   1760042401                       # number of overall MSHR miss cycles
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2    903394412                       # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total    903394412                       # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2    551786925                       # number of WriteReq MSHR uncacheable cycles
-system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total    551786925                       # number of WriteReq MSHR uncacheable cycles
-system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2   1455181337                       # number of overall MSHR uncacheable cycles
-system.cpu2.l1c.overall_mshr_uncacheable_latency::total   1455181337                       # number of overall MSHR uncacheable cycles
-system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2     0.801880                       # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_mshr_miss_rate::total     0.801880                       # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2     0.955057                       # mshr miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_mshr_miss_rate::total     0.955057                       # mshr miss rate for WriteReq accesses
-system.cpu2.l1c.demand_mshr_miss_rate::cpu2     0.855457                       # mshr miss rate for demand accesses
-system.cpu2.l1c.demand_mshr_miss_rate::total     0.855457                       # mshr miss rate for demand accesses
-system.cpu2.l1c.overall_mshr_miss_rate::cpu2     0.855457                       # mshr miss rate for overall accesses
-system.cpu2.l1c.overall_mshr_miss_rate::total     0.855457                       # mshr miss rate for overall accesses
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 25067.623312                       # average ReadReq mshr miss latency
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 25067.623312                       # average ReadReq mshr miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 37350.669332                       # average WriteReq mshr miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 37350.669332                       # average WriteReq mshr miss latency
-system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 29864.128294                       # average overall mshr miss latency
-system.cpu2.l1c.demand_avg_mshr_miss_latency::total 29864.128294                       # average overall mshr miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 29864.128294                       # average overall mshr miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency::total 29864.128294                       # average overall mshr miss latency
+system.cpu2.l1c.writebacks::writebacks           9600                       # number of writebacks
+system.cpu2.l1c.writebacks::total                9600                       # number of writebacks
+system.cpu2.l1c.ReadReq_mshr_misses::cpu2        36026                       # number of ReadReq MSHR misses
+system.cpu2.l1c.ReadReq_mshr_misses::total        36026                       # number of ReadReq MSHR misses
+system.cpu2.l1c.WriteReq_mshr_misses::cpu2        23186                       # number of WriteReq MSHR misses
+system.cpu2.l1c.WriteReq_mshr_misses::total        23186                       # number of WriteReq MSHR misses
+system.cpu2.l1c.demand_mshr_misses::cpu2        59212                       # number of demand (read+write) MSHR misses
+system.cpu2.l1c.demand_mshr_misses::total        59212                       # number of demand (read+write) MSHR misses
+system.cpu2.l1c.overall_mshr_misses::cpu2        59212                       # number of overall MSHR misses
+system.cpu2.l1c.overall_mshr_misses::total        59212                       # number of overall MSHR misses
+system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2    862954550                       # number of ReadReq MSHR miss cycles
+system.cpu2.l1c.ReadReq_mshr_miss_latency::total    862954550                       # number of ReadReq MSHR miss cycles
+system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2    790376865                       # number of WriteReq MSHR miss cycles
+system.cpu2.l1c.WriteReq_mshr_miss_latency::total    790376865                       # number of WriteReq MSHR miss cycles
+system.cpu2.l1c.demand_mshr_miss_latency::cpu2   1653331415                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.l1c.demand_mshr_miss_latency::total   1653331415                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.l1c.overall_mshr_miss_latency::cpu2   1653331415                       # number of overall MSHR miss cycles
+system.cpu2.l1c.overall_mshr_miss_latency::total   1653331415                       # number of overall MSHR miss cycles
+system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2    676110998                       # number of ReadReq MSHR uncacheable cycles
+system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total    676110998                       # number of ReadReq MSHR uncacheable cycles
+system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2    681557695                       # number of WriteReq MSHR uncacheable cycles
+system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total    681557695                       # number of WriteReq MSHR uncacheable cycles
+system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2   1357668693                       # number of overall MSHR uncacheable cycles
+system.cpu2.l1c.overall_mshr_uncacheable_latency::total   1357668693                       # number of overall MSHR uncacheable cycles
+system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2     0.805122                       # mshr miss rate for ReadReq accesses
+system.cpu2.l1c.ReadReq_mshr_miss_rate::total     0.805122                       # mshr miss rate for ReadReq accesses
+system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2     0.955100                       # mshr miss rate for WriteReq accesses
+system.cpu2.l1c.WriteReq_mshr_miss_rate::total     0.955100                       # mshr miss rate for WriteReq accesses
+system.cpu2.l1c.demand_mshr_miss_rate::cpu2     0.857871                       # mshr miss rate for demand accesses
+system.cpu2.l1c.demand_mshr_miss_rate::total     0.857871                       # mshr miss rate for demand accesses
+system.cpu2.l1c.overall_mshr_miss_rate::cpu2     0.857871                       # mshr miss rate for overall accesses
+system.cpu2.l1c.overall_mshr_miss_rate::total     0.857871                       # mshr miss rate for overall accesses
+system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 23953.659857                       # average ReadReq mshr miss latency
+system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 23953.659857                       # average ReadReq mshr miss latency
+system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 34088.538989                       # average WriteReq mshr miss latency
+system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 34088.538989                       # average WriteReq mshr miss latency
+system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 27922.235611                       # average overall mshr miss latency
+system.cpu2.l1c.demand_avg_mshr_miss_latency::total 27922.235611                       # average overall mshr miss latency
+system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 27922.235611                       # average overall mshr miss latency
+system.cpu2.l1c.overall_avg_mshr_miss_latency::total 27922.235611                       # average overall mshr miss latency
 system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2          inf                       # average ReadReq mshr uncacheable latency
 system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2          inf                       # average WriteReq mshr uncacheable latency
@@ -1005,114 +1008,114 @@ system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2          inf                       # average overall mshr uncacheable latency
 system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu2.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu3.num_reads                           98310                       # number of read accesses completed
-system.cpu3.num_writes                          53451                       # number of write accesses completed
+system.cpu3.num_reads                           98954                       # number of read accesses completed
+system.cpu3.num_writes                          53519                       # number of write accesses completed
 system.cpu3.num_copies                              0                       # number of copy accesses completed
-system.cpu3.l1c.replacements                    21775                       # number of replacements
-system.cpu3.l1c.tagsinuse                  395.971374                       # Cycle average of tags in use
-system.cpu3.l1c.total_refs                      13179                       # Total number of references to valid blocks.
-system.cpu3.l1c.sampled_refs                    22179                       # Sample count of references to valid blocks.
-system.cpu3.l1c.avg_refs                     0.594211                       # Average number of references to valid blocks.
+system.cpu3.l1c.replacements                    21866                       # number of replacements
+system.cpu3.l1c.tagsinuse                  395.683419                       # Cycle average of tags in use
+system.cpu3.l1c.total_refs                      13218                       # Total number of references to valid blocks.
+system.cpu3.l1c.sampled_refs                    22277                       # Sample count of references to valid blocks.
+system.cpu3.l1c.avg_refs                     0.593347                       # Average number of references to valid blocks.
 system.cpu3.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.cpu3.l1c.occ_blocks::cpu3           395.971374                       # Average occupied blocks per requestor
-system.cpu3.l1c.occ_percent::cpu3            0.773382                       # Average percentage of cache occupancy
-system.cpu3.l1c.occ_percent::total           0.773382                       # Average percentage of cache occupancy
-system.cpu3.l1c.ReadReq_hits::cpu3               8374                       # number of ReadReq hits
-system.cpu3.l1c.ReadReq_hits::total              8374                       # number of ReadReq hits
-system.cpu3.l1c.WriteReq_hits::cpu3              1100                       # number of WriteReq hits
-system.cpu3.l1c.WriteReq_hits::total             1100                       # number of WriteReq hits
-system.cpu3.l1c.demand_hits::cpu3                9474                       # number of demand (read+write) hits
-system.cpu3.l1c.demand_hits::total               9474                       # number of demand (read+write) hits
-system.cpu3.l1c.overall_hits::cpu3               9474                       # number of overall hits
-system.cpu3.l1c.overall_hits::total              9474                       # number of overall hits
-system.cpu3.l1c.ReadReq_misses::cpu3            35667                       # number of ReadReq misses
-system.cpu3.l1c.ReadReq_misses::total           35667                       # number of ReadReq misses
-system.cpu3.l1c.WriteReq_misses::cpu3           23305                       # number of WriteReq misses
-system.cpu3.l1c.WriteReq_misses::total          23305                       # number of WriteReq misses
-system.cpu3.l1c.demand_misses::cpu3             58972                       # number of demand (read+write) misses
-system.cpu3.l1c.demand_misses::total            58972                       # number of demand (read+write) misses
-system.cpu3.l1c.overall_misses::cpu3            58972                       # number of overall misses
-system.cpu3.l1c.overall_misses::total           58972                       # number of overall misses
-system.cpu3.l1c.ReadReq_miss_latency::cpu3    919630073                       # number of ReadReq miss cycles
-system.cpu3.l1c.ReadReq_miss_latency::total    919630073                       # number of ReadReq miss cycles
-system.cpu3.l1c.WriteReq_miss_latency::cpu3    893117472                       # number of WriteReq miss cycles
-system.cpu3.l1c.WriteReq_miss_latency::total    893117472                       # number of WriteReq miss cycles
-system.cpu3.l1c.demand_miss_latency::cpu3   1812747545                       # number of demand (read+write) miss cycles
-system.cpu3.l1c.demand_miss_latency::total   1812747545                       # number of demand (read+write) miss cycles
-system.cpu3.l1c.overall_miss_latency::cpu3   1812747545                       # number of overall miss cycles
-system.cpu3.l1c.overall_miss_latency::total   1812747545                       # number of overall miss cycles
-system.cpu3.l1c.ReadReq_accesses::cpu3          44041                       # number of ReadReq accesses(hits+misses)
-system.cpu3.l1c.ReadReq_accesses::total         44041                       # number of ReadReq accesses(hits+misses)
-system.cpu3.l1c.WriteReq_accesses::cpu3         24405                       # number of WriteReq accesses(hits+misses)
-system.cpu3.l1c.WriteReq_accesses::total        24405                       # number of WriteReq accesses(hits+misses)
-system.cpu3.l1c.demand_accesses::cpu3           68446                       # number of demand (read+write) accesses
-system.cpu3.l1c.demand_accesses::total          68446                       # number of demand (read+write) accesses
-system.cpu3.l1c.overall_accesses::cpu3          68446                       # number of overall (read+write) accesses
-system.cpu3.l1c.overall_accesses::total         68446                       # number of overall (read+write) accesses
-system.cpu3.l1c.ReadReq_miss_rate::cpu3      0.809859                       # miss rate for ReadReq accesses
-system.cpu3.l1c.ReadReq_miss_rate::total     0.809859                       # miss rate for ReadReq accesses
-system.cpu3.l1c.WriteReq_miss_rate::cpu3     0.954927                       # miss rate for WriteReq accesses
-system.cpu3.l1c.WriteReq_miss_rate::total     0.954927                       # miss rate for WriteReq accesses
-system.cpu3.l1c.demand_miss_rate::cpu3       0.861584                       # miss rate for demand accesses
-system.cpu3.l1c.demand_miss_rate::total      0.861584                       # miss rate for demand accesses
-system.cpu3.l1c.overall_miss_rate::cpu3      0.861584                       # miss rate for overall accesses
-system.cpu3.l1c.overall_miss_rate::total     0.861584                       # miss rate for overall accesses
-system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 25783.779768                       # average ReadReq miss latency
-system.cpu3.l1c.ReadReq_avg_miss_latency::total 25783.779768                       # average ReadReq miss latency
-system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 38322.998155                       # average WriteReq miss latency
-system.cpu3.l1c.WriteReq_avg_miss_latency::total 38322.998155                       # average WriteReq miss latency
-system.cpu3.l1c.demand_avg_miss_latency::cpu3 30739.122719                       # average overall miss latency
-system.cpu3.l1c.demand_avg_miss_latency::total 30739.122719                       # average overall miss latency
-system.cpu3.l1c.overall_avg_miss_latency::cpu3 30739.122719                       # average overall miss latency
-system.cpu3.l1c.overall_avg_miss_latency::total 30739.122719                       # average overall miss latency
-system.cpu3.l1c.blocked_cycles::no_mshrs    213693223                       # number of cycles access was blocked
+system.cpu3.l1c.occ_blocks::cpu3           395.683419                       # Average occupied blocks per requestor
+system.cpu3.l1c.occ_percent::cpu3            0.772819                       # Average percentage of cache occupancy
+system.cpu3.l1c.occ_percent::total           0.772819                       # Average percentage of cache occupancy
+system.cpu3.l1c.ReadReq_hits::cpu3               8562                       # number of ReadReq hits
+system.cpu3.l1c.ReadReq_hits::total              8562                       # number of ReadReq hits
+system.cpu3.l1c.WriteReq_hits::cpu3              1098                       # number of WriteReq hits
+system.cpu3.l1c.WriteReq_hits::total             1098                       # number of WriteReq hits
+system.cpu3.l1c.demand_hits::cpu3                9660                       # number of demand (read+write) hits
+system.cpu3.l1c.demand_hits::total               9660                       # number of demand (read+write) hits
+system.cpu3.l1c.overall_hits::cpu3               9660                       # number of overall hits
+system.cpu3.l1c.overall_hits::total              9660                       # number of overall hits
+system.cpu3.l1c.ReadReq_misses::cpu3            35996                       # number of ReadReq misses
+system.cpu3.l1c.ReadReq_misses::total           35996                       # number of ReadReq misses
+system.cpu3.l1c.WriteReq_misses::cpu3           23029                       # number of WriteReq misses
+system.cpu3.l1c.WriteReq_misses::total          23029                       # number of WriteReq misses
+system.cpu3.l1c.demand_misses::cpu3             59025                       # number of demand (read+write) misses
+system.cpu3.l1c.demand_misses::total            59025                       # number of demand (read+write) misses
+system.cpu3.l1c.overall_misses::cpu3            59025                       # number of overall misses
+system.cpu3.l1c.overall_misses::total           59025                       # number of overall misses
+system.cpu3.l1c.ReadReq_miss_latency::cpu3    899058428                       # number of ReadReq miss cycles
+system.cpu3.l1c.ReadReq_miss_latency::total    899058428                       # number of ReadReq miss cycles
+system.cpu3.l1c.WriteReq_miss_latency::cpu3    817455350                       # number of WriteReq miss cycles
+system.cpu3.l1c.WriteReq_miss_latency::total    817455350                       # number of WriteReq miss cycles
+system.cpu3.l1c.demand_miss_latency::cpu3   1716513778                       # number of demand (read+write) miss cycles
+system.cpu3.l1c.demand_miss_latency::total   1716513778                       # number of demand (read+write) miss cycles
+system.cpu3.l1c.overall_miss_latency::cpu3   1716513778                       # number of overall miss cycles
+system.cpu3.l1c.overall_miss_latency::total   1716513778                       # number of overall miss cycles
+system.cpu3.l1c.ReadReq_accesses::cpu3          44558                       # number of ReadReq accesses(hits+misses)
+system.cpu3.l1c.ReadReq_accesses::total         44558                       # number of ReadReq accesses(hits+misses)
+system.cpu3.l1c.WriteReq_accesses::cpu3         24127                       # number of WriteReq accesses(hits+misses)
+system.cpu3.l1c.WriteReq_accesses::total        24127                       # number of WriteReq accesses(hits+misses)
+system.cpu3.l1c.demand_accesses::cpu3           68685                       # number of demand (read+write) accesses
+system.cpu3.l1c.demand_accesses::total          68685                       # number of demand (read+write) accesses
+system.cpu3.l1c.overall_accesses::cpu3          68685                       # number of overall (read+write) accesses
+system.cpu3.l1c.overall_accesses::total         68685                       # number of overall (read+write) accesses
+system.cpu3.l1c.ReadReq_miss_rate::cpu3      0.807846                       # miss rate for ReadReq accesses
+system.cpu3.l1c.ReadReq_miss_rate::total     0.807846                       # miss rate for ReadReq accesses
+system.cpu3.l1c.WriteReq_miss_rate::cpu3     0.954491                       # miss rate for WriteReq accesses
+system.cpu3.l1c.WriteReq_miss_rate::total     0.954491                       # miss rate for WriteReq accesses
+system.cpu3.l1c.demand_miss_rate::cpu3       0.859358                       # miss rate for demand accesses
+system.cpu3.l1c.demand_miss_rate::total      0.859358                       # miss rate for demand accesses
+system.cpu3.l1c.overall_miss_rate::cpu3      0.859358                       # miss rate for overall accesses
+system.cpu3.l1c.overall_miss_rate::total     0.859358                       # miss rate for overall accesses
+system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 24976.620402                       # average ReadReq miss latency
+system.cpu3.l1c.ReadReq_avg_miss_latency::total 24976.620402                       # average ReadReq miss latency
+system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 35496.780147                       # average WriteReq miss latency
+system.cpu3.l1c.WriteReq_avg_miss_latency::total 35496.780147                       # average WriteReq miss latency
+system.cpu3.l1c.demand_avg_miss_latency::cpu3 29081.131351                       # average overall miss latency
+system.cpu3.l1c.demand_avg_miss_latency::total 29081.131351                       # average overall miss latency
+system.cpu3.l1c.overall_avg_miss_latency::cpu3 29081.131351                       # average overall miss latency
+system.cpu3.l1c.overall_avg_miss_latency::total 29081.131351                       # average overall miss latency
+system.cpu3.l1c.blocked_cycles::no_mshrs    155038956                       # number of cycles access was blocked
 system.cpu3.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu3.l1c.blocked::no_mshrs               67039                       # number of cycles access was blocked
+system.cpu3.l1c.blocked::no_mshrs               53124                       # number of cycles access was blocked
 system.cpu3.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu3.l1c.avg_blocked_cycles::no_mshrs  3187.595623                       # average number of cycles each access was blocked
+system.cpu3.l1c.avg_blocked_cycles::no_mshrs  2918.435283                       # average number of cycles each access was blocked
 system.cpu3.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu3.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu3.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu3.l1c.writebacks::writebacks           9546                       # number of writebacks
-system.cpu3.l1c.writebacks::total                9546                       # number of writebacks
-system.cpu3.l1c.ReadReq_mshr_misses::cpu3        35667                       # number of ReadReq MSHR misses
-system.cpu3.l1c.ReadReq_mshr_misses::total        35667                       # number of ReadReq MSHR misses
-system.cpu3.l1c.WriteReq_mshr_misses::cpu3        23305                       # number of WriteReq MSHR misses
-system.cpu3.l1c.WriteReq_mshr_misses::total        23305                       # number of WriteReq MSHR misses
-system.cpu3.l1c.demand_mshr_misses::cpu3        58972                       # number of demand (read+write) MSHR misses
-system.cpu3.l1c.demand_mshr_misses::total        58972                       # number of demand (read+write) MSHR misses
-system.cpu3.l1c.overall_mshr_misses::cpu3        58972                       # number of overall MSHR misses
-system.cpu3.l1c.overall_mshr_misses::total        58972                       # number of overall MSHR misses
-system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3    883822339                       # number of ReadReq MSHR miss cycles
-system.cpu3.l1c.ReadReq_mshr_miss_latency::total    883822339                       # number of ReadReq MSHR miss cycles
-system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3    869724232                       # number of WriteReq MSHR miss cycles
-system.cpu3.l1c.WriteReq_mshr_miss_latency::total    869724232                       # number of WriteReq MSHR miss cycles
-system.cpu3.l1c.demand_mshr_miss_latency::cpu3   1753546571                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.l1c.demand_mshr_miss_latency::total   1753546571                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_latency::cpu3   1753546571                       # number of overall MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_latency::total   1753546571                       # number of overall MSHR miss cycles
-system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3    901886993                       # number of ReadReq MSHR uncacheable cycles
-system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total    901886993                       # number of ReadReq MSHR uncacheable cycles
-system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3    561139437                       # number of WriteReq MSHR uncacheable cycles
-system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total    561139437                       # number of WriteReq MSHR uncacheable cycles
-system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3   1463026430                       # number of overall MSHR uncacheable cycles
-system.cpu3.l1c.overall_mshr_uncacheable_latency::total   1463026430                       # number of overall MSHR uncacheable cycles
-system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3     0.809859                       # mshr miss rate for ReadReq accesses
-system.cpu3.l1c.ReadReq_mshr_miss_rate::total     0.809859                       # mshr miss rate for ReadReq accesses
-system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3     0.954927                       # mshr miss rate for WriteReq accesses
-system.cpu3.l1c.WriteReq_mshr_miss_rate::total     0.954927                       # mshr miss rate for WriteReq accesses
-system.cpu3.l1c.demand_mshr_miss_rate::cpu3     0.861584                       # mshr miss rate for demand accesses
-system.cpu3.l1c.demand_mshr_miss_rate::total     0.861584                       # mshr miss rate for demand accesses
-system.cpu3.l1c.overall_mshr_miss_rate::cpu3     0.861584                       # mshr miss rate for overall accesses
-system.cpu3.l1c.overall_mshr_miss_rate::total     0.861584                       # mshr miss rate for overall accesses
-system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 24779.833992                       # average ReadReq mshr miss latency
-system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 24779.833992                       # average ReadReq mshr miss latency
-system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 37319.211843                       # average WriteReq mshr miss latency
-system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 37319.211843                       # average WriteReq mshr miss latency
-system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 29735.239961                       # average overall mshr miss latency
-system.cpu3.l1c.demand_avg_mshr_miss_latency::total 29735.239961                       # average overall mshr miss latency
-system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 29735.239961                       # average overall mshr miss latency
-system.cpu3.l1c.overall_avg_mshr_miss_latency::total 29735.239961                       # average overall mshr miss latency
+system.cpu3.l1c.writebacks::writebacks           9442                       # number of writebacks
+system.cpu3.l1c.writebacks::total                9442                       # number of writebacks
+system.cpu3.l1c.ReadReq_mshr_misses::cpu3        35996                       # number of ReadReq MSHR misses
+system.cpu3.l1c.ReadReq_mshr_misses::total        35996                       # number of ReadReq MSHR misses
+system.cpu3.l1c.WriteReq_mshr_misses::cpu3        23029                       # number of WriteReq MSHR misses
+system.cpu3.l1c.WriteReq_mshr_misses::total        23029                       # number of WriteReq MSHR misses
+system.cpu3.l1c.demand_mshr_misses::cpu3        59025                       # number of demand (read+write) MSHR misses
+system.cpu3.l1c.demand_mshr_misses::total        59025                       # number of demand (read+write) MSHR misses
+system.cpu3.l1c.overall_mshr_misses::cpu3        59025                       # number of overall MSHR misses
+system.cpu3.l1c.overall_mshr_misses::total        59025                       # number of overall MSHR misses
+system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3    862924447                       # number of ReadReq MSHR miss cycles
+system.cpu3.l1c.ReadReq_mshr_miss_latency::total    862924447                       # number of ReadReq MSHR miss cycles
+system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3    794336234                       # number of WriteReq MSHR miss cycles
+system.cpu3.l1c.WriteReq_mshr_miss_latency::total    794336234                       # number of WriteReq MSHR miss cycles
+system.cpu3.l1c.demand_mshr_miss_latency::cpu3   1657260681                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.l1c.demand_mshr_miss_latency::total   1657260681                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.l1c.overall_mshr_miss_latency::cpu3   1657260681                       # number of overall MSHR miss cycles
+system.cpu3.l1c.overall_mshr_miss_latency::total   1657260681                       # number of overall MSHR miss cycles
+system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3    680106792                       # number of ReadReq MSHR uncacheable cycles
+system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total    680106792                       # number of ReadReq MSHR uncacheable cycles
+system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3    674669668                       # number of WriteReq MSHR uncacheable cycles
+system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total    674669668                       # number of WriteReq MSHR uncacheable cycles
+system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3   1354776460                       # number of overall MSHR uncacheable cycles
+system.cpu3.l1c.overall_mshr_uncacheable_latency::total   1354776460                       # number of overall MSHR uncacheable cycles
+system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3     0.807846                       # mshr miss rate for ReadReq accesses
+system.cpu3.l1c.ReadReq_mshr_miss_rate::total     0.807846                       # mshr miss rate for ReadReq accesses
+system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3     0.954491                       # mshr miss rate for WriteReq accesses
+system.cpu3.l1c.WriteReq_mshr_miss_rate::total     0.954491                       # mshr miss rate for WriteReq accesses
+system.cpu3.l1c.demand_mshr_miss_rate::cpu3     0.859358                       # mshr miss rate for demand accesses
+system.cpu3.l1c.demand_mshr_miss_rate::total     0.859358                       # mshr miss rate for demand accesses
+system.cpu3.l1c.overall_mshr_miss_rate::cpu3     0.859358                       # mshr miss rate for overall accesses
+system.cpu3.l1c.overall_mshr_miss_rate::total     0.859358                       # mshr miss rate for overall accesses
+system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 23972.787171                       # average ReadReq mshr miss latency
+system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 23972.787171                       # average ReadReq mshr miss latency
+system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 34492.866994                       # average WriteReq mshr miss latency
+system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 34492.866994                       # average WriteReq mshr miss latency
+system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 28077.266938                       # average overall mshr miss latency
+system.cpu3.l1c.demand_avg_mshr_miss_latency::total 28077.266938                       # average overall mshr miss latency
+system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 28077.266938                       # average overall mshr miss latency
+system.cpu3.l1c.overall_avg_mshr_miss_latency::total 28077.266938                       # average overall mshr miss latency
 system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3          inf                       # average ReadReq mshr uncacheable latency
 system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3          inf                       # average WriteReq mshr uncacheable latency
@@ -1120,114 +1123,114 @@ system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3          inf                       # average overall mshr uncacheable latency
 system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu3.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu4.num_reads                          100000                       # number of read accesses completed
-system.cpu4.num_writes                          53697                       # number of write accesses completed
+system.cpu4.num_reads                           99591                       # number of read accesses completed
+system.cpu4.num_writes                          53646                       # number of write accesses completed
 system.cpu4.num_copies                              0                       # number of copy accesses completed
-system.cpu4.l1c.replacements                    22069                       # number of replacements
-system.cpu4.l1c.tagsinuse                  396.565187                       # Cycle average of tags in use
-system.cpu4.l1c.total_refs                      13244                       # Total number of references to valid blocks.
-system.cpu4.l1c.sampled_refs                    22489                       # Sample count of references to valid blocks.
-system.cpu4.l1c.avg_refs                     0.588910                       # Average number of references to valid blocks.
+system.cpu4.l1c.replacements                    22293                       # number of replacements
+system.cpu4.l1c.tagsinuse                  397.816545                       # Cycle average of tags in use
+system.cpu4.l1c.total_refs                      13327                       # Total number of references to valid blocks.
+system.cpu4.l1c.sampled_refs                    22684                       # Sample count of references to valid blocks.
+system.cpu4.l1c.avg_refs                     0.587507                       # Average number of references to valid blocks.
 system.cpu4.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.cpu4.l1c.occ_blocks::cpu4           396.565187                       # Average occupied blocks per requestor
-system.cpu4.l1c.occ_percent::cpu4            0.774541                       # Average percentage of cache occupancy
-system.cpu4.l1c.occ_percent::total           0.774541                       # Average percentage of cache occupancy
-system.cpu4.l1c.ReadReq_hits::cpu4               8614                       # number of ReadReq hits
-system.cpu4.l1c.ReadReq_hits::total              8614                       # number of ReadReq hits
-system.cpu4.l1c.WriteReq_hits::cpu4              1053                       # number of WriteReq hits
-system.cpu4.l1c.WriteReq_hits::total             1053                       # number of WriteReq hits
-system.cpu4.l1c.demand_hits::cpu4                9667                       # number of demand (read+write) hits
-system.cpu4.l1c.demand_hits::total               9667                       # number of demand (read+write) hits
-system.cpu4.l1c.overall_hits::cpu4               9667                       # number of overall hits
-system.cpu4.l1c.overall_hits::total              9667                       # number of overall hits
-system.cpu4.l1c.ReadReq_misses::cpu4            36078                       # number of ReadReq misses
-system.cpu4.l1c.ReadReq_misses::total           36078                       # number of ReadReq misses
-system.cpu4.l1c.WriteReq_misses::cpu4           23045                       # number of WriteReq misses
-system.cpu4.l1c.WriteReq_misses::total          23045                       # number of WriteReq misses
-system.cpu4.l1c.demand_misses::cpu4             59123                       # number of demand (read+write) misses
-system.cpu4.l1c.demand_misses::total            59123                       # number of demand (read+write) misses
-system.cpu4.l1c.overall_misses::cpu4            59123                       # number of overall misses
-system.cpu4.l1c.overall_misses::total           59123                       # number of overall misses
-system.cpu4.l1c.ReadReq_miss_latency::cpu4    933502205                       # number of ReadReq miss cycles
-system.cpu4.l1c.ReadReq_miss_latency::total    933502205                       # number of ReadReq miss cycles
-system.cpu4.l1c.WriteReq_miss_latency::cpu4    883607398                       # number of WriteReq miss cycles
-system.cpu4.l1c.WriteReq_miss_latency::total    883607398                       # number of WriteReq miss cycles
-system.cpu4.l1c.demand_miss_latency::cpu4   1817109603                       # number of demand (read+write) miss cycles
-system.cpu4.l1c.demand_miss_latency::total   1817109603                       # number of demand (read+write) miss cycles
-system.cpu4.l1c.overall_miss_latency::cpu4   1817109603                       # number of overall miss cycles
-system.cpu4.l1c.overall_miss_latency::total   1817109603                       # number of overall miss cycles
-system.cpu4.l1c.ReadReq_accesses::cpu4          44692                       # number of ReadReq accesses(hits+misses)
-system.cpu4.l1c.ReadReq_accesses::total         44692                       # number of ReadReq accesses(hits+misses)
-system.cpu4.l1c.WriteReq_accesses::cpu4         24098                       # number of WriteReq accesses(hits+misses)
-system.cpu4.l1c.WriteReq_accesses::total        24098                       # number of WriteReq accesses(hits+misses)
-system.cpu4.l1c.demand_accesses::cpu4           68790                       # number of demand (read+write) accesses
-system.cpu4.l1c.demand_accesses::total          68790                       # number of demand (read+write) accesses
-system.cpu4.l1c.overall_accesses::cpu4          68790                       # number of overall (read+write) accesses
-system.cpu4.l1c.overall_accesses::total         68790                       # number of overall (read+write) accesses
-system.cpu4.l1c.ReadReq_miss_rate::cpu4      0.807259                       # miss rate for ReadReq accesses
-system.cpu4.l1c.ReadReq_miss_rate::total     0.807259                       # miss rate for ReadReq accesses
-system.cpu4.l1c.WriteReq_miss_rate::cpu4     0.956303                       # miss rate for WriteReq accesses
-system.cpu4.l1c.WriteReq_miss_rate::total     0.956303                       # miss rate for WriteReq accesses
-system.cpu4.l1c.demand_miss_rate::cpu4       0.859471                       # miss rate for demand accesses
-system.cpu4.l1c.demand_miss_rate::total      0.859471                       # miss rate for demand accesses
-system.cpu4.l1c.overall_miss_rate::cpu4      0.859471                       # miss rate for overall accesses
-system.cpu4.l1c.overall_miss_rate::total     0.859471                       # miss rate for overall accesses
-system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 25874.555269                       # average ReadReq miss latency
-system.cpu4.l1c.ReadReq_avg_miss_latency::total 25874.555269                       # average ReadReq miss latency
-system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 38342.694641                       # average WriteReq miss latency
-system.cpu4.l1c.WriteReq_avg_miss_latency::total 38342.694641                       # average WriteReq miss latency
-system.cpu4.l1c.demand_avg_miss_latency::cpu4 30734.394449                       # average overall miss latency
-system.cpu4.l1c.demand_avg_miss_latency::total 30734.394449                       # average overall miss latency
-system.cpu4.l1c.overall_avg_miss_latency::cpu4 30734.394449                       # average overall miss latency
-system.cpu4.l1c.overall_avg_miss_latency::total 30734.394449                       # average overall miss latency
-system.cpu4.l1c.blocked_cycles::no_mshrs    213249503                       # number of cycles access was blocked
+system.cpu4.l1c.occ_blocks::cpu4           397.816545                       # Average occupied blocks per requestor
+system.cpu4.l1c.occ_percent::cpu4            0.776985                       # Average percentage of cache occupancy
+system.cpu4.l1c.occ_percent::total           0.776985                       # Average percentage of cache occupancy
+system.cpu4.l1c.ReadReq_hits::cpu4               8743                       # number of ReadReq hits
+system.cpu4.l1c.ReadReq_hits::total              8743                       # number of ReadReq hits
+system.cpu4.l1c.WriteReq_hits::cpu4              1036                       # number of WriteReq hits
+system.cpu4.l1c.WriteReq_hits::total             1036                       # number of WriteReq hits
+system.cpu4.l1c.demand_hits::cpu4                9779                       # number of demand (read+write) hits
+system.cpu4.l1c.demand_hits::total               9779                       # number of demand (read+write) hits
+system.cpu4.l1c.overall_hits::cpu4               9779                       # number of overall hits
+system.cpu4.l1c.overall_hits::total              9779                       # number of overall hits
+system.cpu4.l1c.ReadReq_misses::cpu4            35998                       # number of ReadReq misses
+system.cpu4.l1c.ReadReq_misses::total           35998                       # number of ReadReq misses
+system.cpu4.l1c.WriteReq_misses::cpu4           23232                       # number of WriteReq misses
+system.cpu4.l1c.WriteReq_misses::total          23232                       # number of WriteReq misses
+system.cpu4.l1c.demand_misses::cpu4             59230                       # number of demand (read+write) misses
+system.cpu4.l1c.demand_misses::total            59230                       # number of demand (read+write) misses
+system.cpu4.l1c.overall_misses::cpu4            59230                       # number of overall misses
+system.cpu4.l1c.overall_misses::total           59230                       # number of overall misses
+system.cpu4.l1c.ReadReq_miss_latency::cpu4    899681935                       # number of ReadReq miss cycles
+system.cpu4.l1c.ReadReq_miss_latency::total    899681935                       # number of ReadReq miss cycles
+system.cpu4.l1c.WriteReq_miss_latency::cpu4    816003996                       # number of WriteReq miss cycles
+system.cpu4.l1c.WriteReq_miss_latency::total    816003996                       # number of WriteReq miss cycles
+system.cpu4.l1c.demand_miss_latency::cpu4   1715685931                       # number of demand (read+write) miss cycles
+system.cpu4.l1c.demand_miss_latency::total   1715685931                       # number of demand (read+write) miss cycles
+system.cpu4.l1c.overall_miss_latency::cpu4   1715685931                       # number of overall miss cycles
+system.cpu4.l1c.overall_miss_latency::total   1715685931                       # number of overall miss cycles
+system.cpu4.l1c.ReadReq_accesses::cpu4          44741                       # number of ReadReq accesses(hits+misses)
+system.cpu4.l1c.ReadReq_accesses::total         44741                       # number of ReadReq accesses(hits+misses)
+system.cpu4.l1c.WriteReq_accesses::cpu4         24268                       # number of WriteReq accesses(hits+misses)
+system.cpu4.l1c.WriteReq_accesses::total        24268                       # number of WriteReq accesses(hits+misses)
+system.cpu4.l1c.demand_accesses::cpu4           69009                       # number of demand (read+write) accesses
+system.cpu4.l1c.demand_accesses::total          69009                       # number of demand (read+write) accesses
+system.cpu4.l1c.overall_accesses::cpu4          69009                       # number of overall (read+write) accesses
+system.cpu4.l1c.overall_accesses::total         69009                       # number of overall (read+write) accesses
+system.cpu4.l1c.ReadReq_miss_rate::cpu4      0.804586                       # miss rate for ReadReq accesses
+system.cpu4.l1c.ReadReq_miss_rate::total     0.804586                       # miss rate for ReadReq accesses
+system.cpu4.l1c.WriteReq_miss_rate::cpu4     0.957310                       # miss rate for WriteReq accesses
+system.cpu4.l1c.WriteReq_miss_rate::total     0.957310                       # miss rate for WriteReq accesses
+system.cpu4.l1c.demand_miss_rate::cpu4       0.858294                       # miss rate for demand accesses
+system.cpu4.l1c.demand_miss_rate::total      0.858294                       # miss rate for demand accesses
+system.cpu4.l1c.overall_miss_rate::cpu4      0.858294                       # miss rate for overall accesses
+system.cpu4.l1c.overall_miss_rate::total     0.858294                       # miss rate for overall accesses
+system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 24992.553336                       # average ReadReq miss latency
+system.cpu4.l1c.ReadReq_avg_miss_latency::total 24992.553336                       # average ReadReq miss latency
+system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 35124.138946                       # average WriteReq miss latency
+system.cpu4.l1c.WriteReq_avg_miss_latency::total 35124.138946                       # average WriteReq miss latency
+system.cpu4.l1c.demand_avg_miss_latency::cpu4 28966.502296                       # average overall miss latency
+system.cpu4.l1c.demand_avg_miss_latency::total 28966.502296                       # average overall miss latency
+system.cpu4.l1c.overall_avg_miss_latency::cpu4 28966.502296                       # average overall miss latency
+system.cpu4.l1c.overall_avg_miss_latency::total 28966.502296                       # average overall miss latency
+system.cpu4.l1c.blocked_cycles::no_mshrs    154355931                       # number of cycles access was blocked
 system.cpu4.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu4.l1c.blocked::no_mshrs               67264                       # number of cycles access was blocked
+system.cpu4.l1c.blocked::no_mshrs               53171                       # number of cycles access was blocked
 system.cpu4.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu4.l1c.avg_blocked_cycles::no_mshrs  3170.336331                       # average number of cycles each access was blocked
+system.cpu4.l1c.avg_blocked_cycles::no_mshrs  2903.009742                       # average number of cycles each access was blocked
 system.cpu4.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu4.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu4.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu4.l1c.writebacks::writebacks           9627                       # number of writebacks
-system.cpu4.l1c.writebacks::total                9627                       # number of writebacks
-system.cpu4.l1c.ReadReq_mshr_misses::cpu4        36078                       # number of ReadReq MSHR misses
-system.cpu4.l1c.ReadReq_mshr_misses::total        36078                       # number of ReadReq MSHR misses
-system.cpu4.l1c.WriteReq_mshr_misses::cpu4        23045                       # number of WriteReq MSHR misses
-system.cpu4.l1c.WriteReq_mshr_misses::total        23045                       # number of WriteReq MSHR misses
-system.cpu4.l1c.demand_mshr_misses::cpu4        59123                       # number of demand (read+write) MSHR misses
-system.cpu4.l1c.demand_mshr_misses::total        59123                       # number of demand (read+write) MSHR misses
-system.cpu4.l1c.overall_mshr_misses::cpu4        59123                       # number of overall MSHR misses
-system.cpu4.l1c.overall_mshr_misses::total        59123                       # number of overall MSHR misses
-system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4    897285830                       # number of ReadReq MSHR miss cycles
-system.cpu4.l1c.ReadReq_mshr_miss_latency::total    897285830                       # number of ReadReq MSHR miss cycles
-system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4    860474190                       # number of WriteReq MSHR miss cycles
-system.cpu4.l1c.WriteReq_mshr_miss_latency::total    860474190                       # number of WriteReq MSHR miss cycles
-system.cpu4.l1c.demand_mshr_miss_latency::cpu4   1757760020                       # number of demand (read+write) MSHR miss cycles
-system.cpu4.l1c.demand_mshr_miss_latency::total   1757760020                       # number of demand (read+write) MSHR miss cycles
-system.cpu4.l1c.overall_mshr_miss_latency::cpu4   1757760020                       # number of overall MSHR miss cycles
-system.cpu4.l1c.overall_mshr_miss_latency::total   1757760020                       # number of overall MSHR miss cycles
-system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4    897898466                       # number of ReadReq MSHR uncacheable cycles
-system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total    897898466                       # number of ReadReq MSHR uncacheable cycles
-system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4    564390024                       # number of WriteReq MSHR uncacheable cycles
-system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total    564390024                       # number of WriteReq MSHR uncacheable cycles
-system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4   1462288490                       # number of overall MSHR uncacheable cycles
-system.cpu4.l1c.overall_mshr_uncacheable_latency::total   1462288490                       # number of overall MSHR uncacheable cycles
-system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4     0.807259                       # mshr miss rate for ReadReq accesses
-system.cpu4.l1c.ReadReq_mshr_miss_rate::total     0.807259                       # mshr miss rate for ReadReq accesses
-system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4     0.956303                       # mshr miss rate for WriteReq accesses
-system.cpu4.l1c.WriteReq_mshr_miss_rate::total     0.956303                       # mshr miss rate for WriteReq accesses
-system.cpu4.l1c.demand_mshr_miss_rate::cpu4     0.859471                       # mshr miss rate for demand accesses
-system.cpu4.l1c.demand_mshr_miss_rate::total     0.859471                       # mshr miss rate for demand accesses
-system.cpu4.l1c.overall_mshr_miss_rate::cpu4     0.859471                       # mshr miss rate for overall accesses
-system.cpu4.l1c.overall_mshr_miss_rate::total     0.859471                       # mshr miss rate for overall accesses
-system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 24870.719829                       # average ReadReq mshr miss latency
-system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 24870.719829                       # average ReadReq mshr miss latency
-system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 37338.866999                       # average WriteReq mshr miss latency
-system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 37338.866999                       # average WriteReq mshr miss latency
-system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 29730.562049                       # average overall mshr miss latency
-system.cpu4.l1c.demand_avg_mshr_miss_latency::total 29730.562049                       # average overall mshr miss latency
-system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 29730.562049                       # average overall mshr miss latency
-system.cpu4.l1c.overall_avg_mshr_miss_latency::total 29730.562049                       # average overall mshr miss latency
+system.cpu4.l1c.writebacks::writebacks           9702                       # number of writebacks
+system.cpu4.l1c.writebacks::total                9702                       # number of writebacks
+system.cpu4.l1c.ReadReq_mshr_misses::cpu4        35998                       # number of ReadReq MSHR misses
+system.cpu4.l1c.ReadReq_mshr_misses::total        35998                       # number of ReadReq MSHR misses
+system.cpu4.l1c.WriteReq_mshr_misses::cpu4        23232                       # number of WriteReq MSHR misses
+system.cpu4.l1c.WriteReq_mshr_misses::total        23232                       # number of WriteReq MSHR misses
+system.cpu4.l1c.demand_mshr_misses::cpu4        59230                       # number of demand (read+write) MSHR misses
+system.cpu4.l1c.demand_mshr_misses::total        59230                       # number of demand (read+write) MSHR misses
+system.cpu4.l1c.overall_mshr_misses::cpu4        59230                       # number of overall MSHR misses
+system.cpu4.l1c.overall_mshr_misses::total        59230                       # number of overall MSHR misses
+system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4    863541936                       # number of ReadReq MSHR miss cycles
+system.cpu4.l1c.ReadReq_mshr_miss_latency::total    863541936                       # number of ReadReq MSHR miss cycles
+system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4    792684079                       # number of WriteReq MSHR miss cycles
+system.cpu4.l1c.WriteReq_mshr_miss_latency::total    792684079                       # number of WriteReq MSHR miss cycles
+system.cpu4.l1c.demand_mshr_miss_latency::cpu4   1656226015                       # number of demand (read+write) MSHR miss cycles
+system.cpu4.l1c.demand_mshr_miss_latency::total   1656226015                       # number of demand (read+write) MSHR miss cycles
+system.cpu4.l1c.overall_mshr_miss_latency::cpu4   1656226015                       # number of overall MSHR miss cycles
+system.cpu4.l1c.overall_mshr_miss_latency::total   1656226015                       # number of overall MSHR miss cycles
+system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4    681350371                       # number of ReadReq MSHR uncacheable cycles
+system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total    681350371                       # number of ReadReq MSHR uncacheable cycles
+system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4    669996228                       # number of WriteReq MSHR uncacheable cycles
+system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total    669996228                       # number of WriteReq MSHR uncacheable cycles
+system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4   1351346599                       # number of overall MSHR uncacheable cycles
+system.cpu4.l1c.overall_mshr_uncacheable_latency::total   1351346599                       # number of overall MSHR uncacheable cycles
+system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4     0.804586                       # mshr miss rate for ReadReq accesses
+system.cpu4.l1c.ReadReq_mshr_miss_rate::total     0.804586                       # mshr miss rate for ReadReq accesses
+system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4     0.957310                       # mshr miss rate for WriteReq accesses
+system.cpu4.l1c.WriteReq_mshr_miss_rate::total     0.957310                       # mshr miss rate for WriteReq accesses
+system.cpu4.l1c.demand_mshr_miss_rate::cpu4     0.858294                       # mshr miss rate for demand accesses
+system.cpu4.l1c.demand_mshr_miss_rate::total     0.858294                       # mshr miss rate for demand accesses
+system.cpu4.l1c.overall_mshr_miss_rate::cpu4     0.858294                       # mshr miss rate for overall accesses
+system.cpu4.l1c.overall_mshr_miss_rate::total     0.858294                       # mshr miss rate for overall accesses
+system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 23988.608700                       # average ReadReq mshr miss latency
+system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 23988.608700                       # average ReadReq mshr miss latency
+system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 34120.354640                       # average WriteReq mshr miss latency
+system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 34120.354640                       # average WriteReq mshr miss latency
+system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 27962.620547                       # average overall mshr miss latency
+system.cpu4.l1c.demand_avg_mshr_miss_latency::total 27962.620547                       # average overall mshr miss latency
+system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 27962.620547                       # average overall mshr miss latency
+system.cpu4.l1c.overall_avg_mshr_miss_latency::total 27962.620547                       # average overall mshr miss latency
 system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4          inf                       # average ReadReq mshr uncacheable latency
 system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4          inf                       # average WriteReq mshr uncacheable latency
@@ -1235,114 +1238,114 @@ system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4          inf                       # average overall mshr uncacheable latency
 system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu4.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu5.num_reads                           98755                       # number of read accesses completed
-system.cpu5.num_writes                          53000                       # number of write accesses completed
+system.cpu5.num_reads                           99523                       # number of read accesses completed
+system.cpu5.num_writes                          53948                       # number of write accesses completed
 system.cpu5.num_copies                              0                       # number of copy accesses completed
-system.cpu5.l1c.replacements                    21964                       # number of replacements
-system.cpu5.l1c.tagsinuse                  395.335157                       # Cycle average of tags in use
-system.cpu5.l1c.total_refs                      13162                       # Total number of references to valid blocks.
-system.cpu5.l1c.sampled_refs                    22364                       # Sample count of references to valid blocks.
-system.cpu5.l1c.avg_refs                     0.588535                       # Average number of references to valid blocks.
+system.cpu5.l1c.replacements                    22088                       # number of replacements
+system.cpu5.l1c.tagsinuse                  397.555659                       # Cycle average of tags in use
+system.cpu5.l1c.total_refs                      13442                       # Total number of references to valid blocks.
+system.cpu5.l1c.sampled_refs                    22486                       # Sample count of references to valid blocks.
+system.cpu5.l1c.avg_refs                     0.597794                       # Average number of references to valid blocks.
 system.cpu5.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.cpu5.l1c.occ_blocks::cpu5           395.335157                       # Average occupied blocks per requestor
-system.cpu5.l1c.occ_percent::cpu5            0.772139                       # Average percentage of cache occupancy
-system.cpu5.l1c.occ_percent::total           0.772139                       # Average percentage of cache occupancy
-system.cpu5.l1c.ReadReq_hits::cpu5               8580                       # number of ReadReq hits
-system.cpu5.l1c.ReadReq_hits::total              8580                       # number of ReadReq hits
-system.cpu5.l1c.WriteReq_hits::cpu5              1063                       # number of WriteReq hits
-system.cpu5.l1c.WriteReq_hits::total             1063                       # number of WriteReq hits
-system.cpu5.l1c.demand_hits::cpu5                9643                       # number of demand (read+write) hits
-system.cpu5.l1c.demand_hits::total               9643                       # number of demand (read+write) hits
-system.cpu5.l1c.overall_hits::cpu5               9643                       # number of overall hits
-system.cpu5.l1c.overall_hits::total              9643                       # number of overall hits
-system.cpu5.l1c.ReadReq_misses::cpu5            36060                       # number of ReadReq misses
-system.cpu5.l1c.ReadReq_misses::total           36060                       # number of ReadReq misses
-system.cpu5.l1c.WriteReq_misses::cpu5           22989                       # number of WriteReq misses
-system.cpu5.l1c.WriteReq_misses::total          22989                       # number of WriteReq misses
-system.cpu5.l1c.demand_misses::cpu5             59049                       # number of demand (read+write) misses
-system.cpu5.l1c.demand_misses::total            59049                       # number of demand (read+write) misses
-system.cpu5.l1c.overall_misses::cpu5            59049                       # number of overall misses
-system.cpu5.l1c.overall_misses::total           59049                       # number of overall misses
-system.cpu5.l1c.ReadReq_miss_latency::cpu5    944228607                       # number of ReadReq miss cycles
-system.cpu5.l1c.ReadReq_miss_latency::total    944228607                       # number of ReadReq miss cycles
-system.cpu5.l1c.WriteReq_miss_latency::cpu5    875107262                       # number of WriteReq miss cycles
-system.cpu5.l1c.WriteReq_miss_latency::total    875107262                       # number of WriteReq miss cycles
-system.cpu5.l1c.demand_miss_latency::cpu5   1819335869                       # number of demand (read+write) miss cycles
-system.cpu5.l1c.demand_miss_latency::total   1819335869                       # number of demand (read+write) miss cycles
-system.cpu5.l1c.overall_miss_latency::cpu5   1819335869                       # number of overall miss cycles
-system.cpu5.l1c.overall_miss_latency::total   1819335869                       # number of overall miss cycles
-system.cpu5.l1c.ReadReq_accesses::cpu5          44640                       # number of ReadReq accesses(hits+misses)
-system.cpu5.l1c.ReadReq_accesses::total         44640                       # number of ReadReq accesses(hits+misses)
-system.cpu5.l1c.WriteReq_accesses::cpu5         24052                       # number of WriteReq accesses(hits+misses)
-system.cpu5.l1c.WriteReq_accesses::total        24052                       # number of WriteReq accesses(hits+misses)
-system.cpu5.l1c.demand_accesses::cpu5           68692                       # number of demand (read+write) accesses
-system.cpu5.l1c.demand_accesses::total          68692                       # number of demand (read+write) accesses
-system.cpu5.l1c.overall_accesses::cpu5          68692                       # number of overall (read+write) accesses
-system.cpu5.l1c.overall_accesses::total         68692                       # number of overall (read+write) accesses
-system.cpu5.l1c.ReadReq_miss_rate::cpu5      0.807796                       # miss rate for ReadReq accesses
-system.cpu5.l1c.ReadReq_miss_rate::total     0.807796                       # miss rate for ReadReq accesses
-system.cpu5.l1c.WriteReq_miss_rate::cpu5     0.955804                       # miss rate for WriteReq accesses
-system.cpu5.l1c.WriteReq_miss_rate::total     0.955804                       # miss rate for WriteReq accesses
-system.cpu5.l1c.demand_miss_rate::cpu5       0.859620                       # miss rate for demand accesses
-system.cpu5.l1c.demand_miss_rate::total      0.859620                       # miss rate for demand accesses
-system.cpu5.l1c.overall_miss_rate::cpu5      0.859620                       # miss rate for overall accesses
-system.cpu5.l1c.overall_miss_rate::total     0.859620                       # miss rate for overall accesses
-system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 26184.930865                       # average ReadReq miss latency
-system.cpu5.l1c.ReadReq_avg_miss_latency::total 26184.930865                       # average ReadReq miss latency
-system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 38066.347471                       # average WriteReq miss latency
-system.cpu5.l1c.WriteReq_avg_miss_latency::total 38066.347471                       # average WriteReq miss latency
-system.cpu5.l1c.demand_avg_miss_latency::cpu5 30810.612695                       # average overall miss latency
-system.cpu5.l1c.demand_avg_miss_latency::total 30810.612695                       # average overall miss latency
-system.cpu5.l1c.overall_avg_miss_latency::cpu5 30810.612695                       # average overall miss latency
-system.cpu5.l1c.overall_avg_miss_latency::total 30810.612695                       # average overall miss latency
-system.cpu5.l1c.blocked_cycles::no_mshrs    213071792                       # number of cycles access was blocked
+system.cpu5.l1c.occ_blocks::cpu5           397.555659                       # Average occupied blocks per requestor
+system.cpu5.l1c.occ_percent::cpu5            0.776476                       # Average percentage of cache occupancy
+system.cpu5.l1c.occ_percent::total           0.776476                       # Average percentage of cache occupancy
+system.cpu5.l1c.ReadReq_hits::cpu5               8700                       # number of ReadReq hits
+system.cpu5.l1c.ReadReq_hits::total              8700                       # number of ReadReq hits
+system.cpu5.l1c.WriteReq_hits::cpu5              1066                       # number of WriteReq hits
+system.cpu5.l1c.WriteReq_hits::total             1066                       # number of WriteReq hits
+system.cpu5.l1c.demand_hits::cpu5                9766                       # number of demand (read+write) hits
+system.cpu5.l1c.demand_hits::total               9766                       # number of demand (read+write) hits
+system.cpu5.l1c.overall_hits::cpu5               9766                       # number of overall hits
+system.cpu5.l1c.overall_hits::total              9766                       # number of overall hits
+system.cpu5.l1c.ReadReq_misses::cpu5            36016                       # number of ReadReq misses
+system.cpu5.l1c.ReadReq_misses::total           36016                       # number of ReadReq misses
+system.cpu5.l1c.WriteReq_misses::cpu5           23333                       # number of WriteReq misses
+system.cpu5.l1c.WriteReq_misses::total          23333                       # number of WriteReq misses
+system.cpu5.l1c.demand_misses::cpu5             59349                       # number of demand (read+write) misses
+system.cpu5.l1c.demand_misses::total            59349                       # number of demand (read+write) misses
+system.cpu5.l1c.overall_misses::cpu5            59349                       # number of overall misses
+system.cpu5.l1c.overall_misses::total           59349                       # number of overall misses
+system.cpu5.l1c.ReadReq_miss_latency::cpu5    899040098                       # number of ReadReq miss cycles
+system.cpu5.l1c.ReadReq_miss_latency::total    899040098                       # number of ReadReq miss cycles
+system.cpu5.l1c.WriteReq_miss_latency::cpu5    826704780                       # number of WriteReq miss cycles
+system.cpu5.l1c.WriteReq_miss_latency::total    826704780                       # number of WriteReq miss cycles
+system.cpu5.l1c.demand_miss_latency::cpu5   1725744878                       # number of demand (read+write) miss cycles
+system.cpu5.l1c.demand_miss_latency::total   1725744878                       # number of demand (read+write) miss cycles
+system.cpu5.l1c.overall_miss_latency::cpu5   1725744878                       # number of overall miss cycles
+system.cpu5.l1c.overall_miss_latency::total   1725744878                       # number of overall miss cycles
+system.cpu5.l1c.ReadReq_accesses::cpu5          44716                       # number of ReadReq accesses(hits+misses)
+system.cpu5.l1c.ReadReq_accesses::total         44716                       # number of ReadReq accesses(hits+misses)
+system.cpu5.l1c.WriteReq_accesses::cpu5         24399                       # number of WriteReq accesses(hits+misses)
+system.cpu5.l1c.WriteReq_accesses::total        24399                       # number of WriteReq accesses(hits+misses)
+system.cpu5.l1c.demand_accesses::cpu5           69115                       # number of demand (read+write) accesses
+system.cpu5.l1c.demand_accesses::total          69115                       # number of demand (read+write) accesses
+system.cpu5.l1c.overall_accesses::cpu5          69115                       # number of overall (read+write) accesses
+system.cpu5.l1c.overall_accesses::total         69115                       # number of overall (read+write) accesses
+system.cpu5.l1c.ReadReq_miss_rate::cpu5      0.805439                       # miss rate for ReadReq accesses
+system.cpu5.l1c.ReadReq_miss_rate::total     0.805439                       # miss rate for ReadReq accesses
+system.cpu5.l1c.WriteReq_miss_rate::cpu5     0.956310                       # miss rate for WriteReq accesses
+system.cpu5.l1c.WriteReq_miss_rate::total     0.956310                       # miss rate for WriteReq accesses
+system.cpu5.l1c.demand_miss_rate::cpu5       0.858699                       # miss rate for demand accesses
+system.cpu5.l1c.demand_miss_rate::total      0.858699                       # miss rate for demand accesses
+system.cpu5.l1c.overall_miss_rate::cpu5      0.858699                       # miss rate for overall accesses
+system.cpu5.l1c.overall_miss_rate::total     0.858699                       # miss rate for overall accesses
+system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 24962.241726                       # average ReadReq miss latency
+system.cpu5.l1c.ReadReq_avg_miss_latency::total 24962.241726                       # average ReadReq miss latency
+system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 35430.711010                       # average WriteReq miss latency
+system.cpu5.l1c.WriteReq_avg_miss_latency::total 35430.711010                       # average WriteReq miss latency
+system.cpu5.l1c.demand_avg_miss_latency::cpu5 29077.909956                       # average overall miss latency
+system.cpu5.l1c.demand_avg_miss_latency::total 29077.909956                       # average overall miss latency
+system.cpu5.l1c.overall_avg_miss_latency::cpu5 29077.909956                       # average overall miss latency
+system.cpu5.l1c.overall_avg_miss_latency::total 29077.909956                       # average overall miss latency
+system.cpu5.l1c.blocked_cycles::no_mshrs    155795508                       # number of cycles access was blocked
 system.cpu5.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu5.l1c.blocked::no_mshrs               67023                       # number of cycles access was blocked
+system.cpu5.l1c.blocked::no_mshrs               53352                       # number of cycles access was blocked
 system.cpu5.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu5.l1c.avg_blocked_cycles::no_mshrs  3179.084672                       # average number of cycles each access was blocked
+system.cpu5.l1c.avg_blocked_cycles::no_mshrs  2920.143725                       # average number of cycles each access was blocked
 system.cpu5.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu5.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu5.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu5.l1c.writebacks::writebacks           9605                       # number of writebacks
-system.cpu5.l1c.writebacks::total                9605                       # number of writebacks
-system.cpu5.l1c.ReadReq_mshr_misses::cpu5        36060                       # number of ReadReq MSHR misses
-system.cpu5.l1c.ReadReq_mshr_misses::total        36060                       # number of ReadReq MSHR misses
-system.cpu5.l1c.WriteReq_mshr_misses::cpu5        22989                       # number of WriteReq MSHR misses
-system.cpu5.l1c.WriteReq_mshr_misses::total        22989                       # number of WriteReq MSHR misses
-system.cpu5.l1c.demand_mshr_misses::cpu5        59049                       # number of demand (read+write) MSHR misses
-system.cpu5.l1c.demand_mshr_misses::total        59049                       # number of demand (read+write) MSHR misses
-system.cpu5.l1c.overall_mshr_misses::cpu5        59049                       # number of overall MSHR misses
-system.cpu5.l1c.overall_mshr_misses::total        59049                       # number of overall MSHR misses
-system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5    908030320                       # number of ReadReq MSHR miss cycles
-system.cpu5.l1c.ReadReq_mshr_miss_latency::total    908030320                       # number of ReadReq MSHR miss cycles
-system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5    852027269                       # number of WriteReq MSHR miss cycles
-system.cpu5.l1c.WriteReq_mshr_miss_latency::total    852027269                       # number of WriteReq MSHR miss cycles
-system.cpu5.l1c.demand_mshr_miss_latency::cpu5   1760057589                       # number of demand (read+write) MSHR miss cycles
-system.cpu5.l1c.demand_mshr_miss_latency::total   1760057589                       # number of demand (read+write) MSHR miss cycles
-system.cpu5.l1c.overall_mshr_miss_latency::cpu5   1760057589                       # number of overall MSHR miss cycles
-system.cpu5.l1c.overall_mshr_miss_latency::total   1760057589                       # number of overall MSHR miss cycles
-system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5    893562759                       # number of ReadReq MSHR uncacheable cycles
-system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total    893562759                       # number of ReadReq MSHR uncacheable cycles
-system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5    567489251                       # number of WriteReq MSHR uncacheable cycles
-system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total    567489251                       # number of WriteReq MSHR uncacheable cycles
-system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5   1461052010                       # number of overall MSHR uncacheable cycles
-system.cpu5.l1c.overall_mshr_uncacheable_latency::total   1461052010                       # number of overall MSHR uncacheable cycles
-system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5     0.807796                       # mshr miss rate for ReadReq accesses
-system.cpu5.l1c.ReadReq_mshr_miss_rate::total     0.807796                       # mshr miss rate for ReadReq accesses
-system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5     0.955804                       # mshr miss rate for WriteReq accesses
-system.cpu5.l1c.WriteReq_mshr_miss_rate::total     0.955804                       # mshr miss rate for WriteReq accesses
-system.cpu5.l1c.demand_mshr_miss_rate::cpu5     0.859620                       # mshr miss rate for demand accesses
-system.cpu5.l1c.demand_mshr_miss_rate::total     0.859620                       # mshr miss rate for demand accesses
-system.cpu5.l1c.overall_mshr_miss_rate::cpu5     0.859620                       # mshr miss rate for overall accesses
-system.cpu5.l1c.overall_mshr_miss_rate::total     0.859620                       # mshr miss rate for overall accesses
-system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 25181.095951                       # average ReadReq mshr miss latency
-system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 25181.095951                       # average ReadReq mshr miss latency
-system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 37062.389360                       # average WriteReq mshr miss latency
-system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 37062.389360                       # average WriteReq mshr miss latency
-system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 29806.729818                       # average overall mshr miss latency
-system.cpu5.l1c.demand_avg_mshr_miss_latency::total 29806.729818                       # average overall mshr miss latency
-system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 29806.729818                       # average overall mshr miss latency
-system.cpu5.l1c.overall_avg_mshr_miss_latency::total 29806.729818                       # average overall mshr miss latency
+system.cpu5.l1c.writebacks::writebacks           9610                       # number of writebacks
+system.cpu5.l1c.writebacks::total                9610                       # number of writebacks
+system.cpu5.l1c.ReadReq_mshr_misses::cpu5        36016                       # number of ReadReq MSHR misses
+system.cpu5.l1c.ReadReq_mshr_misses::total        36016                       # number of ReadReq MSHR misses
+system.cpu5.l1c.WriteReq_mshr_misses::cpu5        23333                       # number of WriteReq MSHR misses
+system.cpu5.l1c.WriteReq_mshr_misses::total        23333                       # number of WriteReq MSHR misses
+system.cpu5.l1c.demand_mshr_misses::cpu5        59349                       # number of demand (read+write) MSHR misses
+system.cpu5.l1c.demand_mshr_misses::total        59349                       # number of demand (read+write) MSHR misses
+system.cpu5.l1c.overall_mshr_misses::cpu5        59349                       # number of overall MSHR misses
+system.cpu5.l1c.overall_mshr_misses::total        59349                       # number of overall MSHR misses
+system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5    862885041                       # number of ReadReq MSHR miss cycles
+system.cpu5.l1c.ReadReq_mshr_miss_latency::total    862885041                       # number of ReadReq MSHR miss cycles
+system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5    803284460                       # number of WriteReq MSHR miss cycles
+system.cpu5.l1c.WriteReq_mshr_miss_latency::total    803284460                       # number of WriteReq MSHR miss cycles
+system.cpu5.l1c.demand_mshr_miss_latency::cpu5   1666169501                       # number of demand (read+write) MSHR miss cycles
+system.cpu5.l1c.demand_mshr_miss_latency::total   1666169501                       # number of demand (read+write) MSHR miss cycles
+system.cpu5.l1c.overall_mshr_miss_latency::cpu5   1666169501                       # number of overall MSHR miss cycles
+system.cpu5.l1c.overall_mshr_miss_latency::total   1666169501                       # number of overall MSHR miss cycles
+system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5    674425818                       # number of ReadReq MSHR uncacheable cycles
+system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total    674425818                       # number of ReadReq MSHR uncacheable cycles
+system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5    675374924                       # number of WriteReq MSHR uncacheable cycles
+system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total    675374924                       # number of WriteReq MSHR uncacheable cycles
+system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5   1349800742                       # number of overall MSHR uncacheable cycles
+system.cpu5.l1c.overall_mshr_uncacheable_latency::total   1349800742                       # number of overall MSHR uncacheable cycles
+system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5     0.805439                       # mshr miss rate for ReadReq accesses
+system.cpu5.l1c.ReadReq_mshr_miss_rate::total     0.805439                       # mshr miss rate for ReadReq accesses
+system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5     0.956310                       # mshr miss rate for WriteReq accesses
+system.cpu5.l1c.WriteReq_mshr_miss_rate::total     0.956310                       # mshr miss rate for WriteReq accesses
+system.cpu5.l1c.demand_mshr_miss_rate::cpu5     0.858699                       # mshr miss rate for demand accesses
+system.cpu5.l1c.demand_mshr_miss_rate::total     0.858699                       # mshr miss rate for demand accesses
+system.cpu5.l1c.overall_mshr_miss_rate::cpu5     0.858699                       # mshr miss rate for overall accesses
+system.cpu5.l1c.overall_mshr_miss_rate::total     0.858699                       # mshr miss rate for overall accesses
+system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 23958.380747                       # average ReadReq mshr miss latency
+system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 23958.380747                       # average ReadReq mshr miss latency
+system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 34426.968671                       # average WriteReq mshr miss latency
+system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 34426.968671                       # average WriteReq mshr miss latency
+system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 28074.095621                       # average overall mshr miss latency
+system.cpu5.l1c.demand_avg_mshr_miss_latency::total 28074.095621                       # average overall mshr miss latency
+system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 28074.095621                       # average overall mshr miss latency
+system.cpu5.l1c.overall_avg_mshr_miss_latency::total 28074.095621                       # average overall mshr miss latency
 system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5          inf                       # average ReadReq mshr uncacheable latency
 system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5          inf                       # average WriteReq mshr uncacheable latency
@@ -1350,114 +1353,114 @@ system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5          inf                       # average overall mshr uncacheable latency
 system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu5.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu6.num_reads                           99515                       # number of read accesses completed
-system.cpu6.num_writes                          53091                       # number of write accesses completed
+system.cpu6.num_reads                          100000                       # number of read accesses completed
+system.cpu6.num_writes                          53510                       # number of write accesses completed
 system.cpu6.num_copies                              0                       # number of copy accesses completed
-system.cpu6.l1c.replacements                    21875                       # number of replacements
-system.cpu6.l1c.tagsinuse                  395.073790                       # Cycle average of tags in use
-system.cpu6.l1c.total_refs                      13163                       # Total number of references to valid blocks.
-system.cpu6.l1c.sampled_refs                    22301                       # Sample count of references to valid blocks.
-system.cpu6.l1c.avg_refs                     0.590243                       # Average number of references to valid blocks.
+system.cpu6.l1c.replacements                    22177                       # number of replacements
+system.cpu6.l1c.tagsinuse                  397.660479                       # Cycle average of tags in use
+system.cpu6.l1c.total_refs                      13364                       # Total number of references to valid blocks.
+system.cpu6.l1c.sampled_refs                    22573                       # Sample count of references to valid blocks.
+system.cpu6.l1c.avg_refs                     0.592035                       # Average number of references to valid blocks.
 system.cpu6.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.cpu6.l1c.occ_blocks::cpu6           395.073790                       # Average occupied blocks per requestor
-system.cpu6.l1c.occ_percent::cpu6            0.771628                       # Average percentage of cache occupancy
-system.cpu6.l1c.occ_percent::total           0.771628                       # Average percentage of cache occupancy
-system.cpu6.l1c.ReadReq_hits::cpu6               8660                       # number of ReadReq hits
-system.cpu6.l1c.ReadReq_hits::total              8660                       # number of ReadReq hits
-system.cpu6.l1c.WriteReq_hits::cpu6              1070                       # number of WriteReq hits
-system.cpu6.l1c.WriteReq_hits::total             1070                       # number of WriteReq hits
-system.cpu6.l1c.demand_hits::cpu6                9730                       # number of demand (read+write) hits
-system.cpu6.l1c.demand_hits::total               9730                       # number of demand (read+write) hits
-system.cpu6.l1c.overall_hits::cpu6               9730                       # number of overall hits
-system.cpu6.l1c.overall_hits::total              9730                       # number of overall hits
-system.cpu6.l1c.ReadReq_misses::cpu6            36079                       # number of ReadReq misses
-system.cpu6.l1c.ReadReq_misses::total           36079                       # number of ReadReq misses
-system.cpu6.l1c.WriteReq_misses::cpu6           22730                       # number of WriteReq misses
-system.cpu6.l1c.WriteReq_misses::total          22730                       # number of WriteReq misses
-system.cpu6.l1c.demand_misses::cpu6             58809                       # number of demand (read+write) misses
-system.cpu6.l1c.demand_misses::total            58809                       # number of demand (read+write) misses
-system.cpu6.l1c.overall_misses::cpu6            58809                       # number of overall misses
-system.cpu6.l1c.overall_misses::total           58809                       # number of overall misses
-system.cpu6.l1c.ReadReq_miss_latency::cpu6    942403765                       # number of ReadReq miss cycles
-system.cpu6.l1c.ReadReq_miss_latency::total    942403765                       # number of ReadReq miss cycles
-system.cpu6.l1c.WriteReq_miss_latency::cpu6    866225957                       # number of WriteReq miss cycles
-system.cpu6.l1c.WriteReq_miss_latency::total    866225957                       # number of WriteReq miss cycles
-system.cpu6.l1c.demand_miss_latency::cpu6   1808629722                       # number of demand (read+write) miss cycles
-system.cpu6.l1c.demand_miss_latency::total   1808629722                       # number of demand (read+write) miss cycles
-system.cpu6.l1c.overall_miss_latency::cpu6   1808629722                       # number of overall miss cycles
-system.cpu6.l1c.overall_miss_latency::total   1808629722                       # number of overall miss cycles
-system.cpu6.l1c.ReadReq_accesses::cpu6          44739                       # number of ReadReq accesses(hits+misses)
-system.cpu6.l1c.ReadReq_accesses::total         44739                       # number of ReadReq accesses(hits+misses)
-system.cpu6.l1c.WriteReq_accesses::cpu6         23800                       # number of WriteReq accesses(hits+misses)
-system.cpu6.l1c.WriteReq_accesses::total        23800                       # number of WriteReq accesses(hits+misses)
-system.cpu6.l1c.demand_accesses::cpu6           68539                       # number of demand (read+write) accesses
-system.cpu6.l1c.demand_accesses::total          68539                       # number of demand (read+write) accesses
-system.cpu6.l1c.overall_accesses::cpu6          68539                       # number of overall (read+write) accesses
-system.cpu6.l1c.overall_accesses::total         68539                       # number of overall (read+write) accesses
-system.cpu6.l1c.ReadReq_miss_rate::cpu6      0.806433                       # miss rate for ReadReq accesses
-system.cpu6.l1c.ReadReq_miss_rate::total     0.806433                       # miss rate for ReadReq accesses
-system.cpu6.l1c.WriteReq_miss_rate::cpu6     0.955042                       # miss rate for WriteReq accesses
-system.cpu6.l1c.WriteReq_miss_rate::total     0.955042                       # miss rate for WriteReq accesses
-system.cpu6.l1c.demand_miss_rate::cpu6       0.858037                       # miss rate for demand accesses
-system.cpu6.l1c.demand_miss_rate::total      0.858037                       # miss rate for demand accesses
-system.cpu6.l1c.overall_miss_rate::cpu6      0.858037                       # miss rate for overall accesses
-system.cpu6.l1c.overall_miss_rate::total     0.858037                       # miss rate for overall accesses
-system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 26120.562238                       # average ReadReq miss latency
-system.cpu6.l1c.ReadReq_avg_miss_latency::total 26120.562238                       # average ReadReq miss latency
-system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 38109.368984                       # average WriteReq miss latency
-system.cpu6.l1c.WriteReq_avg_miss_latency::total 38109.368984                       # average WriteReq miss latency
-system.cpu6.l1c.demand_avg_miss_latency::cpu6 30754.301586                       # average overall miss latency
-system.cpu6.l1c.demand_avg_miss_latency::total 30754.301586                       # average overall miss latency
-system.cpu6.l1c.overall_avg_miss_latency::cpu6 30754.301586                       # average overall miss latency
-system.cpu6.l1c.overall_avg_miss_latency::total 30754.301586                       # average overall miss latency
-system.cpu6.l1c.blocked_cycles::no_mshrs    212806358                       # number of cycles access was blocked
+system.cpu6.l1c.occ_blocks::cpu6           397.660479                       # Average occupied blocks per requestor
+system.cpu6.l1c.occ_percent::cpu6            0.776681                       # Average percentage of cache occupancy
+system.cpu6.l1c.occ_percent::total           0.776681                       # Average percentage of cache occupancy
+system.cpu6.l1c.ReadReq_hits::cpu6               8760                       # number of ReadReq hits
+system.cpu6.l1c.ReadReq_hits::total              8760                       # number of ReadReq hits
+system.cpu6.l1c.WriteReq_hits::cpu6              1035                       # number of WriteReq hits
+system.cpu6.l1c.WriteReq_hits::total             1035                       # number of WriteReq hits
+system.cpu6.l1c.demand_hits::cpu6                9795                       # number of demand (read+write) hits
+system.cpu6.l1c.demand_hits::total               9795                       # number of demand (read+write) hits
+system.cpu6.l1c.overall_hits::cpu6               9795                       # number of overall hits
+system.cpu6.l1c.overall_hits::total              9795                       # number of overall hits
+system.cpu6.l1c.ReadReq_misses::cpu6            36279                       # number of ReadReq misses
+system.cpu6.l1c.ReadReq_misses::total           36279                       # number of ReadReq misses
+system.cpu6.l1c.WriteReq_misses::cpu6           23033                       # number of WriteReq misses
+system.cpu6.l1c.WriteReq_misses::total          23033                       # number of WriteReq misses
+system.cpu6.l1c.demand_misses::cpu6             59312                       # number of demand (read+write) misses
+system.cpu6.l1c.demand_misses::total            59312                       # number of demand (read+write) misses
+system.cpu6.l1c.overall_misses::cpu6            59312                       # number of overall misses
+system.cpu6.l1c.overall_misses::total           59312                       # number of overall misses
+system.cpu6.l1c.ReadReq_miss_latency::cpu6    908517794                       # number of ReadReq miss cycles
+system.cpu6.l1c.ReadReq_miss_latency::total    908517794                       # number of ReadReq miss cycles
+system.cpu6.l1c.WriteReq_miss_latency::cpu6    809582336                       # number of WriteReq miss cycles
+system.cpu6.l1c.WriteReq_miss_latency::total    809582336                       # number of WriteReq miss cycles
+system.cpu6.l1c.demand_miss_latency::cpu6   1718100130                       # number of demand (read+write) miss cycles
+system.cpu6.l1c.demand_miss_latency::total   1718100130                       # number of demand (read+write) miss cycles
+system.cpu6.l1c.overall_miss_latency::cpu6   1718100130                       # number of overall miss cycles
+system.cpu6.l1c.overall_miss_latency::total   1718100130                       # number of overall miss cycles
+system.cpu6.l1c.ReadReq_accesses::cpu6          45039                       # number of ReadReq accesses(hits+misses)
+system.cpu6.l1c.ReadReq_accesses::total         45039                       # number of ReadReq accesses(hits+misses)
+system.cpu6.l1c.WriteReq_accesses::cpu6         24068                       # number of WriteReq accesses(hits+misses)
+system.cpu6.l1c.WriteReq_accesses::total        24068                       # number of WriteReq accesses(hits+misses)
+system.cpu6.l1c.demand_accesses::cpu6           69107                       # number of demand (read+write) accesses
+system.cpu6.l1c.demand_accesses::total          69107                       # number of demand (read+write) accesses
+system.cpu6.l1c.overall_accesses::cpu6          69107                       # number of overall (read+write) accesses
+system.cpu6.l1c.overall_accesses::total         69107                       # number of overall (read+write) accesses
+system.cpu6.l1c.ReadReq_miss_rate::cpu6      0.805502                       # miss rate for ReadReq accesses
+system.cpu6.l1c.ReadReq_miss_rate::total     0.805502                       # miss rate for ReadReq accesses
+system.cpu6.l1c.WriteReq_miss_rate::cpu6     0.956997                       # miss rate for WriteReq accesses
+system.cpu6.l1c.WriteReq_miss_rate::total     0.956997                       # miss rate for WriteReq accesses
+system.cpu6.l1c.demand_miss_rate::cpu6       0.858263                       # miss rate for demand accesses
+system.cpu6.l1c.demand_miss_rate::total      0.858263                       # miss rate for demand accesses
+system.cpu6.l1c.overall_miss_rate::cpu6      0.858263                       # miss rate for overall accesses
+system.cpu6.l1c.overall_miss_rate::total     0.858263                       # miss rate for overall accesses
+system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 25042.525814                       # average ReadReq miss latency
+system.cpu6.l1c.ReadReq_avg_miss_latency::total 25042.525814                       # average ReadReq miss latency
+system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 35148.801111                       # average WriteReq miss latency
+system.cpu6.l1c.WriteReq_avg_miss_latency::total 35148.801111                       # average WriteReq miss latency
+system.cpu6.l1c.demand_avg_miss_latency::cpu6 28967.158922                       # average overall miss latency
+system.cpu6.l1c.demand_avg_miss_latency::total 28967.158922                       # average overall miss latency
+system.cpu6.l1c.overall_avg_miss_latency::cpu6 28967.158922                       # average overall miss latency
+system.cpu6.l1c.overall_avg_miss_latency::total 28967.158922                       # average overall miss latency
+system.cpu6.l1c.blocked_cycles::no_mshrs    154185284                       # number of cycles access was blocked
 system.cpu6.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu6.l1c.blocked::no_mshrs               66914                       # number of cycles access was blocked
+system.cpu6.l1c.blocked::no_mshrs               52977                       # number of cycles access was blocked
 system.cpu6.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu6.l1c.avg_blocked_cycles::no_mshrs  3180.296470                       # average number of cycles each access was blocked
+system.cpu6.l1c.avg_blocked_cycles::no_mshrs  2910.419314                       # average number of cycles each access was blocked
 system.cpu6.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu6.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu6.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu6.l1c.writebacks::writebacks           9438                       # number of writebacks
-system.cpu6.l1c.writebacks::total                9438                       # number of writebacks
-system.cpu6.l1c.ReadReq_mshr_misses::cpu6        36079                       # number of ReadReq MSHR misses
-system.cpu6.l1c.ReadReq_mshr_misses::total        36079                       # number of ReadReq MSHR misses
-system.cpu6.l1c.WriteReq_mshr_misses::cpu6        22730                       # number of WriteReq MSHR misses
-system.cpu6.l1c.WriteReq_mshr_misses::total        22730                       # number of WriteReq MSHR misses
-system.cpu6.l1c.demand_mshr_misses::cpu6        58809                       # number of demand (read+write) MSHR misses
-system.cpu6.l1c.demand_mshr_misses::total        58809                       # number of demand (read+write) MSHR misses
-system.cpu6.l1c.overall_mshr_misses::cpu6        58809                       # number of overall MSHR misses
-system.cpu6.l1c.overall_mshr_misses::total        58809                       # number of overall MSHR misses
-system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6    906189412                       # number of ReadReq MSHR miss cycles
-system.cpu6.l1c.ReadReq_mshr_miss_latency::total    906189412                       # number of ReadReq MSHR miss cycles
-system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6    843405989                       # number of WriteReq MSHR miss cycles
-system.cpu6.l1c.WriteReq_mshr_miss_latency::total    843405989                       # number of WriteReq MSHR miss cycles
-system.cpu6.l1c.demand_mshr_miss_latency::cpu6   1749595401                       # number of demand (read+write) MSHR miss cycles
-system.cpu6.l1c.demand_mshr_miss_latency::total   1749595401                       # number of demand (read+write) MSHR miss cycles
-system.cpu6.l1c.overall_mshr_miss_latency::cpu6   1749595401                       # number of overall MSHR miss cycles
-system.cpu6.l1c.overall_mshr_miss_latency::total   1749595401                       # number of overall MSHR miss cycles
-system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6    905213986                       # number of ReadReq MSHR uncacheable cycles
-system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total    905213986                       # number of ReadReq MSHR uncacheable cycles
-system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6    576398345                       # number of WriteReq MSHR uncacheable cycles
-system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total    576398345                       # number of WriteReq MSHR uncacheable cycles
-system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6   1481612331                       # number of overall MSHR uncacheable cycles
-system.cpu6.l1c.overall_mshr_uncacheable_latency::total   1481612331                       # number of overall MSHR uncacheable cycles
-system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6     0.806433                       # mshr miss rate for ReadReq accesses
-system.cpu6.l1c.ReadReq_mshr_miss_rate::total     0.806433                       # mshr miss rate for ReadReq accesses
-system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6     0.955042                       # mshr miss rate for WriteReq accesses
-system.cpu6.l1c.WriteReq_mshr_miss_rate::total     0.955042                       # mshr miss rate for WriteReq accesses
-system.cpu6.l1c.demand_mshr_miss_rate::cpu6     0.858037                       # mshr miss rate for demand accesses
-system.cpu6.l1c.demand_mshr_miss_rate::total     0.858037                       # mshr miss rate for demand accesses
-system.cpu6.l1c.overall_mshr_miss_rate::cpu6     0.858037                       # mshr miss rate for overall accesses
-system.cpu6.l1c.overall_mshr_miss_rate::total     0.858037                       # mshr miss rate for overall accesses
-system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 25116.810665                       # average ReadReq mshr miss latency
-system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 25116.810665                       # average ReadReq mshr miss latency
-system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 37105.410867                       # average WriteReq mshr miss latency
-system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 37105.410867                       # average WriteReq mshr miss latency
-system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 29750.470183                       # average overall mshr miss latency
-system.cpu6.l1c.demand_avg_mshr_miss_latency::total 29750.470183                       # average overall mshr miss latency
-system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 29750.470183                       # average overall mshr miss latency
-system.cpu6.l1c.overall_avg_mshr_miss_latency::total 29750.470183                       # average overall mshr miss latency
+system.cpu6.l1c.writebacks::writebacks           9564                       # number of writebacks
+system.cpu6.l1c.writebacks::total                9564                       # number of writebacks
+system.cpu6.l1c.ReadReq_mshr_misses::cpu6        36279                       # number of ReadReq MSHR misses
+system.cpu6.l1c.ReadReq_mshr_misses::total        36279                       # number of ReadReq MSHR misses
+system.cpu6.l1c.WriteReq_mshr_misses::cpu6        23033                       # number of WriteReq MSHR misses
+system.cpu6.l1c.WriteReq_mshr_misses::total        23033                       # number of WriteReq MSHR misses
+system.cpu6.l1c.demand_mshr_misses::cpu6        59312                       # number of demand (read+write) MSHR misses
+system.cpu6.l1c.demand_mshr_misses::total        59312                       # number of demand (read+write) MSHR misses
+system.cpu6.l1c.overall_mshr_misses::cpu6        59312                       # number of overall MSHR misses
+system.cpu6.l1c.overall_mshr_misses::total        59312                       # number of overall MSHR misses
+system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6    872097671                       # number of ReadReq MSHR miss cycles
+system.cpu6.l1c.ReadReq_mshr_miss_latency::total    872097671                       # number of ReadReq MSHR miss cycles
+system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6    786461211                       # number of WriteReq MSHR miss cycles
+system.cpu6.l1c.WriteReq_mshr_miss_latency::total    786461211                       # number of WriteReq MSHR miss cycles
+system.cpu6.l1c.demand_mshr_miss_latency::cpu6   1658558882                       # number of demand (read+write) MSHR miss cycles
+system.cpu6.l1c.demand_mshr_miss_latency::total   1658558882                       # number of demand (read+write) MSHR miss cycles
+system.cpu6.l1c.overall_mshr_miss_latency::cpu6   1658558882                       # number of overall MSHR miss cycles
+system.cpu6.l1c.overall_mshr_miss_latency::total   1658558882                       # number of overall MSHR miss cycles
+system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6    680107967                       # number of ReadReq MSHR uncacheable cycles
+system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total    680107967                       # number of ReadReq MSHR uncacheable cycles
+system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6    681972539                       # number of WriteReq MSHR uncacheable cycles
+system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total    681972539                       # number of WriteReq MSHR uncacheable cycles
+system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6   1362080506                       # number of overall MSHR uncacheable cycles
+system.cpu6.l1c.overall_mshr_uncacheable_latency::total   1362080506                       # number of overall MSHR uncacheable cycles
+system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6     0.805502                       # mshr miss rate for ReadReq accesses
+system.cpu6.l1c.ReadReq_mshr_miss_rate::total     0.805502                       # mshr miss rate for ReadReq accesses
+system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6     0.956997                       # mshr miss rate for WriteReq accesses
+system.cpu6.l1c.WriteReq_mshr_miss_rate::total     0.956997                       # mshr miss rate for WriteReq accesses
+system.cpu6.l1c.demand_mshr_miss_rate::cpu6     0.858263                       # mshr miss rate for demand accesses
+system.cpu6.l1c.demand_mshr_miss_rate::total     0.858263                       # mshr miss rate for demand accesses
+system.cpu6.l1c.overall_mshr_miss_rate::cpu6     0.858263                       # mshr miss rate for overall accesses
+system.cpu6.l1c.overall_mshr_miss_rate::total     0.858263                       # mshr miss rate for overall accesses
+system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 24038.635878                       # average ReadReq mshr miss latency
+system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 24038.635878                       # average ReadReq mshr miss latency
+system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 34144.975079                       # average WriteReq mshr miss latency
+system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 34144.975079                       # average WriteReq mshr miss latency
+system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 27963.293802                       # average overall mshr miss latency
+system.cpu6.l1c.demand_avg_mshr_miss_latency::total 27963.293802                       # average overall mshr miss latency
+system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 27963.293802                       # average overall mshr miss latency
+system.cpu6.l1c.overall_avg_mshr_miss_latency::total 27963.293802                       # average overall mshr miss latency
 system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6          inf                       # average ReadReq mshr uncacheable latency
 system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6          inf                       # average WriteReq mshr uncacheable latency
@@ -1465,114 +1468,114 @@ system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6          inf                       # average overall mshr uncacheable latency
 system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu6.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu7.num_reads                           98608                       # number of read accesses completed
-system.cpu7.num_writes                          53688                       # number of write accesses completed
+system.cpu7.num_reads                           99201                       # number of read accesses completed
+system.cpu7.num_writes                          53497                       # number of write accesses completed
 system.cpu7.num_copies                              0                       # number of copy accesses completed
-system.cpu7.l1c.replacements                    21767                       # number of replacements
-system.cpu7.l1c.tagsinuse                  394.473547                       # Cycle average of tags in use
-system.cpu7.l1c.total_refs                      13199                       # Total number of references to valid blocks.
-system.cpu7.l1c.sampled_refs                    22171                       # Sample count of references to valid blocks.
-system.cpu7.l1c.avg_refs                     0.595327                       # Average number of references to valid blocks.
+system.cpu7.l1c.replacements                    22218                       # number of replacements
+system.cpu7.l1c.tagsinuse                  396.828031                       # Cycle average of tags in use
+system.cpu7.l1c.total_refs                      13271                       # Total number of references to valid blocks.
+system.cpu7.l1c.sampled_refs                    22622                       # Sample count of references to valid blocks.
+system.cpu7.l1c.avg_refs                     0.586641                       # Average number of references to valid blocks.
 system.cpu7.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.cpu7.l1c.occ_blocks::cpu7           394.473547                       # Average occupied blocks per requestor
-system.cpu7.l1c.occ_percent::cpu7            0.770456                       # Average percentage of cache occupancy
-system.cpu7.l1c.occ_percent::total           0.770456                       # Average percentage of cache occupancy
-system.cpu7.l1c.ReadReq_hits::cpu7               8649                       # number of ReadReq hits
-system.cpu7.l1c.ReadReq_hits::total              8649                       # number of ReadReq hits
-system.cpu7.l1c.WriteReq_hits::cpu7               995                       # number of WriteReq hits
-system.cpu7.l1c.WriteReq_hits::total              995                       # number of WriteReq hits
-system.cpu7.l1c.demand_hits::cpu7                9644                       # number of demand (read+write) hits
-system.cpu7.l1c.demand_hits::total               9644                       # number of demand (read+write) hits
-system.cpu7.l1c.overall_hits::cpu7               9644                       # number of overall hits
-system.cpu7.l1c.overall_hits::total              9644                       # number of overall hits
-system.cpu7.l1c.ReadReq_misses::cpu7            35884                       # number of ReadReq misses
-system.cpu7.l1c.ReadReq_misses::total           35884                       # number of ReadReq misses
-system.cpu7.l1c.WriteReq_misses::cpu7           23099                       # number of WriteReq misses
-system.cpu7.l1c.WriteReq_misses::total          23099                       # number of WriteReq misses
-system.cpu7.l1c.demand_misses::cpu7             58983                       # number of demand (read+write) misses
-system.cpu7.l1c.demand_misses::total            58983                       # number of demand (read+write) misses
-system.cpu7.l1c.overall_misses::cpu7            58983                       # number of overall misses
-system.cpu7.l1c.overall_misses::total           58983                       # number of overall misses
-system.cpu7.l1c.ReadReq_miss_latency::cpu7    932010776                       # number of ReadReq miss cycles
-system.cpu7.l1c.ReadReq_miss_latency::total    932010776                       # number of ReadReq miss cycles
-system.cpu7.l1c.WriteReq_miss_latency::cpu7    877703149                       # number of WriteReq miss cycles
-system.cpu7.l1c.WriteReq_miss_latency::total    877703149                       # number of WriteReq miss cycles
-system.cpu7.l1c.demand_miss_latency::cpu7   1809713925                       # number of demand (read+write) miss cycles
-system.cpu7.l1c.demand_miss_latency::total   1809713925                       # number of demand (read+write) miss cycles
-system.cpu7.l1c.overall_miss_latency::cpu7   1809713925                       # number of overall miss cycles
-system.cpu7.l1c.overall_miss_latency::total   1809713925                       # number of overall miss cycles
-system.cpu7.l1c.ReadReq_accesses::cpu7          44533                       # number of ReadReq accesses(hits+misses)
-system.cpu7.l1c.ReadReq_accesses::total         44533                       # number of ReadReq accesses(hits+misses)
-system.cpu7.l1c.WriteReq_accesses::cpu7         24094                       # number of WriteReq accesses(hits+misses)
-system.cpu7.l1c.WriteReq_accesses::total        24094                       # number of WriteReq accesses(hits+misses)
-system.cpu7.l1c.demand_accesses::cpu7           68627                       # number of demand (read+write) accesses
-system.cpu7.l1c.demand_accesses::total          68627                       # number of demand (read+write) accesses
-system.cpu7.l1c.overall_accesses::cpu7          68627                       # number of overall (read+write) accesses
-system.cpu7.l1c.overall_accesses::total         68627                       # number of overall (read+write) accesses
-system.cpu7.l1c.ReadReq_miss_rate::cpu7      0.805784                       # miss rate for ReadReq accesses
-system.cpu7.l1c.ReadReq_miss_rate::total     0.805784                       # miss rate for ReadReq accesses
-system.cpu7.l1c.WriteReq_miss_rate::cpu7     0.958703                       # miss rate for WriteReq accesses
-system.cpu7.l1c.WriteReq_miss_rate::total     0.958703                       # miss rate for WriteReq accesses
-system.cpu7.l1c.demand_miss_rate::cpu7       0.859472                       # miss rate for demand accesses
-system.cpu7.l1c.demand_miss_rate::total      0.859472                       # miss rate for demand accesses
-system.cpu7.l1c.overall_miss_rate::cpu7      0.859472                       # miss rate for overall accesses
-system.cpu7.l1c.overall_miss_rate::total     0.859472                       # miss rate for overall accesses
-system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 25972.878609                       # average ReadReq miss latency
-system.cpu7.l1c.ReadReq_avg_miss_latency::total 25972.878609                       # average ReadReq miss latency
-system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 37997.452227                       # average WriteReq miss latency
-system.cpu7.l1c.WriteReq_avg_miss_latency::total 37997.452227                       # average WriteReq miss latency
-system.cpu7.l1c.demand_avg_miss_latency::cpu7 30681.957937                       # average overall miss latency
-system.cpu7.l1c.demand_avg_miss_latency::total 30681.957937                       # average overall miss latency
-system.cpu7.l1c.overall_avg_miss_latency::cpu7 30681.957937                       # average overall miss latency
-system.cpu7.l1c.overall_avg_miss_latency::total 30681.957937                       # average overall miss latency
-system.cpu7.l1c.blocked_cycles::no_mshrs    213241981                       # number of cycles access was blocked
+system.cpu7.l1c.occ_blocks::cpu7           396.828031                       # Average occupied blocks per requestor
+system.cpu7.l1c.occ_percent::cpu7            0.775055                       # Average percentage of cache occupancy
+system.cpu7.l1c.occ_percent::total           0.775055                       # Average percentage of cache occupancy
+system.cpu7.l1c.ReadReq_hits::cpu7               8703                       # number of ReadReq hits
+system.cpu7.l1c.ReadReq_hits::total              8703                       # number of ReadReq hits
+system.cpu7.l1c.WriteReq_hits::cpu7              1096                       # number of WriteReq hits
+system.cpu7.l1c.WriteReq_hits::total             1096                       # number of WriteReq hits
+system.cpu7.l1c.demand_hits::cpu7                9799                       # number of demand (read+write) hits
+system.cpu7.l1c.demand_hits::total               9799                       # number of demand (read+write) hits
+system.cpu7.l1c.overall_hits::cpu7               9799                       # number of overall hits
+system.cpu7.l1c.overall_hits::total              9799                       # number of overall hits
+system.cpu7.l1c.ReadReq_misses::cpu7            36453                       # number of ReadReq misses
+system.cpu7.l1c.ReadReq_misses::total           36453                       # number of ReadReq misses
+system.cpu7.l1c.WriteReq_misses::cpu7           22910                       # number of WriteReq misses
+system.cpu7.l1c.WriteReq_misses::total          22910                       # number of WriteReq misses
+system.cpu7.l1c.demand_misses::cpu7             59363                       # number of demand (read+write) misses
+system.cpu7.l1c.demand_misses::total            59363                       # number of demand (read+write) misses
+system.cpu7.l1c.overall_misses::cpu7            59363                       # number of overall misses
+system.cpu7.l1c.overall_misses::total           59363                       # number of overall misses
+system.cpu7.l1c.ReadReq_miss_latency::cpu7    908883238                       # number of ReadReq miss cycles
+system.cpu7.l1c.ReadReq_miss_latency::total    908883238                       # number of ReadReq miss cycles
+system.cpu7.l1c.WriteReq_miss_latency::cpu7    808946616                       # number of WriteReq miss cycles
+system.cpu7.l1c.WriteReq_miss_latency::total    808946616                       # number of WriteReq miss cycles
+system.cpu7.l1c.demand_miss_latency::cpu7   1717829854                       # number of demand (read+write) miss cycles
+system.cpu7.l1c.demand_miss_latency::total   1717829854                       # number of demand (read+write) miss cycles
+system.cpu7.l1c.overall_miss_latency::cpu7   1717829854                       # number of overall miss cycles
+system.cpu7.l1c.overall_miss_latency::total   1717829854                       # number of overall miss cycles
+system.cpu7.l1c.ReadReq_accesses::cpu7          45156                       # number of ReadReq accesses(hits+misses)
+system.cpu7.l1c.ReadReq_accesses::total         45156                       # number of ReadReq accesses(hits+misses)
+system.cpu7.l1c.WriteReq_accesses::cpu7         24006                       # number of WriteReq accesses(hits+misses)
+system.cpu7.l1c.WriteReq_accesses::total        24006                       # number of WriteReq accesses(hits+misses)
+system.cpu7.l1c.demand_accesses::cpu7           69162                       # number of demand (read+write) accesses
+system.cpu7.l1c.demand_accesses::total          69162                       # number of demand (read+write) accesses
+system.cpu7.l1c.overall_accesses::cpu7          69162                       # number of overall (read+write) accesses
+system.cpu7.l1c.overall_accesses::total         69162                       # number of overall (read+write) accesses
+system.cpu7.l1c.ReadReq_miss_rate::cpu7      0.807268                       # miss rate for ReadReq accesses
+system.cpu7.l1c.ReadReq_miss_rate::total     0.807268                       # miss rate for ReadReq accesses
+system.cpu7.l1c.WriteReq_miss_rate::cpu7     0.954345                       # miss rate for WriteReq accesses
+system.cpu7.l1c.WriteReq_miss_rate::total     0.954345                       # miss rate for WriteReq accesses
+system.cpu7.l1c.demand_miss_rate::cpu7       0.858318                       # miss rate for demand accesses
+system.cpu7.l1c.demand_miss_rate::total      0.858318                       # miss rate for demand accesses
+system.cpu7.l1c.overall_miss_rate::cpu7      0.858318                       # miss rate for overall accesses
+system.cpu7.l1c.overall_miss_rate::total     0.858318                       # miss rate for overall accesses
+system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 24933.016158                       # average ReadReq miss latency
+system.cpu7.l1c.ReadReq_avg_miss_latency::total 24933.016158                       # average ReadReq miss latency
+system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 35309.760629                       # average WriteReq miss latency
+system.cpu7.l1c.WriteReq_avg_miss_latency::total 35309.760629                       # average WriteReq miss latency
+system.cpu7.l1c.demand_avg_miss_latency::cpu7 28937.719691                       # average overall miss latency
+system.cpu7.l1c.demand_avg_miss_latency::total 28937.719691                       # average overall miss latency
+system.cpu7.l1c.overall_avg_miss_latency::cpu7 28937.719691                       # average overall miss latency
+system.cpu7.l1c.overall_avg_miss_latency::total 28937.719691                       # average overall miss latency
+system.cpu7.l1c.blocked_cycles::no_mshrs    153732048                       # number of cycles access was blocked
 system.cpu7.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu7.l1c.blocked::no_mshrs               67091                       # number of cycles access was blocked
+system.cpu7.l1c.blocked::no_mshrs               53029                       # number of cycles access was blocked
 system.cpu7.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
-system.cpu7.l1c.avg_blocked_cycles::no_mshrs  3178.399204                       # average number of cycles each access was blocked
+system.cpu7.l1c.avg_blocked_cycles::no_mshrs  2899.018424                       # average number of cycles each access was blocked
 system.cpu7.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu7.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu7.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu7.l1c.writebacks::writebacks           9457                       # number of writebacks
-system.cpu7.l1c.writebacks::total                9457                       # number of writebacks
-system.cpu7.l1c.ReadReq_mshr_misses::cpu7        35884                       # number of ReadReq MSHR misses
-system.cpu7.l1c.ReadReq_mshr_misses::total        35884                       # number of ReadReq MSHR misses
-system.cpu7.l1c.WriteReq_mshr_misses::cpu7        23099                       # number of WriteReq MSHR misses
-system.cpu7.l1c.WriteReq_mshr_misses::total        23099                       # number of WriteReq MSHR misses
-system.cpu7.l1c.demand_mshr_misses::cpu7        58983                       # number of demand (read+write) MSHR misses
-system.cpu7.l1c.demand_mshr_misses::total        58983                       # number of demand (read+write) MSHR misses
-system.cpu7.l1c.overall_mshr_misses::cpu7        58983                       # number of overall MSHR misses
-system.cpu7.l1c.overall_mshr_misses::total        58983                       # number of overall MSHR misses
-system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7    895990178                       # number of ReadReq MSHR miss cycles
-system.cpu7.l1c.ReadReq_mshr_miss_latency::total    895990178                       # number of ReadReq MSHR miss cycles
-system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7    854514720                       # number of WriteReq MSHR miss cycles
-system.cpu7.l1c.WriteReq_mshr_miss_latency::total    854514720                       # number of WriteReq MSHR miss cycles
-system.cpu7.l1c.demand_mshr_miss_latency::cpu7   1750504898                       # number of demand (read+write) MSHR miss cycles
-system.cpu7.l1c.demand_mshr_miss_latency::total   1750504898                       # number of demand (read+write) MSHR miss cycles
-system.cpu7.l1c.overall_mshr_miss_latency::cpu7   1750504898                       # number of overall MSHR miss cycles
-system.cpu7.l1c.overall_mshr_miss_latency::total   1750504898                       # number of overall MSHR miss cycles
-system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7    906836045                       # number of ReadReq MSHR uncacheable cycles
-system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total    906836045                       # number of ReadReq MSHR uncacheable cycles
-system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7    572746318                       # number of WriteReq MSHR uncacheable cycles
-system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total    572746318                       # number of WriteReq MSHR uncacheable cycles
-system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7   1479582363                       # number of overall MSHR uncacheable cycles
-system.cpu7.l1c.overall_mshr_uncacheable_latency::total   1479582363                       # number of overall MSHR uncacheable cycles
-system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7     0.805784                       # mshr miss rate for ReadReq accesses
-system.cpu7.l1c.ReadReq_mshr_miss_rate::total     0.805784                       # mshr miss rate for ReadReq accesses
-system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7     0.958703                       # mshr miss rate for WriteReq accesses
-system.cpu7.l1c.WriteReq_mshr_miss_rate::total     0.958703                       # mshr miss rate for WriteReq accesses
-system.cpu7.l1c.demand_mshr_miss_rate::cpu7     0.859472                       # mshr miss rate for demand accesses
-system.cpu7.l1c.demand_mshr_miss_rate::total     0.859472                       # mshr miss rate for demand accesses
-system.cpu7.l1c.overall_mshr_miss_rate::cpu7     0.859472                       # mshr miss rate for overall accesses
-system.cpu7.l1c.overall_mshr_miss_rate::total     0.859472                       # mshr miss rate for overall accesses
-system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 24969.071954                       # average ReadReq mshr miss latency
-system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 24969.071954                       # average ReadReq mshr miss latency
-system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 36993.580674                       # average WriteReq mshr miss latency
-system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 36993.580674                       # average WriteReq mshr miss latency
-system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 29678.125867                       # average overall mshr miss latency
-system.cpu7.l1c.demand_avg_mshr_miss_latency::total 29678.125867                       # average overall mshr miss latency
-system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 29678.125867                       # average overall mshr miss latency
-system.cpu7.l1c.overall_avg_mshr_miss_latency::total 29678.125867                       # average overall mshr miss latency
+system.cpu7.l1c.writebacks::writebacks           9581                       # number of writebacks
+system.cpu7.l1c.writebacks::total                9581                       # number of writebacks
+system.cpu7.l1c.ReadReq_mshr_misses::cpu7        36453                       # number of ReadReq MSHR misses
+system.cpu7.l1c.ReadReq_mshr_misses::total        36453                       # number of ReadReq MSHR misses
+system.cpu7.l1c.WriteReq_mshr_misses::cpu7        22910                       # number of WriteReq MSHR misses
+system.cpu7.l1c.WriteReq_mshr_misses::total        22910                       # number of WriteReq MSHR misses
+system.cpu7.l1c.demand_mshr_misses::cpu7        59363                       # number of demand (read+write) MSHR misses
+system.cpu7.l1c.demand_mshr_misses::total        59363                       # number of demand (read+write) MSHR misses
+system.cpu7.l1c.overall_mshr_misses::cpu7        59363                       # number of overall MSHR misses
+system.cpu7.l1c.overall_mshr_misses::total        59363                       # number of overall MSHR misses
+system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7    872289420                       # number of ReadReq MSHR miss cycles
+system.cpu7.l1c.ReadReq_mshr_miss_latency::total    872289420                       # number of ReadReq MSHR miss cycles
+system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7    785947981                       # number of WriteReq MSHR miss cycles
+system.cpu7.l1c.WriteReq_mshr_miss_latency::total    785947981                       # number of WriteReq MSHR miss cycles
+system.cpu7.l1c.demand_mshr_miss_latency::cpu7   1658237401                       # number of demand (read+write) MSHR miss cycles
+system.cpu7.l1c.demand_mshr_miss_latency::total   1658237401                       # number of demand (read+write) MSHR miss cycles
+system.cpu7.l1c.overall_mshr_miss_latency::cpu7   1658237401                       # number of overall MSHR miss cycles
+system.cpu7.l1c.overall_mshr_miss_latency::total   1658237401                       # number of overall MSHR miss cycles
+system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7    674384984                       # number of ReadReq MSHR uncacheable cycles
+system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total    674384984                       # number of ReadReq MSHR uncacheable cycles
+system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7    681937361                       # number of WriteReq MSHR uncacheable cycles
+system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total    681937361                       # number of WriteReq MSHR uncacheable cycles
+system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7   1356322345                       # number of overall MSHR uncacheable cycles
+system.cpu7.l1c.overall_mshr_uncacheable_latency::total   1356322345                       # number of overall MSHR uncacheable cycles
+system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7     0.807268                       # mshr miss rate for ReadReq accesses
+system.cpu7.l1c.ReadReq_mshr_miss_rate::total     0.807268                       # mshr miss rate for ReadReq accesses
+system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7     0.954345                       # mshr miss rate for WriteReq accesses
+system.cpu7.l1c.WriteReq_mshr_miss_rate::total     0.954345                       # mshr miss rate for WriteReq accesses
+system.cpu7.l1c.demand_mshr_miss_rate::cpu7     0.858318                       # mshr miss rate for demand accesses
+system.cpu7.l1c.demand_mshr_miss_rate::total     0.858318                       # mshr miss rate for demand accesses
+system.cpu7.l1c.overall_mshr_miss_rate::cpu7     0.858318                       # mshr miss rate for overall accesses
+system.cpu7.l1c.overall_mshr_miss_rate::total     0.858318                       # mshr miss rate for overall accesses
+system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 23929.153156                       # average ReadReq mshr miss latency
+system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 23929.153156                       # average ReadReq mshr miss latency
+system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 34305.891794                       # average WriteReq mshr miss latency
+system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 34305.891794                       # average WriteReq mshr miss latency
+system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 27933.854438                       # average overall mshr miss latency
+system.cpu7.l1c.demand_avg_mshr_miss_latency::total 27933.854438                       # average overall mshr miss latency
+system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 27933.854438                       # average overall mshr miss latency
+system.cpu7.l1c.overall_avg_mshr_miss_latency::total 27933.854438                       # average overall mshr miss latency
 system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7          inf                       # average ReadReq mshr uncacheable latency
 system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7          inf                       # average WriteReq mshr uncacheable latency
-- 
2.30.2