From fdba782098076205d7740fc091d925d63b29a194 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 12 Aug 2022 14:14:44 +0100
Subject: [PATCH] remove LDSTBREV condition, used for ld-st-with-shift

---
 openpower/isatables/LDSTRM-2P-1S1D-PU.csv | 12 ++++----
 openpower/isatables/LDSTRM-2P-1S1D.csv    |  9 ------
 openpower/isatables/LDSTRM-2P-1S2D.csv    | 12 ++++----
 openpower/isatables/LDSTRM-2P-2S1D.csv    |  6 ----
 openpower/isatables/major.csv             | 36 ++++++++---------------
 src/openpower/decoder/power_decoder.py    |  4 +--
 src/openpower/decoder/power_decoder2.py   |  8 +----
 7 files changed, 27 insertions(+), 60 deletions(-)
 delete mode 100644 openpower/isatables/LDSTRM-2P-1S1D.csv

diff --git a/openpower/isatables/LDSTRM-2P-1S1D-PU.csv b/openpower/isatables/LDSTRM-2P-1S1D-PU.csv
index 37b384aa..d8a64dbe 100644
--- a/openpower/isatables/LDSTRM-2P-1S1D-PU.csv
+++ b/openpower/isatables/LDSTRM-2P-1S1D-PU.csv
@@ -1,9 +1,9 @@
 insn,mode,CONDITIONS,Ptype,Etype,0,1,2,3,in1,in2,in3,out,CR in,CR out,PU,out2
-lwz,LDST,~SVP64BREV,2P,EXTRA2,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,1,0
-lbz,LDST,~SVP64BREV,2P,EXTRA2,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,1,0
-lhz,LDST,~SVP64BREV,2P,EXTRA2,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,1,0
-lha,LDST,~SVP64BREV,2P,EXTRA2,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,1,0
-lfs,LDST,~SVP64BREV,2P,EXTRA2,d:FRT,s:RA,0,0,RA_OR_ZERO,0,0,FRT,0,0,1,0
-lfd,LDST,~SVP64BREV,2P,EXTRA2,d:FRT,s:RA,0,0,RA_OR_ZERO,0,0,FRT,0,0,1,0
+lwz,LDST,,2P,EXTRA2,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,1,0
+lbz,LDST,,2P,EXTRA2,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,1,0
+lhz,LDST,,2P,EXTRA2,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,1,0
+lha,LDST,,2P,EXTRA2,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,1,0
+lfs,LDST,,2P,EXTRA2,d:FRT,s:RA,0,0,RA_OR_ZERO,0,0,FRT,0,0,1,0
+lfd,LDST,,2P,EXTRA2,d:FRT,s:RA,0,0,RA_OR_ZERO,0,0,FRT,0,0,1,0
 ld,LDST,,2P,EXTRA2,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,1,0
 lwa,LDST,,2P,EXTRA2,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,1,0
diff --git a/openpower/isatables/LDSTRM-2P-1S1D.csv b/openpower/isatables/LDSTRM-2P-1S1D.csv
deleted file mode 100644
index 9e3a5fb5..00000000
--- a/openpower/isatables/LDSTRM-2P-1S1D.csv
+++ /dev/null
@@ -1,9 +0,0 @@
-insn,mode,CONDITIONS,Ptype,Etype,0,1,2,3,in1,in2,in3,out,CR in,CR out,out2
-lwz,LDST,~SVP64BREV,2P,EXTRA3,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,0
-lbz,LDST,~SVP64BREV,2P,EXTRA3,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,0
-lhz,LDST,~SVP64BREV,2P,EXTRA3,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,0
-lha,LDST,~SVP64BREV,2P,EXTRA3,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,0
-lfs,LDST,~SVP64BREV,2P,EXTRA3,d:FRT,s:RA,0,0,RA_OR_ZERO,0,0,FRT,0,0,0
-lfd,LDST,~SVP64BREV,2P,EXTRA3,d:FRT,s:RA,0,0,RA_OR_ZERO,0,0,FRT,0,0,0
-ld,LDST,,2P,EXTRA3,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,0
-lwa,LDST,,2P,EXTRA3,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,0
diff --git a/openpower/isatables/LDSTRM-2P-1S2D.csv b/openpower/isatables/LDSTRM-2P-1S2D.csv
index f4d8755e..93fd896a 100644
--- a/openpower/isatables/LDSTRM-2P-1S2D.csv
+++ b/openpower/isatables/LDSTRM-2P-1S2D.csv
@@ -1,8 +1,8 @@
 insn,mode,CONDITIONS,Ptype,Etype,0,1,2,3,in1,in2,in3,out,CR in,CR out,PU,out2
-lwzu,LDST,~SVP64BREV,2P,EXTRA2,d:RT,d:RA,s:RA,0,RA_OR_ZERO,0,0,RT,0,0,0,RA
-lbzu,LDST,~SVP64BREV,2P,EXTRA2,d:RT,d:RA,s:RA,0,RA_OR_ZERO,0,0,RT,0,0,0,RA
-lhzu,LDST,~SVP64BREV,2P,EXTRA2,d:RT,d:RA,s:RA,0,RA_OR_ZERO,0,0,RT,0,0,0,RA
-lhau,LDST,~SVP64BREV,2P,EXTRA2,d:RT,d:RA,s:RA,0,RA_OR_ZERO,0,0,RT,0,0,0,RA
-lfsu,LDST,~SVP64BREV,2P,EXTRA2,d:FRT,d:RA,s:RA,0,RA,0,0,FRT,0,0,0,RA
-lfdu,LDST,~SVP64BREV,2P,EXTRA2,d:FRT,d:RA,s:RA,0,RA,0,0,FRT,0,0,0,RA
+lwzu,LDST,,2P,EXTRA2,d:RT,d:RA,s:RA,0,RA_OR_ZERO,0,0,RT,0,0,0,RA
+lbzu,LDST,,2P,EXTRA2,d:RT,d:RA,s:RA,0,RA_OR_ZERO,0,0,RT,0,0,0,RA
+lhzu,LDST,,2P,EXTRA2,d:RT,d:RA,s:RA,0,RA_OR_ZERO,0,0,RT,0,0,0,RA
+lhau,LDST,,2P,EXTRA2,d:RT,d:RA,s:RA,0,RA_OR_ZERO,0,0,RT,0,0,0,RA
+lfsu,LDST,,2P,EXTRA2,d:FRT,d:RA,s:RA,0,RA,0,0,FRT,0,0,0,RA
+lfdu,LDST,,2P,EXTRA2,d:FRT,d:RA,s:RA,0,RA,0,0,FRT,0,0,0,RA
 ldu,LDST,,2P,EXTRA2,d:RT,d:RA,s:RA,0,RA_OR_ZERO,0,0,RT,0,0,0,RA
diff --git a/openpower/isatables/LDSTRM-2P-2S1D.csv b/openpower/isatables/LDSTRM-2P-2S1D.csv
index d1753d95..2e6e2b24 100644
--- a/openpower/isatables/LDSTRM-2P-2S1D.csv
+++ b/openpower/isatables/LDSTRM-2P-2S1D.csv
@@ -20,15 +20,9 @@ lbzcix,LDST,,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0,0
 lfiwax,LDST,,2P,EXTRA2,d:FRT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,FRT,0,0,0,0
 ldcix,LDST,,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0,0
 lfiwzx,LDST,,2P,EXTRA2,d:FRT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,FRT,0,0,0,0
-lwz,LDST,SVP64BREV,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,0,RC,RT,0,0,0,0
-lbz,LDST,SVP64BREV,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,0,RC,RT,0,0,0,0
 stwu,LDST,,2P,EXTRA2,d:RA,s:RS,s:RA,0,RA_OR_ZERO,0,RS,0,0,0,0,RA
 stbu,LDST,,2P,EXTRA2,d:RA,s:RS,s:RA,0,RA_OR_ZERO,0,RS,0,0,0,0,RA
-lhz,LDST,SVP64BREV,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,0,RC,RT,0,0,0,0
-lha,LDST,SVP64BREV,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,0,RC,RT,0,0,0,0
 sthu,LDST,,2P,EXTRA2,d:RA,s:RS,s:RA,0,RA_OR_ZERO,0,RS,0,0,0,0,RA
-lfs,LDST,SVP64BREV,2P,EXTRA2,d:FRT,s:RA,s:RB,0,RA_OR_ZERO,0,RC,FRT,0,0,0,0
-lfd,LDST,SVP64BREV,2P,EXTRA2,d:FRT,s:RA,s:RB,0,RA_OR_ZERO,0,RC,FRT,0,0,0,0
 stfsu,LDST,,2P,EXTRA2,d:RA,s:FRS,s:RA,0,RA,0,FRS,0,0,0,0,RA
 stfdu,LDST,,2P,EXTRA2,d:RA,s:FRS,s:RA,0,RA,0,FRS,0,0,0,0,RA
 stdu,LDST,,2P,EXTRA2,d:RA,s:RS,s:RA,0,RA_OR_ZERO,0,RS,0,0,0,0,RA
diff --git a/openpower/isatables/major.csv b/openpower/isatables/major.csv
index 8fd9235f..d06d5a39 100644
--- a/openpower/isatables/major.csv
+++ b/openpower/isatables/major.csv
@@ -1,16 +1,4 @@
 opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form,CONDITIONS
-34,LDST,OP_LOAD,RA_OR_ZERO,CONST_SVD,RC,RT,NONE,NONE,0,0,ZERO,0,is1B,0,0,0,0,0,0,NONE,0,1,lbz,SVD,SVP64BREV
-35,LDST,OP_LOAD,RA_OR_ZERO,CONST_SVD,RC,RT,NONE,NONE,0,0,ZERO,0,is1B,0,0,1,0,0,0,NONE,0,1,lbzu,SVD,SVP64BREV
-50,LDST,OP_LOAD,RA_OR_ZERO,CONST_SVD,RC,FRT,NONE,NONE,0,0,ZERO,0,is8B,0,0,0,0,0,0,NONE,0,1,lfd,SVD,SVP64BREV
-51,LDST,OP_LOAD,RA,CONST_SVD,RC,FRT,NONE,NONE,0,0,ZERO,0,is8B,0,0,1,0,0,0,NONE,0,1,lfdu,SVD,SVP64BREV
-48,LDST,OP_LOAD,RA_OR_ZERO,CONST_SVD,RC,FRT,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,0,1,0,NONE,0,1,lfs,SVD,SVP64BREV
-49,LDST,OP_LOAD,RA,CONST_SVD,RC,FRT,NONE,NONE,0,0,ZERO,0,is4B,0,0,1,0,1,0,NONE,0,1,lfsu,SVD,SVP64BREV
-42,LDST,OP_LOAD,RA_OR_ZERO,CONST_SVD,RC,RT,NONE,NONE,0,0,ZERO,0,is2B,0,1,0,0,0,0,NONE,0,1,lha,SVD,SVP64BREV
-43,LDST,OP_LOAD,RA_OR_ZERO,CONST_SVD,RC,RT,NONE,NONE,0,0,ZERO,0,is2B,0,1,1,0,0,0,NONE,0,1,lhau,SVD,SVP64BREV
-40,LDST,OP_LOAD,RA_OR_ZERO,CONST_SVD,RC,RT,NONE,NONE,0,0,ZERO,0,is2B,0,0,0,0,0,0,NONE,0,1,lhz,SVD,SVP64BREV
-41,LDST,OP_LOAD,RA_OR_ZERO,CONST_SVD,RC,RT,NONE,NONE,0,0,ZERO,0,is2B,0,0,1,0,0,0,NONE,0,1,lhzu,SVD,SVP64BREV
-32,LDST,OP_LOAD,RA_OR_ZERO,CONST_SVD,RC,RT,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,0,0,0,NONE,0,1,lwz,SVD,SVP64BREV
-33,LDST,OP_LOAD,RA_OR_ZERO,CONST_SVD,RC,RT,NONE,NONE,0,0,ZERO,0,is4B,0,0,1,0,0,0,NONE,0,1,lwzu,SVD,SVP64BREV
 12,ALU,OP_ADD,RA,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,1,NONE,0,0,0,0,0,0,NONE,0,0,addic,D,
 13,ALU,OP_ADD,RA,CONST_SI,NONE,RT,NONE,CR0,0,0,ZERO,1,NONE,0,0,0,0,0,0,ONE,0,0,addic.,D,
 14,ALU,OP_ADD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,addi,D,
@@ -22,18 +10,18 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou
 16,BRANCH,OP_BC,SPR,CONST_BD,NONE,SPR,BI,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,1,0,bc,B,
 11,ALU,OP_CMP,RA,CONST_SI,NONE,NONE,NONE,BF,1,0,ONE,0,NONE,0,0,0,0,0,1,NONE,0,0,cmpi,D,
 10,ALU,OP_CMP,RA,CONST_UI,NONE,NONE,NONE,BF,1,0,ONE,0,NONE,0,0,0,0,0,0,NONE,0,0,cmpli,D,
-34,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is1B,0,0,0,0,0,0,NONE,0,1,lbz,D,~SVP64BREV
-35,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is1B,0,0,1,0,0,0,NONE,0,1,lbzu,D,~SVP64BREV
-50,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,FRT,NONE,NONE,0,0,ZERO,0,is8B,0,0,0,0,0,0,NONE,0,1,lfd,D,~SVP64BREV
-51,LDST,OP_LOAD,RA,CONST_SI,NONE,FRT,NONE,NONE,0,0,ZERO,0,is8B,0,0,1,0,0,0,NONE,0,1,lfdu,D,~SVP64BREV
-48,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,FRT,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,0,1,0,NONE,0,1,lfs,D,~SVP64BREV
-49,LDST,OP_LOAD,RA,CONST_SI,NONE,FRT,NONE,NONE,0,0,ZERO,0,is4B,0,0,1,0,1,0,NONE,0,1,lfsu,D,~SVP64BREV
-42,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is2B,0,1,0,0,0,0,NONE,0,1,lha,D,~SVP64BREV
-43,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is2B,0,1,1,0,0,0,NONE,0,1,lhau,D,~SVP64BREV
-40,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is2B,0,0,0,0,0,0,NONE,0,1,lhz,D,~SVP64BREV
-41,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is2B,0,0,1,0,0,0,NONE,0,1,lhzu,D,~SVP64BREV
-32,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,0,0,0,NONE,0,1,lwz,D,~SVP64BREV
-33,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is4B,0,0,1,0,0,0,NONE,0,1,lwzu,D,~SVP64BREV
+34,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is1B,0,0,0,0,0,0,NONE,0,1,lbz,D,
+35,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is1B,0,0,1,0,0,0,NONE,0,1,lbzu,D,
+50,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,FRT,NONE,NONE,0,0,ZERO,0,is8B,0,0,0,0,0,0,NONE,0,1,lfd,D,
+51,LDST,OP_LOAD,RA,CONST_SI,NONE,FRT,NONE,NONE,0,0,ZERO,0,is8B,0,0,1,0,0,0,NONE,0,1,lfdu,D,
+48,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,FRT,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,0,1,0,NONE,0,1,lfs,D,
+49,LDST,OP_LOAD,RA,CONST_SI,NONE,FRT,NONE,NONE,0,0,ZERO,0,is4B,0,0,1,0,1,0,NONE,0,1,lfsu,D,
+42,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is2B,0,1,0,0,0,0,NONE,0,1,lha,D,
+43,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is2B,0,1,1,0,0,0,NONE,0,1,lhau,D,
+40,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is2B,0,0,0,0,0,0,NONE,0,1,lhz,D,
+41,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is2B,0,0,1,0,0,0,NONE,0,1,lhzu,D,
+32,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,0,0,0,NONE,0,1,lwz,D,
+33,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,NONE,NONE,0,0,ZERO,0,is4B,0,0,1,0,0,0,NONE,0,1,lwzu,D,
 7,MUL,OP_MUL_L64,RA,CONST_SI,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,1,NONE,0,0,mulli,D,
 24,LOGICAL,OP_OR,RS,CONST_UI,NONE,RA,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,ori,D,
 25,LOGICAL,OP_OR,RS,CONST_UI_HI,NONE,RA,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,oris,D,
diff --git a/src/openpower/decoder/power_decoder.py b/src/openpower/decoder/power_decoder.py
index 2b4799c6..7e629632 100644
--- a/src/openpower/decoder/power_decoder.py
+++ b/src/openpower/decoder/power_decoder.py
@@ -326,7 +326,7 @@ class PowerDecoder(Elaboratable):
                  row_subset=None, conditions=None):
         if conditions is None:
             # XXX conditions = {}
-            conditions = {'SVP64BREV': Const(0, 1),
+            conditions = {
                           'SVP64FFT': Const(0, 1),
                           }
         self.actually_does_something = False
@@ -802,7 +802,7 @@ if __name__ == '__main__':
             log("row_subset", opcode, row)
             return row['unit'] in ['LDST', 'FPU']
 
-        conditions = {'SVP64BREV': Signal(name="svp64brev", reset_less=True),
+        conditions = {
                       'SVP64FFT': Signal(name="svp64fft", reset_less=True),
                       }
         pdecode = create_pdecode(name="rowsub",
diff --git a/src/openpower/decoder/power_decoder2.py b/src/openpower/decoder/power_decoder2.py
index a0ebf7f8..f2c4a0f6 100644
--- a/src/openpower/decoder/power_decoder2.py
+++ b/src/openpower/decoder/power_decoder2.py
@@ -788,7 +788,6 @@ class PowerDecodeSubset(Elaboratable):
         self.regreduce_en = regreduce_en
         if svp64_en:
             self.is_svp64_mode = Signal()  # mark decoding as SVP64 Mode
-            self.use_svp64_ldst_dec = Signal()  # must use LDST decoder
             self.use_svp64_fft = Signal()      # FFT Mode
             self.sv_rm = SVP64Rec(name="dec_svp64")  # SVP64 RM field
             self.rm_dec = SVP64RMModeDecode("svp64_rm_dec")
@@ -813,7 +812,7 @@ class PowerDecodeSubset(Elaboratable):
         # alternatives.  useful for PCR (Program Compatibility Register)
         # amongst other things
         if svp64_en:
-            conditions = {'SVP64BREV': self.use_svp64_ldst_dec,
+            conditions = {
                           'SVP64FFT': self.use_svp64_fft,
                           }
         else:
@@ -876,7 +875,6 @@ class PowerDecodeSubset(Elaboratable):
         if self.svp64_en:
             ports += self.sv_rm.ports()
             ports.append(self.is_svp64_mode)
-            ports.append(self.use_svp64_ldst_dec)
             ports.append(self.use_svp64_fft)
         return ports
 
@@ -1060,10 +1058,6 @@ class PowerDecodeSubset(Elaboratable):
                 comb += rm_dec.ldst_imz_in.eq(bzero)  # B immediate is zero
 
             # main PowerDecoder2 determines if different SVP64 modes enabled
-            if not self.final:
-                # if shift mode requested
-                shiftmode = rm_dec.ldstmode == SVP64LDSTmode.SHIFT
-                comb += self.use_svp64_ldst_dec.eq(shiftmode)
             # detect if SVP64 FFT mode enabled (really bad hack),
             # exclude fcfids and others
             # XXX this is a REALLY bad hack, REALLY has to be done better.
-- 
2.30.2