From fdc2ce3fb07e41720d2083ba39892bb08c3d5e7a Mon Sep 17 00:00:00 2001 From: Kaz Kojima Date: Thu, 16 Jul 2015 00:48:33 +0000 Subject: [PATCH] re PR target/65249 (unable to find a register to spill in class 'R0_REGS' when compiling protobuf on sh4) PR target/65249 * config/sh/sh.md (movdi): Split simple reg move to two movsi when the destination is R0 so as to lower R0-register pressure. From-SVN: r225856 --- gcc/ChangeLog | 6 ++++++ gcc/config/sh/sh.md | 18 ++++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6f5459d4797..603c5e3a1e4 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2015-07-16 Kaz Kojima + + PR target/65249 + * config/sh/sh.md (movdi): Split simple reg move to two movsi + when the destination is R0. + 2015-07-16 Uros Bizjak PR target/66866 diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md index f0cb3cfe8c4..61f663778d0 100644 --- a/gcc/config/sh/sh.md +++ b/gcc/config/sh/sh.md @@ -7892,6 +7892,24 @@ label: "" { prepare_move_operands (operands, DImode); + if (TARGET_SH1) + { + /* When the dest operand is (R0, R1) register pair, split it to + two movsi of which dest is R1 and R0 so as to lower R0-register + pressure on the first movsi. Apply only for simple source not + to make complex rtl here. */ + if (REG_P (operands[0]) + && REGNO (operands[0]) == R0_REG + && REG_P (operands[1]) + && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER) + { + emit_insn (gen_movsi (gen_rtx_REG (SImode, R1_REG), + gen_rtx_SUBREG (SImode, operands[1], 4))); + emit_insn (gen_movsi (gen_rtx_REG (SImode, R0_REG), + gen_rtx_SUBREG (SImode, operands[1], 0))); + DONE; + } + } }) (define_insn "movdf_media" -- 2.30.2