From fddf07e9cd7c56115b26f4e888c86d3208ebb15b Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 15 Nov 2020 17:59:05 +0000 Subject: [PATCH] --- openpower/sv/16_bit_compressed.mdwn | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/openpower/sv/16_bit_compressed.mdwn b/openpower/sv/16_bit_compressed.mdwn index b9ba2a901..f0b630928 100644 --- a/openpower/sv/16_bit_compressed.mdwn +++ b/openpower/sv/16_bit_compressed.mdwn @@ -81,16 +81,28 @@ The current "top" idea for 0b11 is to use it for a new encoding format of predominantly "immediates-based" 16-bit instructions (branch-conditional, addi, mulli etc.) +### Immediate Opcodes + +only available in 16-bit mode + + | 0 | 1 | 2 3 4 | | 567 | 8 9 a | b c d | e | f | + | 1 | offs2 | | 000 | o BI | o BO | LK | 1 | bc + | 1 | o2 | RT | | 010 | RB | offs | 1 | addis + | 1 | o2 | RT | | 011 | RB | offs | 1 | mulis + | 1 | o2 | | | 100 | | offs | 1 | + | 1 | o2 | | | 101 | | offs | 1 | ldi + | 1 | o2 | | | 110 | | offs | 1 | sti + ### Branch 10 bit mode may be expanded by 16 bit mode later, adding capabilities that do not fit in the extreme limited space. | 16-bit mode | | 10-bit mode | - | 0 1 | 2 3 4 | | 567 | 8 9 a | b c d | e | f | - | offs2 | | 000 | offs | LK | M | b - | BO2 | BI3 | | 001 | 0 BI | 0 BO | LK | M | bclr - | BO2 | BI3 | | 001 | 0 BI | 1 BO | LK | M | bctar + | 0 | 1 | 2 3 4 | | 567 | 8 9 a | b c d | e | f | + | N | offs2 | | 000 | offs | LK | M | b + | BO2 | BI3 | | 001 | 0 BI | 0 BO | LK | M | bclr + | BO2 | BI3 | | 001 | 0 BI | 1 BO | LK | M | bctar 16 bit mode: -- 2.30.2