From fde3100fe65a175f034c77e7989601839c9983bb Mon Sep 17 00:00:00 2001 From: Matt Turner Date: Thu, 2 Apr 2015 16:15:53 -0700 Subject: [PATCH] i965/fs: Emit ADDs for gl_FragCoord, not virtual opcodes. These were used only on Gen4 and 5. emit_interpolation_setup_gen6() emits ADDs directly. The virtual opcodes weren't providing anything useful. I'm going to repurpose these opcodes, so deleting and readding them makes it simpler to see what's going on. Reviewed-by: Jason Ekstrand --- src/mesa/drivers/dri/i965/brw_defines.h | 2 - src/mesa/drivers/dri/i965/brw_fs.h | 1 - .../drivers/dri/i965/brw_fs_generator.cpp | 40 ------------------- src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 11 +++-- src/mesa/drivers/dri/i965/brw_shader.cpp | 5 --- 5 files changed, 8 insertions(+), 51 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index a97a9443f3d..5962b000d89 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -923,8 +923,6 @@ enum opcode { */ FS_OPCODE_DDY_COARSE, FS_OPCODE_DDY_FINE, - FS_OPCODE_PIXEL_X, - FS_OPCODE_PIXEL_Y, FS_OPCODE_CINTERP, FS_OPCODE_LINTERP, FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD, diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h index 32063f01b8c..d625d91e60e 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.h +++ b/src/mesa/drivers/dri/i965/brw_fs.h @@ -557,7 +557,6 @@ private: void generate_fb_write(fs_inst *inst, struct brw_reg payload); void generate_urb_write(fs_inst *inst, struct brw_reg payload); void generate_blorp_fb_write(fs_inst *inst); - void generate_pixel_xy(struct brw_reg dst, bool is_x); void generate_linterp(fs_inst *inst, struct brw_reg dst, struct brw_reg *src); void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src, diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp index 397d8257a91..353f35adda0 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp @@ -387,40 +387,6 @@ fs_generator::generate_blorp_fb_write(fs_inst *inst) inst->header_present); } -/* Computes the integer pixel x,y values from the origin. - * - * This is the basis of gl_FragCoord computation, but is also used - * pre-gen6 for computing the deltas from v0 for computing - * interpolation. - */ -void -fs_generator::generate_pixel_xy(struct brw_reg dst, bool is_x) -{ - struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW); - struct brw_reg src; - struct brw_reg deltas; - - if (is_x) { - src = stride(suboffset(g1_uw, 4), 2, 4, 0); - deltas = brw_imm_v(0x10101010); - } else { - src = stride(suboffset(g1_uw, 5), 2, 4, 0); - deltas = brw_imm_v(0x11001100); - } - - if (dispatch_width == 16) { - dst = vec16(dst); - } - - /* We do this SIMD8 or SIMD16, but since the destination is UW we - * don't do compression in the SIMD16 case. - */ - brw_push_insn_state(p); - brw_set_default_compression_control(p, BRW_COMPRESSION_NONE); - brw_ADD(p, dst, src, deltas); - brw_pop_insn_state(p); -} - void fs_generator::generate_linterp(fs_inst *inst, struct brw_reg dst, struct brw_reg *src) @@ -1949,12 +1915,6 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width) generate_math_gen4(inst, dst, src[0]); } break; - case FS_OPCODE_PIXEL_X: - generate_pixel_xy(dst, true); - break; - case FS_OPCODE_PIXEL_Y: - generate_pixel_xy(dst, false); - break; case FS_OPCODE_CINTERP: brw_MOV(p, dst, src[0]); break; diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp index 4e9936626a0..98c6988f6ad 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp @@ -3428,14 +3428,19 @@ fs_visitor::interp_reg(int location, int channel) void fs_visitor::emit_interpolation_setup_gen4() { + struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW); + this->current_annotation = "compute pixel centers"; this->pixel_x = vgrf(glsl_type::uint_type); this->pixel_y = vgrf(glsl_type::uint_type); this->pixel_x.type = BRW_REGISTER_TYPE_UW; this->pixel_y.type = BRW_REGISTER_TYPE_UW; - - emit(FS_OPCODE_PIXEL_X, this->pixel_x); - emit(FS_OPCODE_PIXEL_Y, this->pixel_y); + emit(ADD(this->pixel_x, + fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)), + fs_reg(brw_imm_v(0x10101010)))); + emit(ADD(this->pixel_y, + fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)), + fs_reg(brw_imm_v(0x11001100)))); this->current_annotation = "compute pixel deltas from v0"; if (brw->has_pln) { diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp index 0d6ac0c9311..d0d5cf9c4dd 100644 --- a/src/mesa/drivers/dri/i965/brw_shader.cpp +++ b/src/mesa/drivers/dri/i965/brw_shader.cpp @@ -512,11 +512,6 @@ brw_instruction_name(enum opcode op) case FS_OPCODE_DDY_FINE: return "ddy_fine"; - case FS_OPCODE_PIXEL_X: - return "pixel_x"; - case FS_OPCODE_PIXEL_Y: - return "pixel_y"; - case FS_OPCODE_CINTERP: return "cinterp"; case FS_OPCODE_LINTERP: -- 2.30.2