From fe14dc98bfe7ac9bf7a5d2adf7d2619147863ba4 Mon Sep 17 00:00:00 2001 From: Matt Turner Date: Fri, 19 Jun 2020 12:32:44 -0700 Subject: [PATCH] intel/compiler: Add assert that set bits are within mask We generate bitfields of bits that we want to retain (mask) and bits that we want to set (brw_mode) in the cr0 register, so the bits we want to set should be in the set of bits we want to retain. Also, remove the initialization of mask from fs_visitor::emit_shader_float_controls_execution_mode since brw_rnd_mode_from_nir initializes the mask parameter unconditionally. Reviewed-by: Lionel Landwerlin Part-of: --- src/intel/compiler/brw_fs_visitor.cpp | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/intel/compiler/brw_fs_visitor.cpp b/src/intel/compiler/brw_fs_visitor.cpp index 22e83f1adb9..bf8e615a274 100644 --- a/src/intel/compiler/brw_fs_visitor.cpp +++ b/src/intel/compiler/brw_fs_visitor.cpp @@ -242,6 +242,9 @@ brw_rnd_mode_from_nir(unsigned mode, unsigned *mask) if (mode == FLOAT_CONTROLS_DEFAULT_FLOAT_CONTROL_MODE) *mask |= BRW_CR0_FP_MODE_MASK; + if (*mask != 0) + assert((*mask & brw_mode) == brw_mode); + return brw_mode; } @@ -253,8 +256,8 @@ fs_visitor::emit_shader_float_controls_execution_mode() return; fs_builder abld = bld.annotate("shader floats control execution mode"); - unsigned mask = 0; - unsigned mode = brw_rnd_mode_from_nir(execution_mode, &mask); + unsigned mask, mode = brw_rnd_mode_from_nir(execution_mode, &mask); + abld.emit(SHADER_OPCODE_FLOAT_CONTROL_MODE, bld.null_reg_ud(), brw_imm_d(mode), brw_imm_d(mask)); } -- 2.30.2