From fe190770cd763589e34d98683fd9723fd535e483 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 29 Jul 2019 14:26:54 +0100 Subject: [PATCH] id_wid (muxid bitwidth) based on num_rows, not the data width --- src/ieee754/fclass/pipeline.py | 7 +++---- src/ieee754/fcvt/pipeline.py | 7 +++---- src/ieee754/fpadd/pipeline.py | 2 +- src/ieee754/fpdiv/pipeline.py | 2 +- src/ieee754/fpmul/pipeline.py | 2 +- 5 files changed, 9 insertions(+), 11 deletions(-) diff --git a/src/ieee754/fclass/pipeline.py b/src/ieee754/fclass/pipeline.py index 0a40d2b6..c00ab6e7 100644 --- a/src/ieee754/fclass/pipeline.py +++ b/src/ieee754/fclass/pipeline.py @@ -63,11 +63,10 @@ class FPClassMuxInOutBase(ReservationStations): def __init__(self, modkls, in_width, out_width, num_rows, op_wid=0, pkls=FPClassBasePipe): self.op_wid = op_wid - self.id_wid = num_bits(in_width) - self.out_id_wid = num_bits(out_width) + self.id_wid = num_bits(num_rows) - self.in_pspec = PipelineSpec(in_width, self.id_wid, self.op_wid) - self.out_pspec = PipelineSpec(out_width, self.out_id_wid, op_wid) + self.in_pspec = PipelineSpec(in_width, self.id_wid, op_wid) + self.out_pspec = PipelineSpec(out_width, self.id_wid, op_wid) self.alu = pkls(modkls, self.in_pspec, self.out_pspec) ReservationStations.__init__(self, num_rows) diff --git a/src/ieee754/fcvt/pipeline.py b/src/ieee754/fcvt/pipeline.py index 505bc6e8..d8f0db06 100644 --- a/src/ieee754/fcvt/pipeline.py +++ b/src/ieee754/fcvt/pipeline.py @@ -97,11 +97,10 @@ class FPCVTMuxInOutBase(ReservationStations): def __init__(self, modkls, e_extra, in_width, out_width, num_rows, op_wid=0, pkls=FPCVTBasePipe): self.op_wid = op_wid - self.id_wid = num_bits(in_width) - self.out_id_wid = num_bits(out_width) + self.id_wid = num_bits(num_rows) - self.in_pspec = PipelineSpec(in_width, self.id_wid, self.op_wid) - self.out_pspec = PipelineSpec(out_width, self.out_id_wid, op_wid) + self.in_pspec = PipelineSpec(in_width, id_wid, self.op_wid) + self.out_pspec = PipelineSpec(out_width, id_wid, op_wid) self.alu = pkls(modkls, e_extra, self.in_pspec, self.out_pspec) ReservationStations.__init__(self, num_rows) diff --git a/src/ieee754/fpadd/pipeline.py b/src/ieee754/fpadd/pipeline.py index 5d622132..424d39e7 100644 --- a/src/ieee754/fpadd/pipeline.py +++ b/src/ieee754/fpadd/pipeline.py @@ -84,7 +84,7 @@ class FPADDMuxInOut(ReservationStations): """ def __init__(self, width, num_rows, op_wid=None): - self.id_wid = num_bits(width) + self.id_wid = num_bits(num_rows) self.op_wid = op_wid self.pspec = PipelineSpec(width, self.id_wid, op_wid) self.alu = FPADDBasePipe(self.pspec) diff --git a/src/ieee754/fpdiv/pipeline.py b/src/ieee754/fpdiv/pipeline.py index bcd99e26..4330df44 100644 --- a/src/ieee754/fpdiv/pipeline.py +++ b/src/ieee754/fpdiv/pipeline.py @@ -156,7 +156,7 @@ class FPDIVMuxInOut(ReservationStations): """ def __init__(self, width, num_rows, op_wid=2): - self.id_wid = num_bits(width) # FIXME: shouldn't this be num_rows? + self.id_wid = num_bits(num_rows) self.pspec = PipelineSpec(width, self.id_wid, op_wid) # get the standard mantissa width, store in the pspec fmt = FPFormat.standard(width) diff --git a/src/ieee754/fpmul/pipeline.py b/src/ieee754/fpmul/pipeline.py index 589d1066..adb66a37 100644 --- a/src/ieee754/fpmul/pipeline.py +++ b/src/ieee754/fpmul/pipeline.py @@ -81,7 +81,7 @@ class FPMULMuxInOut(ReservationStations): """ def __init__(self, width, num_rows, op_wid=0): - self.id_wid = num_bits(width) + self.id_wid = num_bits(num_rows) self.op_wid = op_wid self.pspec = PipelineSpec(width, self.id_wid, self.op_wid) self.alu = FPMULBasePipe(self.pspec) -- 2.30.2