From fe38e12b2190253b784fe9c9301ce10773c3b1b3 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 28 Jul 2020 18:10:32 +0200 Subject: [PATCH] cpu/vexriscv_smp: move litedram import, remove os.path import. --- litex/soc/cores/cpu/vexriscv_smp/core.py | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/litex/soc/cores/cpu/vexriscv_smp/core.py b/litex/soc/cores/cpu/vexriscv_smp/core.py index c775ffa2..c88c84a4 100644 --- a/litex/soc/cores/cpu/vexriscv_smp/core.py +++ b/litex/soc/cores/cpu/vexriscv_smp/core.py @@ -12,10 +12,7 @@ from litex.soc.interconnect import wishbone from litex.soc.interconnect.csr import * from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV32 -from litedram.common import LiteDRAMNativePort - import os -import os.path CPU_VARIANTS = { @@ -228,6 +225,7 @@ class VexRiscvSMP(CPU): ) ] + from litedram.common import LiteDRAMNativePort if "mp" in variant: ncpus = int(variant[-2]) # FIXME for n in range(ncpus): -- 2.30.2