From fe4a8df9a8e906fd8037027c898d35af718fa9ea Mon Sep 17 00:00:00 2001 From: Jonathan Marek Date: Thu, 19 Dec 2019 10:40:35 -0500 Subject: [PATCH] freedreno/ir3: fix vertex shader sysvals with pre_assign_inputs The first pre_assign_inputs loop doesn't pre-assign sysvals, so skip the second part for sysvals. The sysvals don't need to be pre-assigned since the state for those isn't shared between binning / nonbinning shaders. Fixes assert failures in cases where the sysvals didn't end up in the same registers for binning / nonbinning. Signed-off-by: Jonathan Marek Reviewed-by: Rob Clark Tested-by: Marge Bot Part-of: --- src/freedreno/ir3/ir3_compiler_nir.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/freedreno/ir3/ir3_compiler_nir.c b/src/freedreno/ir3/ir3_compiler_nir.c index 82149c98e60..b6fc39f2fb1 100644 --- a/src/freedreno/ir3/ir3_compiler_nir.c +++ b/src/freedreno/ir3/ir3_compiler_nir.c @@ -3495,7 +3495,7 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler, assert(in->opc == OPC_META_INPUT); unsigned inidx = in->input.inidx; - if (pre_assign_inputs) { + if (pre_assign_inputs && !so->inputs[inidx].sysval) { if (VALIDREG(so->nonbinning->inputs[inidx].regid)) { compile_assert(ctx, in->regs[0]->num == so->nonbinning->inputs[inidx].regid); -- 2.30.2