From fe4bf68ff9dce7e855821ff1867810bbbd3c6057 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 11 Jul 2022 13:29:47 +0100 Subject: [PATCH] add mm=1 svindex test, setting single targetted SVSHAPE --- openpower/isa/simplev.mdwn | 19 ++--- .../decoder/isa/test_caller_svindex.py | 73 ++++++++++++++++++- 2 files changed, 81 insertions(+), 11 deletions(-) diff --git a/openpower/isa/simplev.mdwn b/openpower/isa/simplev.mdwn index 62f762be..648f43d8 100644 --- a/openpower/isa/simplev.mdwn +++ b/openpower/isa/simplev.mdwn @@ -314,19 +314,20 @@ Pseudo-code: if idx = 1 then SVSHAPE1 <- shape if idx = 2 then SVSHAPE2 <- shape if idx = 3 then SVSHAPE3 <- shape - SVSTATE[32+bit*2:33+bit*2] <- idx + SVSTATE[bit*2+32:bit*2+33] <- idx # increment shape index, modulo 4 if idx = 3 then idx <- 0 else idx <- idx + 1 else - # refined SVSHAPE/REMAP update mode - bit <- rmm[0:2] - idx <- rmm[3:4] - if idx = 0 then SVSHAPE0 <- shape - if idx = 1 then SVSHAPE1 <- shape - if idx = 2 then SVSHAPE2 <- shape - if idx = 3 then SVSHAPE3 <- shape - SVSTATE[32+bit*2:33+bit*2] <- idx + # refined SVSHAPE/REMAP update mode + bit <- rmm[0:2] + idx <- rmm[3:4] + if idx = 0 then SVSHAPE0 <- shape + if idx = 1 then SVSHAPE1 <- shape + if idx = 2 then SVSHAPE2 <- shape + if idx = 3 then SVSHAPE3 <- shape + SVSTATE[bit*2+32:bit*2+33] <- idx + SVSTATE[46-bit] <- 1 Special Registers Altered: diff --git a/src/openpower/decoder/isa/test_caller_svindex.py b/src/openpower/decoder/isa/test_caller_svindex.py index 36bb6e83..d91a07e6 100644 --- a/src/openpower/decoder/isa/test_caller_svindex.py +++ b/src/openpower/decoder/isa/test_caller_svindex.py @@ -1,5 +1,5 @@ """SVP64 unit test for svindex -svindex SVG,rmm,SVd,ew,yx,mr,sk +svindex SVG,rmm,SVd,ew,yx,mm,sk """ from nmigen import Module, Signal from nmigen.back.pysim import Simulator, Delay, Settle @@ -29,7 +29,7 @@ class SVSTATETestCase(FHDLTestCase): "GPR %d %x expected %x" % (i, sim.gpr(i).value, expected[i])) def test_0_sv_index(self): - """sets VL=10 (via SVSTATE) then does svindex, checks SPRs after + """sets VL=10 (via SVSTATE) then does svindex mm=0, checks SPRs after """ isa = SVP64Asm(['svindex 1, 15, 5, 0, 0, 0, 0' ]) @@ -89,6 +89,75 @@ class SVSTATETestCase(FHDLTestCase): shape = sim.spr['SVSHAPE%d' % i] self.assertEqual(shape.svgpr, 2) # SVG is shifted up by 1 + def test_1_sv_index(self): + """sets VL=10 (via SVSTATE) then does svindex mm=1, checks SPRs after + """ + # rmm: bits 0-2 (MSB0) are 0b011 and bits 3-4 are 0b10. + # therefore rmm is 0b011 || 0b10 --> 0b01110 -> 14 + isa = SVP64Asm(['svindex 1, 14, 5, 0, 0, 1, 0' + ]) + lst = list(isa) + print ("listing", lst) + + # initial values in GPR regfile + initial_regs = [0] * 32 + initial_regs[9] = 0x1234 + initial_regs[10] = 0x1111 + initial_regs[5] = 0x4321 + initial_regs[6] = 0x2223 + + # SVSTATE vl=10 + svstate = SVP64State() + svstate.vl = 10 # VL + svstate.maxvl = 10 # MAXVL + print ("SVSTATE", bin(svstate.asint())) + + # copy before running + expected_regs = deepcopy(initial_regs) + #expected_regs[1] = 0x3334 + + with Program(lst, bigendian=False) as program: + sim = self.run_tst_program(program, initial_regs, svstate=svstate) + self._check_regs(sim, expected_regs) + + print (sim.spr) + SVSHAPE2 = sim.spr['SVSHAPE2'] + print ("SVSTATE after", bin(sim.svstate.asint())) + print (" vl", bin(sim.svstate.vl)) + print (" mvl", bin(sim.svstate.maxvl)) + print (" srcstep", bin(sim.svstate.srcstep)) + print (" dststep", bin(sim.svstate.dststep)) + print (" RMpst", bin(sim.svstate.RMpst)) + print (" SVme", bin(sim.svstate.SVme)) + print (" mo0", bin(sim.svstate.mo0)) + print (" mo1", bin(sim.svstate.mo1)) + print (" mi0", bin(sim.svstate.mi0)) + print (" mi1", bin(sim.svstate.mi1)) + print (" mi2", bin(sim.svstate.mi2)) + print ("STATE2svgpr", hex(SVSHAPE2.svgpr)) + print ("STATE2 xdim", SVSHAPE2.xdimsz) + print ("STATE2 ydim", SVSHAPE2.ydimsz) + print ("STATE2 skip", bin(SVSHAPE2.skip)) + print ("STATE2 inv", SVSHAPE2.invxyz) + print ("STATE2order", SVSHAPE2.order) + self.assertEqual(sim.svstate.RMpst, 1) # mm=1 so persist=1 + # rmm is 0b01110 which means mo0 = 2 + self.assertEqual(sim.svstate.mi0, 0) + self.assertEqual(sim.svstate.mi1, 0) + self.assertEqual(sim.svstate.mi2, 0) + self.assertEqual(sim.svstate.mo0, 2) + self.assertEqual(sim.svstate.mo1, 0) + # and mo0 should be activated + self.assertEqual(sim.svstate.SVme, 0b01000) + # now check the SVSHAPEs. 2 was the one targetted + self.assertEqual(SVSHAPE2.svgpr, 2) # SVG is shifted up by 1 + self.assertEqual(SVSHAPE2.xdimsz, 5) # SHAPE2 xdim set to 5 + self.assertEqual(SVSHAPE2.ydimsz, 1) # SHAPE2 ydim 1 + # all others must be zero + for i in [0,1,3]: + shape = sim.spr['SVSHAPE%d' % i] + self.assertEqual(shape.asint(), 0) # all others zero + def test_0_sv_index_add(self): """sets VL=6 (via SVSTATE) then does svindex, and an add. -- 2.30.2