From fe4c1ea4e196bb84dc06fc081fa39c192ba64b0f Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 2 May 2023 18:53:15 +0100 Subject: [PATCH] add quick preamble header --- src/openpower/cyclemodel/inorder.py | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/openpower/cyclemodel/inorder.py b/src/openpower/cyclemodel/inorder.py index 5d311c69..15281d24 100644 --- a/src/openpower/cyclemodel/inorder.py +++ b/src/openpower/cyclemodel/inorder.py @@ -1,5 +1,9 @@ #!/usr/bin/env python3 # An In-order cycle-accurate model of a Power ISA 3.0 hardware implementation +# LGPLv3+ +# Funded by NLnet +# +# Bugs: https://bugs.libre-soc.org/show_bug.cgi?id=1039 class RegisterWrite(set): """RegisterWrite: contains the set of Read-after-Write Hazards. -- 2.30.2