From fe4eeff50d4c7a4b50854893c144edb034736ee7 Mon Sep 17 00:00:00 2001
From: Dmitry Selyutin <ghostmansd@gmail.com>
Date: Sun, 18 Sep 2022 21:55:49 +0300
Subject: [PATCH] power_insn: support ff/pr predicates

---
 src/openpower/decoder/power_insn.py | 46 ++++++++++++++++++++++++++---
 1 file changed, 42 insertions(+), 4 deletions(-)

diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py
index b859c822..933c9009 100644
--- a/src/openpower/decoder/power_insn.py
+++ b/src/openpower/decoder/power_insn.py
@@ -1298,6 +1298,26 @@ class BaseRM(_Mapping):
                 yield f"{indent}{', '.join(map(str, members))}"
 
 
+class FFPRRc1BaseRM(BaseRM):
+    def specifiers(self, record, mode):
+        inv = _SelectableInt(value=int(self.inv), bits=1)
+        CR = _SelectableInt(value=int(self.CR), bits=2)
+        mask = int(_selectconcat(inv, CR))
+        predicate = {
+            0b000: "lt",
+            0b001: "ge",
+            0b010: "gt",
+            0b011: "le",
+            0b100: "eq",
+            0b101: "ne",
+            0b110: "so",
+            0b111: "ns",
+        }[mask]
+        yield f"{mode}={predicate}"
+
+        yield from super().specifiers(record=record)
+
+
 class FFPRRc0BaseRM(BaseRM):
     def specifiers(self, record, mode):
         if self.RC1:
@@ -1429,11 +1449,14 @@ class NormalReservedRM(NormalBaseRM):
     pass
 
 
-class NormalFFRc1RM(NormalBaseRM):
+class NormalFFRc1RM(FFPRRc1BaseRM, NormalBaseRM):
     """normal: Rc=1: ffirst CR sel"""
     inv: BaseRM.mode[2]
     CR: BaseRM.mode[3, 4]
 
+    def specifiers(self, record):
+        yield from super().specifiers(record=record, mode="ff")
+
 
 class NormalFFRc0RM(FFPRRc0BaseRM, NormalBaseRM):
     """normal: Rc=0: ffirst z/nonz"""
@@ -1452,11 +1475,14 @@ class NormalSatRM(SatBaseRM, DZBaseRM, SZBaseRM, NormalBaseRM):
     sz: BaseRM.mode[4]
 
 
-class NormalPRRc1RM(NormalBaseRM):
+class NormalPRRc1RM(FFPRRc1BaseRM, NormalBaseRM):
     """normal: Rc=1: pred-result CR sel"""
     inv: BaseRM.mode[2]
     CR: BaseRM.mode[3, 4]
 
+    def specifiers(self, record):
+        yield from super().specifiers(record=record, mode="pr")
+
 
 class NormalPRRc0RM(FFPRRc0BaseRM, ZZBaseRM, NormalBaseRM):
     """normal: Rc=0: pred-result z/nonz"""
@@ -1502,11 +1528,14 @@ class LDSTImmReservedRM(LDSTImmBaseRM):
     pass
 
 
-class LDSTImmFFRc1RM(LDSTImmBaseRM):
+class LDSTImmFFRc1RM(FFPRRc1BaseRM, LDSTImmBaseRM):
     """ld/st immediate: Rc=1: ffirst CR sel"""
     inv: BaseRM.mode[2]
     CR: BaseRM.mode[3, 4]
 
+    def specifiers(self, record):
+        yield from super().specifiers(record=record, mode="ff")
+
 
 class LDSTImmFFRc0RM(FFPRRc0BaseRM, LDSTImmBaseRM):
     """ld/st immediate: Rc=0: ffirst z/nonz"""
@@ -1527,11 +1556,14 @@ class LDSTImmSatRM(SatBaseRM, ZZBaseRM, LDSTImmBaseRM):
     sz: BaseRM.mode[3]
 
 
-class LDSTImmPRRc1RM(LDSTImmBaseRM):
+class LDSTImmPRRc1RM(FFPRRc1BaseRM, LDSTImmBaseRM):
     """ld/st immediate: Rc=1: pred-result CR sel"""
     inv: BaseRM.mode[2]
     CR: BaseRM.mode[3, 4]
 
+    def specifiers(self, record):
+        yield from super().specifiers(record=record, mode="pr")
+
 
 class LDSTImmPRRc0RM(FFPRRc0BaseRM, LDSTImmBaseRM):
     """ld/st immediate: Rc=0: pred-result z/nonz"""
@@ -1587,6 +1619,9 @@ class LDSTIdxPRRc1RM(LDSTIdxBaseRM):
     inv: BaseRM.mode[2]
     CR: BaseRM.mode[3, 4]
 
+    def specifiers(self, record):
+        yield from super().specifiers(record=record, mode="pr")
+
 
 class LDSTIdxPRRc0RM(FFPRRc0BaseRM, ZZBaseRM, LDSTIdxBaseRM):
     """ld/st index: Rc=0: pred-result z/nonz"""
@@ -1651,6 +1686,9 @@ class CROpFF3RM(ZZBaseRM, CROpBaseRM):
     sz: BaseRM[21]
     dz: BaseRM[22]
 
+    def specifiers(self, record):
+        yield from super().specifiers(record=record, mode="ff")
+
 
 class CROpFF5RM(DZBaseRM, SZBaseRM, CROpBaseRM):
     """cr_op: ffirst 5-bit mode"""
-- 
2.30.2