From fe68d351901088aa274a0052369f9bdeb67fec91 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 4 Jun 2018 15:16:50 +0100
Subject: [PATCH] clarify

---
 simple_v_extension/simple_v_chennai_2018.tex | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index fa4fe0cda..a2c45ce6f 100644
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -475,16 +475,16 @@ for (i = 0; i < 16; i++) // 16 CSRs?
 \begin{semiverbatim}
 function op\_add(rd, rs1, rs2, predr) # add not VADD!
   int i, id=0, irs1=0, irs2=0;
-  rd  = int_vec[rd ].isvector ? int_vec[rd ].regidx : rd;
-  rs1 = int_vec[rs1].isvector ? int_vec[rs1].regidx : rs1;
-  rs2 = int_vec[rs2].isvector ? int_vec[rs2].regidx : rs2;
-  predval = get\_pred_val(FALSE, rd);
+  rd  = int\_vec[rd ].isvector ? int\_vec[rd ].regidx : rd;
+  rs1 = int\_vec[rs1].isvector ? int\_vec[rs1].regidx : rs1;
+  rs2 = int\_vec[rs2].isvector ? int\_vec[rs2].regidx : rs2;
+  predval = get\_pred\_val(FALSE, rd);
   for (i = 0; i < VL; i++)
     if (predval \& 1<<i) # predication uses intregs
        ireg[rd+id] <= ireg[rs1+irs1] + ireg[rs2+irs2];
-    if (int_vec[rd].isvector) \  \{ id += 1; \}
-    if (int_vec[rs1].isvector)\  \{ irs1 += 1; \}
-    if (int_vec[rs2].isvector) \ \{ irs2 += 1; \}
+    if (int\_vec[rd ].isvector)  \{ id += 1; \}
+    if (int\_vec[rs1].isvector)  \{ irs1 += 1; \}
+    if (int\_vec[rs2].isvector)  \{ irs2 += 1; \}
 \end{semiverbatim}
 
   \begin{itemize}
-- 
2.30.2