From fea7b9774215becbaaa58ac825b189460801fac1 Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Fri, 30 May 2014 17:29:55 -0700 Subject: [PATCH] i965: Eliminate brw_set_conditionalmod from the Gen4-5 compilers. With the predication changes eliminated, all this does is set the conditional modifier on a single instruction. Doing that directly is easy, and avoids mucking about with default state. Signed-off-by: Kenneth Graunke Reviewed-by: Matt Turner --- src/mesa/drivers/dri/i965/brw_clip_line.c | 8 ++++---- src/mesa/drivers/dri/i965/brw_clip_tri.c | 18 +++++++++--------- src/mesa/drivers/dri/i965/brw_clip_unfilled.c | 10 +++++----- src/mesa/drivers/dri/i965/brw_clip_util.c | 2 +- src/mesa/drivers/dri/i965/brw_gs_emit.c | 4 ++-- src/mesa/drivers/dri/i965/brw_sf_emit.c | 6 +++--- 6 files changed, 24 insertions(+), 24 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_clip_line.c b/src/mesa/drivers/dri/i965/brw_clip_line.c index cc5fc38329c..7e218f5c293 100644 --- a/src/mesa/drivers/dri/i965/brw_clip_line.c +++ b/src/mesa/drivers/dri/i965/brw_clip_line.c @@ -156,9 +156,9 @@ static void clip_and_emit_line( struct brw_clip_compile *c ) /* -ve rhw workaround */ if (brw->has_negative_rhw_bug) { - brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ); brw_AND(p, brw_null_reg(), get_element_ud(c->reg.R0, 2), brw_imm_ud(1<<20)); + brw_last_inst->header.destreg__conditionalmod = BRW_CONDITIONAL_NZ; brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud(0x3f)); brw_last_inst->header.predicate_control = BRW_PREDICATE_NORMAL; } @@ -176,13 +176,13 @@ static void clip_and_emit_line( struct brw_clip_compile *c ) { /* if (planemask & 1) */ - brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ); brw_AND(p, v1_null_ud, c->reg.planemask, brw_imm_ud(1)); + brw_last_inst->header.destreg__conditionalmod = BRW_CONDITIONAL_NZ; brw_IF(p, BRW_EXECUTE_1); { - brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ); brw_AND(p, v1_null_ud, c->reg.vertex_src_mask, brw_imm_ud(1)); + brw_last_inst->header.destreg__conditionalmod = BRW_CONDITIONAL_NZ; brw_IF(p, BRW_EXECUTE_1); { /* user clip distance: just fetch the correct float from each vertex */ @@ -267,8 +267,8 @@ static void clip_and_emit_line( struct brw_clip_compile *c ) /* while (planemask>>=1) != 0 */ - brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ); brw_SHR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud(1)); + brw_last_inst->header.destreg__conditionalmod = BRW_CONDITIONAL_NZ; brw_SHR(p, c->reg.vertex_src_mask, c->reg.vertex_src_mask, brw_imm_ud(1)); brw_last_inst->header.predicate_control = BRW_PREDICATE_NORMAL; brw_ADD(p, c->reg.clipdistance_offset, c->reg.clipdistance_offset, brw_imm_w(sizeof(float))); diff --git a/src/mesa/drivers/dri/i965/brw_clip_tri.c b/src/mesa/drivers/dri/i965/brw_clip_tri.c index 9118cf79e48..77cae290c65 100644 --- a/src/mesa/drivers/dri/i965/brw_clip_tri.c +++ b/src/mesa/drivers/dri/i965/brw_clip_tri.c @@ -237,8 +237,8 @@ load_clip_distance(struct brw_clip_compile *c, struct brw_indirect vtx, struct brw_compile *p = &c->func; dst = vec4(dst); - brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ); brw_AND(p, vec1(brw_null_reg()), c->reg.vertex_src_mask, brw_imm_ud(1)); + brw_last_inst->header.destreg__conditionalmod = BRW_CONDITIONAL_NZ; brw_IF(p, BRW_EXECUTE_1); { struct brw_indirect temp_ptr = brw_indirect(7, 0); @@ -293,8 +293,8 @@ void brw_clip_tri( struct brw_clip_compile *c ) { /* if (planemask & 1) */ - brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ); brw_AND(p, vec1(brw_null_reg()), c->reg.planemask, brw_imm_ud(1)); + brw_last_inst->header.destreg__conditionalmod = BRW_CONDITIONAL_NZ; brw_IF(p, BRW_EXECUTE_1); { @@ -403,8 +403,8 @@ void brw_clip_tri( struct brw_clip_compile *c ) /* while (--loopcount != 0) */ - brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ); brw_ADD(p, c->reg.loopcount, c->reg.loopcount, brw_imm_d(-1)); + brw_last_inst->header.destreg__conditionalmod = BRW_CONDITIONAL_NZ; } brw_WHILE(p); brw_last_inst->header.predicate_control = BRW_PREDICATE_NORMAL; @@ -437,8 +437,8 @@ void brw_clip_tri( struct brw_clip_compile *c ) /* && (planemask>>=1) != 0 */ - brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ); brw_SHR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud(1)); + brw_last_inst->header.destreg__conditionalmod = BRW_CONDITIONAL_NZ; brw_SHR(p, c->reg.vertex_src_mask, c->reg.vertex_src_mask, brw_imm_ud(1)); brw_ADD(p, c->reg.clipdistance_offset, c->reg.clipdistance_offset, brw_imm_w(sizeof(float))); } @@ -453,11 +453,11 @@ void brw_clip_tri_emit_polygon(struct brw_clip_compile *c) /* for (loopcount = nr_verts-2; loopcount > 0; loopcount--) */ - brw_set_conditionalmod(p, BRW_CONDITIONAL_G); brw_ADD(p, c->reg.loopcount, c->reg.nr_verts, brw_imm_d(-2)); + brw_last_inst->header.destreg__conditionalmod = BRW_CONDITIONAL_G; brw_IF(p, BRW_EXECUTE_1); { @@ -482,8 +482,8 @@ void brw_clip_tri_emit_polygon(struct brw_clip_compile *c) brw_ADD(p, get_addr_reg(vptr), get_addr_reg(vptr), brw_imm_uw(2)); brw_MOV(p, get_addr_reg(v0), deref_1uw(vptr, 0)); - brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ); brw_ADD(p, c->reg.loopcount, c->reg.loopcount, brw_imm_d(-1)); + brw_last_inst->header.destreg__conditionalmod = BRW_CONDITIONAL_NZ; } brw_WHILE(p); brw_last_inst->header.predicate_control = BRW_PREDICATE_NORMAL; @@ -555,8 +555,8 @@ static void brw_clip_test( struct brw_clip_compile *c ) brw_AND(p, t, t, t3); brw_OR(p, tmp0, get_element(t, 0), get_element(t, 1)); brw_OR(p, tmp0, tmp0, get_element(t, 2)); - brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ); brw_AND(p, brw_null_reg(), tmp0, brw_imm_ud(0x1)); + brw_last_inst->header.destreg__conditionalmod = BRW_CONDITIONAL_NZ; brw_IF(p, BRW_EXECUTE_1); { brw_clip_kill_thread(c); @@ -593,8 +593,8 @@ static void brw_clip_test( struct brw_clip_compile *c ) brw_AND(p, t, t, t3); brw_OR(p, tmp0, get_element(t, 0), get_element(t, 1)); brw_OR(p, tmp0, tmp0, get_element(t, 2)); - brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ); brw_AND(p, brw_null_reg(), tmp0, brw_imm_ud(0x1)); + brw_last_inst->header.destreg__conditionalmod = BRW_CONDITIONAL_NZ; brw_IF(p, BRW_EXECUTE_1); { brw_clip_kill_thread(c); @@ -636,9 +636,9 @@ void brw_emit_tri_clip( struct brw_clip_compile *c ) /* if -ve rhw workaround bit is set, do cliptest */ if (brw->has_negative_rhw_bug) { - brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ); brw_AND(p, brw_null_reg(), get_element_ud(c->reg.R0, 2), brw_imm_ud(1<<20)); + brw_last_inst->header.destreg__conditionalmod = BRW_CONDITIONAL_NZ; brw_IF(p, BRW_EXECUTE_1); { brw_clip_test(c); diff --git a/src/mesa/drivers/dri/i965/brw_clip_unfilled.c b/src/mesa/drivers/dri/i965/brw_clip_unfilled.c index d8deaa49ef3..302fdc4bbe8 100644 --- a/src/mesa/drivers/dri/i965/brw_clip_unfilled.c +++ b/src/mesa/drivers/dri/i965/brw_clip_unfilled.c @@ -231,16 +231,16 @@ static void merge_edgeflags( struct brw_clip_compile *c ) */ brw_IF(p, BRW_EXECUTE_1); { - brw_set_conditionalmod(p, BRW_CONDITIONAL_EQ); brw_AND(p, vec1(brw_null_reg()), get_element_ud(c->reg.R0, 2), brw_imm_ud(1<<8)); + brw_last_inst->header.destreg__conditionalmod = BRW_CONDITIONAL_EQ; brw_MOV(p, byte_offset(c->reg.vertex[0], brw_varying_to_offset(&c->vue_map, VARYING_SLOT_EDGE)), brw_imm_f(0)); brw_last_inst->header.predicate_control = BRW_PREDICATE_NORMAL; - brw_set_conditionalmod(p, BRW_CONDITIONAL_EQ); brw_AND(p, vec1(brw_null_reg()), get_element_ud(c->reg.R0, 2), brw_imm_ud(1<<9)); + brw_last_inst->header.destreg__conditionalmod = BRW_CONDITIONAL_EQ; brw_MOV(p, byte_offset(c->reg.vertex[2], brw_varying_to_offset(&c->vue_map, VARYING_SLOT_EDGE)), @@ -291,8 +291,8 @@ static void emit_lines(struct brw_clip_compile *c, apply_one_offset(c, v0); - brw_set_conditionalmod(p, BRW_CONDITIONAL_G); brw_ADD(p, c->reg.loopcount, c->reg.loopcount, brw_imm_d(-1)); + brw_last_inst->header.destreg__conditionalmod = BRW_CONDITIONAL_G; } brw_WHILE(p); brw_last_inst->header.predicate_control = BRW_PREDICATE_NORMAL; @@ -330,8 +330,8 @@ static void emit_lines(struct brw_clip_compile *c, } brw_ENDIF(p); - brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ); brw_ADD(p, c->reg.loopcount, c->reg.loopcount, brw_imm_d(-1)); + brw_last_inst->header.destreg__conditionalmod = BRW_CONDITIONAL_NZ; } brw_WHILE(p); brw_last_inst->header.predicate_control = BRW_PREDICATE_NORMAL; @@ -373,8 +373,8 @@ static void emit_points(struct brw_clip_compile *c, } brw_ENDIF(p); - brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ); brw_ADD(p, c->reg.loopcount, c->reg.loopcount, brw_imm_d(-1)); + brw_last_inst->header.destreg__conditionalmod = BRW_CONDITIONAL_NZ; } brw_WHILE(p); brw_last_inst->header.predicate_control = BRW_PREDICATE_NORMAL; diff --git a/src/mesa/drivers/dri/i965/brw_clip_util.c b/src/mesa/drivers/dri/i965/brw_clip_util.c index 10ec2667067..239a04acee9 100644 --- a/src/mesa/drivers/dri/i965/brw_clip_util.c +++ b/src/mesa/drivers/dri/i965/brw_clip_util.c @@ -447,8 +447,8 @@ void brw_clip_ff_sync(struct brw_clip_compile *c) struct brw_context *brw = p->brw; if (brw->gen == 5) { - brw_set_conditionalmod(p, BRW_CONDITIONAL_Z); brw_AND(p, brw_null_reg(), c->reg.ff_sync, brw_imm_ud(0x1)); + brw_last_inst->header.destreg__conditionalmod = BRW_CONDITIONAL_Z; brw_IF(p, BRW_EXECUTE_1); { brw_OR(p, c->reg.ff_sync, c->reg.ff_sync, brw_imm_ud(0x1)); diff --git a/src/mesa/drivers/dri/i965/brw_gs_emit.c b/src/mesa/drivers/dri/i965/brw_gs_emit.c index f74ac6891e6..58b9d86c114 100644 --- a/src/mesa/drivers/dri/i965/brw_gs_emit.c +++ b/src/mesa/drivers/dri/i965/brw_gs_emit.c @@ -498,10 +498,10 @@ gen6_sol_program(struct brw_ff_gs_compile *c, struct brw_ff_gs_prog_key *key, /* Only emit vertices 0 and 1 if this is the first triangle of the * polygon. Otherwise they are redundant. */ - brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ); brw_AND(p, retype(brw_null_reg(), BRW_REGISTER_TYPE_UD), get_element_ud(c->reg.R0, 2), brw_imm_ud(BRW_GS_EDGE_INDICATOR_0)); + brw_last_inst->header.destreg__conditionalmod = BRW_CONDITIONAL_NZ; brw_IF(p, BRW_EXECUTE_1); } brw_ff_gs_offset_header_dw2(c, URB_WRITE_PRIM_START); @@ -514,10 +514,10 @@ gen6_sol_program(struct brw_ff_gs_compile *c, struct brw_ff_gs_prog_key *key, * of the polygon. Otherwise leave the primitive incomplete because * there are more polygon vertices coming. */ - brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ); brw_AND(p, retype(brw_null_reg(), BRW_REGISTER_TYPE_UD), get_element_ud(c->reg.R0, 2), brw_imm_ud(BRW_GS_EDGE_INDICATOR_1)); + brw_last_inst->header.destreg__conditionalmod = BRW_CONDITIONAL_NZ; brw_set_predicate_control(p, BRW_PREDICATE_NORMAL); } brw_ff_gs_offset_header_dw2(c, URB_WRITE_PRIM_END); diff --git a/src/mesa/drivers/dri/i965/brw_sf_emit.c b/src/mesa/drivers/dri/i965/brw_sf_emit.c index 479d6d57105..8897596a80b 100644 --- a/src/mesa/drivers/dri/i965/brw_sf_emit.c +++ b/src/mesa/drivers/dri/i965/brw_sf_emit.c @@ -762,7 +762,6 @@ void brw_emit_anyprim_setup( struct brw_sf_compile *c ) brw_MOV(p, primmask, brw_imm_ud(1)); brw_SHL(p, primmask, primmask, payload_prim); - brw_set_conditionalmod(p, BRW_CONDITIONAL_Z); brw_AND(p, v1_null_ud, primmask, brw_imm_ud((1<<_3DPRIM_TRILIST) | (1<<_3DPRIM_TRISTRIP) | (1<<_3DPRIM_TRIFAN) | @@ -770,23 +769,24 @@ void brw_emit_anyprim_setup( struct brw_sf_compile *c ) (1<<_3DPRIM_POLYGON) | (1<<_3DPRIM_RECTLIST) | (1<<_3DPRIM_TRIFAN_NOSTIPPLE))); + brw_last_inst->header.destreg__conditionalmod = BRW_CONDITIONAL_Z; jmp = brw_JMPI(p, brw_imm_d(0), BRW_PREDICATE_NORMAL) - p->store; brw_emit_tri_setup(c, false); brw_land_fwd_jump(p, jmp); - brw_set_conditionalmod(p, BRW_CONDITIONAL_Z); brw_AND(p, v1_null_ud, primmask, brw_imm_ud((1<<_3DPRIM_LINELIST) | (1<<_3DPRIM_LINESTRIP) | (1<<_3DPRIM_LINELOOP) | (1<<_3DPRIM_LINESTRIP_CONT) | (1<<_3DPRIM_LINESTRIP_BF) | (1<<_3DPRIM_LINESTRIP_CONT_BF))); + brw_last_inst->header.destreg__conditionalmod = BRW_CONDITIONAL_Z; jmp = brw_JMPI(p, brw_imm_d(0), BRW_PREDICATE_NORMAL) - p->store; brw_emit_line_setup(c, false); brw_land_fwd_jump(p, jmp); - brw_set_conditionalmod(p, BRW_CONDITIONAL_Z); brw_AND(p, v1_null_ud, payload_attr, brw_imm_ud(1<header.destreg__conditionalmod = BRW_CONDITIONAL_Z; jmp = brw_JMPI(p, brw_imm_d(0), BRW_PREDICATE_NORMAL) - p->store; brw_emit_point_sprite_setup(c, false); brw_land_fwd_jump(p, jmp); -- 2.30.2