From feb4fc23d6dbe1a3f5fde3dabcca5aa24a65deff Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 25 Nov 2018 06:23:36 +0000 Subject: [PATCH] minor reorg, add alu --- cpu.py | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/cpu.py b/cpu.py index 4e769f9..a7e3ab3 100644 --- a/cpu.py +++ b/cpu.py @@ -264,6 +264,17 @@ class CPU(Module): register_rs2, dc.immediate)) + ali = Instance("cpu_alu", name="alu", + i_funct7 = dc.funct7, + i_funct3 = dc.funct3, + i_opcode = dc.opcode, + i_a = alu_a, + i_b = alu_b, + o_result = alu_result + ) + self.specials += ali + + if __name__ == "__main__": example = CPU() print(verilog.convert(example, @@ -279,15 +290,6 @@ if __name__ == "__main__": """ - cpu_alu alu( - .funct7(decoder_funct7), - .funct3(decoder_funct3), - .opcode(decoder_opcode), - .a(alu_a), - .b(alu_b), - .result(alu_result) - ); - wire [31:0] lui_auipc_result = decoder_opcode[5] ? decoder_immediate : decoder_immediate + fetch_output_pc; assign fetch_target_pc[31:1] = ((decoder_opcode != `opcode_jalr ? fetch_output_pc[31:1] : register_rs1[31:1]) + decoder_immediate[31:1]); -- 2.30.2