From fede68ebc8eb2130201d75fcefb1a2ab2a9b6812 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 30 Nov 2021 11:49:33 +0000 Subject: [PATCH] move sim call before core run in test_core.py to give PC a chance to settle in regfile --- src/soc/simple/test/test_core.py | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py index 14354873..0c1be141 100644 --- a/src/soc/simple/test/test_core.py +++ b/src/soc/simple/test/test_core.py @@ -278,18 +278,6 @@ class TestRunner(FHDLTestCase): # ask the decoder to decode this binary data (endian'd) yield instruction.eq(ins) # raw binary instr. yield Settle() - yield core.p.i_valid.eq(1) - yield - o_ready = yield core.p.o_ready - while True: - if o_ready: - break - yield - o_ready = yield core.p.o_ready - yield core.p.i_valid.eq(0) - - # set operand and get inputs - yield from wait_for_busy_clear(core) print("sim", code) # call simulated operation @@ -306,6 +294,19 @@ class TestRunner(FHDLTestCase): yield stateregs.regs[pc_regnum].reg.eq(pc) yield Settle() + yield core.p.i_valid.eq(1) + yield + o_ready = yield core.p.o_ready + while True: + if o_ready: + break + yield + o_ready = yield core.p.o_ready + yield core.p.i_valid.eq(0) + + # set operand and get inputs + yield from wait_for_busy_clear(core) + # register check yield from check_regs(self, sim, core, test, code) -- 2.30.2