From feee3050d389697ccb56c8caa847ae8694e2251b Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Wed, 14 Nov 2018 15:20:13 -0500 Subject: [PATCH] freedreno/ir3: split out a4xx+ instructions Note that image/ssbo support is currently only implemented for a5xx. But the instruction encoding is the same for a4xx. Signed-off-by: Rob Clark --- src/freedreno/Makefile.sources | 1 + src/freedreno/ir3/ir3.h | 8 +- src/freedreno/ir3/ir3_a4xx.c | 366 +++++++++++++++++++++++++++ src/freedreno/ir3/ir3_compiler_nir.c | 334 +----------------------- src/freedreno/ir3/ir3_context.c | 4 + src/freedreno/ir3/ir3_context.h | 12 + src/freedreno/ir3/meson.build | 1 + 7 files changed, 394 insertions(+), 332 deletions(-) create mode 100644 src/freedreno/ir3/ir3_a4xx.c diff --git a/src/freedreno/Makefile.sources b/src/freedreno/Makefile.sources index 36841a98fe4..2d83f70f13e 100644 --- a/src/freedreno/Makefile.sources +++ b/src/freedreno/Makefile.sources @@ -19,6 +19,7 @@ ir3_SOURCES := \ ir3/disasm-a3xx.c \ ir3/instr-a3xx.h \ ir3/ir3.c \ + ir3/ir3_a4xx.c \ ir3/ir3_compiler.c \ ir3/ir3_compiler.h \ ir3/ir3_compiler_nir.c \ diff --git a/src/freedreno/ir3/ir3.h b/src/freedreno/ir3/ir3.h index 742b649d011..deede024dee 100644 --- a/src/freedreno/ir3/ir3.h +++ b/src/freedreno/ir3/ir3.h @@ -1325,9 +1325,6 @@ INSTR2(LDG) INSTR2(LDL) INSTR3(STG) INSTR3(STL) -INSTR3(LDGB) -INSTR4(STGB) -INSTR4(STIB) INSTR1(RESINFO) INSTR1(RESFMT) INSTR2(ATOMIC_ADD) @@ -1341,6 +1338,10 @@ INSTR2(ATOMIC_MAX) INSTR2(ATOMIC_AND) INSTR2(ATOMIC_OR) INSTR2(ATOMIC_XOR) +#if GPU >= 400 +INSTR3(LDGB) +INSTR4(STGB) +INSTR4(STIB) INSTR4F(G, ATOMIC_ADD) INSTR4F(G, ATOMIC_SUB) INSTR4F(G, ATOMIC_XCHG) @@ -1352,6 +1353,7 @@ INSTR4F(G, ATOMIC_MAX) INSTR4F(G, ATOMIC_AND) INSTR4F(G, ATOMIC_OR) INSTR4F(G, ATOMIC_XOR) +#endif /* cat7 instructions: */ INSTR0(BAR) diff --git a/src/freedreno/ir3/ir3_a4xx.c b/src/freedreno/ir3/ir3_a4xx.c new file mode 100644 index 00000000000..a327a5c9f29 --- /dev/null +++ b/src/freedreno/ir3/ir3_a4xx.c @@ -0,0 +1,366 @@ +/* + * Copyright (C) 2017-2018 Rob Clark + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Authors: + * Rob Clark + */ + +#define GPU 400 + +#include "ir3_context.h" +#include "ir3_image.h" + +/* + * Handlers for instructions changed/added in a4xx: + */ + + +/* src[] = { buffer_index, offset }. No const_index */ +static void +emit_intrinsic_load_ssbo(struct ir3_context *ctx, nir_intrinsic_instr *intr, + struct ir3_instruction **dst) +{ + struct ir3_block *b = ctx->block; + struct ir3_instruction *ldgb, *src0, *src1, *offset; + nir_const_value *const_offset; + + /* can this be non-const buffer_index? how do we handle that? */ + const_offset = nir_src_as_const_value(intr->src[0]); + compile_assert(ctx, const_offset); + + offset = ir3_get_src(ctx, &intr->src[1])[0]; + + /* src0 is uvec2(offset*4, 0), src1 is offset.. nir already *= 4: */ + src0 = ir3_create_collect(ctx, (struct ir3_instruction*[]){ + offset, + create_immed(b, 0), + }, 2); + src1 = ir3_SHR_B(b, offset, 0, create_immed(b, 2), 0); + + ldgb = ir3_LDGB(b, create_immed(b, const_offset->u32[0]), 0, + src0, 0, src1, 0); + ldgb->regs[0]->wrmask = MASK(intr->num_components); + ldgb->cat6.iim_val = intr->num_components; + ldgb->cat6.d = 4; + ldgb->cat6.type = TYPE_U32; + ldgb->barrier_class = IR3_BARRIER_BUFFER_R; + ldgb->barrier_conflict = IR3_BARRIER_BUFFER_W; + + ir3_split_dest(b, dst, ldgb, 0, intr->num_components); +} + +/* src[] = { value, block_index, offset }. const_index[] = { write_mask } */ +static void +emit_intrinsic_store_ssbo(struct ir3_context *ctx, nir_intrinsic_instr *intr) +{ + struct ir3_block *b = ctx->block; + struct ir3_instruction *stgb, *src0, *src1, *src2, *offset; + nir_const_value *const_offset; + /* TODO handle wrmask properly, see _store_shared().. but I think + * it is more a PITA than that, since blob ends up loading the + * masked components and writing them back out. + */ + unsigned wrmask = intr->const_index[0]; + unsigned ncomp = ffs(~wrmask) - 1; + + /* can this be non-const buffer_index? how do we handle that? */ + const_offset = nir_src_as_const_value(intr->src[1]); + compile_assert(ctx, const_offset); + + offset = ir3_get_src(ctx, &intr->src[2])[0]; + + /* src0 is value, src1 is offset, src2 is uvec2(offset*4, 0).. + * nir already *= 4: + */ + src0 = ir3_create_collect(ctx, ir3_get_src(ctx, &intr->src[0]), ncomp); + src1 = ir3_SHR_B(b, offset, 0, create_immed(b, 2), 0); + src2 = ir3_create_collect(ctx, (struct ir3_instruction*[]){ + offset, + create_immed(b, 0), + }, 2); + + stgb = ir3_STGB(b, create_immed(b, const_offset->u32[0]), 0, + src0, 0, src1, 0, src2, 0); + stgb->cat6.iim_val = ncomp; + stgb->cat6.d = 4; + stgb->cat6.type = TYPE_U32; + stgb->barrier_class = IR3_BARRIER_BUFFER_W; + stgb->barrier_conflict = IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W; + + array_insert(b, b->keeps, stgb); +} + +/* + * SSBO atomic intrinsics + * + * All of the SSBO atomic memory operations read a value from memory, + * compute a new value using one of the operations below, write the new + * value to memory, and return the original value read. + * + * All operations take 3 sources except CompSwap that takes 4. These + * sources represent: + * + * 0: The SSBO buffer index. + * 1: The offset into the SSBO buffer of the variable that the atomic + * operation will operate on. + * 2: The data parameter to the atomic function (i.e. the value to add + * in ssbo_atomic_add, etc). + * 3: For CompSwap only: the second data parameter. + */ +static struct ir3_instruction * +emit_intrinsic_atomic_ssbo(struct ir3_context *ctx, nir_intrinsic_instr *intr) +{ + struct ir3_block *b = ctx->block; + struct ir3_instruction *atomic, *ssbo, *src0, *src1, *src2, *offset; + nir_const_value *const_offset; + type_t type = TYPE_U32; + + /* can this be non-const buffer_index? how do we handle that? */ + const_offset = nir_src_as_const_value(intr->src[0]); + compile_assert(ctx, const_offset); + ssbo = create_immed(b, const_offset->u32[0]); + + offset = ir3_get_src(ctx, &intr->src[1])[0]; + + /* src0 is data (or uvec2(data, compare)) + * src1 is offset + * src2 is uvec2(offset*4, 0) (appears to be 64b byte offset) + * + * Note that nir already multiplies the offset by four + */ + src0 = ir3_get_src(ctx, &intr->src[2])[0]; + src1 = ir3_SHR_B(b, offset, 0, create_immed(b, 2), 0); + src2 = ir3_create_collect(ctx, (struct ir3_instruction*[]){ + offset, + create_immed(b, 0), + }, 2); + + switch (intr->intrinsic) { + case nir_intrinsic_ssbo_atomic_add: + atomic = ir3_ATOMIC_ADD_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0); + break; + case nir_intrinsic_ssbo_atomic_imin: + atomic = ir3_ATOMIC_MIN_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0); + type = TYPE_S32; + break; + case nir_intrinsic_ssbo_atomic_umin: + atomic = ir3_ATOMIC_MIN_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0); + break; + case nir_intrinsic_ssbo_atomic_imax: + atomic = ir3_ATOMIC_MAX_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0); + type = TYPE_S32; + break; + case nir_intrinsic_ssbo_atomic_umax: + atomic = ir3_ATOMIC_MAX_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0); + break; + case nir_intrinsic_ssbo_atomic_and: + atomic = ir3_ATOMIC_AND_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0); + break; + case nir_intrinsic_ssbo_atomic_or: + atomic = ir3_ATOMIC_OR_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0); + break; + case nir_intrinsic_ssbo_atomic_xor: + atomic = ir3_ATOMIC_XOR_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0); + break; + case nir_intrinsic_ssbo_atomic_exchange: + atomic = ir3_ATOMIC_XCHG_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0); + break; + case nir_intrinsic_ssbo_atomic_comp_swap: + /* for cmpxchg, src0 is [ui]vec2(data, compare): */ + src0 = ir3_create_collect(ctx, (struct ir3_instruction*[]){ + ir3_get_src(ctx, &intr->src[3])[0], + src0, + }, 2); + atomic = ir3_ATOMIC_CMPXCHG_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0); + break; + default: + unreachable("boo"); + } + + atomic->cat6.iim_val = 1; + atomic->cat6.d = 4; + atomic->cat6.type = type; + atomic->barrier_class = IR3_BARRIER_BUFFER_W; + atomic->barrier_conflict = IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W; + + /* even if nothing consume the result, we can't DCE the instruction: */ + array_insert(b, b->keeps, atomic); + + return atomic; +} + +static struct ir3_instruction * +get_image_offset(struct ir3_context *ctx, const nir_variable *var, + struct ir3_instruction * const *coords, bool byteoff) +{ + struct ir3_block *b = ctx->block; + struct ir3_instruction *offset; + unsigned ncoords = ir3_get_image_coords(var, NULL); + + /* to calculate the byte offset (yes, uggg) we need (up to) three + * const values to know the bytes per pixel, and y and z stride: + */ + unsigned cb = regid(ctx->so->constbase.image_dims, 0) + + ctx->so->const_layout.image_dims.off[var->data.driver_location]; + + debug_assert(ctx->so->const_layout.image_dims.mask & + (1 << var->data.driver_location)); + + /* offset = coords.x * bytes_per_pixel: */ + offset = ir3_MUL_S(b, coords[0], 0, create_uniform(b, cb + 0), 0); + if (ncoords > 1) { + /* offset += coords.y * y_pitch: */ + offset = ir3_MAD_S24(b, create_uniform(b, cb + 1), 0, + coords[1], 0, offset, 0); + } + if (ncoords > 2) { + /* offset += coords.z * z_pitch: */ + offset = ir3_MAD_S24(b, create_uniform(b, cb + 2), 0, + coords[2], 0, offset, 0); + } + + if (!byteoff) { + /* Some cases, like atomics, seem to use dword offset instead + * of byte offsets.. blob just puts an extra shr.b in there + * in those cases: + */ + offset = ir3_SHR_B(b, offset, 0, create_immed(b, 2), 0); + } + + return ir3_create_collect(ctx, (struct ir3_instruction*[]){ + offset, + create_immed(b, 0), + }, 2); +} + +/* src[] = { deref, coord, sample_index, value }. const_index[] = {} */ +static void +emit_intrinsic_store_image(struct ir3_context *ctx, nir_intrinsic_instr *intr) +{ + struct ir3_block *b = ctx->block; + const nir_variable *var = nir_intrinsic_get_var(intr, 0); + struct ir3_instruction *stib, *offset; + struct ir3_instruction * const *value = ir3_get_src(ctx, &intr->src[3]); + struct ir3_instruction * const *coords = ir3_get_src(ctx, &intr->src[1]); + unsigned ncoords = ir3_get_image_coords(var, NULL); + unsigned tex_idx = ir3_get_image_slot(ctx, nir_src_as_deref(intr->src[0])); + + /* src0 is value + * src1 is coords + * src2 is 64b byte offset + */ + + offset = get_image_offset(ctx, var, coords, true); + + /* NOTE: stib seems to take byte offset, but stgb.typed can be used + * too and takes a dword offset.. not quite sure yet why blob uses + * one over the other in various cases. + */ + + stib = ir3_STIB(b, create_immed(b, tex_idx), 0, + ir3_create_collect(ctx, value, 4), 0, + ir3_create_collect(ctx, coords, ncoords), 0, + offset, 0); + stib->cat6.iim_val = 4; + stib->cat6.d = ncoords; + stib->cat6.type = ir3_get_image_type(var); + stib->cat6.typed = true; + stib->barrier_class = IR3_BARRIER_IMAGE_W; + stib->barrier_conflict = IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W; + + array_insert(b, b->keeps, stib); +} + +/* src[] = { deref, coord, sample_index, value, compare }. const_index[] = {} */ +static struct ir3_instruction * +emit_intrinsic_atomic_image(struct ir3_context *ctx, nir_intrinsic_instr *intr) +{ + struct ir3_block *b = ctx->block; + const nir_variable *var = nir_intrinsic_get_var(intr, 0); + struct ir3_instruction *atomic, *image, *src0, *src1, *src2; + struct ir3_instruction * const *coords = ir3_get_src(ctx, &intr->src[1]); + unsigned ncoords = ir3_get_image_coords(var, NULL); + + image = create_immed(b, ir3_get_image_slot(ctx, nir_src_as_deref(intr->src[0]))); + + /* src0 is value (or uvec2(value, compare)) + * src1 is coords + * src2 is 64b byte offset + */ + src0 = ir3_get_src(ctx, &intr->src[3])[0]; + src1 = ir3_create_collect(ctx, coords, ncoords); + src2 = get_image_offset(ctx, var, coords, false); + + switch (intr->intrinsic) { + case nir_intrinsic_image_deref_atomic_add: + atomic = ir3_ATOMIC_ADD_G(b, image, 0, src0, 0, src1, 0, src2, 0); + break; + case nir_intrinsic_image_deref_atomic_min: + atomic = ir3_ATOMIC_MIN_G(b, image, 0, src0, 0, src1, 0, src2, 0); + break; + case nir_intrinsic_image_deref_atomic_max: + atomic = ir3_ATOMIC_MAX_G(b, image, 0, src0, 0, src1, 0, src2, 0); + break; + case nir_intrinsic_image_deref_atomic_and: + atomic = ir3_ATOMIC_AND_G(b, image, 0, src0, 0, src1, 0, src2, 0); + break; + case nir_intrinsic_image_deref_atomic_or: + atomic = ir3_ATOMIC_OR_G(b, image, 0, src0, 0, src1, 0, src2, 0); + break; + case nir_intrinsic_image_deref_atomic_xor: + atomic = ir3_ATOMIC_XOR_G(b, image, 0, src0, 0, src1, 0, src2, 0); + break; + case nir_intrinsic_image_deref_atomic_exchange: + atomic = ir3_ATOMIC_XCHG_G(b, image, 0, src0, 0, src1, 0, src2, 0); + break; + case nir_intrinsic_image_deref_atomic_comp_swap: + /* for cmpxchg, src0 is [ui]vec2(data, compare): */ + src0 = ir3_create_collect(ctx, (struct ir3_instruction*[]){ + ir3_get_src(ctx, &intr->src[4])[0], + src0, + }, 2); + atomic = ir3_ATOMIC_CMPXCHG_G(b, image, 0, src0, 0, src1, 0, src2, 0); + break; + default: + unreachable("boo"); + } + + atomic->cat6.iim_val = 1; + atomic->cat6.d = ncoords; + atomic->cat6.type = ir3_get_image_type(var); + atomic->cat6.typed = true; + atomic->barrier_class = IR3_BARRIER_IMAGE_W; + atomic->barrier_conflict = IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W; + + /* even if nothing consume the result, we can't DCE the instruction: */ + array_insert(b, b->keeps, atomic); + + return atomic; +} + +const struct ir3_context_funcs ir3_a4xx_funcs = { + .emit_intrinsic_load_ssbo = emit_intrinsic_load_ssbo, + .emit_intrinsic_store_ssbo = emit_intrinsic_store_ssbo, + .emit_intrinsic_atomic_ssbo = emit_intrinsic_atomic_ssbo, + .emit_intrinsic_store_image = emit_intrinsic_store_image, + .emit_intrinsic_atomic_image = emit_intrinsic_atomic_image, +}; diff --git a/src/freedreno/ir3/ir3_compiler_nir.c b/src/freedreno/ir3/ir3_compiler_nir.c index 4aa0015866e..f4745ec83bd 100644 --- a/src/freedreno/ir3/ir3_compiler_nir.c +++ b/src/freedreno/ir3/ir3_compiler_nir.c @@ -724,81 +724,6 @@ emit_intrinsic_load_ubo(struct ir3_context *ctx, nir_intrinsic_instr *intr, } } -/* src[] = { buffer_index, offset }. No const_index */ -static void -emit_intrinsic_load_ssbo(struct ir3_context *ctx, nir_intrinsic_instr *intr, - struct ir3_instruction **dst) -{ - struct ir3_block *b = ctx->block; - struct ir3_instruction *ldgb, *src0, *src1, *offset; - nir_const_value *const_offset; - - /* can this be non-const buffer_index? how do we handle that? */ - const_offset = nir_src_as_const_value(intr->src[0]); - compile_assert(ctx, const_offset); - - offset = ir3_get_src(ctx, &intr->src[1])[0]; - - /* src0 is uvec2(offset*4, 0), src1 is offset.. nir already *= 4: */ - src0 = ir3_create_collect(ctx, (struct ir3_instruction*[]){ - offset, - create_immed(b, 0), - }, 2); - src1 = ir3_SHR_B(b, offset, 0, create_immed(b, 2), 0); - - ldgb = ir3_LDGB(b, create_immed(b, const_offset->u32[0]), 0, - src0, 0, src1, 0); - ldgb->regs[0]->wrmask = MASK(intr->num_components); - ldgb->cat6.iim_val = intr->num_components; - ldgb->cat6.d = 4; - ldgb->cat6.type = TYPE_U32; - ldgb->barrier_class = IR3_BARRIER_BUFFER_R; - ldgb->barrier_conflict = IR3_BARRIER_BUFFER_W; - - ir3_split_dest(b, dst, ldgb, 0, intr->num_components); -} - -/* src[] = { value, block_index, offset }. const_index[] = { write_mask } */ -static void -emit_intrinsic_store_ssbo(struct ir3_context *ctx, nir_intrinsic_instr *intr) -{ - struct ir3_block *b = ctx->block; - struct ir3_instruction *stgb, *src0, *src1, *src2, *offset; - nir_const_value *const_offset; - /* TODO handle wrmask properly, see _store_shared().. but I think - * it is more a PITA than that, since blob ends up loading the - * masked components and writing them back out. - */ - unsigned wrmask = intr->const_index[0]; - unsigned ncomp = ffs(~wrmask) - 1; - - /* can this be non-const buffer_index? how do we handle that? */ - const_offset = nir_src_as_const_value(intr->src[1]); - compile_assert(ctx, const_offset); - - offset = ir3_get_src(ctx, &intr->src[2])[0]; - - /* src0 is value, src1 is offset, src2 is uvec2(offset*4, 0).. - * nir already *= 4: - */ - src0 = ir3_create_collect(ctx, ir3_get_src(ctx, &intr->src[0]), ncomp); - src1 = ir3_SHR_B(b, offset, 0, create_immed(b, 2), 0); - src2 = ir3_create_collect(ctx, (struct ir3_instruction*[]){ - offset, - create_immed(b, 0), - }, 2); - - stgb = ir3_STGB(b, create_immed(b, const_offset->u32[0]), 0, - src0, 0, src1, 0, src2, 0); - stgb->cat6.iim_val = ncomp; - stgb->cat6.d = 4; - stgb->cat6.type = TYPE_U32; - stgb->barrier_class = IR3_BARRIER_BUFFER_W; - stgb->barrier_conflict = IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W; - - array_insert(b, b->keeps, stgb); -} - /* src[] = { block_index } */ static void emit_intrinsic_ssbo_size(struct ir3_context *ctx, nir_intrinsic_instr *intr, @@ -814,105 +739,6 @@ emit_intrinsic_ssbo_size(struct ir3_context *ctx, nir_intrinsic_instr *intr, dst[0] = create_uniform(ctx->block, idx); } -/* - * SSBO atomic intrinsics - * - * All of the SSBO atomic memory operations read a value from memory, - * compute a new value using one of the operations below, write the new - * value to memory, and return the original value read. - * - * All operations take 3 sources except CompSwap that takes 4. These - * sources represent: - * - * 0: The SSBO buffer index. - * 1: The offset into the SSBO buffer of the variable that the atomic - * operation will operate on. - * 2: The data parameter to the atomic function (i.e. the value to add - * in ssbo_atomic_add, etc). - * 3: For CompSwap only: the second data parameter. - */ -static struct ir3_instruction * -emit_intrinsic_atomic_ssbo(struct ir3_context *ctx, nir_intrinsic_instr *intr) -{ - struct ir3_block *b = ctx->block; - struct ir3_instruction *atomic, *ssbo, *src0, *src1, *src2, *offset; - nir_const_value *const_offset; - type_t type = TYPE_U32; - - /* can this be non-const buffer_index? how do we handle that? */ - const_offset = nir_src_as_const_value(intr->src[0]); - compile_assert(ctx, const_offset); - ssbo = create_immed(b, const_offset->u32[0]); - - offset = ir3_get_src(ctx, &intr->src[1])[0]; - - /* src0 is data (or uvec2(data, compare)) - * src1 is offset - * src2 is uvec2(offset*4, 0) (appears to be 64b byte offset) - * - * Note that nir already multiplies the offset by four - */ - src0 = ir3_get_src(ctx, &intr->src[2])[0]; - src1 = ir3_SHR_B(b, offset, 0, create_immed(b, 2), 0); - src2 = ir3_create_collect(ctx, (struct ir3_instruction*[]){ - offset, - create_immed(b, 0), - }, 2); - - switch (intr->intrinsic) { - case nir_intrinsic_ssbo_atomic_add: - atomic = ir3_ATOMIC_ADD_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0); - break; - case nir_intrinsic_ssbo_atomic_imin: - atomic = ir3_ATOMIC_MIN_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0); - type = TYPE_S32; - break; - case nir_intrinsic_ssbo_atomic_umin: - atomic = ir3_ATOMIC_MIN_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0); - break; - case nir_intrinsic_ssbo_atomic_imax: - atomic = ir3_ATOMIC_MAX_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0); - type = TYPE_S32; - break; - case nir_intrinsic_ssbo_atomic_umax: - atomic = ir3_ATOMIC_MAX_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0); - break; - case nir_intrinsic_ssbo_atomic_and: - atomic = ir3_ATOMIC_AND_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0); - break; - case nir_intrinsic_ssbo_atomic_or: - atomic = ir3_ATOMIC_OR_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0); - break; - case nir_intrinsic_ssbo_atomic_xor: - atomic = ir3_ATOMIC_XOR_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0); - break; - case nir_intrinsic_ssbo_atomic_exchange: - atomic = ir3_ATOMIC_XCHG_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0); - break; - case nir_intrinsic_ssbo_atomic_comp_swap: - /* for cmpxchg, src0 is [ui]vec2(data, compare): */ - src0 = ir3_create_collect(ctx, (struct ir3_instruction*[]){ - ir3_get_src(ctx, &intr->src[3])[0], - src0, - }, 2); - atomic = ir3_ATOMIC_CMPXCHG_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0); - break; - default: - unreachable("boo"); - } - - atomic->cat6.iim_val = 1; - atomic->cat6.d = 4; - atomic->cat6.type = type; - atomic->barrier_class = IR3_BARRIER_BUFFER_W; - atomic->barrier_conflict = IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W; - - /* even if nothing consume the result, we can't DCE the instruction: */ - array_insert(b, b->keeps, atomic); - - return atomic; -} - /* src[] = { offset }. const_index[] = { base } */ static void emit_intrinsic_load_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr, @@ -1059,50 +885,6 @@ emit_intrinsic_atomic_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr) return atomic; } -static struct ir3_instruction * -get_image_offset(struct ir3_context *ctx, const nir_variable *var, - struct ir3_instruction * const *coords, bool byteoff) -{ - struct ir3_block *b = ctx->block; - struct ir3_instruction *offset; - unsigned ncoords = ir3_get_image_coords(var, NULL); - - /* to calculate the byte offset (yes, uggg) we need (up to) three - * const values to know the bytes per pixel, and y and z stride: - */ - unsigned cb = regid(ctx->so->constbase.image_dims, 0) + - ctx->so->const_layout.image_dims.off[var->data.driver_location]; - - debug_assert(ctx->so->const_layout.image_dims.mask & - (1 << var->data.driver_location)); - - /* offset = coords.x * bytes_per_pixel: */ - offset = ir3_MUL_S(b, coords[0], 0, create_uniform(b, cb + 0), 0); - if (ncoords > 1) { - /* offset += coords.y * y_pitch: */ - offset = ir3_MAD_S24(b, create_uniform(b, cb + 1), 0, - coords[1], 0, offset, 0); - } - if (ncoords > 2) { - /* offset += coords.z * z_pitch: */ - offset = ir3_MAD_S24(b, create_uniform(b, cb + 2), 0, - coords[2], 0, offset, 0); - } - - if (!byteoff) { - /* Some cases, like atomics, seem to use dword offset instead - * of byte offsets.. blob just puts an extra shr.b in there - * in those cases: - */ - offset = ir3_SHR_B(b, offset, 0, create_immed(b, 2), 0); - } - - return ir3_create_collect(ctx, (struct ir3_instruction*[]){ - offset, - create_immed(b, 0), - }, 2); -} - /* src[] = { deref, coord, sample_index }. const_index[] = {} */ static void emit_intrinsic_load_image(struct ir3_context *ctx, nir_intrinsic_instr *intr, @@ -1140,45 +922,6 @@ emit_intrinsic_load_image(struct ir3_context *ctx, nir_intrinsic_instr *intr, ir3_split_dest(b, dst, sam, 0, 4); } -/* src[] = { deref, coord, sample_index, value }. const_index[] = {} */ -static void -emit_intrinsic_store_image(struct ir3_context *ctx, nir_intrinsic_instr *intr) -{ - struct ir3_block *b = ctx->block; - const nir_variable *var = nir_intrinsic_get_var(intr, 0); - struct ir3_instruction *stib, *offset; - struct ir3_instruction * const *value = ir3_get_src(ctx, &intr->src[3]); - struct ir3_instruction * const *coords = ir3_get_src(ctx, &intr->src[1]); - unsigned ncoords = ir3_get_image_coords(var, NULL); - unsigned tex_idx = ir3_get_image_slot(ctx, nir_src_as_deref(intr->src[0])); - unsigned ncomp = ir3_get_num_components_for_glformat(var->data.image.format); - - /* src0 is value - * src1 is coords - * src2 is 64b byte offset - */ - - offset = get_image_offset(ctx, var, coords, true); - - /* NOTE: stib seems to take byte offset, but stgb.typed can be used - * too and takes a dword offset.. not quite sure yet why blob uses - * one over the other in various cases. - */ - - stib = ir3_STIB(b, create_immed(b, tex_idx), 0, - ir3_create_collect(ctx, value, ncomp), 0, - ir3_create_collect(ctx, coords, ncoords), 0, - offset, 0); - stib->cat6.iim_val = ncomp; - stib->cat6.d = ncoords; - stib->cat6.type = ir3_get_image_type(var); - stib->cat6.typed = true; - stib->barrier_class = IR3_BARRIER_IMAGE_W; - stib->barrier_conflict = IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W; - - array_insert(b, b->keeps, stib); -} - static void emit_intrinsic_image_size(struct ir3_context *ctx, nir_intrinsic_instr *intr, struct ir3_instruction **dst) @@ -1242,73 +985,6 @@ emit_intrinsic_image_size(struct ir3_context *ctx, nir_intrinsic_instr *intr, } } -/* src[] = { deref, coord, sample_index, value, compare }. const_index[] = {} */ -static struct ir3_instruction * -emit_intrinsic_atomic_image(struct ir3_context *ctx, nir_intrinsic_instr *intr) -{ - struct ir3_block *b = ctx->block; - const nir_variable *var = nir_intrinsic_get_var(intr, 0); - struct ir3_instruction *atomic, *image, *src0, *src1, *src2; - struct ir3_instruction * const *coords = ir3_get_src(ctx, &intr->src[1]); - unsigned ncoords = ir3_get_image_coords(var, NULL); - - image = create_immed(b, ir3_get_image_slot(ctx, nir_src_as_deref(intr->src[0]))); - - /* src0 is value (or uvec2(value, compare)) - * src1 is coords - * src2 is 64b byte offset - */ - src0 = ir3_get_src(ctx, &intr->src[3])[0]; - src1 = ir3_create_collect(ctx, coords, ncoords); - src2 = get_image_offset(ctx, var, coords, false); - - switch (intr->intrinsic) { - case nir_intrinsic_image_deref_atomic_add: - atomic = ir3_ATOMIC_ADD_G(b, image, 0, src0, 0, src1, 0, src2, 0); - break; - case nir_intrinsic_image_deref_atomic_min: - atomic = ir3_ATOMIC_MIN_G(b, image, 0, src0, 0, src1, 0, src2, 0); - break; - case nir_intrinsic_image_deref_atomic_max: - atomic = ir3_ATOMIC_MAX_G(b, image, 0, src0, 0, src1, 0, src2, 0); - break; - case nir_intrinsic_image_deref_atomic_and: - atomic = ir3_ATOMIC_AND_G(b, image, 0, src0, 0, src1, 0, src2, 0); - break; - case nir_intrinsic_image_deref_atomic_or: - atomic = ir3_ATOMIC_OR_G(b, image, 0, src0, 0, src1, 0, src2, 0); - break; - case nir_intrinsic_image_deref_atomic_xor: - atomic = ir3_ATOMIC_XOR_G(b, image, 0, src0, 0, src1, 0, src2, 0); - break; - case nir_intrinsic_image_deref_atomic_exchange: - atomic = ir3_ATOMIC_XCHG_G(b, image, 0, src0, 0, src1, 0, src2, 0); - break; - case nir_intrinsic_image_deref_atomic_comp_swap: - /* for cmpxchg, src0 is [ui]vec2(data, compare): */ - src0 = ir3_create_collect(ctx, (struct ir3_instruction*[]){ - ir3_get_src(ctx, &intr->src[4])[0], - src0, - }, 2); - atomic = ir3_ATOMIC_CMPXCHG_G(b, image, 0, src0, 0, src1, 0, src2, 0); - break; - default: - unreachable("boo"); - } - - atomic->cat6.iim_val = 1; - atomic->cat6.d = ncoords; - atomic->cat6.type = ir3_get_image_type(var); - atomic->cat6.typed = true; - atomic->barrier_class = IR3_BARRIER_IMAGE_W; - atomic->barrier_conflict = IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W; - - /* even if nothing consume the result, we can't DCE the instruction: */ - array_insert(b, b->keeps, atomic); - - return atomic; -} - static void emit_intrinsic_barrier(struct ir3_context *ctx, nir_intrinsic_instr *intr) { @@ -1479,10 +1155,10 @@ emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr) } break; case nir_intrinsic_load_ssbo: - emit_intrinsic_load_ssbo(ctx, intr, dst); + ctx->funcs->emit_intrinsic_load_ssbo(ctx, intr, dst); break; case nir_intrinsic_store_ssbo: - emit_intrinsic_store_ssbo(ctx, intr); + ctx->funcs->emit_intrinsic_store_ssbo(ctx, intr); break; case nir_intrinsic_get_buffer_size: emit_intrinsic_ssbo_size(ctx, intr, dst); @@ -1497,7 +1173,7 @@ emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr) case nir_intrinsic_ssbo_atomic_xor: case nir_intrinsic_ssbo_atomic_exchange: case nir_intrinsic_ssbo_atomic_comp_swap: - dst[0] = emit_intrinsic_atomic_ssbo(ctx, intr); + dst[0] = ctx->funcs->emit_intrinsic_atomic_ssbo(ctx, intr); break; case nir_intrinsic_load_shared: emit_intrinsic_load_shared(ctx, intr, dst); @@ -1521,7 +1197,7 @@ emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr) emit_intrinsic_load_image(ctx, intr, dst); break; case nir_intrinsic_image_deref_store: - emit_intrinsic_store_image(ctx, intr); + ctx->funcs->emit_intrinsic_store_image(ctx, intr); break; case nir_intrinsic_image_deref_size: emit_intrinsic_image_size(ctx, intr, dst); @@ -1534,7 +1210,7 @@ emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr) case nir_intrinsic_image_deref_atomic_xor: case nir_intrinsic_image_deref_atomic_exchange: case nir_intrinsic_image_deref_atomic_comp_swap: - dst[0] = emit_intrinsic_atomic_image(ctx, intr); + dst[0] = ctx->funcs->emit_intrinsic_atomic_image(ctx, intr); break; case nir_intrinsic_barrier: case nir_intrinsic_memory_barrier: diff --git a/src/freedreno/ir3/ir3_context.c b/src/freedreno/ir3/ir3_context.c index c2d01666cff..d121559833b 100644 --- a/src/freedreno/ir3/ir3_context.c +++ b/src/freedreno/ir3/ir3_context.c @@ -52,6 +52,10 @@ ir3_context_init(struct ir3_compiler *compiler, } } + if (compiler->gpu_id >= 400) { + ctx->funcs = &ir3_a4xx_funcs; + } + ctx->compiler = compiler; ctx->so = so; ctx->def_ht = _mesa_hash_table_create(ctx, diff --git a/src/freedreno/ir3/ir3_context.h b/src/freedreno/ir3/ir3_context.h index adcc6b82213..c49b41dbd56 100644 --- a/src/freedreno/ir3/ir3_context.h +++ b/src/freedreno/ir3/ir3_context.h @@ -43,6 +43,7 @@ */ struct ir3_context { struct ir3_compiler *compiler; + const struct ir3_context_funcs *funcs; struct nir_shader *s; @@ -127,6 +128,17 @@ struct ir3_context { bool error; }; +struct ir3_context_funcs { + void (*emit_intrinsic_load_ssbo)(struct ir3_context *ctx, nir_intrinsic_instr *intr, + struct ir3_instruction **dst); + void (*emit_intrinsic_store_ssbo)(struct ir3_context *ctx, nir_intrinsic_instr *intr); + struct ir3_instruction * (*emit_intrinsic_atomic_ssbo)(struct ir3_context *ctx, nir_intrinsic_instr *intr); + void (*emit_intrinsic_store_image)(struct ir3_context *ctx, nir_intrinsic_instr *intr); + struct ir3_instruction * (*emit_intrinsic_atomic_image)(struct ir3_context *ctx, nir_intrinsic_instr *intr); +}; + +extern const struct ir3_context_funcs ir3_a4xx_funcs; + struct ir3_context * ir3_context_init(struct ir3_compiler *compiler, struct ir3_shader_variant *so); void ir3_context_free(struct ir3_context *ctx); diff --git a/src/freedreno/ir3/meson.build b/src/freedreno/ir3/meson.build index 23029d53007..2fd5d362e3b 100644 --- a/src/freedreno/ir3/meson.build +++ b/src/freedreno/ir3/meson.build @@ -34,6 +34,7 @@ libfreedreno_ir3_files = files( 'disasm-a3xx.c', 'instr-a3xx.h', 'ir3.c', + 'ir3_a4xx.c', 'ir3_compiler_nir.c', 'ir3_compiler.c', 'ir3_compiler.h', -- 2.30.2