From fef034988c6bc46a9241a3a7ba9d2a90ac88783f Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 30 Nov 2021 10:43:47 +0000 Subject: [PATCH] attempting to use PowerDecode2 in non-svp64 mode --- src/openpower/decoder/isa/caller.py | 8 ++++++-- src/openpower/test/runner.py | 2 +- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py index 275136e9..51dfd6fe 100644 --- a/src/openpower/decoder/isa/caller.py +++ b/src/openpower/decoder/isa/caller.py @@ -1298,7 +1298,8 @@ class ISACaller(ISACallerHelper, ISAFPHelpers): remap_en = self.svstate.SVme persist = self.svstate.RMpst active = (persist or self.last_op_svshape) and remap_en != 0 - yield self.dec2.remap_active.eq(remap_en if active else 0) + if self.is_svp64_mode: + yield self.dec2.remap_active.eq(remap_en if active else 0) yield Settle() if persist or self.last_op_svshape: remaps = self.get_remap_indices() @@ -1345,7 +1346,10 @@ class ISACaller(ISACallerHelper, ISAFPHelpers): # after that, settle down (combinatorial) to let Vector reg numbers # work themselves out yield Settle() - remap_active = yield self.dec2.remap_active + if self.is_svp64_mode: + remap_active = yield self.dec2.remap_active + else: + remap_active = False log ("remap active", bin(remap_active)) # main input registers (RT, RA ...) diff --git a/src/openpower/test/runner.py b/src/openpower/test/runner.py index 40572713..550d7eb2 100644 --- a/src/openpower/test/runner.py +++ b/src/openpower/test/runner.py @@ -140,7 +140,7 @@ class TestRunnerBase(FHDLTestCase): nocore=False, xics=False, gpio=False, - regreduce=True, + regreduce=not self.allow_overlap, svp64=self.svp64, allow_overlap=self.allow_overlap, mmu=self.microwatt_mmu, -- 2.30.2