From fefae2b2ba8863edc08fdc769f26d187dbd9edb0 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Sun, 28 Nov 2021 21:43:22 +0000
Subject: [PATCH]

---
 docs/pinmux.mdwn | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/docs/pinmux.mdwn b/docs/pinmux.mdwn
index 3588d4670..34af8030a 100644
--- a/docs/pinmux.mdwn
+++ b/docs/pinmux.mdwn
@@ -217,3 +217,13 @@ an FPGA or an ASIC, a full array of IO Connections:
        resources.append(clk)
        resources.append(rst)
        return resources
+
+For an FPGA, the Pins names are typically the Ball Grid Array
+Pad or Pin name: A12, or N20.  ASICs can do likewise: it is
+for convenience when referring to schematics, to use the most
+recogniseable well-known name.
+
+Next, these Resources need to be handed to a ResourceManager or
+a Platform (Platform derives from ResourceManager)
+
+     
-- 
2.30.2