From ff036796aabdc7bef9df3b6a3ca0511d8c126567 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Sun, 3 Apr 2022 22:41:12 -0700 Subject: [PATCH] fix tests --- src/nmigen_gf/hdl/test/__init__.py | 0 src/nmigen_gf/hdl/test/test_clmul.py | 2 +- 2 files changed, 1 insertion(+), 1 deletion(-) create mode 100644 src/nmigen_gf/hdl/test/__init__.py diff --git a/src/nmigen_gf/hdl/test/__init__.py b/src/nmigen_gf/hdl/test/__init__.py new file mode 100644 index 0000000..e69de29 diff --git a/src/nmigen_gf/hdl/test/test_clmul.py b/src/nmigen_gf/hdl/test/test_clmul.py index ffff3f0..ed39fed 100644 --- a/src/nmigen_gf/hdl/test/test_clmul.py +++ b/src/nmigen_gf/hdl/test/test_clmul.py @@ -11,7 +11,7 @@ from nmigen.hdl.ast import (AnyConst, Assert, Signal, Const, unsigned, signed, Mux) from nmigen.hdl.dsl import Module from nmutil.formaltest import FHDLTestCase -from nmutil.openpower_sv_bitmanip_in_wiki.clmul import clmul +from nmigen_gf.reference.clmul import clmul from nmutil.clmul import BitwiseXorReduce, CLMulAdd from nmigen.sim import Delay from nmutil.sim_util import do_sim, hash_256 -- 2.30.2