From ff0fa168b62d4c182592437ae6f54fa764dbe8a7 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 12 May 2022 07:34:23 +0100
Subject: [PATCH] add "DRAFT" in front of svfparith instruction descriptions

---
 openpower/isa/svfparith.mdwn | 30 +++++++++++++++---------------
 1 file changed, 15 insertions(+), 15 deletions(-)

diff --git a/openpower/isa/svfparith.mdwn b/openpower/isa/svfparith.mdwn
index 2bbf1429..4fa9939b 100644
--- a/openpower/isa/svfparith.mdwn
+++ b/openpower/isa/svfparith.mdwn
@@ -7,7 +7,7 @@
 
 <!-- PLEASE NOTE THESE ARE UNAPPROVED AND DRAFT, NOT SUBMITTED TO OPF ISA WG -->
 
-# Floating Add FFT/DCT [Single]
+# [DRAFT] Floating Add FFT/DCT [Single]
 
 A-Form
 
@@ -26,7 +26,7 @@ Special Registers Altered:
     VXSNAN VXISI
     CR1          (if Rc=1)
 
-# Floating Add FFT/DCT [Double]
+# [DRAFT] Floating Add FFT/DCT [Double]
 
 A-Form
 
@@ -45,7 +45,7 @@ Special Registers Altered:
     VXSNAN VXISI
     CR1          (if Rc=1)
 
-# Floating Subtract FFT/DCT [Single]
+# [DRAFT] Floating Subtract FFT/DCT [Single]
 
 A-Form
 
@@ -64,7 +64,7 @@ Special Registers Altered:
     VXSNAN VXISI
     CR1          (if Rc=1)
 
-# Floating Subtract FFT/DCT [Double]
+# [DRAFT] Floating Subtract FFT/DCT [Double]
 
 A-Form
 
@@ -83,7 +83,7 @@ Special Registers Altered:
     VXSNAN VXISI
     CR1          (if Rc=1)
 
-# Floating Multiply FFT/DCT [Single]
+# [DRAFT] Floating Multiply FFT/DCT [Single]
 
 A-Form
 
@@ -102,7 +102,7 @@ Special Registers Altered:
     VXSNAN VXISI
     CR1          (if Rc=1)
 
-# Floating Multiply FFT/DCT [Double]
+# [DRAFT] Floating Multiply FFT/DCT [Double]
 
 A-Form
 
@@ -121,7 +121,7 @@ Special Registers Altered:
     VXSNAN VXISI
     CR1          (if Rc=1)
 
-# Floating Divide FFT/DCT [Single]
+# [DRAFT] Floating Divide FFT/DCT [Single]
 
 A-Form
 
@@ -140,7 +140,7 @@ Special Registers Altered:
     VXSNAN VXISI
     CR1          (if Rc=1)
 
-# Floating Divide FFT/DCT [Double]
+# [DRAFT] Floating Divide FFT/DCT [Double]
 
 A-Form
 
@@ -159,7 +159,7 @@ Special Registers Altered:
     VXSNAN VXISI
     CR1          (if Rc=1)
 
-# Floating Twin Multiply-Add DCT [Single]
+# [DRAFT] Floating Twin Multiply-Add DCT [Single]
 
 A-Form
 
@@ -179,7 +179,7 @@ Special Registers Altered:
     VXSNAN VXISI VXIMZ
     CR1          (if Rc=1)
 
-# Floating Multiply-Add FFT [Single]
+# [DRAFT] Floating Multiply-Add FFT [Single]
 
 A-Form
 
@@ -198,7 +198,7 @@ Special Registers Altered:
     VXSNAN VXISI VXIMZ
     CR1          (if Rc=1)
 
-# Floating Multiply-Sub FFT [Single]
+# [DRAFT] Floating Multiply-Sub FFT [Single]
 
 A-Form
 
@@ -217,7 +217,7 @@ Special Registers Altered:
     VXSNAN VXISI VXIMZ
     CR1          (if Rc=1)
 
-# Floating Negative Multiply-Add FFT [Single]
+# [DRAFT] Floating Negative Multiply-Add FFT [Single]
 
 A-Form
 
@@ -236,7 +236,7 @@ Special Registers Altered:
     VXSNAN VXISI VXIMZ
     CR1          (if Rc=1)
 
-# Floating Negative Multiply-Sub FFT [Single]
+# [DRAFT] Floating Negative Multiply-Sub FFT [Single]
 
 A-Form
 
@@ -255,7 +255,7 @@ Special Registers Altered:
     VXSNAN VXISI VXIMZ
     CR1          (if Rc=1)
 
-# Floating SIN [Single]
+# [DRAFT] Floating SIN [Single]
 
 X-Form
 
@@ -273,7 +273,7 @@ Special Registers Altered:
     VXSNAN VXISI VXIMZ
     CR1          (if Rc=1)
 
-# Floating COS [Single]
+# [DRAFT] Floating COS [Single]
 
 X-Form
 
-- 
2.30.2