From ff18c773fa3b7d799e5ecb8cb348f55e2acb4661 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 5 Apr 2019 04:41:37 +0100
Subject: [PATCH] add example ready for adding delay (data_ready) to pipeline
 API

---
 src/add/singlepipe.py    |  2 +-
 src/add/test_buf_pipe.py | 65 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 66 insertions(+), 1 deletion(-)

diff --git a/src/add/singlepipe.py b/src/add/singlepipe.py
index 9dc0ee5e..9459eb09 100644
--- a/src/add/singlepipe.py
+++ b/src/add/singlepipe.py
@@ -257,7 +257,7 @@ def eq(o, i):
     if not isinstance(o, Sequence):
         o, i = [o], [i]
     for (ao, ai) in zip(o, i):
-        print ("eq", ao, ai)
+        #print ("eq", ao, ai)
         if isinstance(ao, Record):
             for idx, (field_name, field_shape, _) in enumerate(ao.layout):
                 if isinstance(field_shape, Layout):
diff --git a/src/add/test_buf_pipe.py b/src/add/test_buf_pipe.py
index fce4ff67..3f3cce21 100644
--- a/src/add/test_buf_pipe.py
+++ b/src/add/test_buf_pipe.py
@@ -576,6 +576,61 @@ def data_2op():
         return data
 
 
+######################################################################
+# Test 12
+######################################################################
+
+class ExampleStageDelayCls(StageCls):
+    """ an example of how to use the buffered pipeline, in a static class
+        fashion
+    """
+
+    def __init__(self):
+        self.count = Signal(3)
+
+    def ispec(self):
+        return Signal(16, name="example_input_signal")
+
+    def ospec(self):
+        return Signal(16, name="example_output_signal")
+
+    def data_ready(self, i):
+        pass
+
+    def process(self, i):
+        """ process the input data and returns it (adds 1)
+        """
+        return i + 1
+
+
+class ExampleBufDelayedPipe(BufferedPipeline):
+    """ an example of how to use the buffered pipeline.
+    """
+
+    def __init__(self):
+        BufferedPipeline.__init__(self, ExampleStageDelayCls())
+
+
+class ExampleBufPipe3(ControlBase):
+    """ Example of how to do delayed pipeline, where the stage signals
+        whether it is ready.
+    """
+
+    def elaborate(self, platform):
+        m = Module()
+
+        pipe1 = ExampleBufPipe()
+        pipe2 = ExampleBufDelayedPipe()
+
+        m.submodules.pipe1 = pipe1
+        m.submodules.pipe2 = pipe2
+
+        m.d.comb += self.connect([pipe1, pipe2])
+
+        return m
+
+
+
 num_tests = 100
 
 if __name__ == '__main__':
@@ -674,3 +729,13 @@ if __name__ == '__main__':
     run_simulation(dut, [test.send, test.rcv], vcd_name="test_addrecord.vcd")
 
 
+    print ("test 12")
+    dut = ExampleBufPipe3()
+    run_simulation(dut, testbench2(dut), vcd_name="test_bufpipe12.vcd")
+    ports = [dut.p.i_valid, dut.n.i_ready,
+             dut.n.o_valid, dut.p.o_ready] + \
+             [dut.p.i_data] + [dut.n.o_data]
+    vl = rtlil.convert(dut, ports=ports)
+    with open("test_bufpipe12.il", "w") as f:
+        f.write(vl)
+
-- 
2.30.2