From ff39f0d59ca0627637423f8a409c0ef645879e15 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Nicolai=20H=C3=A4hnle?= Date: Wed, 12 Apr 2017 10:00:18 +0200 Subject: [PATCH] radeonsi: emit VS_STATE register explicitly from si_draw_vbo MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit We will merge other derived state information into this register. Reviewed-by: Marek Olšák --- src/gallium/drivers/radeonsi/si_hw_context.c | 1 + src/gallium/drivers/radeonsi/si_pipe.h | 2 ++ src/gallium/drivers/radeonsi/si_shader.h | 5 +++++ src/gallium/drivers/radeonsi/si_state.c | 6 ++++-- src/gallium/drivers/radeonsi/si_state.h | 1 + src/gallium/drivers/radeonsi/si_state_draw.c | 14 ++++++++++++++ 6 files changed, 27 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_hw_context.c b/src/gallium/drivers/radeonsi/si_hw_context.c index c80b884970a..e51abfc5c53 100644 --- a/src/gallium/drivers/radeonsi/si_hw_context.c +++ b/src/gallium/drivers/radeonsi/si_hw_context.c @@ -257,6 +257,7 @@ void si_begin_new_cs(struct si_context *ctx) ctx->last_multi_vgt_param = -1; ctx->last_rast_prim = -1; ctx->last_sc_line_stipple = ~0; + ctx->last_vs_state = ~0; ctx->last_ls = NULL; ctx->last_tcs = NULL; ctx->last_tes_sh_base = -1; diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h index daf29325f76..09788316a49 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.h +++ b/src/gallium/drivers/radeonsi/si_pipe.h @@ -348,6 +348,8 @@ struct si_context { int last_multi_vgt_param; int last_rast_prim; unsigned last_sc_line_stipple; + unsigned current_vs_state; + unsigned last_vs_state; enum pipe_prim_type current_rast_prim; /* primitive type after TES, GS */ bool gs_tri_strip_adj_fix; diff --git a/src/gallium/drivers/radeonsi/si_shader.h b/src/gallium/drivers/radeonsi/si_shader.h index 17ffc5d8c78..4a0f2704564 100644 --- a/src/gallium/drivers/radeonsi/si_shader.h +++ b/src/gallium/drivers/radeonsi/si_shader.h @@ -226,6 +226,11 @@ enum { SI_NUM_PARAMS = SI_PARAM_POS_FIXED_PT + 9, /* +8 for COLOR[0..1] */ }; +/* Fields of driver-defined VS state SGPR. */ +/* Clamp vertex color output (only used in VS as VS). */ +#define S_VS_STATE_CLAMP_VERTEX_COLOR(x) (((unsigned)(x) & 0x1) << 0) +#define C_VS_STATE_CLAMP_VERTEX_COLOR 0xFFFFFFFE + /* SI-specific system values. */ enum { TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI = TGSI_SEMANTIC_COUNT, diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 4a6b61587fb..a55f024c843 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -796,6 +796,7 @@ static void *si_create_rs_state(struct pipe_context *ctx, rs->uses_poly_offset = state->offset_point || state->offset_line || state->offset_tri; rs->clamp_fragment_color = state->clamp_fragment_color; + rs->clamp_vertex_color = state->clamp_vertex_color; rs->flatshade = state->flatshade; rs->sprite_coord_enable = state->sprite_coord_enable; rs->rasterizer_discard = state->rasterizer_discard; @@ -862,8 +863,6 @@ static void *si_create_rs_state(struct pipe_context *ctx, state->fill_back != PIPE_POLYGON_MODE_FILL) | S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) | S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back))); - si_pm4_set_reg(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0 + - SI_SGPR_VS_STATE_BITS * 4, state->clamp_vertex_color); /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */ for (i = 0; i < 3; i++) { @@ -926,6 +925,9 @@ static void si_bind_rs_state(struct pipe_context *ctx, void *state) si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom); } + sctx->current_vs_state &= C_VS_STATE_CLAMP_VERTEX_COLOR; + sctx->current_vs_state |= S_VS_STATE_CLAMP_VERTEX_COLOR(rs->clamp_vertex_color); + r600_viewport_set_rast_deps(&sctx->b, rs->scissor_enable, rs->clip_halfz); si_pm4_bind_state(sctx, rasterizer, rs); diff --git a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h index aad1c8343f1..6257299fc3a 100644 --- a/src/gallium/drivers/radeonsi/si_state.h +++ b/src/gallium/drivers/radeonsi/si_state.h @@ -74,6 +74,7 @@ struct si_state_rasterizer { bool poly_smooth; bool uses_poly_offset; bool clamp_fragment_color; + bool clamp_vertex_color; bool rasterizer_discard; bool scissor_enable; bool clip_halfz; diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index 65b33cee4ef..54e02d217a9 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -494,6 +494,19 @@ static void si_emit_rasterizer_prim_state(struct si_context *sctx) sctx->last_sc_line_stipple = rs->pa_sc_line_stipple; } +static void si_emit_vs_state(struct si_context *sctx) +{ + if (sctx->current_vs_state != sctx->last_vs_state) { + struct radeon_winsys_cs *cs = sctx->b.gfx.cs; + + radeon_set_sh_reg(cs, + R_00B130_SPI_SHADER_USER_DATA_VS_0 + SI_SGPR_VS_STATE_BITS * 4, + sctx->current_vs_state); + + sctx->last_vs_state = sctx->current_vs_state; + } +} + static void si_emit_draw_registers(struct si_context *sctx, const struct pipe_draw_info *info, unsigned num_patches) @@ -1291,6 +1304,7 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info) si_emit_rasterizer_prim_state(sctx); if (sctx->tes_shader.cso) si_emit_derived_tess_state(sctx, info, &num_patches); + si_emit_vs_state(sctx); si_emit_draw_registers(sctx, info, num_patches); si_ce_pre_draw_synchronization(sctx); -- 2.30.2