From ff3b0c2c4676a9b717929920fa27098c5f9b53e5 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 22 Mar 2022 14:22:32 +0100 Subject: [PATCH] Proper SigBit forming in sim --- passes/sat/sim.cc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index f225ebd15..b56ccb987 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -1138,13 +1138,13 @@ struct SimWorker : SimShared if (index < w->start_offset || index > w->start_offset + w->width) log_error("Index %d for wire %s is out of range\n", index, log_signal(w)); if (type == "input") { - inputs[variable] = {SigBit(w,index), false}; + inputs[variable] = {SigBit(w,index-w->start_offset), false}; } else if (type == "init") { - inits[variable] = {SigBit(w,index), false}; + inits[variable] = {SigBit(w,index-w->start_offset), false}; } else if (type == "latch") { - latches[variable] = {SigBit(w,index), false}; + latches[variable] = {SigBit(w,index-w->start_offset), false}; } else if (type == "invlatch") { - latches[variable] = {SigBit(w,index), true}; + latches[variable] = {SigBit(w,index-w->start_offset), true}; } } -- 2.30.2