From ff3ea3b3bb36e7ca3c65a64bee0a422346bb39b5 Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Fri, 14 Aug 2020 11:03:46 -0400 Subject: [PATCH] pan/mdg: Fix auxiliary load/store swizzle packing It needs to respect the existing swizzle, as well as the type size. Signed-off-by: Alyssa Rosenzweig Reviewed-by: Tomeu Vizoso Part-of: --- src/panfrost/midgard/helpers.h | 12 +++++++++++- src/panfrost/midgard/midgard_emit.c | 6 ++++-- src/panfrost/midgard/midgard_ra.c | 8 ++++---- 3 files changed, 19 insertions(+), 7 deletions(-) diff --git a/src/panfrost/midgard/helpers.h b/src/panfrost/midgard/helpers.h index 6f6f82cc70a..73f82a5aaaf 100644 --- a/src/panfrost/midgard/helpers.h +++ b/src/panfrost/midgard/helpers.h @@ -310,9 +310,19 @@ mir_is_simple_swizzle(unsigned *swizzle, unsigned mask) /* Packs a load/store argument */ static inline uint8_t -midgard_ldst_reg(unsigned reg, unsigned component) +midgard_ldst_reg(unsigned reg, unsigned component, unsigned size) { assert((reg == REGISTER_LDST_BASE) || (reg == REGISTER_LDST_BASE + 1)); + assert(size == 16 || size == 32 || size == 64); + + /* Shift so everything is in terms of 32-bit units */ + if (size == 64) { + assert(component < 2); + component <<= 1; + } else if (size == 16) { + assert((component & 1) == 0); + component >>= 1; + } midgard_ldst_register_select sel = { .component = component, diff --git a/src/panfrost/midgard/midgard_emit.c b/src/panfrost/midgard/midgard_emit.c index 8b022554a94..77f2e3b7bf2 100644 --- a/src/panfrost/midgard/midgard_emit.c +++ b/src/panfrost/midgard/midgard_emit.c @@ -501,12 +501,14 @@ load_store_from_instr(midgard_instruction *ins) if (ins->src[1] != ~0) { unsigned src = SSA_REG_FROM_FIXED(ins->src[1]); - ldst.arg_1 |= midgard_ldst_reg(src, ins->swizzle[1][0]); + unsigned sz = nir_alu_type_get_type_size(ins->src_types[1]); + ldst.arg_1 |= midgard_ldst_reg(src, ins->swizzle[1][0], sz); } if (ins->src[2] != ~0) { unsigned src = SSA_REG_FROM_FIXED(ins->src[2]); - ldst.arg_2 |= midgard_ldst_reg(src, ins->swizzle[2][0]); + unsigned sz = nir_alu_type_get_type_size(ins->src_types[2]); + ldst.arg_2 |= midgard_ldst_reg(src, ins->swizzle[2][0], sz); } return ldst; diff --git a/src/panfrost/midgard/midgard_ra.c b/src/panfrost/midgard/midgard_ra.c index b06eb97ab8e..bb95d385429 100644 --- a/src/panfrost/midgard/midgard_ra.c +++ b/src/panfrost/midgard/midgard_ra.c @@ -723,19 +723,19 @@ install_registers_instr( unsigned src3 = ins->src[2]; if (src2 != ~0) { - struct phys_reg src = index_to_reg(ctx, l, src2, 2); + struct phys_reg src = index_to_reg(ctx, l, src2, src_shift[1]); unsigned component = src.offset >> src.shift; assert(component << src.shift == src.offset); ins->src[1] = SSA_FIXED_REGISTER(src.reg); - ins->swizzle[1][0] = component; + ins->swizzle[1][0] += component; } if (src3 != ~0) { - struct phys_reg src = index_to_reg(ctx, l, src3, 2); + struct phys_reg src = index_to_reg(ctx, l, src3, src_shift[2]); unsigned component = src.offset >> src.shift; assert(component << src.shift == src.offset); ins->src[2] = SSA_FIXED_REGISTER(src.reg); - ins->swizzle[2][0] = component; + ins->swizzle[2][0] += component; } break; -- 2.30.2