From ff417388719828b3b5f0c9e3c0b076e9cff99ff7 Mon Sep 17 00:00:00 2001
From: Jordan Justen <jordan.l.justen@intel.com>
Date: Sat, 2 Apr 2016 01:25:05 -0700
Subject: [PATCH] genxml/hsw: Add L3 cache control registers

These were added to the i965 driver in
5912da45a69923afa1b7f2eb5bb371d848813c41.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
---
 src/intel/genxml/gen75.xml | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml
index 698d93f12ae..2258dee3960 100644
--- a/src/intel/genxml/gen75.xml
+++ b/src/intel/genxml/gen75.xml
@@ -2932,4 +2932,12 @@
     <field name="T Low Bandwidth" start="21" end="21" type="uint"/>
   </register>
 
+  <register name="SCRATCH1" length="1" num="0xb038">
+    <field name="L3 Atomic Disable" start="27" end="27" type="uint"/>
+  </register>
+
+  <register name="CHICKEN3" length="1" num="0xe49c">
+    <field name="L3 Atomic Disable" start="6" end="6" type="uint"/>
+  </register>
+
 </genxml>
-- 
2.30.2