From ff42c387796ad3f22bb4be9f3f09f765ef475fa1 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Wed, 5 Jan 2022 20:57:46 -0800 Subject: [PATCH] add grev[w][i] instructions --- openpower/isatables/RM-1P-2S1D.csv | 2 ++ openpower/isatables/RM-2P-1S1D.csv | 2 ++ openpower/isatables/fields.text | 16 ++++++++++++---- openpower/isatables/minor_5.csv | 4 ++++ src/openpower/decoder/formal/proof_decoder2.py | 2 ++ src/openpower/decoder/power_decoder2.py | 3 +++ src/openpower/decoder/power_enums.py | 3 +++ 7 files changed, 28 insertions(+), 4 deletions(-) diff --git a/openpower/isatables/RM-1P-2S1D.csv b/openpower/isatables/RM-1P-2S1D.csv index 8da5faab..ec967834 100644 --- a/openpower/isatables/RM-1P-2S1D.csv +++ b/openpower/isatables/RM-1P-2S1D.csv @@ -80,6 +80,8 @@ divduo,,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 divwuo,,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 divdo,,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 divwo,,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 +grev,,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 +grevw,,1P,EXTRA3,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 ffadds,,1P,EXTRA3,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 fdivs,,1P,EXTRA3,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 fsubs,,1P,EXTRA3,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 diff --git a/openpower/isatables/RM-2P-1S1D.csv b/openpower/isatables/RM-2P-1S1D.csv index 1ce99641..68c9b221 100644 --- a/openpower/isatables/RM-2P-1S1D.csv +++ b/openpower/isatables/RM-2P-1S1D.csv @@ -88,3 +88,5 @@ sradi,,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,0,0,RS,RA,0,CR0,0 sradi,,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,0,0,RS,RA,0,CR0,0 extswsli,,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,0,0,RS,RA,0,CR0,0 extswsli,,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,0,0,RS,RA,0,CR0,0 +grevi,,2P,EXTRA3,d:RT;d:CR0,s:RA,0,0,RA,0,0,RT,0,CR0,0 +grevwi,,2P,EXTRA3,d:RT;d:CR0,s:RA,0,0,RA,0,0,RT,0,CR0,0 diff --git a/openpower/isatables/fields.text b/openpower/isatables/fields.text index aadf9f5d..d4b5075f 100644 --- a/openpower/isatables/fields.text +++ b/openpower/isatables/fields.text @@ -160,6 +160,10 @@ |0 |6 |11 |16 |21 |30|31 | | PO | RS | RA | sh | XO |sh|Rc | +# 1.6.15 XB-FORM + |0 |6 |11 |16 |22 |31 | + | PO | RT | RA | XBI | XO |Rc | + # 1.6.16 XO-FORM |0 |6 |11 |16 |21 |22 |31 | | PO | RT| RA| RB |OE | XO |Rc | @@ -658,7 +662,7 @@ RA (11:15) Field used to specify a GPR to be used as a source or as a target. - Formats: A, D, DQ, DQE, DS, M, MD, MDS, TX, VA, VX, X, XO, XS, SVL + Formats: A, D, DQ, DQE, DS, M, MD, MDS, TX, VA, VX, X, XO, XS, SVL, XB RB (16:20) Field used to specify a GPR to be used as a source. @@ -680,7 +684,7 @@ 1 Set Condition Register Field 0 or Field 1 as described in Section 2.3.1, 'Condition Regis- ter' on page 30. - Formats: A, M, MD, MDS, X, XFL, XO, XS, Z22, Z23, SVL + Formats: A, M, MD, MDS, X, XFL, XO, XS, Z22, Z23, SVL, XB RIC (12:13) Field used to specify what types of entries to inval- idate for tlbie[l]. @@ -706,7 +710,7 @@ Formats: DS, X RT (6:10) Field used to specify a GPR to be used as a target. - Formats: A, D, DQE, DS, DX, VA, VX, X, XFX, XO, XX2, SVL + Formats: A, D, DQE, DS, DX, VA, VX, X, XFX, XO, XX2, SVL, XB RTp (6:10) Field used to specify an even/odd pair of GPRs to be concatenated and used as a target. @@ -908,6 +912,10 @@ XBI (21:24) Field used to specify a bit in the XER. Formats: MDS, MDS, TX + XBI (16:21) + Field used to specify a 6-bit unsigned immediate for bit manipulation + instructions, such as grevi. + Formats: XB XO (21,23:31) Extended opcode field. Formats: VX @@ -931,7 +939,7 @@ Formats: VX XO (22:30) Extended opcode field. - Formats: XO, XX3, Z22 + Formats: XO, XX3, Z22, XB XO (22:31) Extended opcode field. Formats: VC diff --git a/openpower/isatables/minor_5.csv b/openpower/isatables/minor_5.csv index 26d7c8b0..ec0cbc17 100644 --- a/openpower/isatables/minor_5.csv +++ b/openpower/isatables/minor_5.csv @@ -1,2 +1,6 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form,CONDITIONS,unofficial,comment2 --------00-,SHIFT_ROT,OP_TERNLOG,RA,RB,RT,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,ternlogi,TLI,,1,unofficial until submitted and approved/renumbered by the opf isa wg +0010010110-,SHIFT_ROT,OP_GREV,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,grev,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg +-011010110-,SHIFT_ROT,OP_GREV,RA,CONST_XBI,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,grevi,XB,,1,unofficial until submitted and approved/renumbered by the opf isa wg +0010110110-,SHIFT_ROT,OP_GREV,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,grevw,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg +0011110110-,SHIFT_ROT,OP_GREV,RA,CONST_SH32,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,grevwi,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg diff --git a/src/openpower/decoder/formal/proof_decoder2.py b/src/openpower/decoder/formal/proof_decoder2.py index a984186f..87f6919b 100644 --- a/src/openpower/decoder/formal/proof_decoder2.py +++ b/src/openpower/decoder/formal/proof_decoder2.py @@ -109,6 +109,8 @@ class Driver(Elaboratable): comb += Assert(pdecode2.e.imm_data.data == dec.sh) with m.Case(In2Sel.CONST_SH32): comb += Assert(pdecode2.e.imm_data.data == dec.SH32) + with m.Case(In2Sel.CONST_XBI): + comb += Assert(pdecode2.e.imm_data.data == dec.FormXB.XBI) with m.Default(): comb += Assert(0) diff --git a/src/openpower/decoder/power_decoder2.py b/src/openpower/decoder/power_decoder2.py index 74144ab9..8714fa3c 100644 --- a/src/openpower/decoder/power_decoder2.py +++ b/src/openpower/decoder/power_decoder2.py @@ -323,6 +323,9 @@ class DecodeBImm(Elaboratable): with m.Case(In2Sel.CONST_SH32): # unsigned - for shift comb += self.imm_out.data.eq(self.dec.SH32) comb += self.imm_out.ok.eq(1) + with m.Case(In2Sel.CONST_XBI): # unsigned - for grevi + comb += self.imm_out.data.eq(self.dec.FormXB.XBI) + comb += self.imm_out.ok.eq(1) return m diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py index cd753b85..757df322 100644 --- a/src/openpower/decoder/power_enums.py +++ b/src/openpower/decoder/power_enums.py @@ -121,6 +121,7 @@ class Form(Enum): SVM = 32 # Simple-V SHAPE mode - TEMPORARY TEMPORARY TEMPORARY SVRM = 33 # Simple-V REMAP mode - TEMPORARY TEMPORARY TEMPORARY TLI = 34 # ternlogi + XB = 35 # Simple-V svp64 fields https://libre-soc.org/openpower/sv/svp64/ @@ -438,6 +439,7 @@ class MicrOp(Enum): OP_CBCDTD = 85 OP_TERNLOG = 86 OP_FETCH_FAILED = 87 + OP_GREV = 88 @unique @@ -470,6 +472,7 @@ class In2Sel(Enum): FRB = 14 CONST_SVD = 15 # for SVD-Form CONST_SVDS = 16 # for SVDS-Form + CONST_XBI = 17 @unique -- 2.30.2