From ff500df311fd6f41c130e641b93184f3b1a025d1 Mon Sep 17 00:00:00 2001 From: lkcl Date: Fri, 24 Jun 2022 22:06:57 +0100 Subject: [PATCH] --- openpower/sv/remap.mdwn | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/openpower/sv/remap.mdwn b/openpower/sv/remap.mdwn index 5ff2c0bf9..69935a18e 100644 --- a/openpower/sv/remap.mdwn +++ b/openpower/sv/remap.mdwn @@ -28,9 +28,12 @@ Vector ISAs which would typically only have a limited set of instructions that can be structure-packed (LD/ST typically), REMAP may be applied to literally any instruction: CRs, Arithmetic, Logical, LD/ST, anything. -Note that REMAP does not apply to sub-vector elements: that is what -swizzle is for. Swizzle *can* however be applied to the same instruction -as REMAP. +Note that REMAP does not *directly* apply to sub-vector elements: that +is what swizzle is for. Swizzle *can* however be applied to the same +instruction as REMAP. As explained in [[sv/mv.swizzle]], [[sv/mv.vec]] and the [[svp64/appendix]], Pack and Unpack EXTRA Mode bits +can extend down into Sub-vector elements to perform vec2/vec3/vec4 +sequential reordering, but even here, REMAP is not extended down to +the actual sub-vector elements themselves. In its general form, REMAP is quite expensive to set up, and on some implementations introduce -- 2.30.2