From ff66f6e835c22459bdf5b0bcd6d4d67a541cdae7 Mon Sep 17 00:00:00 2001 From: Patrick Palka Date: Wed, 1 Jun 2016 02:36:27 +0000 Subject: [PATCH] re PR tree-optimization/71077 (gcc -lto raises ICE) Fix PR tree-optimization/71077 gcc/ChangeLog: PR tree-optimization/71077 * tree-ssa-threadedge.c (simplify_control_stmt_condition_1): In the combining step, use boolean_false_node and boolean_true_node as the designated false/true return values. gcc/testsuite/ChangeLog: PR tree-optimization/71077 * gcc.dg/tree-ssa/pr71077.c: New test. From-SVN: r236973 --- gcc/ChangeLog | 7 +++++++ gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gcc.dg/tree-ssa/pr71077.c | 18 +++++++++++++++++ gcc/tree-ssa-threadedge.c | 26 ++++++++++++------------- 4 files changed, 42 insertions(+), 14 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr71077.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 45f31d4882c..a27cc911359 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2016-06-01 Patrick Palka + + PR tree-optimization/71077 + * tree-ssa-threadedge.c (simplify_control_stmt_condition_1): In + the combining step, use boolean_false_node and boolean_true_node + as the designated false/true return values. + 2016-05-31 Jan Hubicka * predict.def (PRED_LOOP_EXTRA_EXIT): Define. diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index df648204b59..17cf2fa6795 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2016-06-01 Patrick Palka + + PR tree-optimization/71077 + * gcc.dg/tree-ssa/pr71077.c: New test. + 2016-05-31 Jan Hubicka * g++.d/predict-lop-exit-1.C: Update template for new predictor name. diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr71077.c b/gcc/testsuite/gcc.dg/tree-ssa/pr71077.c new file mode 100644 index 00000000000..4753740f762 --- /dev/null +++ b/gcc/testsuite/gcc.dg/tree-ssa/pr71077.c @@ -0,0 +1,18 @@ +/* PR c++/71077 */ +/* { dg-do link { target { i?86-*-* x86_64-*-* } } } */ +/* { dg-options "-O3 -flto -march=core-avx2" } */ + +int *a; +int b, c, d, e; +int sched_analyze(void) { + for (; b; b++) { + c = 0; + for (; c < 32; c++) + if (b & 1 << c) + a[b + c] = d; + } + return 0; +} + +void schedule_insns(void) { e = sched_analyze(); } +int main(void) { schedule_insns(); } diff --git a/gcc/tree-ssa-threadedge.c b/gcc/tree-ssa-threadedge.c index 5fd5b98afe8..de671b94637 100644 --- a/gcc/tree-ssa-threadedge.c +++ b/gcc/tree-ssa-threadedge.c @@ -572,8 +572,6 @@ simplify_control_stmt_condition_1 (edge e, enum tree_code rhs_code = gimple_assign_rhs_code (def_stmt); const tree rhs1 = gimple_assign_rhs1 (def_stmt); const tree rhs2 = gimple_assign_rhs2 (def_stmt); - const tree zero_cst = build_zero_cst (TREE_TYPE (op0)); - const tree one_cst = build_one_cst (TREE_TYPE (op0)); /* Is A != 0 ? */ const tree res1 @@ -588,19 +586,19 @@ simplify_control_stmt_condition_1 (edge e, { /* If A == 0 then (A & B) != 0 is always false. */ if (cond_code == NE_EXPR) - return zero_cst; + return boolean_false_node; /* If A == 0 then (A & B) == 0 is always true. */ if (cond_code == EQ_EXPR) - return one_cst; + return boolean_true_node; } else if (rhs_code == BIT_IOR_EXPR && integer_nonzerop (res1)) { /* If A != 0 then (A | B) != 0 is always true. */ if (cond_code == NE_EXPR) - return one_cst; + return boolean_true_node; /* If A != 0 then (A | B) == 0 is always false. */ if (cond_code == EQ_EXPR) - return zero_cst; + return boolean_false_node; } /* Is B != 0 ? */ @@ -616,19 +614,19 @@ simplify_control_stmt_condition_1 (edge e, { /* If B == 0 then (A & B) != 0 is always false. */ if (cond_code == NE_EXPR) - return zero_cst; + return boolean_false_node; /* If B == 0 then (A & B) == 0 is always true. */ if (cond_code == EQ_EXPR) - return one_cst; + return boolean_true_node; } else if (rhs_code == BIT_IOR_EXPR && integer_nonzerop (res2)) { /* If B != 0 then (A | B) != 0 is always true. */ if (cond_code == NE_EXPR) - return one_cst; + return boolean_true_node; /* If B != 0 then (A | B) == 0 is always false. */ if (cond_code == EQ_EXPR) - return zero_cst; + return boolean_false_node; } if (res1 != NULL_TREE && res2 != NULL_TREE) @@ -640,10 +638,10 @@ simplify_control_stmt_condition_1 (edge e, { /* If A != 0 and B != 0 then (bool)(A & B) != 0 is true. */ if (cond_code == NE_EXPR) - return one_cst; + return boolean_true_node; /* If A != 0 and B != 0 then (bool)(A & B) == 0 is false. */ if (cond_code == EQ_EXPR) - return zero_cst; + return boolean_false_node; } if (rhs_code == BIT_IOR_EXPR @@ -652,10 +650,10 @@ simplify_control_stmt_condition_1 (edge e, { /* If A == 0 and B == 0 then (A | B) != 0 is false. */ if (cond_code == NE_EXPR) - return zero_cst; + return boolean_false_node; /* If A == 0 and B == 0 then (A | B) == 0 is true. */ if (cond_code == EQ_EXPR) - return one_cst; + return boolean_true_node; } } } -- 2.30.2