From ff6f572f8b0a1f60246f90683e51635744cb7d36 Mon Sep 17 00:00:00 2001 From: Daniel Jacobowitz Date: Mon, 26 Feb 2007 19:18:53 +0000 Subject: [PATCH] * arm-tdep.c (arm_scan_prologue): Do not record FPA register saves if there are no FPA registers. (arm_dwarf_reg_to_regnum): New function. (arm_register_type, arm_register_name): Return minimal values for unsupported registers. (arm_register_sim_regno): Handle iWMMXt registers. (arm_gdbarch_init): Record missing FPA registers if indicated by a target description. Recognize iWMMXt registers. Only register "info float" for FPA. Use ARM_NUM_REGS. Register arm_dwarf_reg_to_regnum. * arm-tdep.h (enum gdb_regnum): Add ARM_NUM_REGS and iWMMXt constants. (struct gdbarch_tdep): Add have_fpa_registers. * features/xscale-iwmmxt.xml: Update capitalization. * regformats/arm-with-iwmmxt.dat: Regenerated. * src/gdb/doc/gdb.texinfo (Standard Target Features): Mention case insensitivity. (ARM Features): Describe org.gnu.gdb.xscale.iwmmxt. * gdb.arch/iwmmxt-regs.c, gdb.arch/iwmmxt-regs.exp: Update register capitalization. --- gdb/ChangeLog | 18 +++++ gdb/arm-tdep.c | 107 ++++++++++++++++++++++++- gdb/arm-tdep.h | 15 ++++ gdb/doc/ChangeLog | 6 ++ gdb/doc/gdb.texinfo | 8 ++ gdb/features/xscale-iwmmxt.xml | 44 +++++----- gdb/regformats/arm-with-iwmmxt.dat | 44 +++++----- gdb/testsuite/ChangeLog | 5 ++ gdb/testsuite/gdb.arch/iwmmxt-regs.c | 88 ++++++++++---------- gdb/testsuite/gdb.arch/iwmmxt-regs.exp | 22 ++--- 10 files changed, 254 insertions(+), 103 deletions(-) diff --git a/gdb/ChangeLog b/gdb/ChangeLog index bd392507130..d9302aa4a70 100644 --- a/gdb/ChangeLog +++ b/gdb/ChangeLog @@ -1,3 +1,21 @@ +2007-02-26 Daniel Jacobowitz + + * arm-tdep.c (arm_scan_prologue): Do not record FPA register saves + if there are no FPA registers. + (arm_dwarf_reg_to_regnum): New function. + (arm_register_type, arm_register_name): Return minimal values for + unsupported registers. + (arm_register_sim_regno): Handle iWMMXt registers. + (arm_gdbarch_init): Record missing FPA registers if indicated by + a target description. Recognize iWMMXt registers. Only register + "info float" for FPA. Use ARM_NUM_REGS. Register + arm_dwarf_reg_to_regnum. + * arm-tdep.h (enum gdb_regnum): Add ARM_NUM_REGS and iWMMXt + constants. + (struct gdbarch_tdep): Add have_fpa_registers. + * features/xscale-iwmmxt.xml: Update capitalization. + * regformats/arm-with-iwmmxt.dat: Regenerated. + 2007-02-24 Kevin Buettner * NEWS (New targets): Add entry for the Toshiba Media Processor. diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index ab7b2e99f3d..869cc3469be 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -832,13 +832,15 @@ arm_scan_prologue (struct frame_info *next_frame, struct arm_prologue_cache *cac imm = (imm >> rot) | (imm << (32 - rot)); sp_offset -= imm; } - else if ((insn & 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */ + else if ((insn & 0xffff7fff) == 0xed6d0103 /* stfe f?, [sp, -#c]! */ + && gdbarch_tdep (current_gdbarch)->have_fpa_registers) { sp_offset -= 12; regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07); cache->saved_regs[regno].addr = sp_offset; } - else if ((insn & 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */ + else if ((insn & 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4, [sp!] */ + && gdbarch_tdep (current_gdbarch)->have_fpa_registers) { int n_saved_fp_regs; unsigned int fp_start_reg, fp_bound_reg; @@ -1383,10 +1385,48 @@ arm_register_type (struct gdbarch *gdbarch, int regnum) return builtin_type_void_data_ptr; else if (regnum == ARM_PC_REGNUM) return builtin_type_void_func_ptr; + else if (regnum >= ARRAY_SIZE (arm_register_names)) + /* These registers are only supported on targets which supply + an XML description. */ + return builtin_type_int0; else return builtin_type_uint32; } +/* Map a DWARF register REGNUM onto the appropriate GDB register + number. */ + +static int +arm_dwarf_reg_to_regnum (int reg) +{ + /* Core integer regs. */ + if (reg >= 0 && reg <= 15) + return reg; + + /* Legacy FPA encoding. These were once used in a way which + overlapped with VFP register numbering, so their use is + discouraged, but GDB doesn't support the ARM toolchain + which used them for VFP. */ + if (reg >= 16 && reg <= 23) + return ARM_F0_REGNUM + reg - 16; + + /* New assignments for the FPA registers. */ + if (reg >= 96 && reg <= 103) + return ARM_F0_REGNUM + reg - 96; + + /* WMMX register assignments. */ + if (reg >= 104 && reg <= 111) + return ARM_WCGR0_REGNUM + reg - 104; + + if (reg >= 112 && reg <= 127) + return ARM_WR0_REGNUM + reg - 112; + + if (reg >= 192 && reg <= 199) + return ARM_WC0_REGNUM + reg - 192; + + return -1; +} + /* Map GDB internal REGNUM onto the Arm simulator register numbers. */ static int arm_register_sim_regno (int regnum) @@ -1394,6 +1434,15 @@ arm_register_sim_regno (int regnum) int reg = regnum; gdb_assert (reg >= 0 && reg < NUM_REGS); + if (regnum >= ARM_WR0_REGNUM && regnum <= ARM_WR15_REGNUM) + return regnum - ARM_WR0_REGNUM + SIM_ARM_IWMMXT_COP0R0_REGNUM; + + if (regnum >= ARM_WC0_REGNUM && regnum <= ARM_WC7_REGNUM) + return regnum - ARM_WC0_REGNUM + SIM_ARM_IWMMXT_COP1R0_REGNUM; + + if (regnum >= ARM_WCGR0_REGNUM && regnum <= ARM_WCGR7_REGNUM) + return regnum - ARM_WCGR0_REGNUM + SIM_ARM_IWMMXT_COP1R8_REGNUM; + if (reg < NUM_GREGS) return SIM_ARM_R0_REGNUM + reg; reg -= NUM_GREGS; @@ -2482,6 +2531,11 @@ set_disassembly_style_sfunc (char *args, int from_tty, static const char * arm_register_name (int i) { + if (i >= ARRAY_SIZE (arm_register_names)) + /* These registers are only supported on targets which supply + an XML description. */ + return ""; + return arm_register_names[i]; } @@ -2597,6 +2651,7 @@ arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) enum arm_float_model fp_model = arm_fp_model; struct tdesc_arch_data *tdesc_data = NULL; int i; + int have_fpa_registers = 1; /* Check any target description for validity. */ if (tdesc_has_registers (info.target_desc)) @@ -2653,6 +2708,43 @@ arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) return NULL; } } + else + have_fpa_registers = 0; + + feature = tdesc_find_feature (info.target_desc, + "org.gnu.gdb.xscale.iwmmxt"); + if (feature != NULL) + { + static const char *const iwmmxt_names[] = { + "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7", + "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15", + "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "", + "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "", + }; + + valid_p = 1; + for (i = ARM_WR0_REGNUM; i <= ARM_WR15_REGNUM; i++) + valid_p + &= tdesc_numbered_register (feature, tdesc_data, i, + iwmmxt_names[i - ARM_WR0_REGNUM]); + + /* Check for the control registers, but do not fail if they + are missing. */ + for (i = ARM_WC0_REGNUM; i <= ARM_WCASF_REGNUM; i++) + tdesc_numbered_register (feature, tdesc_data, i, + iwmmxt_names[i - ARM_WR0_REGNUM]); + + for (i = ARM_WCGR0_REGNUM; i <= ARM_WCGR3_REGNUM; i++) + valid_p + &= tdesc_numbered_register (feature, tdesc_data, i, + iwmmxt_names[i - ARM_WR0_REGNUM]); + + if (!valid_p) + { + tdesc_data_cleanup (tdesc_data); + return NULL; + } + } } /* If we have an object to base this architecture on, try to determine @@ -2796,6 +2888,7 @@ arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) These are gdbarch discriminators, like the OSABI. */ tdep->arm_abi = arm_abi; tdep->fp_model = fp_model; + tdep->have_fpa_registers = have_fpa_registers; /* Breakpoints. */ switch (info.byte_order) @@ -2858,14 +2951,20 @@ arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc); /* Information about registers, etc. */ - set_gdbarch_print_float_info (gdbarch, arm_print_float_info); set_gdbarch_deprecated_fp_regnum (gdbarch, ARM_FP_REGNUM); /* ??? */ set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM); set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM); - set_gdbarch_num_regs (gdbarch, NUM_GREGS + NUM_FREGS + NUM_SREGS); + set_gdbarch_num_regs (gdbarch, ARM_NUM_REGS); set_gdbarch_register_type (gdbarch, arm_register_type); + /* This "info float" is FPA-specific. Use the generic version if we + do not have FPA. */ + if (gdbarch_tdep (gdbarch)->have_fpa_registers) + set_gdbarch_print_float_info (gdbarch, arm_print_float_info); + /* Internal <-> external register number maps. */ + set_gdbarch_dwarf_reg_to_regnum (gdbarch, arm_dwarf_reg_to_regnum); + set_gdbarch_dwarf2_reg_to_regnum (gdbarch, arm_dwarf_reg_to_regnum); set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno); /* Integer registers are 4 bytes. */ diff --git a/gdb/arm-tdep.h b/gdb/arm-tdep.h index 3bb76217b7c..c5c69297cca 100644 --- a/gdb/arm-tdep.h +++ b/gdb/arm-tdep.h @@ -44,6 +44,19 @@ enum gdb_regnum { ARM_F7_REGNUM = 23, /* last floating point register */ ARM_FPS_REGNUM = 24, /* floating point status register */ ARM_PS_REGNUM = 25, /* Contains processor status */ + ARM_WR0_REGNUM, /* WMMX data registers. */ + ARM_WR15_REGNUM = ARM_WR0_REGNUM + 15, + ARM_WC0_REGNUM, /* WMMX control registers. */ + ARM_WCSSF_REGNUM = ARM_WC0_REGNUM + 2, + ARM_WCASF_REGNUM = ARM_WC0_REGNUM + 3, + ARM_WC7_REGNUM = ARM_WC0_REGNUM + 7, + ARM_WCGR0_REGNUM, /* WMMX general purpose registers. */ + ARM_WCGR3_REGNUM = ARM_WCGR0_REGNUM + 3, + ARM_WCGR7_REGNUM = ARM_WCGR0_REGNUM + 7, + + ARM_NUM_REGS, + + /* Other useful registers. */ ARM_FP_REGNUM = 11, /* Frame register in ARM code, if used. */ THUMB_FP_REGNUM = 7, /* Frame register in Thumb code, if used. */ ARM_NUM_ARG_REGS = 4, @@ -146,6 +159,8 @@ struct gdbarch_tdep enum arm_float_model fp_model; /* Floating point calling conventions. */ + int have_fpa_registers; /* Does the target report the FPA registers? */ + CORE_ADDR lowest_pc; /* Lowest address at which instructions will appear. */ diff --git a/gdb/doc/ChangeLog b/gdb/doc/ChangeLog index cd752d196a8..f083bb226d3 100644 --- a/gdb/doc/ChangeLog +++ b/gdb/doc/ChangeLog @@ -1,3 +1,9 @@ +2007-02-26 Daniel Jacobowitz + + * src/gdb/doc/gdb.texinfo (Standard Target Features): Mention + case insensitivity. + (ARM Features): Describe org.gnu.gdb.xscale.iwmmxt. + 2007-02-18 Nick Roberts * gdb.texinfo (Top): Put Appendix A after numbered sections. diff --git a/gdb/doc/gdb.texinfo b/gdb/doc/gdb.texinfo index a31cfd6250a..a2d27e353d9 100644 --- a/gdb/doc/gdb.texinfo +++ b/gdb/doc/gdb.texinfo @@ -26082,6 +26082,10 @@ company or organization which selected the name, and the overall architecture to which the feature applies; so e.g.@: the feature containing ARM core registers is named @samp{org.gnu.gdb.arm.core}. +The names of registers are not case sensitive for the purpose +of recognizing standard features, but @value{GDBN} will only display +registers using the capitalization used in the description. + @subsection ARM Features @cindex target descriptions, ARM features @@ -26092,6 +26096,10 @@ It should contain registers @samp{r0} through @samp{r13}, @samp{sp}, The @samp{org.gnu.gdb.arm.fpa} feature is optional. If present, it should contain registers @samp{f0} through @samp{f7} and @samp{fps}. +The @samp{org.gnu.gdb.xscale.iwmmxt} feature is optional. If present, +it should contain at least registers @samp{wR0} through @samp{wR15} and +@samp{wCGR0} through @samp{wCGR3}. The @samp{wCID}, @samp{wCon}, +@samp{wCSSF}, and @samp{wCASF} registers are optional. @include gpl.texi diff --git a/gdb/features/xscale-iwmmxt.xml b/gdb/features/xscale-iwmmxt.xml index 46fbf4148b0..bedf1d78a86 100644 --- a/gdb/features/xscale-iwmmxt.xml +++ b/gdb/features/xscale-iwmmxt.xml @@ -17,28 +17,28 @@ - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + - - + + - - - - + + + + diff --git a/gdb/regformats/arm-with-iwmmxt.dat b/gdb/regformats/arm-with-iwmmxt.dat index 9bfd4cc868c..17bfec26c13 100644 --- a/gdb/regformats/arm-with-iwmmxt.dat +++ b/gdb/regformats/arm-with-iwmmxt.dat @@ -27,25 +27,25 @@ expedite:r11,sp,pc 0: 0: 32:cpsr -64:wr0 -64:wr1 -64:wr2 -64:wr3 -64:wr4 -64:wr5 -64:wr6 -64:wr7 -64:wr8 -64:wr9 -64:wr10 -64:wr11 -64:wr12 -64:wr13 -64:wr14 -64:wr15 -32:wcssf -32:wcasf -32:wcgr0 -32:wcgr1 -32:wcgr2 -32:wcgr3 +64:wR0 +64:wR1 +64:wR2 +64:wR3 +64:wR4 +64:wR5 +64:wR6 +64:wR7 +64:wR8 +64:wR9 +64:wR10 +64:wR11 +64:wR12 +64:wR13 +64:wR14 +64:wR15 +32:wCSSF +32:wCASF +32:wCGR0 +32:wCGR1 +32:wCGR2 +32:wCGR3 diff --git a/gdb/testsuite/ChangeLog b/gdb/testsuite/ChangeLog index 3925705d2f8..656d0c82bbf 100644 --- a/gdb/testsuite/ChangeLog +++ b/gdb/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2007-02-26 Daniel Jacobowitz + + * gdb.arch/iwmmxt-regs.c, gdb.arch/iwmmxt-regs.exp: Update + register capitalization. + 2007-02-13 Denis Pilat * gdb.mi/mi-var-invalidate.exp: New file. diff --git a/gdb/testsuite/gdb.arch/iwmmxt-regs.c b/gdb/testsuite/gdb.arch/iwmmxt-regs.c index 9c305700d38..534fd162e0d 100644 --- a/gdb/testsuite/gdb.arch/iwmmxt-regs.c +++ b/gdb/testsuite/gdb.arch/iwmmxt-regs.c @@ -22,57 +22,57 @@ void read_regs (unsigned long long regs[16], unsigned long control_regs[6]) { - asm volatile ("wstrd wr0, %0" : "=m" (regs[0])); - asm volatile ("wstrd wr1, %0" : "=m" (regs[1])); - asm volatile ("wstrd wr2, %0" : "=m" (regs[2])); - asm volatile ("wstrd wr3, %0" : "=m" (regs[3])); - asm volatile ("wstrd wr4, %0" : "=m" (regs[4])); - asm volatile ("wstrd wr5, %0" : "=m" (regs[5])); - asm volatile ("wstrd wr6, %0" : "=m" (regs[6])); - asm volatile ("wstrd wr7, %0" : "=m" (regs[7])); - asm volatile ("wstrd wr8, %0" : "=m" (regs[8])); - asm volatile ("wstrd wr9, %0" : "=m" (regs[9])); - asm volatile ("wstrd wr10, %0" : "=m" (regs[10])); - asm volatile ("wstrd wr11, %0" : "=m" (regs[11])); - asm volatile ("wstrd wr12, %0" : "=m" (regs[12])); - asm volatile ("wstrd wr13, %0" : "=m" (regs[13])); - asm volatile ("wstrd wr14, %0" : "=m" (regs[14])); - asm volatile ("wstrd wr15, %0" : "=m" (regs[15])); + asm volatile ("wstrd wR0, %0" : "=m" (regs[0])); + asm volatile ("wstrd wR1, %0" : "=m" (regs[1])); + asm volatile ("wstrd wR2, %0" : "=m" (regs[2])); + asm volatile ("wstrd wR3, %0" : "=m" (regs[3])); + asm volatile ("wstrd wR4, %0" : "=m" (regs[4])); + asm volatile ("wstrd wR5, %0" : "=m" (regs[5])); + asm volatile ("wstrd wR6, %0" : "=m" (regs[6])); + asm volatile ("wstrd wR7, %0" : "=m" (regs[7])); + asm volatile ("wstrd wR8, %0" : "=m" (regs[8])); + asm volatile ("wstrd wR9, %0" : "=m" (regs[9])); + asm volatile ("wstrd wR10, %0" : "=m" (regs[10])); + asm volatile ("wstrd wR11, %0" : "=m" (regs[11])); + asm volatile ("wstrd wR12, %0" : "=m" (regs[12])); + asm volatile ("wstrd wR13, %0" : "=m" (regs[13])); + asm volatile ("wstrd wR14, %0" : "=m" (regs[14])); + asm volatile ("wstrd wR15, %0" : "=m" (regs[15])); - asm volatile ("wstrw wcssf, %0" : "=m" (control_regs[0])); - asm volatile ("wstrw wcasf, %0" : "=m" (control_regs[1])); - asm volatile ("wstrw wcgr0, %0" : "=m" (control_regs[2])); - asm volatile ("wstrw wcgr1, %0" : "=m" (control_regs[3])); - asm volatile ("wstrw wcgr2, %0" : "=m" (control_regs[4])); - asm volatile ("wstrw wcgr3, %0" : "=m" (control_regs[5])); + asm volatile ("wstrw wCSSF, %0" : "=m" (control_regs[0])); + asm volatile ("wstrw wCASF, %0" : "=m" (control_regs[1])); + asm volatile ("wstrw wCGR0, %0" : "=m" (control_regs[2])); + asm volatile ("wstrw wCGR1, %0" : "=m" (control_regs[3])); + asm volatile ("wstrw wCGR2, %0" : "=m" (control_regs[4])); + asm volatile ("wstrw wCGR3, %0" : "=m" (control_regs[5])); } void write_regs (unsigned long long regs[16], unsigned long control_regs[6]) { - asm volatile ("wldrd wr0, %0" : : "m" (regs[0])); - asm volatile ("wldrd wr1, %0" : : "m" (regs[1])); - asm volatile ("wldrd wr2, %0" : : "m" (regs[2])); - asm volatile ("wldrd wr3, %0" : : "m" (regs[3])); - asm volatile ("wldrd wr4, %0" : : "m" (regs[4])); - asm volatile ("wldrd wr5, %0" : : "m" (regs[5])); - asm volatile ("wldrd wr6, %0" : : "m" (regs[6])); - asm volatile ("wldrd wr7, %0" : : "m" (regs[7])); - asm volatile ("wldrd wr8, %0" : : "m" (regs[8])); - asm volatile ("wldrd wr9, %0" : : "m" (regs[9])); - asm volatile ("wldrd wr10, %0" : : "m" (regs[10])); - asm volatile ("wldrd wr11, %0" : : "m" (regs[11])); - asm volatile ("wldrd wr12, %0" : : "m" (regs[12])); - asm volatile ("wldrd wr13, %0" : : "m" (regs[13])); - asm volatile ("wldrd wr14, %0" : : "m" (regs[14])); - asm volatile ("wldrd wr15, %0" : : "m" (regs[15])); + asm volatile ("wldrd wR0, %0" : : "m" (regs[0])); + asm volatile ("wldrd wR1, %0" : : "m" (regs[1])); + asm volatile ("wldrd wR2, %0" : : "m" (regs[2])); + asm volatile ("wldrd wR3, %0" : : "m" (regs[3])); + asm volatile ("wldrd wR4, %0" : : "m" (regs[4])); + asm volatile ("wldrd wR5, %0" : : "m" (regs[5])); + asm volatile ("wldrd wR6, %0" : : "m" (regs[6])); + asm volatile ("wldrd wR7, %0" : : "m" (regs[7])); + asm volatile ("wldrd wR8, %0" : : "m" (regs[8])); + asm volatile ("wldrd wR9, %0" : : "m" (regs[9])); + asm volatile ("wldrd wR10, %0" : : "m" (regs[10])); + asm volatile ("wldrd wR11, %0" : : "m" (regs[11])); + asm volatile ("wldrd wR12, %0" : : "m" (regs[12])); + asm volatile ("wldrd wR13, %0" : : "m" (regs[13])); + asm volatile ("wldrd wR14, %0" : : "m" (regs[14])); + asm volatile ("wldrd wR15, %0" : : "m" (regs[15])); - asm volatile ("wldrw wcssf, %0" : : "m" (control_regs[0])); - asm volatile ("wldrw wcasf, %0" : : "m" (control_regs[1])); - asm volatile ("wldrw wcgr0, %0" : : "m" (control_regs[2])); - asm volatile ("wldrw wcgr1, %0" : : "m" (control_regs[3])); - asm volatile ("wldrw wcgr2, %0" : : "m" (control_regs[4])); - asm volatile ("wldrw wcgr3, %0" : : "m" (control_regs[5])); + asm volatile ("wldrw wCSSF, %0" : : "m" (control_regs[0])); + asm volatile ("wldrw wCASF, %0" : : "m" (control_regs[1])); + asm volatile ("wldrw wCGR0, %0" : : "m" (control_regs[2])); + asm volatile ("wldrw wCGR1, %0" : : "m" (control_regs[3])); + asm volatile ("wldrw wCGR2, %0" : : "m" (control_regs[4])); + asm volatile ("wldrw wCGR3, %0" : : "m" (control_regs[5])); } int diff --git a/gdb/testsuite/gdb.arch/iwmmxt-regs.exp b/gdb/testsuite/gdb.arch/iwmmxt-regs.exp index c04015706e4..81db2153c2b 100644 --- a/gdb/testsuite/gdb.arch/iwmmxt-regs.exp +++ b/gdb/testsuite/gdb.arch/iwmmxt-regs.exp @@ -47,32 +47,32 @@ if ![runto_main] then { # Set all the registers to arbitrary values. for {set i 0} {$i < 16} {incr i 1} { - gdb_test "set \$wr$i.u64 = ((${i}LL << 32) | ${i})" "" "set reg wr$i" + gdb_test "set \$wR$i.u64 = ((${i}LL << 32) | ${i})" "" "set reg wR$i" } -gdb_test "set \$wcssf = 300" "" "set reg wcssf" -gdb_test "set \$wcasf = 200" "" "set reg wcasf" +gdb_test "set \$wCSSF = 300" "" "set reg wCSSF" +gdb_test "set \$wCASF = 200" "" "set reg wCASF" for {set i 0} {$i < 4} {incr i 1} { - gdb_test "set \$wcgr$i = 100 + $i" "" "set reg wcgr$i" + gdb_test "set \$wCGR$i = 100 + $i" "" "set reg wCGR$i" } # See if the sets stuck. gdb_test "next" ".*write_regs.*" "next over read_regs" for {set i 0} {$i < 16} {incr i 1} { - gdb_test "p \$wr$i.u64 == ((${i}LL << 32) | ${i})" "\\\$$decimal = 1" "test reg wr$i" + gdb_test "p \$wR$i.u64 == ((${i}LL << 32) | ${i})" "\\\$$decimal = 1" "test reg wR$i" } -# Don't test wcssf. -gdb_test "p \$wcasf" "\\\$$decimal = 200" "test reg wcasf" +# Don't test wCSSF. +gdb_test "p \$wCASF" "\\\$$decimal = 200" "test reg wCASF" for {set i 0} {$i < 4} {incr i 1} { - gdb_test "p \$wcgr$i == 100 + $i" "\\\$$decimal = 1" "test reg wcgr$i" + gdb_test "p \$wCGR$i == 100 + $i" "\\\$$decimal = 1" "test reg wCGR$i" } # Also verify the copies read by the target. for {set i 0} {$i < 16} {incr i 1} { - gdb_test "p regs\[$i\] == ((${i}LL << 32) | ${i})" "\\\$$decimal = 1" "test stored wr$i" + gdb_test "p regs\[$i\] == ((${i}LL << 32) | ${i})" "\\\$$decimal = 1" "test stored wR$i" } # Don't test wcssf. -gdb_test "p control_regs\[1\]" "\\\$$decimal = 200" "test stored wcasf" +gdb_test "p control_regs\[1\]" "\\\$$decimal = 200" "test stored wCASF" for {set i 0} {$i < 4} {incr i 1} { - gdb_test "p control_regs\[$i + 2\] == 100 + $i" "\\\$$decimal = 1" "test stored wcgr$i" + gdb_test "p control_regs\[$i + 2\] == 100 + $i" "\\\$$decimal = 1" "test stored wCGR$i" } -- 2.30.2