From ff83dd1be113c4c53acf68530d5e32df1017d5ca Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 27 May 2021 18:37:38 +0100 Subject: [PATCH] debug print qemu and simulator LR --- src/openpower/decoder/isa/pypowersim.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/openpower/decoder/isa/pypowersim.py b/src/openpower/decoder/isa/pypowersim.py index 5a4d3e6d..159c7c56 100644 --- a/src/openpower/decoder/isa/pypowersim.py +++ b/src/openpower/decoder/isa/pypowersim.py @@ -93,13 +93,16 @@ def qemu_register_compare(sim, q, regs, fprs): sim_cr = sim.cr.value sim_pc = sim.pc.CIA.value sim_xer = sim.spr['XER'].value + sim_lr = sim.spr['LR'].value print("qemu pc", hex(qpc)) print("qemu cr", hex(qcr)) + print("qemu lr", bin(qlr)) print("qemu xer", bin(qxer)) print("sim nia", hex(sim.pc.NIA.value)) print("sim pc", hex(sim.pc.CIA.value)) print("sim cr", hex(sim_cr)) print("sim xer", hex(sim_xer)) + print("sim lr", hex(sim_lr)) #self.assertEqual(qpc, sim_pc) for reg in regs: qemu_val = q.get_gpr(reg) -- 2.30.2