From ffb14e2b7bb17556459d68d930f91672bca89c0d Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 4 Jun 2020 20:05:33 +0100 Subject: [PATCH] whoops, docstring indentation --- src/soc/simple/core.py | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py index 35becb01..d543203a 100644 --- a/src/soc/simple/core.py +++ b/src/soc/simple/core.py @@ -90,11 +90,12 @@ class NonProductionCore(Elaboratable): return fu_bitdict def connect_rdports(self, m, fu_bitdict): - """connect read ports + """connect read ports - orders the read regspecs into a dict-of-dicts, by regfile, by regport name, - then connects all FUs that want that regport by way of a PriorityPicker. - """ + orders the read regspecs into a dict-of-dicts, by regfile, by + regport name, then connects all FUs that want that regport by + way of a PriorityPicker. + """ comb, sync = m.d.comb, m.d.sync fus = self.fus.fus regs = self.regs @@ -154,15 +155,16 @@ class NonProductionCore(Elaboratable): comb += src.eq(rport.data_o) # all FUs connect to same port def connect_wrports(self, m, fu_bitdict): - """connect write ports + """connect write ports - orders the write regspecs into a dict-of-dicts, by regfile, by regport name, - then connects all FUs that want that regport by way of a PriorityPicker. + orders the write regspecs into a dict-of-dicts, by regfile, + by regport name, then connects all FUs that want that regport + by way of a PriorityPicker. - note that the write-port wen, write-port data, and go_wr_i all need to - be on the exact same clock cycle. as there is a combinatorial loop bug - at the moment, these all use sync. - """ + note that the write-port wen, write-port data, and go_wr_i all need to + be on the exact same clock cycle. as there is a combinatorial loop bug + at the moment, these all use sync. + """ comb, sync = m.d.comb, m.d.sync fus = self.fus.fus regs = self.regs -- 2.30.2