From ffcf0f458cef79466e33d81e09a8d9b647f50c4d Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 28 Jul 2019 13:09:46 +0100 Subject: [PATCH] add debug prints --- src/ieee754/div_rem_sqrt_rsqrt/core.py | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/ieee754/div_rem_sqrt_rsqrt/core.py b/src/ieee754/div_rem_sqrt_rsqrt/core.py index b62a9574..3d56413f 100644 --- a/src/ieee754/div_rem_sqrt_rsqrt/core.py +++ b/src/ieee754/div_rem_sqrt_rsqrt/core.py @@ -38,6 +38,7 @@ class DivPipeCoreConfig: self.bit_width = bit_width self.fract_width = fract_width self.log2_radix = log2_radix + print(f"{self}: n_stages={self.n_stages}") def __repr__(self): """ Get repr. """ @@ -383,6 +384,10 @@ class DivPipeCoreCalculateStage(Elaboratable): log2_radix = min(log2_radix, current_shift) assert log2_radix > 0 current_shift -= log2_radix + print(f"DivPipeCoreCalc: stage {self.stage_index}" + + f" of {self.core_config.n_stages} handling " + + f"bits [{current_shift}, {current_shift+log2_radix})" + + f" of {self.core_config.bit_width}") radix = 1 << log2_radix # trials within this radix range. carried out by Trial module, -- 2.30.2