From ffd10e3042be9700644ee1d23961af51277e43e4 Mon Sep 17 00:00:00 2001 From: whitequark Date: Sat, 26 Oct 2019 01:52:34 +0000 Subject: [PATCH] back.rtlil: fix lowering of Part() on LHS to account for stride. --- examples/basic/sel.py | 30 ++++++++++++++++++++++++++++++ nmigen/back/rtlil.py | 8 ++++++-- 2 files changed, 36 insertions(+), 2 deletions(-) create mode 100644 examples/basic/sel.py diff --git a/examples/basic/sel.py b/examples/basic/sel.py new file mode 100644 index 0000000..b4797ec --- /dev/null +++ b/examples/basic/sel.py @@ -0,0 +1,30 @@ +from types import SimpleNamespace +from nmigen import * +from nmigen.cli import main + + +class FlatGPIO(Elaboratable): + def __init__(self, pins, bus): + self.pins = pins + self.bus = bus + + def elaborate(self, platform): + bus = self.bus + + m = Module() + m.d.comb += bus.r_data.eq(self.pins.word_select(bus.addr, len(bus.r_data))) + with m.If(bus.we): + m.d.sync += self.pins.word_select(bus.addr, len(bus.w_data)).eq(bus.w_data) + return m + + +if __name__ == "__main__": + bus = Record([ + ("addr", 3), + ("r_data", 2), + ("w_data", 2), + ("we", 1), + ]) + pins = Signal(8) + gpio = FlatGPIO(pins, bus) + main(gpio, ports=[pins, bus.addr, bus.r_data, bus.w_data, bus.we]) diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py index 5a847c5..bb52721 100644 --- a/nmigen/back/rtlil.py +++ b/nmigen/back/rtlil.py @@ -622,9 +622,13 @@ class _LHSValueCompiler(_ValueCompiler): def on_Part(self, value): offset = self.s.expand(value.offset) if isinstance(offset, ast.Const): - return self(ast.Slice(value.value, offset.value, offset.value + value.width)) + return self(ast.Slice(value.value, + offset.value * value.stride, + offset.value * value.stride + value.width)) else: - raise LegalizeValue(value.offset, range((1 << len(value.offset))), value.src_loc) + raise LegalizeValue(value.offset, + range((1 << len(value.offset)) // value.stride), + value.src_loc) def on_Repl(self, value): raise TypeError # :nocov: -- 2.30.2