From ffd38cb5ea7a6b7d93a49c90bf603131f6c760af Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 6 Jan 2020 09:03:18 -0800 Subject: [PATCH] Reword (* abc9_flop *) description --- README.md | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/README.md b/README.md index aab1c7d6b..77e9410da 100644 --- a/README.md +++ b/README.md @@ -376,10 +376,11 @@ Verilog Attributes and non-standard features - The port attribute ``abc9_arrival`` specifies an integer (for output ports only) to be used as the arrival time of this sequential port. It can be used, for example, to specify the clk-to-Q delay of a flip-flop for consideration - during techmapping. + during `abc9` techmapping. - The module attribute ``abc9_flop`` is a boolean marking the module as a - whitebox that describes the synchronous behaviour of a flip-flop. + flip-flop. This allows `abc9` to analyse its contents in order to perform + sequential synthesis. - The frontend sets attributes ``always_comb``, ``always_latch`` and ``always_ff`` on processes derived from SystemVerilog style always blocks -- 2.30.2