From ffdfe62279fdff8c695d57ca4d8dccdd719074d4 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 8 Oct 2020 18:13:50 +0100 Subject: [PATCH] add incoming PortInterface to be connected to LoadStoreCompUnit --- src/soc/fu/mmu/fsm.py | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/soc/fu/mmu/fsm.py b/src/soc/fu/mmu/fsm.py index fc950026..04160db8 100644 --- a/src/soc/fu/mmu/fsm.py +++ b/src/soc/fu/mmu/fsm.py @@ -11,6 +11,7 @@ from soc.decoder.power_fieldsn import SignalBitRange from soc.decoder.power_decoder2 import decode_spr_num from soc.decoder.power_enums import MicrOp, SPR, XER_bits +from soc.experiment.pimem import PortInterface class FSMMMUStage(ControlBase): def __init__(self, pspec): @@ -21,6 +22,9 @@ class FSMMMUStage(ControlBase): self.p.data_i = MMUInputData(pspec) self.n.data_o = MMUOutputData(pspec) + # incoming PortInterface + self.pi = PortInterface("mmupi") + # this Function Unit is extremely unusual in that it actually stores a # "thing" rather than "processes inputs and produces outputs". hence # why it has to be a FSM. linking up LD/ST however is going to have -- 2.30.2