From fff08681b2e012b6f2b2ee8506216d753b74fa0e Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 9 Oct 2021 20:52:14 +0100 Subject: [PATCH] altered test_partsig2.py removed outval, run with outval2 instead --- src/ieee754/part/test/test_partsig.py | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/ieee754/part/test/test_partsig.py b/src/ieee754/part/test/test_partsig.py index 1830af12..f5294a84 100644 --- a/src/ieee754/part/test/test_partsig.py +++ b/src/ieee754/part/test/test_partsig.py @@ -322,9 +322,8 @@ class TestMux(unittest.TestCase): outval2 = (yield module.mux_out2) msg = f"{msg_prefix}: mux " + \ f"0x{sel:X} ? 0x{a:X} : 0x{b:X}" + \ - f" => 0x{y:X} != 0x{outval:X}, masklist %s" + f" => 0x{y:X} != 0x{outval2:X}, masklist %s" # print ((msg % str(maskbit_list)).format(locals())) - self.assertEqual(y, outval, msg % str(maskbit_list)) self.assertEqual(y, outval2, msg % str(maskbit_list)) yield part_mask.eq(0) -- 2.30.2