From fff94262f49a1213bcddad2535cbe284b3a65b7b Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 3 Jul 2020 04:32:30 +0100 Subject: [PATCH] cut root_times_radicand if not doing Sqrt --- src/ieee754/div_rem_sqrt_rsqrt/core.py | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/src/ieee754/div_rem_sqrt_rsqrt/core.py b/src/ieee754/div_rem_sqrt_rsqrt/core.py index 45a02fb7..603af40a 100644 --- a/src/ieee754/div_rem_sqrt_rsqrt/core.py +++ b/src/ieee754/div_rem_sqrt_rsqrt/core.py @@ -377,6 +377,7 @@ class DivPipeCoreCalculateStage(Elaboratable): """ Elaborate into ``Module``. """ m = Module() comb = m.d.comb + cc = self.core_config # copy invariant inputs to outputs (for next stage) comb += self.o.divisor_radicand.eq(self.i.divisor_radicand) @@ -445,10 +446,11 @@ class DivPipeCoreCalculateStage(Elaboratable): # create outputs for next phase qr = self.i.quotient_root | (next_bits << current_shift) - rr = self.i.root_times_radicand + ((self.i.divisor_radicand * next_bits) - << current_shift) comb += self.o.quotient_root.eq(qr) - comb += self.o.root_times_radicand.eq(rr) + if DP.RSqrtRem in cc.supported: + rr = self.i.root_times_radicand + ((self.i.divisor_radicand * + next_bits) << current_shift) + comb += self.o.root_times_radicand.eq(rr) return m -- 2.30.2