From f195d6739272d5524e4081e70bda9b68c1b5013e Mon Sep 17 00:00:00 2001 From: Jack Koenig Date: Thu, 1 Mar 2018 15:35:35 -0800 Subject: [PATCH] Consistently use private val for autoclonetype --- src/main/scala/devices/gpio/GPIO.scala | 2 +- src/main/scala/devices/gpio/GPIOPins.scala | 4 ++-- src/main/scala/devices/spi/SPIBundle.scala | 2 +- src/main/scala/devices/spi/SPIPins.scala | 2 +- src/main/scala/util/Timer.scala | 2 +- 5 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/main/scala/devices/gpio/GPIO.scala b/src/main/scala/devices/gpio/GPIO.scala index ce1089a..a1b166f 100644 --- a/src/main/scala/devices/gpio/GPIO.scala +++ b/src/main/scala/devices/gpio/GPIO.scala @@ -75,7 +75,7 @@ object BasePinToIOF { // level, and we have to do the pinmux // outside of RocketChipTop. -class GPIOPortIO(val c: GPIOParams) extends Bundle { +class GPIOPortIO(private val c: GPIOParams) extends Bundle { val pins = Vec(c.width, new EnhancedPin()) val iof_0 = if (c.includeIOF) Some(Vec(c.width, new IOFPin).flip) else None val iof_1 = if (c.includeIOF) Some(Vec(c.width, new IOFPin).flip) else None diff --git a/src/main/scala/devices/gpio/GPIOPins.scala b/src/main/scala/devices/gpio/GPIOPins.scala index 2cae881..da6ade3 100644 --- a/src/main/scala/devices/gpio/GPIOPins.scala +++ b/src/main/scala/devices/gpio/GPIOPins.scala @@ -9,11 +9,11 @@ import sifive.blocks.devices.pinctrl.{Pin} // even though it looks like something that more directly talks to // a pin. It also makes it possible to change the exact // type of pad this connects to. -class GPIOSignals[T <: Data](private val pingen: ()=> T, val c: GPIOParams) extends Bundle { +class GPIOSignals[T <: Data](private val pingen: () => T, private val c: GPIOParams) extends Bundle { val pins = Vec(c.width, pingen()) } -class GPIOPins[T <: Pin](pingen: ()=> T, c: GPIOParams) extends GPIOSignals[T](pingen, c) +class GPIOPins[T <: Pin](pingen: () => T, c: GPIOParams) extends GPIOSignals[T](pingen, c) object GPIOPinsFromPort { diff --git a/src/main/scala/devices/spi/SPIBundle.scala b/src/main/scala/devices/spi/SPIBundle.scala index aaef313..e7abde6 100644 --- a/src/main/scala/devices/spi/SPIBundle.scala +++ b/src/main/scala/devices/spi/SPIBundle.scala @@ -3,7 +3,7 @@ package sifive.blocks.devices.spi import Chisel._ -abstract class SPIBundle(val c: SPIParamsBase) extends Bundle +abstract class SPIBundle(private val c: SPIParamsBase) extends Bundle class SPIDataIO extends Bundle { val i = Bool(INPUT) diff --git a/src/main/scala/devices/spi/SPIPins.scala b/src/main/scala/devices/spi/SPIPins.scala index bad0e6f..f8ce8e1 100644 --- a/src/main/scala/devices/spi/SPIPins.scala +++ b/src/main/scala/devices/spi/SPIPins.scala @@ -5,7 +5,7 @@ import Chisel._ import chisel3.experimental.{withClockAndReset} import sifive.blocks.devices.pinctrl.{PinCtrl, Pin} -class SPISignals[T <: Data](val pingen: ()=> T, c: SPIParamsBase) extends SPIBundle(c) { +class SPISignals[T <: Data](private val pingen: () => T, c: SPIParamsBase) extends SPIBundle(c) { val sck = pingen() val dq = Vec(4, pingen()) diff --git a/src/main/scala/util/Timer.scala b/src/main/scala/util/Timer.scala index cc9c85d..35e4a83 100644 --- a/src/main/scala/util/Timer.scala +++ b/src/main/scala/util/Timer.scala @@ -6,7 +6,7 @@ import Chisel.ImplicitConversions._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.util.WideCounter -class SlaveRegIF(val w: Int) extends Bundle { +class SlaveRegIF(private val w: Int) extends Bundle { val write = Valid(UInt(width = w)).flip val read = UInt(OUTPUT, w) -- 2.30.2