From dea437afb25dbf082532a39f8e2d122d079e6b10 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Wed, 20 Sep 2023 15:38:37 -0700 Subject: [PATCH] make scalar EXTRA2 encoding match between tables and algorithms Fixes: https://bugs.libre-soc.org/show_bug.cgi?id=1161 --- openpower/sv/svp64.mdwn | 6 ++++-- openpower/sv/svp64/appendix.mdwn | 6 ++++-- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn index c623c123a..227abd8ce 100644 --- a/openpower/sv/svp64.mdwn +++ b/openpower/sv/svp64.mdwn @@ -1195,8 +1195,10 @@ A pseudocode algorithm explains the relationship, for INT/FP (see ``` if extra3_mode: spec = EXTRA3 - else: - spec = EXTRA2 << 1 # same as EXTRA3, shifted + elif EXTRA2[0]: # vector mode, can express even registers in r0-126 + spec = EXTRA2 << 1 # same as EXTRA3, shifted + else: # scalar mode, can express registers in r0-63 + spec = (EXTRA2[0] << 2) | EXTRA2[1] if spec[0]: # vector return (RA << 2) | spec[1:2] else: # scalar diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn index 73426d430..25c62d769 100644 --- a/openpower/sv/svp64/appendix.mdwn +++ b/openpower/sv/svp64/appendix.mdwn @@ -616,8 +616,10 @@ applies, **not** the `CR_bit` portion (bits 3-4): ``` if extra3_mode: spec = EXTRA3 - else: - spec = EXTRA2<<1 | 0b0 + elif EXTRA2[0]: # vector mode + spec = EXTRA2 << 1 # same as EXTRA3, shifted + else: # scalar mode + spec = (EXTRA2[0] << 2) | EXTRA2[1] if spec[0]: # vector constructs "BA[0:2] spec[1:2] 00 BA[3:4]" return ((BA >> 2)<<6) | # hi 3 bits shifted up -- 2.30.2