From be96bff2a401920cac82dedbc1f7a1c27345e25d Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Wed, 20 Sep 2023 15:45:54 -0700 Subject: [PATCH] make scalar EXTRA2 encoding match between tables and algorithms corresponding libreriscv.git commit: 7a232bcca2 Fixes: https://bugs.libre-soc.org/show_bug.cgi?id=1161 --- src/openpower/decoder/power_svp64_extra.py | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/src/openpower/decoder/power_svp64_extra.py b/src/openpower/decoder/power_svp64_extra.py index 0c54cd3b..71903f0a 100644 --- a/src/openpower/decoder/power_svp64_extra.py +++ b/src/openpower/decoder/power_svp64_extra.py @@ -38,19 +38,25 @@ class SVP64ExtraSpec(Elaboratable): with m.Switch(self.etype): # 2-bit index selection mode with m.Case(SVEType.EXTRA2): + extra2_lsb = Signal(1) with m.Switch(self.idx): with m.Case(SVEXTRA.Idx0): # 1st 2 bits [0:1] comb += spec[SPEC.VEC].eq(extra[EXTRA2.IDX0_VEC]) - comb += spec[SPEC.MSB].eq(extra[EXTRA2.IDX0_MSB]) + comb += extra2_lsb.eq(extra[EXTRA2.IDX0_MSB]) with m.Case(SVEXTRA.Idx1): # 2nd 2 bits [2:3] comb += spec[SPEC.VEC].eq(extra[EXTRA2.IDX1_VEC]) - comb += spec[SPEC.MSB].eq(extra[EXTRA2.IDX1_MSB]) + comb += extra2_lsb.eq(extra[EXTRA2.IDX1_MSB]) with m.Case(SVEXTRA.Idx2): # 3rd 2 bits [4:5] comb += spec[SPEC.VEC].eq(extra[EXTRA2.IDX2_VEC]) - comb += spec[SPEC.MSB].eq(extra[EXTRA2.IDX2_MSB]) + comb += extra2_lsb.eq(extra[EXTRA2.IDX2_MSB]) with m.Case(SVEXTRA.Idx3): # 4th 2 bits [6:7] comb += spec[SPEC.VEC].eq(extra[EXTRA2.IDX3_VEC]) - comb += spec[SPEC.MSB].eq(extra[EXTRA2.IDX3_MSB]) + comb += extra2_lsb.eq(extra[EXTRA2.IDX3_MSB]) + with m.If(spec[SPEC.VEC]): # vector mode + # can express reg numbers range(0, 127, 2) + comb += spec[SPEC.MSB].eq(extra2_lsb) + with m.Else(): # scalar mode: can express r0-63 + comb += spec[SPEC.LSB].eq(extra2_lsb) # 3-bit index selection mode with m.Case(SVEType.EXTRA3): with m.Switch(self.idx): -- 2.30.2