From 1e8ec11a10625c905317cbfcdf6ebc7323b0a465 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Thu, 10 Aug 2017 13:26:28 -0700 Subject: [PATCH] uart: output JSON pointing to the TX registers for tapping output --- src/main/scala/devices/uart/UART.scala | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/main/scala/devices/uart/UART.scala b/src/main/scala/devices/uart/UART.scala index 58722e1..3612bce 100644 --- a/src/main/scala/devices/uart/UART.scala +++ b/src/main/scala/devices/uart/UART.scala @@ -69,10 +69,12 @@ class UARTTx(c: UARTParams)(implicit p: Parameters) extends UARTModule(c)(p) { val out = Reg(init = Bits(1, 1)) io.out := out + // Report the UART registers so we can backdoor functionality in simulation + ElaborationArtefacts.add(f"uart-${c.address}%x.json", s"""{"counter":["${counter.pathName}"],"shifter":["${shifter.pathName}"]}\n""") + val busy = (counter =/= UInt(0)) io.in.ready := io.en && !busy when (io.in.fire()) { - printf("%c", io.in.bits) shifter := Cat(io.in.bits, Bits(0, 1)) counter := Mux1H((0 until uartStopBits).map(i => (io.nstop === UInt(i)) -> UInt(n + i + 1))) -- 2.30.2