From 0434ba1d907755fe3057f1d2f2f1d487b02279b9 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Tue, 27 Nov 2018 23:54:15 -0800 Subject: [PATCH] add instructions for using iverilog --- .gitignore | 2 ++ ReadMe.md | 22 ++++++++++++++++++++++ main_test.v | 14 +++++++++++++- 3 files changed, 37 insertions(+), 1 deletion(-) diff --git a/.gitignore b/.gitignore index 20598f5..ccb0f2e 100644 --- a/.gitignore +++ b/.gitignore @@ -75,3 +75,5 @@ /xlnx_auto_0_xdb /xst /output.bit +/dump.vcd +/rv32 diff --git a/ReadMe.md b/ReadMe.md index e777adb..c204664 100644 --- a/ReadMe.md +++ b/ReadMe.md @@ -45,6 +45,28 @@ Requires Xilinx's ISE v. 14.7 to be installed in /opt/Xilinx (just leave the def # at this point the built bitstream is in output.bit djtgcfg prog -d JtagHS2 -i 0 -f output.bit # program the FPGA +## Simulating using Icarus Verilog +Doesn't require Xilinx's ISE or Digilent's programmer + + sudo apt-get install git g++ autoconf automake autotools-dev curl libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev libexpat-dev + sudo mkdir /opt/riscv + sudo chown $USER /opt/riscv # so you don't need root when building; you can change back after building riscv-gnu-toolchain + git clone --recursive https://github.com/riscv/riscv-gnu-toolchain.git + export PATH=/opt/riscv/bin:"$PATH" + cd riscv-gnu-toolchain + ./configure --prefix=/opt/riscv --with-arch=rv32i + make + sudo chown -R root:root /opt/riscv # change owner back to root as the compiler is finished installing + cd .. + git clone https://github.com/programmerjake/rv32.git + cd rv32/software + make ram0_byte0.hex + cd .. + iveriog -o rv32 -Wall *.v + vvp -n rv32 # doesn't terminate, press Ctrl+C when it's generated enough output + +The output is in `dump.vcd`, which can be viewed with GTKWave. + ## Building the hardware (only required if verilog source is modified) Requires having built the software at least once to generate the ram initialization files. diff --git a/main_test.v b/main_test.v index 404b101..12e6801 100644 --- a/main_test.v +++ b/main_test.v @@ -26,6 +26,8 @@ module main_test; // Inputs reg clk; + reg switch_2; + reg switch_3; // Outputs wire [7:0] vga_r; @@ -35,6 +37,9 @@ module main_test; wire vga_vsync; wire vga_blank; wire vga_pixel_clock; + wire led_1; + wire led_3; + // Instantiate the Unit Under Test (UUT) main uut ( @@ -45,12 +50,19 @@ module main_test; .vga_hsync(vga_hsync), .vga_vsync(vga_vsync), .vga_blank(vga_blank), - .vga_pixel_clock(vga_pixel_clock) + .vga_pixel_clock(vga_pixel_clock), + .switch_2(switch_2), + .switch_3(switch_3), + .led_1(led_1), + .led_3(led_3) ); initial begin // Initialize Inputs + $dumpvars; clk = 0; + switch_2 = 0; + switch_3 = 0; // Add stimulus here -- 2.30.2