From 0ec80944ebd0e60189156f35af9285bcb4bf5fa9 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 5 Feb 2024 21:24:16 +0000 Subject: [PATCH] bug 676: maxloc, use crternlogi to reduce op count --- src/openpower/decoder/isa/test_caller_svp64_maxloc.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/openpower/decoder/isa/test_caller_svp64_maxloc.py b/src/openpower/decoder/isa/test_caller_svp64_maxloc.py index 1395d3fb..f7b508b2 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_maxloc.py +++ b/src/openpower/decoder/isa/test_caller_svp64_maxloc.py @@ -89,14 +89,14 @@ class DDFFirstTestCase(FHDLTestCase): "mtcrf 128, 0", # clear CR0 (in case VL=0?) # while (im): "sv.minmax./ff=le/m=ge 4, *10, 4, 1", # uses r4 as accumulator - #"crternlogi 0,1,2,127" # test greater/equal or VL=0 - "cror 0,1,0", # test for greater or equal, or VL=0 - "cror 0,2,0", # test for greater or equal, or VL=0 + "crternlogi 0,1,2,127", # test greater/equal or VL=0 + #"cror 0,1,0", # test for greater or equal, or VL=0 + #"cror 0,2,0", # test for greater or equal, or VL=0 "sv.creqv *19,*16,*16", # set mask on already-tested "sv.crand *19,*19,0", # clear if CR0=0 "sv.svstep/mr/m=so 1, 0, 6, 1", # svstep: get vector dststep "sv.creqv *16,*16,*16", # set mask on already-tested - "bc 12,0, -0x4c" # CR0 lt bit clear, branch back + "bc 12,0, -0x48" # CR0 lt bit clear, branch back ]) lst = list(lst) -- 2.30.2