From 4e82969afd88858a544795bc93caf8dde9c529f5 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 28 Jun 2022 14:53:41 +0100
Subject: [PATCH] add RG0 and RG1 to descripiton

---
 src/spec/ls2.py | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/spec/ls2.py b/src/spec/ls2.py
index f686db9..7ed9f62 100644
--- a/src/spec/ls2.py
+++ b/src/spec/ls2.py
@@ -141,6 +141,7 @@ def pinspec():
             'UART0', 'GPIOS', 'GPIOE', 'JTAG', 'PWM', 'EINT',
              'VDD', 'VSS', 'SYS',
                 'MTWI', 'MSPI0',
+                'RG0', 'RG1',
                 # 'MSPI1', litex problem 25mar2021
                 'SDR']
     ls180_eint = []
@@ -153,6 +154,8 @@ def pinspec():
         'MSPI1': '',
         'UART0': '',
         'LPC1': '',
+        'RG0': '',
+        'RG1': '',
         'SYS': '',
         'LPC2': '',
         'SDR': '',
-- 
2.30.2